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lab22.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 15:41:18 December 25, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# lab22_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C5E144C8
set_global_assignment -name TOP_LEVEL_ENTITY lab22
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:18 DECEMBER 25, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE lab22.v
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_22 -to CLK
set_location_assignment PIN_126 -to COMM[1]
set_location_assignment PIN_125 -to COMM[2]
set_location_assignment PIN_135 -to DATA_B[0]
set_location_assignment PIN_136 -to DATA_B[1]
set_location_assignment PIN_137 -to DATA_B[2]
set_location_assignment PIN_138 -to DATA_B[3]
set_location_assignment PIN_141 -to DATA_B[4]
set_location_assignment PIN_142 -to DATA_B[5]
set_location_assignment PIN_143 -to DATA_B[6]
set_location_assignment PIN_144 -to DATA_B[7]
set_location_assignment PIN_72 -to DATA_G[0]
set_location_assignment PIN_73 -to DATA_G[1]
set_location_assignment PIN_74 -to DATA_G[2]
set_location_assignment PIN_75 -to DATA_G[3]
set_location_assignment PIN_76 -to DATA_G[4]
set_location_assignment PIN_77 -to DATA_G[5]
set_location_assignment PIN_79 -to DATA_G[6]
set_location_assignment PIN_80 -to DATA_G[7]
set_location_assignment PIN_64 -to DATA_R[0]
set_location_assignment PIN_65 -to DATA_R[1]
set_location_assignment PIN_66 -to DATA_R[2]
set_location_assignment PIN_67 -to DATA_R[3]
set_location_assignment PIN_68 -to DATA_R[4]
set_location_assignment PIN_69 -to DATA_R[5]
set_location_assignment PIN_70 -to DATA_R[6]
set_location_assignment PIN_71 -to DATA_R[7]
set_location_assignment PIN_124 -to enable
set_location_assignment PIN_127 -to COMM[0]
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_129 -to s[1]
set_location_assignment PIN_132 -to s[2]
set_location_assignment PIN_128 -to s[0]
set_location_assignment PIN_133 -to testled
set_location_assignment PIN_115 -to left
set_location_assignment PIN_120 -to right
set_location_assignment PIN_121 -to down
set_location_assignment PIN_119 -to change
set_location_assignment PIN_39 -to level[1]
set_location_assignment PIN_42 -to level[2]
set_location_assignment PIN_43 -to level[3]
set_location_assignment PIN_44 -to level[4]
set_location_assignment PIN_46 -to level[5]
set_location_assignment PIN_49 -to level[6]
set_location_assignment PIN_50 -to level[7]
set_location_assignment PIN_38 -to level[0]
set_location_assignment PIN_51 -to z[0]
set_location_assignment PIN_52 -to z[1]
set_location_assignment PIN_53 -to z[2]
set_location_assignment PIN_54 -to z[3]
set_location_assignment PIN_55 -to z[4]
set_location_assignment PIN_58 -to z[5]
set_location_assignment PIN_59 -to z[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top