RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 92 public repositories matching this topic...
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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Feb 7, 2025 - Verilog
RISC-V Embedded Processor for Approximate Computing
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Nov 2, 2024 - Verilog
XCrypto: a cryptographic ISE for RISC-V
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Jan 5, 2023 - Verilog
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
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Nov 6, 2023 - Verilog
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
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Dec 17, 2023 - Verilog
SCARV: a side-channel hardened RISC-V platform
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Jan 11, 2023 - Verilog