<= rendered as "less than or equal" in Verilog & VHDL

[qrqiuren]

In Verilog and VHDL, <= is a symbol of assignment. For example:

always @ (posedge clk or negedge xrstn)
begin
	if(!xrstn)
	begin
		sum_d <= 0;
	end
	else
	begin
		sum_d <= sum;
	end
end

However, in Fira Code, the assignment symbol <= is rendered as a "less than or equal to" sign.

I hope there could be a stylistic option of rendering it.

[tonsky]

Yes. Same in Erlang. Will make in a stylistic set. Thanks!

[qrqiuren]

I found it has been mentioned in #696

<= in both VHDL and Verilog/SystemVerilog has 2 meanings: 1. less than or equal 2. non-blocking assignment. It seems to be quite difficult for font designers to decide the ligature on the context.

Maybe we can develop a plugin for editors to render different ligatures by the context in each programming language?

[bkDJ]

@qrqiuren The latest VS Code supports ligature stylistic sets globally and on a per-language basis.

[qrqiuren]

@qrqiuren The latest VS Code supports ligature stylistic sets globally and on a per-language basis.

Thank you. I already disabled ligatures for Verilog. Actually, it was me to submit the feature request of stylistic set support in VS Code.

[tonsky]

Will be in v6 as cv20-cv22

[shivampotdar]

In case someone reaches here via search, this can be used to disable ligatures for Verilog and VHDL in VSCode till we get v6: microsoft/vscode#43440 (comment)

[siddhpant]

<= in both VHDL and Verilog/SystemVerilog has 2 meanings: 1. less than or equal 2. non-blocking assignment. It seems to be quite difficult for font designers to decide the ligature on the context.

Maybe we can develop a plugin for editors to render different ligatures by the context in each programming language?

It seems iosevka has verilog set which features both variants: https://github.com/be5invis/Iosevka/blob/main/doc/language-specific-ligation-sets.md (search for VRLG). Didn't try it though. But it seems to be possible.

Edit: Since release 21 (SVG as on release commits: 20, 21).