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chip-6522.a
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;license:MIT
;(c) 2021-2024 by Tom Charlesworth
;
; 6522 related
;
;------------------------------------------------------------------------------
Detect6522
; Pre: X=slot#
; Post: X=slot#
jsr SetMBBase
; 6522's IER.b7 is always 1
; . Due to floating bus (and the visible TEXT screen being mainly $A0 values), then empty slots will likely pass this IER.b7 check
ldy #SY6522_A_BASE+SY6522_IER
lda (MBBase),y
bmi @checkT2_A
;
; Could still be MegaAudio, so use TIMER1 (IER.b7 reads as 0, and TIMER2 isn't supported!)
;
ldy #SY6522_A_BASE+SY6522_TIMER1L_COUNTER
jsr @Check6522
bne +
inc slotInfo,x ; bit0=1
+
@checkT1_B
ldy #SY6522_B_BASE+SY6522_TIMER1L_COUNTER
jsr @Check6522
bne +
inc slotInfo,x
inc slotInfo,x ; bit1=1
+
rts
;
; For a regular Mockingboard, use TIMER2
;
@checkT2_A
ldy #SY6522_A_BASE+SY6522_TIMER2L_COUNTER
jsr @Check6522
bne +
inc slotInfo,x ; bit0=1
+
@checkT2_B
ldy #SY6522_B_BASE+SY6522_TIMER2L_COUNTER
jsr @Check6522
bne +
inc slotInfo,x
inc slotInfo,x ; bit1=1
+
rts
;
@Check6522
; Pre: Y = SY6522_TIMER1L_COUNTER or SY6522_TIMER2L_COUNTER for chip A or B
; NB. Checking with T2 is more robust than with T1, as there's no latch for T2
; Post: Z=1(OK), Z=0(NG)
lda #4 ; try 4 checks (avoid floating bus giving a false-positive)
sta zpTmp1
lda #1 ; failures (can have 1 failure - eg. for that flaky card that works most of the time)
sta zpTmp2
- jsr SF_GetTimerL
beq +
dec zpTmp2
bmi ++
+ dec zpTmp1
bne -
++ rts
;
SF_GetTimerL ; Based on Skyfox's detection code
; Pre: Y = SY6522_TIMER1L_COUNTER or SY6522_TIMER2L_COUNTER for chip A or B
; MBBaseL=$00 (whether checking chip A or B)
; Post: Z=1(OK), Z=0(NG)
lda (MBBase),y
cmp MBBaseL ; 3cy, C=1 since A>=0 as (MBBaseL) == 0x00
sbc (MBBase),y ; 5cy
cmp #$08
beq +
cmp #$09 ; FASTChip //e (Ref: https://github.com/a2-4am/4cade)
+ rts
;------------------------------------------------------------------------------
DetectMegaAudioCard
; Pre: zpTmp1 = slotInfo[slot]
; Post: isMegaAudioCard
; Z=1: no MegaAudio
lda #0
sta isMegaAudioCard
lda zpTmp1
and #HAS_BOTH_6522s
cmp #HAS_BOTH_6522s
bne @done
sei
lda #<Check6522ISR
ldx #>Check6522ISR
jsr SetIrqNmiVectors
lda #0
sta isrCopyA
sta isrIFR_A
jsr WaitT1OneShotUnderflow ; T1C=$0101 (minus a few cycles)
lda #ACR_ONESHOT
ldy #SY6522_ACR
sta (MBBase),y
lda #IER_SET|IxR_TIMER1
ldy #SY6522_IER
sta (MBBase),y
lda #$06
ldy #SY6522_TIMER1L_COUNTER
sta (MBBase),y
lda #$00
ldy #SY6522_TIMER1H_COUNTER
sta (MBBase),y ; (and clears IFR.T1)
; T1C
; $0006
lda #2 ; 2cy ; $0004
ldx #1 ; 2cy ; $0002
cli ; 2cy ; $0000
sta zpTmp2 ; 3cy ; $ffff
; $0002 : real 6522 - IRQ occurs on 2nd cycle... so IRQ occurs after this 'sta zp'
; $0001 : FPGA 6522 - IRQ occurs on 3rd cycle... so IRQ deferred until after next 'stx zp'
stx zpTmp2
lda isrCopyA
and #1
sta isMegaAudioCard
@done
rts
;------------------------------------------------------------------------------
DetectMB4CorEchoPlusorSDM
; Pre:
; Post: isMB4C, isEchoPlus, isSDMusic
; Z=1: no MB4C/EchoPlus/SD Music
; MB4C/Echo+ only has 1x 6522, but mapped to both $00 and $80
; . MB4C: assume it'll use the 6522's b7 addr to determine which AY8913 to write to
; . Echo+ uses 6522's PORTB (bits 4 & 3) to chip-select each AY8913
; . SD Music / SD Music Deluxe: like MB4C for selecting AY8913
lda #0
sta isMB4C
sta isEchoPlus
sta isSDMusic
ldy #SY6522_A_BASE+SY6522_DDRB
lda #$FF
sta (MBBase),y
iny ; Y=SY6522_DDRA
sta (MBBase),y
ldy #SY6522_B_BASE+SY6522_DDRB
lda #$69
sta (MBBase),y
lda #$96
iny ; Y=SY6522_DDRA
sta (MBBase),y
ldy #SY6522_A_BASE+SY6522_DDRB
@loop lda #$69
cmp (MBBase),y
bne @notDetected
lda #$96
iny ; Y=SY6522_DDRA
cmp (MBBase),y
bne @notDetected
cpy #SY6522_B_BASE+SY6522_DDRA
beq +
ldy #SY6522_B_BASE+SY6522_DDRB
bne @loop
+ ; MB4C is only in a //c, and Echo+ is never in a //c
jsr isIIc
bne @EchoPlusOrSDMusic
;@MB4C
lda #1
sta isMB4C
rts
@EchoPlusOrSDMusic
jsr IsEchoPlus ; post: isEchoPlus
lda #1 ; Z=0: detected something
bcc + ; C=0 => Echo+ detected
sta isSDMusic
+ rts
@notDetected
lda #0
rts
;------------------------------------------------------------------------------
Check6522
; Pre: X=slot#
; Post: C=0(OK), C=1(NG)
; errorActual, errorExpected
jsr SetMBBase
lda slotInfo,x
and #3 ; just 6522's
sta zpTmp1
; Temporarily set isMegaAudioCard for Check6522Addrlines()
jsr DetectMegaAudioCard ; Pre: zpTmp1; Post: isMegaAudioCard
lda #COMPONENT_6522+0 ; test component $10
sta testComponentNum
lda MBBaseL ; $00 = tests are for both 6522-A/B
jsr initSoakDisplayTest0
jsr incSoakDisplayTest
lda #0
sta errorValid
sta errorValid6522B
sta @errorFlag
@repeat jsr incSoakDisplayRept ; NB. "00:nn" - just inc's rept#nn
lda #$ff
sta testNum
; Test 6522-B first, then 6522-A
; . so that error codes are in the right order for printing!
;@6522_B
lda zpTmp1
and #HAS_6522B
beq @6522_A
lda #COMPONENT_6522B ; test component $60
sta testComponentNum
lda #SY6522_B_BASE
sta MBBaseL
@next inc testNum ; test #00,04
jsr Check6522Datalines1
bcs @error
inc testNum ; test #01,05
jsr Check6522Datalines2
bcs @error
inc testNum ; test #02,06
jsr Check6522Addrlines
bcs @error
inc testNum ; test #03,07
jsr Check6522IRQ
bcs @error
@6522_A lda zpTmp1
and #HAS_6522A
beq @done
lda MBBaseL
bpl @done
lda #$03
sta testNum
lda #COMPONENT_6522A ; test component $50
sta testComponentNum
lda #SY6522_A_BASE
sta MBBaseL
beq @next ; (bra)
;
@done lda #SY6522_A_BASE
sta MBBaseL
; if we've had an error from either 6522 then bail
lda @errorFlag
bne @errorDone
; else: no 6522 errors, so finish with this mixed test
lda #COMPONENT_6522+0 ; test component $10
sta testComponentNum
lda #$10
sta testNum ; test #$10 (mixed test for 6522 A & B)
jsr Check6522ABDatalines1 ; Pre: MBBaseL = 0
bcs @error
jsr incSoakTestNum
bne @repeat
clc ; C=0(OK)
rts
@error
; Pre: X = expected value
; A = actual value
; Post: C=1(NG)
inc @errorFlag
ldy MBBaseL
bpl +
; 6522-B failed, save error then test 6522-A
jsr SetError6522B ; for 6522-B
jmp @6522_A
+ jsr SetError ; for 6522-A
@errorDone
sec ; C=1(NG)
rts
@errorFlag !byte 0
;------------------
Check6522Datalines1
; Pre: MBBaseL
; Post: C=0(OK), C=1(NG)
; On C=1: X=expected, A=actual
; Uses: zpTmp2, zpTmp3
;
; Check r/w of all 8 data lines
;
; subTest:
; #0 #1 #2 #3
; 6522: DDRB = $55 $69 $AA $96
; 6522: DDRA = $AA $96 $55 $69
; check: DDRB == $55 $69 $AA $96
; check: DDRA == $AA $96 $55 $69
jsr resetSubTestMinus1
lda #0
sta zpTmp2
@loop jsr incSubTestNum ; subTest #0,2
ldy #SY6522_DDRB
lda #$55
eor zpTmp2
sta (MBBase),y
lda #$aa
eor zpTmp2
iny ; Y=SY6522_DDRA
sta (MBBase),y
dey ; Y=SY6522_DDRB
lda #$55
eor zpTmp2
jsr @check
bne @6522_err
lda #$aa
eor zpTmp2
iny ; Y=SY6522_DDRA
jsr @check
bne @6522_err
;
jsr incSubTestNum ; subTest #1,3
dey ; Y=SY6522_DDRB
lda #$69
eor zpTmp2
sta (MBBase),y
lda #$96
eor zpTmp2
iny ; Y=SY6522_DDRA
sta (MBBase),y
dey ; Y=SY6522_DDRB
lda #$69
eor zpTmp2
jsr @check
bne @6522_err
lda #$96
eor zpTmp2
iny ; Y=SY6522_DDRA
jsr @check
bne @6522_err
lda #$ff
eor zpTmp2
sta zpTmp2
bne @loop
clc ; OK
rts
@6522_err
; Pre: zpTmp3 = expected value
; A = actual value
; Post: C=1(NG)
ldx zpTmp3
sec
rts
;
@check
sta zpTmp3 ; expected
lda (MBBase),y ; actual
cmp zpTmp3
rts
;------------------
Check6522Datalines2
; Pre: MBBaseL
; Post: C=0(OK), C=1(NG)
; On C=1: X=expected, A=actual
; Uses: zpTmp2, zpTmp3
;
; Check r/w of all 8 data lines
;
; loop n = {0,1,...$ff}
; 6522: DDRB = n
; 6522: DDRA = ~n
; check: DDRB = n
; check: DDRA = ~n
;
jsr resetSubTest ; subTest #0
ldy #SY6522_DDRB
lda #0
sta zpTmp2
@6522_w lda zpTmp2
sta (MBBase),y
iny ; Y=SY6522_DDRA
eor #$ff
sta (MBBase),y
@6522_r dey ; Y=SY6522_DDRB
lda zpTmp2
jsr @check
bne @6522_err
iny ; Y=SY6522_DDRA
lda zpTmp2
eor #$ff
jsr @check
bne @6522_err
dey ; Y=SY6522_DDRB
@next inc zpTmp2
bne @6522_w
@6522_ok
clc
rts
@6522_err
; Pre: zpTmp3 = expected value
; A = actual value
; Post: C=1(NG)
ldx zpTmp3
sec
rts
;
@check
sta zpTmp3 ; expected
lda (MBBase),y ; actual
cmp zpTmp3
rts
;------------------
Check6522ABDatalines1
; Pre: zpTmp1 = slotInfo[slot]
; MBBaseL = 0
; Post: C=0(OK), C=1(NG)
; On C=1: X=expected, A=actual
; Uses: zpTmp2, zpTmp3
; Just return OK if same 6522 is mapped to both $00 and $80
jsr DetectMB4CorEchoPlusorSDM ; Pre: MBBaseL = 0
beq +
clc
rts
+
;
; Check r/w of all 8 data lines
; . NB. Check 6522-A interleaved with 6522-B (doesn't work with a single 6522 mapped at both $00 and $80)
; (NB. my real Phasor occasionally powers-on with r/w to 2nd 6522's DDRA with b7=1!)
;
; 1st loop 2nd loop
; 6522-A: DDRB = $55 $AA
; 6522-A: DDRA = $AA $55
; 6522-B: DDRB = $69 $96
; 6522-B: DDRA = $96 $69
; check A: DDRB == $55 $AA
; check A: DDRA == $AA $55
; check B: DDRB == $69 $96
; check B: DDRA == $96 $69
jsr resetSubTestMinus1
lda #0
sta zpTmp2
@loop
jsr incSubTestNum ; subTest #0,1 (for 1st/2nd loop)
;@6522_A_w
lda zpTmp1
and #HAS_6522A
beq @6522_B_w
ldy #SY6522_A_BASE+SY6522_DDRB
lda #$55
eor zpTmp2
sta (MBBase),y
lda #$aa
eor zpTmp2
iny ; Y=SY6522_DDRA
sta (MBBase),y
@6522_B_w
lda zpTmp1
and #HAS_6522B
beq @6522_A_r
ldy #SY6522_B_BASE+SY6522_DDRB
lda #$69
eor zpTmp2
sta (MBBase),y
lda #$96
eor zpTmp2
iny ; Y=SY6522_DDRA
sta (MBBase),y
@6522_A_r
lda zpTmp1
and #HAS_6522A
beq @6522_B_r
ldy #SY6522_A_BASE+SY6522_DDRB
lda #$55
eor zpTmp2
jsr @check
bne @6522_err
lda #$aa
eor zpTmp2
iny ; Y=SY6522_DDRA
jsr @check
bne @6522_err
@6522_B_r
lda zpTmp1
and #HAS_6522B
beq @next
ldy #SY6522_B_BASE+SY6522_DDRB
lda #$69
eor zpTmp2
jsr @check
bne @6522_err
lda #$96
eor zpTmp2
iny ; Y=SY6522_DDRA
jsr @check
bne @6522_err
@next
lda #$ff
eor zpTmp2
sta zpTmp2
bne @loop
;@6522_ok
clc
rts
@6522_err
; Pre: zpTmp3 = expected value
; A = actual value
; Post: C=1(NG)
ldx zpTmp3
sec
rts
;
@check
sta zpTmp3 ; expected
lda (MBBase),y ; actual
cmp zpTmp3
rts
;------------------
Check6522Addrlines
; Pre: MBBaseL
; Post: C=0(OK), C=1(NG)
; On C=1: X=expected, A=actual
jsr resetSubTest ; subTest #0
cli ; No ints generated by this routine, so safe to enable ints
; Since IRQ/NMI handler hasn't been setup yet, then any spurious ints will exit to Monitor
; write
lda #$AA
ldy #SY6522_DDRA ; %0011 (a0)
sta (MBBase),y
lda #$55
ldy #SY6522_DDRB ; %0010 (a1)
sta (MBBase),y
lda #$69
ldy #SY6522_TIMER1H_LATCH ; %0111 (a2)
sta (MBBase),y
lda #IER_SET|IxR_TIMER1|IxR_TIMER2 ; $E0
ldy #SY6522_IFR
sta (MBBase),y ; Clear any pending T1|T2 ints (just in case)
ldy #SY6522_IER ; %1110 (a3)
sta (MBBase),y ; NB. Writing IER with b7=1 will set the bits=1
eor #$ff
sta (MBBase),y ; NB. Writing IER with b7=0 will clear the bits=1
; read
lda #$AA
ldy #SY6522_DDRA ; %0011 (a0)
jsr @check
bne @6522_err
lda #$55
ldy #SY6522_DDRB ; %0010 (a1)
jsr @check
bne @6522_err
lda #$69
ldy #SY6522_TIMER1H_LATCH ; %0111 (a2)
jsr @check
bne @6522_err
lda isMegaAudioCard
beq +
lda #IER_CLR|IxR_TIMER1|IxR_TIMER2 ; $60 - MegaAudio always returns 6522.IER.b7=0
bne ++
+ lda #IER_SET|IxR_TIMER1|IxR_TIMER2 ; $E0 - Real 6522 always returns 6522.IER.b7=1
++ ldy #SY6522_IER ; %1110 (a3)
jsr @check
bne @6522_err
lda #$7f
sta (MBBase),y ; IER=0
;@6522_ok
clc
rts
@6522_err
; Pre: zpTmp3 = expected value
; A = actual value
; Post: C=1(NG)
ldx zpTmp3
sec
rts
;
@check
sta zpTmp3 ; expected
lda (MBBase),y ; actual
cmp zpTmp3
rts
;------------------
Check6522IRQ
; Pre: MBBaseL
; Post: C=0(OK), C=1(NG)
; On C=1: X=expected, A=actual
;
; Check interrupt line(s)
;
jsr resetSubTest
sei
lda #<Check6522ISR
ldx #>Check6522ISR
jsr SetIrqNmiVectors
lda #0
sta isrNMIcount
sta isrIFR_A
sta isrIFR_B
lda #1
ldy #SY6522_TIMER1L_COUNTER
sta (MBBase),y
iny ; Y=SY6522_TIMER1H_COUNTER
sta (MBBase),y ; T1C=0x0101
lda #ACR_ONESHOT
ldy #SY6522_ACR
sta (MBBase),y
lda #IER_SET|IxR_TIMER1
ldy #SY6522_IER
sta (MBBase),y
lda #$f ; wait 0x304 cycles (and NMI may have occurred)
jsr myWAIT
lda MBBaseL
bmi @6522B
;@6522A
lda isrNMIcount
sta isrNMIcount_A
bne + ; NMI occurred, so IFR.TIMER1 already cleared!
ldy #SY6522_IFR ; subTest #0
lda #IxR_TIMER1
and (MBBase),y
beq @6522_err
cli
sei
jsr incSubTestNum ; subTest #1
and isrIFR_A
beq @6522_err
bne + ; (bra)
@6522B
lda isrNMIcount
sta isrNMIcount_B
bne + ; NMI occurred, so IFR.TIMER1 already cleared!
ldy #SY6522_IFR ; subTest #0
lda #IxR_TIMER1
and (MBBase),y
beq @6522_err
cli
sei
jsr incSubTestNum ; subTest #1
and isrIFR_B
beq @6522_err
+
;@6522_ok
clc
rts
@6522_err
ldx #IxR_TIMER1 ; expected
lda #0 ; actual
sec
rts
;------------------------------------------------------------------------------
Check6522ISR
; Pre:
; 6502 has pushed P
; Apple ROM has stored A to $45 (not Apple //e ROM!)
;
lda zpTmp2
sta isrCopyA
txa
pha
tya
pha
;------
; Cope with the case where a single 6522 is mapped to both $00 and $80
; . read IFR from both A & B, *before* clearing IFR
; . otherwise reading & clear A first, means that B (read second) will always reads as 0.
; NB. Needed for Check6522IRQ, eg. for EchoPlus
ldx MBBaseL ; save MBBaseL
lda #SY6522_A_BASE
sta MBBaseL
ldy #SY6522_A_BASE+SY6522_IFR
lda (MBBase),y
sta isrIFR_A
ldy #SY6522_B_BASE+SY6522_IFR
lda (MBBase),y
sta isrIFR_B
sta (MBBase),y ; clear 6522_B's IFR
ldy #SY6522_A_BASE+SY6522_IFR
lda isrIFR_A
sta (MBBase),y ; clear 6522_A's IFR
stx MBBaseL ; restore MBBaseL
;------
pla
tay
pla
tax
lda $45 ; for Apple II/II+
rti
;------------------------------------------------------------------------------
; Notes:
; . [T6522_0] Check inactive T1+T2 counters don't set IFR bits on underflow
; T1:
; . [T6522_1, T6522_2] oneshot|continuous x IRQ|poll
; . [T6522_3, T6522_5] 6502|65C02 addr modes access of 6522 T1C
; . [T6522_7, T6522_9, T6522_A, T6522_C] oneshot|continuous underflow, then T1L -> T1C
; . [T6522_B] T1L=$0000, can only read T1C values of $00 and $FF
; . [T6522_A, T6522_E] 6522 T1 period is N+2 cycles
; . [T6522_F] Alt test that 6522 T1 period is N+2 cycles
; . [T6522_15] T1 int cleared/not cleared by certain register r/w's
; T2:
; . [T6522_2] oneshot x IRQ|poll
; . [T6522_4, T6522_6] 6502|65C02 addr modes access of 6522 T2C
; . [T6522_8, T6522_9, T6522_D] oneshot underflow, then T1L -> T1C
; [T6522_10, T6522_11] Test sub-opcode accuracy for reading IFR
; [T6522_12] Test 6522s at $Cn10 and $Cn90
; [T6522_13] Test Phasor can switch to Echo+
; [T6522_14] Both 6522s: test T1 & T2 (from chips A&B) all running at the same time
; [T6522_16] Check T1 & T2 ints occur the correct number of times over a longer interval
; [T6522_17] Check T1 int re-triggers every few opcodes when T1L=$0000
; [T6522_18] Calls MCT6522_1, except for 1 card (so uses 6522 A & B)
; [Test6522MultiCard] 2 cards:
; . [MCT6522_0] Both 6522s: test T1 & T2 (from chips A&B) all running at the same time
; . [MCT6522_1] 2 timers: 1 high-freq (no IRQ), 1 low-freq (IRQ). Check high-freq doesn't mask IRQ
; [Test6522AfterReset] 6522 IRQ pending, CTRL+RESET should clear it
;
Test6522
; Pre: has6522
; Post: C=0(OK), C=1(NG)
; MBBaseL = $00
; errorActual, errorExpected
; Uses: zpTmp1 (so don't use in sub-funcs)
sei
lda isMegaAudioCard
bne +
lda #<testTbl
ldx #>testTbl
bne ++
+ lda #<testTbl_MegaAudio
ldx #>testTbl_MegaAudio
++ sta @testTblX1+1
sta @testTblX2+1
stx @testTblX1+2
stx @testTblX2+2
lda #<Test6522ISR
ldx #>Test6522ISR
jsr SetIrqNmiVectors
lda #COMPONENT_6522+1 ; test component $11
sta testComponentNum
lda #$ff
sta testNum ; test #$00
lda has6522
lsr
sta zpTmp1
bcc @next6522
@loop lda #0
sta testTblIdx
lda MBBaseL
jsr initSoakDisplayTest0
@nextTest jsr incSoakDisplayTest
ldx testTblIdx
@testTblX1 lda testTbl,x ; smc
sta @jmpTest+1
inx
@testTblX2 lda testTbl,x ; smc
sta @jmpTest+2
inx
stx testTblIdx
ora @jmpTest+1
beq @done
inc testNum
@repeat jsr incSoakDisplayRept
@jmpTest jsr $0000
bcs @error
jsr incSoakTestNum
bne @repeat
jmp @nextTest
@done jsr WaitT1OneShotUnderflow ; clear & disable any T1 ints
jsr WaitT2OneShotUnderflow ; clear & disable any T2 ints
@next6522
lda MBBaseL
eor #$80
sta MBBaseL
lda #$1f
sta testNum ; test #$20
lsr zpTmp1
bcs @loop
lda #0
sta MBBaseL
clc ; C=0(OK)
rts
@error
Test6522Error
; Pre: zpTmp2 = expected value
; A = actual value
; Post: C=1(NG)
ldx zpTmp2
jsr SetError
lda #SY6522_A_BASE
sta MBBaseL
sec ; C=1(NG)
rts
;
testTblIdx
!byte 0
testTbl
; MBBaseL = $00 and $80
!word T6522_0 ; 20
!word T6522_1 ; 21
!word T6522_2 ; 22
!word T6522_3 ; 23
!word T6522_4 ; 24
!word T6522_5 ; 25
!word T6522_6 ; 26
!word T6522_7 ; 27
!word T6522_8 ; 28
!word T6522_9 ; 29
!word T6522_A ; 2A
!word T6522_B ; 2B
!word T6522_C ; 2C
!word T6522_D ; 2D
!word T6522_E ; 2E
!word T6522_F ; 2F
!word T6522_10 ; 30
!word T6522_11 ; 31
!word T6522_12 ; 32
!word T6522_13 ; 33
!word T6522_14 ; 34
!word T6522_15 ; 35