diff --git a/.github/workflows/python-package.yml b/.github/workflows/python-package.yml index 24255b1..c6077cf 100644 --- a/.github/workflows/python-package.yml +++ b/.github/workflows/python-package.yml @@ -52,6 +52,7 @@ jobs: pip install -U git+https://github.com/tancheng/pymtl3.1@yo-struct-list-fix pip install hypothesis pip install pytest + pip install py-markdown-table pip list - name: Test and translate with pytest diff --git a/cgra/CGRAKingMeshRTL.py b/cgra/CGRAKingMeshRTL.py index e9e37b0..70cac58 100644 --- a/cgra/CGRAKingMeshRTL.py +++ b/cgra/CGRAKingMeshRTL.py @@ -150,10 +150,23 @@ def construct( s, DataType, PredicateType, CtrlType, width, height, s.tile[i].to_mem_wdata.rdy //= 0 # Line trace - def line_trace( s ): - # str = "||".join([ x.element.line_trace() for x in s.tile ]) - # str += " :: [" + s.data_mem.line_trace() + "]" - res = "||\n".join([ (("[tile"+str(i)+"]: ") + x.line_trace() + x.ctrl_mem.line_trace()) - for (i,x) in enumerate(s.tile) ]) - res += "\n :: [" + s.data_mem.line_trace() + "] \n" + def line_trace(s, verbosity = 0): + if verbosity == 0: + # str = "||".join([ x.element.line_trace() for x in s.tile ]) + # str += " :: [" + s.data_mem.line_trace() + "]" + res = "||\n".join([(("[tile" + str(i) + "]: ") + x.line_trace() + x.ctrl_mem.line_trace()) + for (i, x) in enumerate(s.tile)]) + res += "\n :: [" + s.data_mem.line_trace() + "] \n" + return res + else: + return s.verbose_trace(verbosity) + + # verbose trace + def verbose_trace(s, verbosity = 1): + res = '' + for (i, x) in enumerate(s.tile): + res += "# [tile" + str(i) + "]: " + x.verbose_trace(verbosity = verbosity) + x.ctrl_mem.verbose_trace( + verbosity = verbosity) + '\n' + res += f"data_mem: {s.data_mem.verbose_trace(verbosity = verbosity)}" + res += "------\n\n" return res diff --git a/cgra/CgraCrossbarDataMemRingCtrlMemRTL.py b/cgra/CgraCrossbarDataMemRingCtrlMemRTL.py index ab7df25..5e0cb06 100644 --- a/cgra/CgraCrossbarDataMemRingCtrlMemRTL.py +++ b/cgra/CgraCrossbarDataMemRingCtrlMemRTL.py @@ -183,11 +183,24 @@ def construct(s, DataType, PredicateType, CtrlPktType, CtrlSignalType, s.tile[i].to_mem_wdata.rdy //= 0 # Line trace - def line_trace( s ): - # str = "||".join([ x.element.line_trace() for x in s.tile ]) - # str += " :: [" + s.data_mem.line_trace() + "]" - res = "||\n".join([ (("[tile"+str(i)+"]: ") + x.line_trace() + x.ctrl_mem.line_trace()) - for (i,x) in enumerate(s.tile) ]) - res += "\n :: [" + s.data_mem.line_trace() + "] \n" + def line_trace(s, verbosity = 0): + if verbosity == 0: + # str = "||".join([ x.element.line_trace() for x in s.tile ]) + # str += " :: [" + s.data_mem.line_trace() + "]" + res = "||\n".join([ (("[tile"+str(i)+"]: ") + x.line_trace() + x.ctrl_mem.line_trace()) + for (i,x) in enumerate(s.tile) ]) + res += "\n :: [" + s.data_mem.line_trace() + "] \n" + return res + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace(self, verbosity = 1): + res = '' + for (i, x) in enumerate(self.tile): + res += "# [tile" + str(i) + "]: " + x.verbose_trace(verbosity = verbosity) + x.ctrl_mem.verbose_trace(verbosity = verbosity) + '\n' + # todo + # no verbose_trace for DataMemWithCrossbarRTL yet + res += f"data_mem: {self.data_mem.line_trace()}" + res += "------\n\n" return res - diff --git a/cgra/translate/VectorCGRAKingMeshRTL_test.py b/cgra/translate/VectorCGRAKingMeshRTL_test.py index f6826de..b87a2bd 100644 --- a/cgra/translate/VectorCGRAKingMeshRTL_test.py +++ b/cgra/translate/VectorCGRAKingMeshRTL_test.py @@ -131,6 +131,7 @@ def test_homo_4x4( cmdline_opts ): else: print( f' - set tile[{idx}] to scalar') th.set_param( f'top.dut.tile[{idx}].construct', FuList=scalar_list ) + th.set_param('top.dut.line_trace', verbosity = 1) th.elaborate() th.dut.set_metadata( VerilogTranslationPass.explicit_module_name, diff --git a/fu/flexible/FlexibleFuRTL.py b/fu/flexible/FlexibleFuRTL.py index 2fdbadd..e1464d5 100644 --- a/fu/flexible/FlexibleFuRTL.py +++ b/fu/flexible/FlexibleFuRTL.py @@ -8,10 +8,8 @@ Date : Dec 24, 2019 """ +from py_markdown_table.markdown_table import markdown_table -from pymtl3 import * -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.AdderRTL import AdderRTL from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * @@ -111,11 +109,50 @@ def comb_logic(): s.fu_recv_in_rdy_vector[port][i] @= s.fu[i].recv_in[port].rdy s.recv_in[port].rdy @= reduce_or( s.fu_recv_in_rdy_vector[port] ) - def line_trace( s ): - opt_str = " #" - if s.recv_opt.en: - opt_str = OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl] - out_str = ",".join([str(x.msg) for x in s.send_out]) - recv_str = ",".join([str(x.msg) for x in s.recv_in]) - return f'[recv: {recv_str}] {opt_str}(P{s.recv_opt.msg.predicate}) (const: {s.recv_const.msg}, en: {s.recv_const.en}) ] = [out: {out_str}] (recv_opt.rdy: {s.recv_opt.rdy}, recv_in[0].rdy: {s.recv_in[0].rdy}, recv_in[1].rdy: {s.recv_in[1].rdy}, recv_predicate.msg: {s.recv_predicate.msg}, {OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl]}, recv_opt.en: {s.recv_opt.en}, send[0].en: {s.send_out[0].en}) ' - + def line_trace(s, verbosity = 0): + if verbosity == 0: + opt_str = " #" + if s.recv_opt.en: + opt_str = OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl] + out_str = ",".join([str(x.msg) for x in s.send_out]) + recv_str = ",".join([str(x.msg) for x in s.recv_in]) + return f'[recv: {recv_str}] {opt_str}(P{s.recv_opt.msg.predicate}) (const: {s.recv_const.msg}, en: {s.recv_const.en}) ] = [out: {out_str}] (recv_opt.rdy: {s.recv_opt.rdy}, recv_in[0].rdy: {s.recv_in[0].rdy}, recv_in[1].rdy: {s.recv_in[1].rdy}, recv_predicate.msg: {s.recv_predicate.msg}, {OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl]}, recv_opt.en: {s.recv_opt.en}, send[0].en: {s.send_out[0].en}) ' + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace_md_formatter(self, data_type, data): + assert data_type in [ "recv", "send" ] + data_list = [ x for x in data ] + result_list = [] + for idx, fu_data in enumerate(data_list): + msg_dict = fu_data.msg.__dict__ + if data_type is "recv": + fu_port_dict = { "fu_inport_idx": idx, "rdy": fu_data.rdy } + else: + fu_port_dict = { "fu_outport_idx": idx, "en": fu_data.en } + fu_port_dict.update(msg_dict) + result_list.append(fu_port_dict) + result_md = markdown_table(result_list).set_params(quote = False).get_markdown() + return result_md + + # verbose trace if verbosity > 0 + def verbose_trace(s, verbosity = 1): + # for clk n + # recv: + # 1. OPT: opt+rdy(if ready to receive opt) + # 2. Data: [rdy(if ready to receive data) and msg(data) for each inport(total 4 for now)] + # out: [en(if data is sent out) and msg for each outport(total 2 for now)] + opt_ctrl = OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl] + opt_rdy = s.recv_opt.rdy + recv_md = s.verbose_trace_md_formatter("recv", s.recv_in) + send_md = s.verbose_trace_md_formatter("send", s.send_out) + + return (f'## class: {s.__class__.__name__}\n' + f'- FU recv:\n' + f' FU opt: {opt_ctrl}, opt_rdy: {opt_rdy}\n' + f' FU data:' + f'{recv_md}\n' + f'===>\n' + f'- FU out:' + f'{send_md}') diff --git a/lib/util/common.py b/lib/util/common.py index b26bfa3..26af6ab 100644 --- a/lib/util/common.py +++ b/lib/util/common.py @@ -21,3 +21,25 @@ LINK_NO_MEM = 0 LINK_FROM_MEM = 1 LINK_TO_MEM = 2 + +TILE_PORT_DIRECTION_DICT_DESC = { + PORT_NORTH: "NORTH", + PORT_SOUTH: "SOUTH", + PORT_WEST: "WEST", + PORT_EAST: "EAST", + PORT_NORTHWEST: "NORTHWEST", + PORT_NORTHEAST: "NORTHEAST", + PORT_SOUTHEAST: "SOUTHEAST", + PORT_SOUTHWEST: "SOUTHWEST" +} + +TILE_PORT_DIRECTION_DICT_SHORT_DESC = { + PORT_NORTH: "N", + PORT_SOUTH: "S", + PORT_WEST: "W", + PORT_EAST: "E", + PORT_NORTHWEST: "NW", + PORT_NORTHEAST: "NE", + PORT_SOUTHEAST: "SE", + PORT_SOUTHWEST: "SW" +} diff --git a/mem/ctrl/CtrlMemDynamicRTL.py b/mem/ctrl/CtrlMemDynamicRTL.py index 9a96fa1..65c98f2 100644 --- a/mem/ctrl/CtrlMemDynamicRTL.py +++ b/mem/ctrl/CtrlMemDynamicRTL.py @@ -8,14 +8,16 @@ Author : Cheng Tan Date : Dec 20, 2024 """ - -from pymtl3 import * +from py_markdown_table.markdown_table import markdown_table from pymtl3.stdlib.primitive import RegisterFile + from ...lib.basic.en_rdy.ifcs import SendIfcRTL from ...lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL from ...lib.basic.val_rdy.queues import NormalQueueRTL from ...lib.cmd_type import * from ...lib.opt_type import * +from ...lib.util.common import TILE_PORT_DIRECTION_DICT_SHORT_DESC + class CtrlMemDynamicRTL(Component): @@ -136,7 +138,126 @@ def update_raddr(): else: s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + CtrlAddrType(1) - def line_trace(s): - config_mem_str = "|".join([str(data) for data in s.reg_file.regs]) - return f'{s.recv_pkt.msg} || config_mem: [{config_mem_str}] || out: {s.send_ctrl.msg}' + def line_trace(s, verbosity = 0): + if verbosity == 0: + config_mem_str = "|".join([str(data) for data in s.reg_file.regs]) + return f'{s.recv_pkt.msg} || config_mem: [{config_mem_str}] || out: {s.send_ctrl.msg}' + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace_normal_processor(self, data_dict): + if 'ctrl_operation' in data_dict: + data_dict['ctrl_operation'] = OPT_SYMBOL_DICT[ data_dict['ctrl_operation'] ] + if 'ctrl' in data_dict: + data_dict['ctrl'] = OPT_SYMBOL_DICT[ data_dict['ctrl'] ] + + def verbose_trace_fu_in_processor(self, data_dict, sub_header, key_prefix = None): + fu_in_key = 'fu_in' + if key_prefix: + fu_in_key = key_prefix + fu_in_key + data_dict[fu_in_key] = [ int(fi) for fi in data_dict[fu_in_key] ] + fu_in_header = [] + for idx, val in enumerate(data_dict[fu_in_key]): + fu_in_header.append(idx) + fu_in_header_str = "|".join([ f"{hd : ^3}" for hd in fu_in_header ]) + data_dict[fu_in_key] = "|".join([ f"{v : ^3}" for v in data_dict[fu_in_key] ]) + sub_header[fu_in_key] = fu_in_header_str + + # outport: fu_xbar_outport, routing_xbar_outport + def verbose_trace_outport_processor(self, data_dict, sub_header, num_direction_ports, outport_key, key_prefix = None): + if key_prefix: + outport_key = key_prefix + outport_key + if outport_key in data_dict: + data_dict[outport_key] = [ int(op) for op in data_dict[outport_key] ] + fu_reg_num = 1 + outport_sub_header = [] + for idx, val in enumerate(data_dict[outport_key]): + # to directions + if idx <= num_direction_ports - 1: + hd = TILE_PORT_DIRECTION_DICT_SHORT_DESC[idx] + outport_sub_header.append(f"{hd : ^{len(hd) + 2}}") + data_dict[outport_key][idx] = f"{TILE_PORT_DIRECTION_DICT_SHORT_DESC[val - 1] if val != 0 else '-' : ^{len(hd) + 2}}" + # to fu regs + else: + hd = f"fu_reg_{fu_reg_num}" + outport_sub_header.append(f"{hd : ^{len(hd)}}") + data_dict[outport_key][idx] = f"{TILE_PORT_DIRECTION_DICT_SHORT_DESC[val - 1] if val != 0 else '-' : ^{len(hd)}}" + fu_reg_num += 1 + outport_sub_header_str = "|".join([ hd for hd in outport_sub_header ]) + data_dict[outport_key] = "|".join([ v for v in data_dict[outport_key] ]) + sub_header[outport_key] = outport_sub_header_str + + def verbose_trace_predicate_in_processor(self, data_dict, sub_header, num_direction_ports, key_prefix = None): + predicate_in_key = 'routing_predicate_in' + if key_prefix: + predicate_in_key = key_prefix + predicate_in_key + if predicate_in_key in data_dict: + data_dict[predicate_in_key] = [ int(pi) for pi in data_dict[predicate_in_key] ] + fu_out_num = 1 + predicate_in_sub_header = [] + for idx, val in enumerate(data_dict[predicate_in_key]): + # from directions + if idx <= num_direction_ports - 1: + hd = TILE_PORT_DIRECTION_DICT_SHORT_DESC[idx] + predicate_in_sub_header.append(f"{hd : ^{len(hd) + 2}}") + data_dict[predicate_in_key][idx] = f"{val : ^{len(hd) + 2}}" + # from fu + else: + hd = f"fu_out_{fu_out_num}" + predicate_in_sub_header.append(f"{hd : ^{len(hd)}}") + data_dict[predicate_in_key][idx] = f"{val : ^{len(hd)}}" + fu_out_num += 1 + predicate_in_sub_header_str = "|".join([ hd for hd in predicate_in_sub_header ]) + data_dict[predicate_in_key] = "|".join([ v for v in data_dict[predicate_in_key] ]) + sub_header[predicate_in_key] = predicate_in_sub_header_str + + def verbose_trace_data_processor(self, data_dict, num_direction_ports, key_prefix = None): + sub_header = {} + for key in data_dict.keys(): + sub_header[key] = '' + self.verbose_trace_normal_processor(data_dict) + self.verbose_trace_fu_in_processor(data_dict, sub_header, key_prefix) + self.verbose_trace_outport_processor(data_dict, sub_header, num_direction_ports, 'fu_xbar_outport', key_prefix) + self.verbose_trace_outport_processor(data_dict, sub_header, num_direction_ports, 'routing_xbar_outport', key_prefix) + self.verbose_trace_predicate_in_processor(data_dict, sub_header, num_direction_ports, key_prefix) + return sub_header + + # verbose trace + def verbose_trace(s, verbosity = 1): + num_routing_outports = len(s.reg_file.wdata[0].routing_xbar_outport) + num_fu_inports = len(s.reg_file.wdata[0].fu_in) + num_tile_outports = num_routing_outports - num_fu_inports + + # recv_ctrl + recv_pkt_msg_dict = dict(s.recv_pkt.msg.__dict__) + recv_pkt_msg_header = s.verbose_trace_data_processor(recv_pkt_msg_dict, num_tile_outports, key_prefix = 'ctrl_') + recv_pkt_msg_list = [recv_pkt_msg_header, recv_pkt_msg_dict] + recv_pkt_msg_md = markdown_table(recv_pkt_msg_list).set_params(quote = False).get_markdown() + + # send_ctrl + send_ctrl_msg_dict = dict(s.send_ctrl.msg.__dict__) + send_ctrl_sub_header = s.verbose_trace_data_processor(send_ctrl_msg_dict, num_tile_outports) + send_ctrl_msg_list = [send_ctrl_sub_header, send_ctrl_msg_dict] + send_ctrl_msg_md = markdown_table(send_ctrl_msg_list).set_params(quote = False).get_markdown() + if verbosity == 1: + return (f'\n## class: {s.__class__.__name__}\n' + f'- recv_pkt_msg:' + f'{recv_pkt_msg_md}\n\n' + f'- send_ctrl_msg:' + f'{send_ctrl_msg_md}\n\n') + else: + # reg + reg_dicts = [ dict(data.__dict__) for data in s.reg_file.regs ] + reg_sub_header = {} + for reg_dict in reg_dicts: + reg_sub_header = s.verbose_trace_data_processor(reg_dict, num_tile_outports) + reg_dicts.insert(0, reg_sub_header) + reg_md = markdown_table(reg_dicts).set_params(quote=False).get_markdown() + return (f'\n## class: {s.__class__.__name__}\n' + f'- recv_pkt_msg:' + f'{recv_pkt_msg_md}\n\n' + f'- send_ctrl_msg:' + f'{send_ctrl_msg_md}\n\n' + f'- config_memory: {reg_md}\n') \ No newline at end of file diff --git a/mem/ctrl/CtrlMemRTL.py b/mem/ctrl/CtrlMemRTL.py index 644882f..e50ff3d 100644 --- a/mem/ctrl/CtrlMemRTL.py +++ b/mem/ctrl/CtrlMemRTL.py @@ -7,12 +7,12 @@ Author : Cheng Tan Date : Dec 21, 2019 """ - - -from pymtl3 import * +from py_markdown_table.markdown_table import markdown_table from pymtl3.stdlib.primitive import RegisterFile + from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * +from ...lib.util.common import TILE_PORT_DIRECTION_DICT_SHORT_DESC class CtrlMemRTL( Component ): @@ -72,7 +72,122 @@ def update_raddr(): else: s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 ) - def line_trace( s ): - out_str = "||".join([ str(data) for data in s.reg_file.regs ]) - return f'{s.recv_ctrl.msg} : [{out_str}] : {s.send_ctrl.msg}' + def line_trace(s, verbosity = 0): + if verbosity == 0: + out_str = "||".join([str(data) for data in s.reg_file.regs]) + return f'{s.recv_ctrl.msg} : [{out_str}] : {s.send_ctrl.msg}' + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace_normal_processor(self, data_dict): + data_dict['ctrl'] = OPT_SYMBOL_DICT[ data_dict['ctrl'] ] + if 'predicate' in data_dict: + data_dict['predicate'] = int(data_dict['predicate']) + if 'routing_xbar_outport' in data_dict: + data_dict['routing_xbar_outport'] = [ int(rxop) for rxop in data_dict['routing_xbar_outport'] ] + if 'fu_xbar_outport' in data_dict: + data_dict['fu_xbar_outport'] = [ int(fxop) for fxop in data_dict['fu_xbar_outport'] ] + if 'routing_predicate_in' in data_dict: + data_dict['routing_predicate_in'] = [ int(rpi) for rpi in data_dict['routing_predicate_in'] ] + + def verbose_trace_fu_in_processor(self, data_dict, sub_header): + data_dict['fu_in'] = [ int(fi) for fi in data_dict['fu_in'] ] + fu_in_header = [] + for idx, val in enumerate(data_dict['fu_in']): + fu_in_header.append(idx) + fu_in_header_str = "|".join([ f"{hd : ^3}" for hd in fu_in_header ]) + data_dict['fu_in'] = "|".join([ f"{v : ^3}" for v in data_dict['fu_in'] ]) + sub_header['fu_in'] = fu_in_header_str + + def verbose_trace_outport_processor(self, data_dict, sub_header, num_direction_ports): + if 'outport' in data_dict: + data_dict['outport'] = [ int(op) for op in data_dict['outport'] ] + fu_reg_num = 1 + outport_sub_header = [] + for idx, val in enumerate(data_dict['outport']): + # to directions + if idx <= num_direction_ports - 1: + hd = TILE_PORT_DIRECTION_DICT_SHORT_DESC[idx] + outport_sub_header.append(f"{hd : ^{len(hd) + 2}}") + data_dict['outport'][idx] = f"{TILE_PORT_DIRECTION_DICT_SHORT_DESC[val - 1] if val != 0 else '-' : ^{len(hd) + 2}}" + # to fu regs + else: + hd = f"fu_reg_{fu_reg_num}" + outport_sub_header.append(f"{hd : ^{len(hd)}}") + data_dict['outport'][idx] = f"{TILE_PORT_DIRECTION_DICT_SHORT_DESC[val - 1] if val != 0 else '-' : ^{len(hd)}}" + fu_reg_num += 1 + outport_sub_header_str = "|".join([ hd for hd in outport_sub_header ]) + data_dict['outport'] = "|".join([ v for v in data_dict['outport'] ]) + sub_header['outport'] = outport_sub_header_str + + def verbose_trace_predicate_in_processor(self, data_dict, sub_header, num_direction_ports): + if 'predicate_in' in data_dict: + data_dict['predicate_in'] = [ int(pi) for pi in data_dict['predicate_in'] ] + fu_out_num = 1 + predicate_in_sub_header = [] + for idx, val in enumerate(data_dict['predicate_in']): + # from directions + if idx <= num_direction_ports - 1: + hd = TILE_PORT_DIRECTION_DICT_SHORT_DESC[idx] + predicate_in_sub_header.append(f"{hd : ^{len(hd) + 2}}") + data_dict['predicate_in'][idx] = f"{val : ^{len(hd) + 2}}" + # from fu + else: + hd = f"fu_out_{fu_out_num}" + predicate_in_sub_header.append(f"{hd : ^{len(hd)}}") + data_dict['predicate_in'][idx] = f"{val : ^{len(hd)}}" + fu_out_num += 1 + predicate_in_sub_header_str = "|".join([ hd for hd in predicate_in_sub_header ]) + data_dict['predicate_in'] = "|".join([ v for v in data_dict['predicate_in'] ]) + sub_header['predicate_in'] = predicate_in_sub_header_str + + def verbose_trace_data_processor(self, data_dict, num_direction_ports): + sub_header = {} + for key in data_dict.keys(): + sub_header[key] = '' + self.verbose_trace_normal_processor(data_dict) + self.verbose_trace_fu_in_processor(data_dict, sub_header) + self.verbose_trace_outport_processor(data_dict, sub_header, num_direction_ports) + self.verbose_trace_predicate_in_processor(data_dict, sub_header, num_direction_ports) + return sub_header + + # verbose trace + def verbose_trace(s, verbosity = 1): + num_fu_in = len(s.reg_file.regs[0].fu_in) + # num_inports = len(s.reg_file.regs[0].predicate_in) + num_outports = len(s.reg_file.regs[0].outport if hasattr(s.reg_file.regs[0], 'outport') else []) + num_direction_ports = num_outports - num_fu_in + + # recv_ctrl + recv_ctrl_msg_dict = dict(s.recv_ctrl.msg.__dict__) + recv_ctrl_sub_header = s.verbose_trace_data_processor(recv_ctrl_msg_dict, num_direction_ports) + recv_ctrl_msg_list = [recv_ctrl_sub_header, recv_ctrl_msg_dict] + recv_ctrl_md = markdown_table(recv_ctrl_msg_list).set_params(quote=False).get_markdown() + + # send_ctrl + send_ctrl_msg_dict = dict(s.send_ctrl.msg.__dict__) + send_ctrl_sub_header = s.verbose_trace_data_processor(send_ctrl_msg_dict, num_direction_ports) + send_ctrl_msg_list = [send_ctrl_sub_header, send_ctrl_msg_dict] + send_ctrl_md = markdown_table(send_ctrl_msg_list).set_params(quote=False).get_markdown() + if verbosity == 1: + return (f'\n## class: {s.__class__.__name__}\n' + f'- recv_ctrl_msg:' + f'{recv_ctrl_md}\n\n' + f'- send_ctrl_msg:' + f'{send_ctrl_md}\n\n') + else: + # reg + reg_dicts = [ dict(data.__dict__) for data in s.reg_file.regs ] + reg_sub_header = {} + for reg_dict in reg_dicts: + reg_sub_header = s.verbose_trace_data_processor(reg_dict, num_direction_ports) + reg_dicts.insert(0, reg_sub_header) + reg_md = markdown_table(reg_dicts).set_params(quote=False).get_markdown() + return (f'\n## class: {s.__class__.__name__}\n' + f'- recv_ctrl_msg:' + f'{recv_ctrl_md}\n\n' + f'- send_ctrl_msg:' + f'{send_ctrl_md}\n\n' + f'- ctrl_memory: {reg_md}\n') \ No newline at end of file diff --git a/mem/data/DataMemRTL.py b/mem/data/DataMemRTL.py index ac7bda0..d4366ad 100644 --- a/mem/data/DataMemRTL.py +++ b/mem/data/DataMemRTL.py @@ -7,10 +7,9 @@ Author : Cheng Tan Date : Dec 20, 2019 """ - - from pymtl3 import * from pymtl3.stdlib.primitive import RegisterFile +from py_markdown_table.markdown_table import markdown_table from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * @@ -98,15 +97,59 @@ def update_signal(): s.recv_waddr[i].rdy @= Bits1( 1 ) s.recv_wdata[i].rdy @= Bits1( 1 ) - def line_trace(s): - recv_raddr_str = "recv_read_addr: " + "|".join([str(data.msg) for data in s.recv_raddr]) - recv_waddr_str = "recv_write_addr: " + "|".join([str(data.msg) for data in s.recv_waddr]) - recv_wdata_str = "recv_write_data: " + "|".join([str(data.msg) for data in s.recv_wdata]) - content_str = "content: " + "|".join([str(data) for data in s.reg_file.regs]) - send_rdata_str = "send_read_data: " + "|".join([str(data.msg) for data in s.send_rdata]) - return f'{recv_raddr_str} || {recv_waddr_str} || {recv_wdata_str} || [{content_str}] || {send_rdata_str}' - # return f'DataMem: {recv_str} : [{out_str}] : {send_str} initWrites: {s.initWrites}' - # return s.reg_file.line_trace() - # return f'<{s.reg_file.wen[0]}>{s.reg_file.waddr[0]}:{s.reg_file.wdata[0]}|{s.reg_file.raddr[0]}:{s.reg_file.rdata[0]}' - # rf_trace = f'<{s.reg_file.wen[0]}>{s.reg_file.waddr[0]}:{s.reg_file.wdata[0]}|{s.reg_file.raddr[0]}:{s.reg_file.rdata[0]}' - # return f'[{s.recv_wdata[0].en & s.recv_waddr[0].en}]{s.recv_waddr[0]}<{s.recv_wdata[0]}({rf_trace}){s.recv_raddr[0]}>{s.send_rdata[0]}' + def line_trace(s, verbosity = 0): + if verbosity == 0: + recv_raddr_str = "recv_read_addr: " + "|".join([str(data.msg) for data in s.recv_raddr]) + recv_waddr_str = "recv_write_addr: " + "|".join([str(data.msg) for data in s.recv_waddr]) + recv_wdata_str = "recv_write_data: " + "|".join([str(data.msg) for data in s.recv_wdata]) + content_str = "content: " + "|".join([str(data) for data in s.reg_file.regs]) + send_rdata_str = "send_read_data: " + "|".join([str(data.msg) for data in s.send_rdata]) + return f'{recv_raddr_str} || {recv_waddr_str} || {recv_wdata_str} || [{content_str}] || {send_rdata_str}' + # return f'DataMem: {recv_str} : [{out_str}] : {send_str} initWrites: {s.initWrites}' + # return s.reg_file.line_trace() + # return f'<{s.reg_file.wen[0]}>{s.reg_file.waddr[0]}:{s.reg_file.wdata[0]}|{s.reg_file.raddr[0]}:{s.reg_file.rdata[0]}' + # rf_trace = f'<{s.reg_file.wen[0]}>{s.reg_file.waddr[0]}:{s.reg_file.wdata[0]}|{s.reg_file.raddr[0]}:{s.reg_file.rdata[0]}' + # return f'[{s.recv_wdata[0].en & s.recv_waddr[0].en}]{s.recv_waddr[0]}<{s.recv_wdata[0]}({rf_trace}){s.recv_raddr[0]}>{s.send_rdata[0]}' + else: + return s.verbose_trace(verbosity = verbosity) + + # verbose trace + def verbose_trace(s, verbosity = 1): + # data memory: mem size, reg + # recv_raddr(rdy, msg), send_rdata(en, msg), recv_waddr(rdy, msg), recv_wdata, tile # + reg_dicts = [dict(data.__dict__) for data in s.reg_file.regs] + reg_list = [] + for idx, data in enumerate(reg_dicts): + reg_dict = { "addr": f"addr {idx}" } + reg_dict.update(data) + reg_list.append(reg_dict) + reg_md = markdown_table(reg_list).set_params(quote = False).get_markdown() + + rw_ports_max_count = max(len(s.recv_raddr), len(s.recv_waddr)) + mem_list = [] + for idx in range(rw_ports_max_count): + recv_raddr_rdy, recv_raddr = None, None + send_rdata_en, send_rdata = None, None + recv_waddr_rdy, recv_waddr = None, None + recv_wdata = None + if idx <= len(s.recv_raddr) - 1: + recv_raddr_rdy = s.recv_raddr[idx].rdy + recv_raddr = s.recv_raddr[idx].msg + send_rdata_en = s.send_rdata[idx].en + send_rdata = s.send_rdata[idx].msg.payload + if idx <= len(s.recv_waddr) - 1: + recv_waddr_rdy = s.recv_waddr[idx].rdy + recv_waddr = s.recv_waddr[idx].msg + recv_wdata = s.recv_wdata[idx].msg.payload + mem_dict = { "recv_raddr(rdy, msg)": f"{recv_raddr_rdy}, {recv_raddr}", + "send_rdata(en, msg)": f"{send_rdata_en}, {send_rdata}", + "recv_waddr(rdy, msg)": f"{recv_waddr_rdy}, {recv_waddr}", + "recv_wdata": f"{recv_wdata}", + "Tiles in Col0": "<--- Tile" } + mem_list.append(mem_dict) + mem_md = markdown_table(mem_list).set_params(quote = False).get_markdown() + + return (f'\nclass: {s.__class__.__name__}\n' + f'- regs(mem size: {len(reg_dicts)}): {reg_md}\n' + f'- mem_r/w:' + f'{mem_md}') diff --git a/scale_out/RingMultiCgraRingCtrlMemRTL.py b/scale_out/RingMultiCgraRingCtrlMemRTL.py index 9dc243c..7d90502 100644 --- a/scale_out/RingMultiCgraRingCtrlMemRTL.py +++ b/scale_out/RingMultiCgraRingCtrlMemRTL.py @@ -98,9 +98,19 @@ def construct(s, CGRADataType, PredicateType, CtrlPktType, s.cgra[cgra_row * cgra_columns + cgra_col].recv_data_on_boundary_east[tile_row].en //= 0 s.cgra[cgra_row * cgra_columns + cgra_col].recv_data_on_boundary_east[tile_row].msg //= CGRADataType() - def line_trace(s): - res = "||\n".join([(("[cgra["+str(i)+"]: ") + x.line_trace()) - for (i,x) in enumerate(s.cgra)]) - res += " ## ring: " + s.ring.line_trace() - return res + def line_trace(s, verbosity = 0): + if verbosity == 0: + res = "||\n".join([(("[cgra["+str(i)+"]: ") + x.line_trace()) + for (i,x) in enumerate(s.cgra)]) + res += " ## ring: " + s.ring.line_trace() + return res + else: + return s.verbose_trace(verbosity = verbosity) + + def verbose_trace(self, verbosity = 1): + res = '' + for (i, x) in enumerate(self.cgra): + res += "# [cgra" + str(i) + "]:\n" + x.verbose_trace(verbosity = verbosity) + '\n' + res += f"## ring: {self.ring.line_trace()}" + return res diff --git a/scale_out/test/RingMultiCgraRingCtrlMemRTL_test.py b/scale_out/test/RingMultiCgraRingCtrlMemRTL_test.py index ea2a223..9be1583 100644 --- a/scale_out/test/RingMultiCgraRingCtrlMemRTL_test.py +++ b/scale_out/test/RingMultiCgraRingCtrlMemRTL_test.py @@ -209,6 +209,8 @@ def test_homo_2x2(cmdline_opts): width, height, ctrl_mem_size, data_mem_size_global, data_mem_size_per_bank, num_banks_per_cgra, src_ctrl_pkt, ctrl_mem_size, controller2addr_map) + th.set_param('top.dut.line_trace', verbosity = 1) + th.elaborate() th.dut.set_metadata(VerilogVerilatorImportPass.vl_Wno_list, ['UNSIGNED', 'UNOPTFLAT', 'WIDTH', 'WIDTHCONCAT', diff --git a/systolic/CgraMemRightAndBottomRTL.py b/systolic/CgraMemRightAndBottomRTL.py index f96550f..fe1ee20 100644 --- a/systolic/CgraMemRightAndBottomRTL.py +++ b/systolic/CgraMemRightAndBottomRTL.py @@ -124,11 +124,24 @@ def construct(s, DataType, PredicateType, CtrlType, width, height, s.tile[i].to_mem_wdata.rdy //= 0 # Line trace - def line_trace(s): - # str = "||".join([ x.element.line_trace() for x in s.tile ]) - # str += " :: [" + s.data_mem.line_trace() + "]" - res = "||\n".join([(("[tile" + str(i) + "]: ") + x.line_trace() + x.ctrl_mem.line_trace()) - for (i,x) in enumerate(s.tile)]) - res += "\n :: SouthMem [" + s.data_mem_south.line_trace() + "] \n" - res += "\n :: EastMem [" + s.data_mem_east.line_trace() + "] \n" + def line_trace(s, verbosity = 0): + if verbosity == 0: + # str = "||".join([ x.element.line_trace() for x in s.tile ]) + # str += " :: [" + s.data_mem.line_trace() + "]" + res = "||\n".join([(("[tile" + str(i) + "]: ") + x.line_trace() + x.ctrl_mem.line_trace()) + for (i,x) in enumerate(s.tile)]) + res += "\n :: SouthMem [" + s.data_mem_south.line_trace() + "] \n" + res += "\n :: EastMem [" + s.data_mem_east.line_trace() + "] \n" + return res + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace(s, verbosity = 1): + res = '' + for (i, x) in enumerate(s.tile): + res += "# [tile" + str(i) + "]: " + x.verbose_trace(verbosity = verbosity) + x.ctrl_mem.verbose_trace(verbosity = verbosity) + '\n' + res += f"# SouthMem: {s.data_mem_south.verbose_trace(verbosity = verbosity)}" + res += f"# EastMem: {s.data_mem_east.verbose_trace(verbosity = verbosity)}" + res += "------\n\n" return res diff --git a/systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py b/systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py index 02dfb58..a339adf 100644 --- a/systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py +++ b/systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py @@ -390,6 +390,7 @@ def test_CGRA_systolic(cmdline_opts): CtrlType, width, height, ctrl_mem_size, data_mem_size, src_opt, ctrl_waddr, preload_mem, preload_const, expected_out) + th.set_param('top.dut.line_trace', verbosity = 1) th.elaborate() th.dut.set_metadata(VerilogTranslationPass.explicit_module_name, diff --git a/tile/TileRTL.py b/tile/TileRTL.py index dd68900..a9dcdd1 100644 --- a/tile/TileRTL.py +++ b/tile/TileRTL.py @@ -6,9 +6,9 @@ Author : Cheng Tan Date : Dec 11, 2019 """ - - +from py_markdown_table.markdown_table import markdown_table from pymtl3 import * + from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL from ..fu.single.AdderRTL import AdderRTL from ..fu.single.BranchRTL import BranchRTL @@ -17,14 +17,16 @@ from ..fu.single.MulRTL import MulRTL from ..fu.single.PhiRTL import PhiRTL from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.util.common import TILE_PORT_DIRECTION_DICT_DESC from ..mem.const.ConstQueueRTL import ConstQueueRTL from ..mem.ctrl.CtrlMemRTL import CtrlMemRTL -from ..noc.CrossbarRTL import CrossbarRTL from ..noc.ChannelRTL import ChannelRTL +from ..noc.CrossbarRTL import CrossbarRTL from ..rf.RegisterRTL import RegisterRTL -# from ..noc.BypassChannelRTL import BypassChannelRTL +# from ..noc.BypassChannelRTL import BypassChannelRTL + class TileRTL( Component ): def construct( s, DataType, PredicateType, CtrlType, @@ -124,11 +126,49 @@ def update_opt(): s.ctrl_mem.send_ctrl.rdy @= s.element.recv_opt.rdy & s.crossbar.recv_opt.rdy # Line trace - def line_trace( s ): - - recv_str = "|".join([ str(x.msg) for x in s.recv_data ]) - channel_recv_str = "|".join([ str(x.recv.msg) for x in s.channel ]) - channel_send_str = "|".join([ str(x.send.msg) for x in s.channel ]) - out_str = "|".join([ "("+str(x.msg.payload)+","+str(x.msg.predicate)+")" for x in s.send_data ]) - return f"{recv_str} => [{s.crossbar.recv_opt.msg}] ({s.element.line_trace()}) => {channel_recv_str} => {channel_send_str} => {out_str}" - + def line_trace(s, verbosity = 0): + if verbosity == 0: + recv_str = "|".join([str(x.msg) for x in s.recv_data]) + channel_recv_str = "|".join([str(x.recv.msg) for x in s.channel]) + channel_send_str = "|".join([str(x.send.msg) for x in s.channel]) + out_str = "|".join(["(" + str(x.msg.payload) + "," + str(x.msg.predicate) + ")" for x in s.send_data]) + return f"{recv_str} => [{s.crossbar.recv_opt.msg}] ({s.element.line_trace()}) => {channel_recv_str} => {channel_send_str} => {out_str}" + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace_md_formatter(self, data_type, data): + assert data_type in [ "recv", "send" ] + data_list = [ x for x in data ] + result_list = [] + for idx, port_data in enumerate(data_list): + msg_dict = port_data.msg.__dict__ + if data_type is "recv": + tile_port_dict = { "tile_inport_direction": TILE_PORT_DIRECTION_DICT_DESC[idx], "rdy": port_data.rdy } + else: + tile_port_dict = { "tile_outport_direction": TILE_PORT_DIRECTION_DICT_DESC[idx], "en": port_data.en } + tile_port_dict.update(msg_dict) + result_list.append(tile_port_dict) + result_md = markdown_table(result_list).set_params(quote = False).get_markdown() + return result_md + + # verbose trace + def verbose_trace(s, verbosity = 1): + # recv: + # 1. rdy (if ready to receive data), if en and rdy: then data has been transferred (val, rdy are new type(protocol)) + # 2. data + # [3. opt will show in FU trace] + # FU: + # FlexibleFuRTL.py + # tile out: + # 1. en (is data transferred) + recv_md = s.verbose_trace_md_formatter("recv", s.recv_data) + send_md = s.verbose_trace_md_formatter("send", s.send_data) + return (f"\n## class[{s.__class__.__name__}]:\n" + f"- Tile recv:" + f"{recv_md}\n\n" + f"- FU element:\n" + f"{s.element.verbose_trace(verbosity=verbosity)}\n" + f"===>\n" + f"- Tile out:" + f"{send_md}\n") diff --git a/tile/TileSeparateCrossbarRTL.py b/tile/TileSeparateCrossbarRTL.py index 0a6250d..cf800d6 100644 --- a/tile/TileSeparateCrossbarRTL.py +++ b/tile/TileSeparateCrossbarRTL.py @@ -13,25 +13,28 @@ Author : Cheng Tan Date : Nov 26, 2024 """ - - from pymtl3 import * +from py_markdown_table.markdown_table import markdown_table from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL from ..fu.single.AdderRTL import AdderRTL from ..fu.single.BranchRTL import BranchRTL -from ..fu.single.PhiRTL import PhiRTL from ..fu.single.CompRTL import CompRTL from ..fu.single.MemUnitRTL import MemUnitRTL from ..fu.single.MulRTL import MulRTL +from ..fu.single.PhiRTL import PhiRTL from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ..lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL +from ..lib.opt_type import OPT_SYMBOL_DICT +from ..lib.util.common import TILE_PORT_DIRECTION_DICT_DESC from ..mem.const.ConstQueueRTL import ConstQueueRTL from ..mem.ctrl.CtrlMemDynamicRTL import CtrlMemDynamicRTL -from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL from ..noc.ChannelNormalRTL import ChannelNormalRTL +from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL from ..noc.LinkOrRTL import LinkOrRTL from ..rf.RegisterRTL import RegisterRTL + + # from ..noc.BypassChannelRTL import BypassChannelRTL class TileSeparateCrossbarRTL(Component): @@ -194,15 +197,87 @@ def update_opt(): s.routing_crossbar.recv_opt.rdy & \ s.fu_crossbar.recv_opt.rdy - # Line trace - def line_trace( s ): - recv_str = "|".join([ str(x.msg) for x in s.recv_data ]) - tile_out_channel_recv_str = "|".join([str(x.recv.msg) for x in s.tile_out_channel]) - tile_out_channel_send_str = "|".join([str(x.send.msg) for x in s.tile_out_channel]) - fu_in_channel_recv_str = "|".join([str(x.recv.msg) for x in s.fu_in_channel]) - fu_in_channel_send_str = "|".join([str(x.send.msg) for x in s.fu_in_channel]) - out_str = "|".join([ "("+str(x.msg.payload)+","+str(x.msg.predicate)+")" for x in s.send_data ]) - return f"tile_inports: {recv_str} => [routing_crossbar: {s.routing_crossbar.recv_opt.msg} || fu_crossbar: {s.fu_crossbar.recv_opt.msg} || element: {s.element.line_trace()} || tile_out_channels: {tile_out_channel_recv_str} => {tile_out_channel_send_str} || fu_in_channels: {fu_in_channel_recv_str} => {fu_in_channel_send_str}] => tile_outports: {out_str} ## " - # return f"{recv_str} => [{s.crossbar.recv_opt.msg}] ({s.element.line_trace()}) => {channel_recv_str} => {channel_send_str} => {out_str}" - + def line_trace(s, verbosity = 0): + if verbosity == 0: + recv_str = "|".join([str(x.msg) for x in s.recv_data]) + tile_out_channel_recv_str = "|".join([str(x.recv.msg) for x in s.tile_out_channel]) + tile_out_channel_send_str = "|".join([str(x.send.msg) for x in s.tile_out_channel]) + fu_in_channel_recv_str = "|".join([str(x.recv.msg) for x in s.fu_in_channel]) + fu_in_channel_send_str = "|".join([str(x.send.msg) for x in s.fu_in_channel]) + out_str = "|".join(["(" + str(x.msg.payload) + "," + str(x.msg.predicate) + ")" for x in s.send_data]) + return f"tile_inports: {recv_str} => [routing_crossbar: {s.routing_crossbar.recv_opt.msg} || fu_crossbar: {s.fu_crossbar.recv_opt.msg} || element: {s.element.line_trace()} || tile_out_channels: {tile_out_channel_recv_str} => {tile_out_channel_send_str} || fu_in_channels: {fu_in_channel_recv_str} => {fu_in_channel_send_str}] => tile_outports: {out_str} ## " + # return f"{recv_str} => [{s.crossbar.recv_opt.msg}] ({s.element.line_trace()}) => {channel_recv_str} => {channel_send_str} => {out_str}" + else: + return s.verbose_trace(verbosity = verbosity) + + + def verbose_trace_str_formatter(self, crossbar_dict): + crossbar_dict['ctrl'] = OPT_SYMBOL_DICT[crossbar_dict['ctrl']] + crossbar_dict['predicate'] = int(crossbar_dict['predicate']) + crossbar_dict['fu_in'] = [ int(fi) for fi in crossbar_dict['fu_in'] ] + crossbar_dict['fu_xbar_outport'] = [ int(fxop) for fxop in crossbar_dict['fu_xbar_outport'] ] + crossbar_dict['routing_predicate_in'] = [ int(rpi) for rpi in crossbar_dict['routing_predicate_in'] ] + crossbar_dict['routing_xbar_outport'] = [ int(rxop) for rxop in crossbar_dict['routing_xbar_outport'] ] + crossbar_str = "\n".join([(key + ": " + str(value)) for key, value in crossbar_dict.items()]) + return crossbar_str + + def verbose_trace_md_formatter(self, header_str, data_dict): + result_list = [] + for idx, data in enumerate(data_dict): + port_direction = TILE_PORT_DIRECTION_DICT_DESC[idx] + dict_with_direction = { header_str: port_direction } + dict_with_direction.update(data) + result_list.append(dict_with_direction) + result_md = markdown_table(result_list).set_params(quote = False).get_markdown() + return result_md + + # verbose trace + def verbose_trace(s, verbosity = 1): + recv_data = [ x.msg.__dict__ for x in s.recv_data ] + recv_md = s.verbose_trace_md_formatter("inport_direction", recv_data) + + routing_crossbar_dict = dict(s.routing_crossbar.recv_opt.msg.__dict__) + routing_crossbar_str = s.verbose_trace_str_formatter(routing_crossbar_dict) + + fu_crossbar_dict = dict(s.fu_crossbar.recv_opt.msg.__dict__) + fu_crossbar_str = s.verbose_trace_str_formatter(fu_crossbar_dict) + + tile_out_channel_recv_data = [ x.recv.msg.__dict__ for x in s.tile_out_channel ] + tile_out_channel_recv_md = s.verbose_trace_md_formatter("inport_direction", tile_out_channel_recv_data) + + tile_out_channel_send_data = [ x.send.msg.__dict__ for x in s.tile_out_channel ] + tile_out_channel_send_md = s.verbose_trace_md_formatter("outport_direction", tile_out_channel_send_data) + + fu_in_channel_recv_data = [ x.recv.msg.__dict__ for x in s.fu_in_channel ] + fu_in_channel_recv_md = s.verbose_trace_md_formatter("inport_direction", fu_in_channel_recv_data) + + fu_in_channel_send_data = [ x.send.msg.__dict__ for x in s.fu_in_channel ] + fu_in_channel_send_md = s.verbose_trace_md_formatter("outport_direction", fu_in_channel_send_data) + + tile_outports_data = [ x.msg.__dict__ for x in s.send_data ] + tile_outports_md = s.verbose_trace_md_formatter("outport_direction", tile_outports_data) + + return (f'\n## class: {s.__class__.__name__}\n' + f'- tile_inports:' + f'{recv_md}\n' + f'===>\n' + f'- routing_crossbar:\n' + f'{routing_crossbar_str}\n' + f'- fu_crossbar:\n' + f'{fu_crossbar_str}\n' + f'- element:\n' + f'{s.element.verbose_trace(verbosity = verbosity)}\n' + f'- tile_out_channels_recv:' + f'{tile_out_channel_recv_md}\n' + f'===>\n' + f'- tile_out_channel_send:' + f'{tile_out_channel_send_md}\n' + f'- fu_in_channels_recv:' + f'{fu_in_channel_recv_md}\n' + f'===>\n' + f'- fu_in_channels_send:' + f'{fu_in_channel_send_md}\n' + f'===>\n' + f'- tile_outports:' + f'{tile_outports_md}\n') diff --git a/tile/test/TileSeparateCrossbarRTL_test.py b/tile/test/TileSeparateCrossbarRTL_test.py index 6ee012b..e75ac4b 100644 --- a/tile/test/TileSeparateCrossbarRTL_test.py +++ b/tile/test/TileSeparateCrossbarRTL_test.py @@ -165,6 +165,8 @@ def test_tile_alu(cmdline_opts): data_mem_size, num_fu_inports, num_fu_outports, num_tile_inports, num_tile_outports, src_data, src_ctrl_pkt, sink_out) + th.set_param('top.dut.line_trace', verbosity = 1) + th.elaborate() th.dut.set_metadata(VerilogVerilatorImportPass.vl_Wno_list, ['UNSIGNED', 'UNOPTFLAT', 'WIDTH', 'WIDTHCONCAT',