From a132e20b9e0d177c1ac2a171a17a9e928d5e3028 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 17:09:17 +0100 Subject: [PATCH 1/6] system(H7) update STM32H7xx HAL Drivers to v1.11.5 Included in STM32CubeH7 FW v1.12.1 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 84 +- .../STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h | 6 + .../Inc/stm32h7xx_hal_adc.h | 6 +- .../Inc/stm32h7xx_hal_adc_ex.h | 82 +- .../Inc/stm32h7xx_hal_comp.h | 6 +- .../Inc/stm32h7xx_hal_conf_template.h | 8 + .../Inc/stm32h7xx_hal_cordic.h | 21 +- .../Inc/stm32h7xx_hal_cortex.h | 2 +- .../Inc/stm32h7xx_hal_cryp.h | 4 +- .../Inc/stm32h7xx_hal_cryp_ex.h | 4 +- .../Inc/stm32h7xx_hal_dac.h | 11 +- .../Inc/stm32h7xx_hal_dcmi.h | 4 +- .../Inc/stm32h7xx_hal_dma.h | 4 +- .../Inc/stm32h7xx_hal_dma2d.h | 8 +- .../Inc/stm32h7xx_hal_dts.h | 2 +- .../Inc/stm32h7xx_hal_eth.h | 37 +- .../Inc/stm32h7xx_hal_exti.h | 10 +- .../Inc/stm32h7xx_hal_fdcan.h | 4 +- .../Inc/stm32h7xx_hal_fmac.h | 12 +- .../Inc/stm32h7xx_hal_gfxmmu.h | 8 +- .../Inc/stm32h7xx_hal_gpio.h | 4 +- .../Inc/stm32h7xx_hal_hash.h | 82 +- .../Inc/stm32h7xx_hal_hash_ex.h | 74 +- .../Inc/stm32h7xx_hal_hrtim.h | 1550 ++++----- .../Inc/stm32h7xx_hal_hsem.h | 12 +- .../Inc/stm32h7xx_hal_i2s.h | 5 + .../Inc/stm32h7xx_hal_ltdc.h | 7 +- .../Inc/stm32h7xx_hal_mdios.h | 8 +- .../Inc/stm32h7xx_hal_mdma.h | 6 +- .../Inc/stm32h7xx_hal_mmc.h | 130 +- .../Inc/stm32h7xx_hal_mmc_ex.h | 3 +- .../Inc/stm32h7xx_hal_nand.h | 2 +- .../Inc/stm32h7xx_hal_opamp.h | 4 +- .../Inc/stm32h7xx_hal_otfdec.h | 8 +- .../Inc/stm32h7xx_hal_pcd_ex.h | 1 - .../Inc/stm32h7xx_hal_pwr.h | 2 +- .../Inc/stm32h7xx_hal_pwr_ex.h | 4 +- .../Inc/stm32h7xx_hal_qspi.h | 3 + .../Inc/stm32h7xx_hal_ramecc.h | 18 +- .../Inc/stm32h7xx_hal_rcc.h | 2 +- .../Inc/stm32h7xx_hal_rcc_ex.h | 2 +- .../Inc/stm32h7xx_hal_rng.h | 3 + .../Inc/stm32h7xx_hal_rng_ex.h | 34 +- .../Inc/stm32h7xx_hal_rtc.h | 44 +- .../Inc/stm32h7xx_hal_rtc_ex.h | 109 +- .../Inc/stm32h7xx_hal_sd.h | 16 +- .../Inc/stm32h7xx_hal_sd_ex.h | 2 + .../Inc/stm32h7xx_hal_sdio.h | 600 ++++ .../Inc/stm32h7xx_hal_sdram.h | 2 +- .../Inc/stm32h7xx_hal_swpmi.h | 36 +- .../Inc/stm32h7xx_hal_uart.h | 5 +- .../Inc/stm32h7xx_hal_usart.h | 3 +- .../Inc/stm32h7xx_hal_wwdg.h | 2 +- .../Inc/stm32h7xx_ll_adc.h | 232 +- .../Inc/stm32h7xx_ll_bdma.h | 160 +- .../Inc/stm32h7xx_ll_comp.h | 30 +- .../Inc/stm32h7xx_ll_cordic.h | 28 +- .../Inc/stm32h7xx_ll_dma.h | 216 +- .../Inc/stm32h7xx_ll_dma2d.h | 129 +- .../Inc/stm32h7xx_ll_dmamux.h | 154 +- .../Inc/stm32h7xx_ll_fmac.h | 6 - .../Inc/stm32h7xx_ll_fmc.h | 55 +- .../Inc/stm32h7xx_ll_gpio.h | 26 +- .../Inc/stm32h7xx_ll_hrtim.h | 449 ++- .../Inc/stm32h7xx_ll_hsem.h | 24 +- .../Inc/stm32h7xx_ll_iwdg.h | 14 +- .../Inc/stm32h7xx_ll_lpuart.h | 15 + .../Inc/stm32h7xx_ll_mdma.h | 220 +- .../Inc/stm32h7xx_ll_opamp.h | 22 +- .../Inc/stm32h7xx_ll_rng.h | 2 +- .../Inc/stm32h7xx_ll_rtc.h | 218 +- .../Inc/stm32h7xx_ll_sdmmc.h | 313 +- .../Inc/stm32h7xx_ll_swpmi.h | 90 +- .../Inc/stm32h7xx_ll_wwdg.h | 12 +- .../STM32H7xx_HAL_Driver/Release_Notes.html | 244 +- .../STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c | 2 +- .../Src/stm32h7xx_hal_adc.c | 13 +- .../Src/stm32h7xx_hal_adc_ex.c | 12 +- .../Src/stm32h7xx_hal_comp.c | 6 +- .../Src/stm32h7xx_hal_cordic.c | 2 +- .../Src/stm32h7xx_hal_cortex.c | 2 +- .../Src/stm32h7xx_hal_crc_ex.c | 2 - .../Src/stm32h7xx_hal_cryp.c | 8 +- .../Src/stm32h7xx_hal_cryp_ex.c | 4 +- .../Src/stm32h7xx_hal_dac.c | 8 + .../Src/stm32h7xx_hal_dac_ex.c | 15 +- .../Src/stm32h7xx_hal_dcmi.c | 4 +- .../Src/stm32h7xx_hal_dma.c | 8 +- .../Src/stm32h7xx_hal_dma2d.c | 13 +- .../Src/stm32h7xx_hal_dts.c | 2 +- .../Src/stm32h7xx_hal_eth.c | 35 +- .../Src/stm32h7xx_hal_exti.c | 12 +- .../Src/stm32h7xx_hal_flash_ex.c | 8 +- .../Src/stm32h7xx_hal_fmac.c | 24 +- .../Src/stm32h7xx_hal_gfxmmu.c | 8 +- .../Src/stm32h7xx_hal_gpio.c | 4 +- .../Src/stm32h7xx_hal_hash.c | 123 +- .../Src/stm32h7xx_hal_hash_ex.c | 79 +- .../Src/stm32h7xx_hal_hcd.c | 6 + .../Src/stm32h7xx_hal_hrtim.c | 2094 ++++++------ .../Src/stm32h7xx_hal_i2c.c | 107 +- .../Src/stm32h7xx_hal_i2s.c | 101 + .../Src/stm32h7xx_hal_iwdg.c | 3 +- .../Src/stm32h7xx_hal_ltdc.c | 28 +- .../Src/stm32h7xx_hal_mdios.c | 8 +- .../Src/stm32h7xx_hal_mdma.c | 6 +- .../Src/stm32h7xx_hal_mmc.c | 1749 +++++++++- .../Src/stm32h7xx_hal_mmc_ex.c | 4 +- .../Src/stm32h7xx_hal_nand.c | 2 +- .../Src/stm32h7xx_hal_opamp.c | 6 +- .../Src/stm32h7xx_hal_ospi.c | 13 +- .../Src/stm32h7xx_hal_otfdec.c | 38 +- .../Src/stm32h7xx_hal_pcd.c | 9 +- .../Src/stm32h7xx_hal_pwr.c | 2 +- .../Src/stm32h7xx_hal_pwr_ex.c | 8 +- .../Src/stm32h7xx_hal_qspi.c | 45 +- .../Src/stm32h7xx_hal_ramecc.c | 18 +- .../Src/stm32h7xx_hal_rcc.c | 2 +- .../Src/stm32h7xx_hal_rcc_ex.c | 10 +- .../Src/stm32h7xx_hal_rng.c | 12 +- .../Src/stm32h7xx_hal_rng_ex.c | 21 +- .../Src/stm32h7xx_hal_rtc.c | 71 +- .../Src/stm32h7xx_hal_rtc_ex.c | 76 +- .../Src/stm32h7xx_hal_sd.c | 162 +- .../Src/stm32h7xx_hal_sd_ex.c | 2 + .../Src/stm32h7xx_hal_sdio.c | 2877 +++++++++++++++++ .../Src/stm32h7xx_hal_sdram.c | 5 +- .../Src/stm32h7xx_hal_smartcard.c | 2 +- .../Src/stm32h7xx_hal_smbus_ex.c | 2 + .../Src/stm32h7xx_hal_spi.c | 12 +- .../Src/stm32h7xx_hal_spi_ex.c | 1 - .../Src/stm32h7xx_hal_sram.c | 3 + .../Src/stm32h7xx_hal_swpmi.c | 93 +- .../Src/stm32h7xx_hal_tim.c | 13 +- .../Src/stm32h7xx_hal_uart.c | 28 +- .../Src/stm32h7xx_hal_uart_ex.c | 2 +- .../Src/stm32h7xx_hal_usart.c | 17 +- .../Src/stm32h7xx_hal_usart_ex.c | 2 +- .../Src/stm32h7xx_hal_wwdg.c | 7 +- .../Src/stm32h7xx_ll_adc.c | 2 +- .../Src/stm32h7xx_ll_dma2d.c | 11 +- .../Src/stm32h7xx_ll_fmac.c | 2 - .../Src/stm32h7xx_ll_fmc.c | 54 +- .../Src/stm32h7xx_ll_gpio.c | 2 +- .../Src/stm32h7xx_ll_hrtim.c | 2 +- .../Src/stm32h7xx_ll_rng.c | 2 +- .../Src/stm32h7xx_ll_sdmmc.c | 248 +- .../Src/stm32h7xx_ll_swpmi.c | 14 +- .../Src/stm32h7xx_ll_usb.c | 20 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 150 files changed, 10268 insertions(+), 3917 deletions(-) create mode 100644 system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h create mode 100644 system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index b4dbed31c1..2308881813 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h index c3760b1735..222a4e9d26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -59,8 +59,14 @@ typedef enum * @{ */ #define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */ +#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */ #define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#if (STM32H7_DEV_ID == 0x450UL) #define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#else +#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */ +#endif /* STM32H7_DEV_ID */ #define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h index 861324a382..7cde9f1e7f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h @@ -1962,7 +1962,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1990,8 +1990,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h index 2da227fa97..d2900314bd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h @@ -1011,6 +1011,80 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) ) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC1. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_16) ? ADC_CHANNEL_17 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC2. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC3. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_13) ? ADC_CHANNEL_14 : \ + ((__CHANNEL__) == ADC_CHANNEL_14) ? ADC_CHANNEL_15 : 0UL) +#endif /* ADC_VER_V5_V90 */ + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC3) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) : 0UL) +#else +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : 0UL) +#endif /* ADC_VER_V5_V90 */ + /** * @brief Verify the ADC single-ended input or differential mode setting. * @param __SING_DIFF__ programmed channel setting. @@ -1311,7 +1385,7 @@ typedef struct /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); @@ -1328,12 +1402,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC multimode */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h index 9d16f6aad9..83265b0149 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h @@ -915,7 +915,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in Interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -926,8 +926,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h index d79bca3646..1be478bd2c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h @@ -85,6 +85,7 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SDIO_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -169,6 +170,8 @@ #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SPI_CRC 1U /*!< use CRC in SPI */ #define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */ +#define USE_SDIO_TRANSCEIVER 0U /*!< use SDIO Transceiver */ +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ @@ -209,6 +212,7 @@ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ @@ -439,6 +443,10 @@ #include "stm32h7xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h7xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32h7xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h index 0aa08c4316..28949bedee 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h index 134fc483f4..cc4c24c755 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h @@ -309,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_EnableRegion(uint32_t RegionNumber); void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h index a6802ed6ba..59bf9cd5a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h @@ -454,11 +454,11 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ /* Interrupt Handler functions **********************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp); void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h index 8820e0b7aa..3c193cde8d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h @@ -91,8 +91,8 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h index 65e5fd938c..90590387b6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h @@ -286,10 +286,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h index a21afc09d5..672d5de0f8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h @@ -569,8 +569,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ * @{ */ /* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h index 82f6f215e5..59ad97a8fe 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -1211,8 +1211,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * @brief Peripheral State functions * @{ */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h index 00f205bc0c..dd32a99b28 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h @@ -511,9 +511,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); @@ -550,8 +550,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t */ /* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h index f9bff1703e..3bb262faf5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h @@ -423,7 +423,7 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts); HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts); void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts); -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts); +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts); /* Callback in Interrupt mode */ void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts); void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h index 726127ea68..b3d9eefbbc 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h index 9e93c22951..1a1e984989 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h @@ -344,16 +344,16 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); @@ -373,7 +373,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h index 1cd9178bbd..e0b75b7039 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -252,7 +252,7 @@ typedef enum * @{ */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} @@ -262,7 +262,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); * @{ */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h index 15b1213f15..54df4670a2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +499,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +519,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +533,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +548,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -571,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash); +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); /** * @} @@ -594,19 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h index 78fc650fc3..2ac9297a91 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h index 7b709f3e7b..a6841ada0e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h @@ -21,7 +21,7 @@ #define STM32H7xx_HAL_HRTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. + uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger @@ -119,7 +119,7 @@ typedef struct __HRTIM_HandleTypeDef typedef struct #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ { - HRTIM_TypeDef * Instance; /*!< Register base address */ + HRTIM_TypeDef *Instance; /*!< Register base address */ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ @@ -129,12 +129,12 @@ typedef struct __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ - DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ + DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ @@ -481,7 +481,8 @@ typedef struct /** * @brief HAL HRTIM Callback ID enumeration definition */ -typedef enum { +typedef enum +{ HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ @@ -510,7 +511,7 @@ typedef enum { HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ -}HAL_HRTIM_CallbackIDTypeDef; +} HAL_HRTIM_CallbackIDTypeDef; /** * @brief HAL HRTIM Callback function pointer definitions @@ -556,8 +557,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit * @{ @@ -567,9 +568,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit * @{ @@ -609,10 +610,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) /** * @} */ @@ -649,10 +650,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ - /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio +/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. - */ + */ #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ @@ -934,9 +935,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) /** * @} */ @@ -1040,9 +1041,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level * @{ @@ -1267,9 +1268,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle * @{ @@ -1804,8 +1805,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) /** * @} */ @@ -1999,169 +2000,169 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ - /* Private macros --------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) + (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ + ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)))) + ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ + (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ + (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ + (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ + (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ + (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TE2)))) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_NONE)|| \ - ((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5) || \ + ((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) #define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5)) + (((FAULT) == HRTIM_FAULT_1) || \ + ((FAULT) == HRTIM_FAULT_2) || \ + ((FAULT) == HRTIM_FAULT_3) || \ + ((FAULT) == HRTIM_FAULT_4) || \ + ((FAULT) == HRTIM_FAULT_5)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) #define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINUOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_CONTINUOUS) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) + (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ + ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) #define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) + (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ + ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) #define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) + (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ + ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) #define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) + (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) #define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) + (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ + ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) #define IS_HRTIM_TIMERBURSTMODE(MODE) \ - (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) + (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ + ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ + ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) + (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ + ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ - ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ - ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) + ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ + ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ - ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) + ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) @@ -2169,128 +2170,128 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) + (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ + ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) /* Auto delayed mode is only available for compare units 2 and 4U */ #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) + ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ + || \ + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) + (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ + ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) + (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ + ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ - (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ - ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) + (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ + ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ - (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) + (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) + (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ + ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ + ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ @@ -2304,420 +2305,420 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) + (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) + (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ + ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) + (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ + ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) + (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ + ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) + (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ + ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) + (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ + ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) + (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ + ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) + (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ + ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) + (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ - (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) + (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ - (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) + (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) + (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) + (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) + (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) #define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_4)) + (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_4)) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ - ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ - || \ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) + ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ + (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ + ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ + || \ + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ - (((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) && \ - (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10))) + (((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) && \ + (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ + ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10))) #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ - ((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) \ - || \ - ((((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) && \ - (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((FILTER) == HRTIM_EVENTFILTER_1) || \ - ((FILTER) == HRTIM_EVENTFILTER_2) || \ - ((FILTER) == HRTIM_EVENTFILTER_3) || \ - ((FILTER) == HRTIM_EVENTFILTER_4) || \ - ((FILTER) == HRTIM_EVENTFILTER_5) || \ - ((FILTER) == HRTIM_EVENTFILTER_6) || \ - ((FILTER) == HRTIM_EVENTFILTER_7) || \ - ((FILTER) == HRTIM_EVENTFILTER_8) || \ - ((FILTER) == HRTIM_EVENTFILTER_9) || \ - ((FILTER) == HRTIM_EVENTFILTER_10) || \ - ((FILTER) == HRTIM_EVENTFILTER_11) || \ - ((FILTER) == HRTIM_EVENTFILTER_12) || \ - ((FILTER) == HRTIM_EVENTFILTER_13) || \ - ((FILTER) == HRTIM_EVENTFILTER_14) || \ - ((FILTER) == HRTIM_EVENTFILTER_15)))) + ((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) \ + || \ + ((((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) && \ + (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ + ((FILTER) == HRTIM_EVENTFILTER_1) || \ + ((FILTER) == HRTIM_EVENTFILTER_2) || \ + ((FILTER) == HRTIM_EVENTFILTER_3) || \ + ((FILTER) == HRTIM_EVENTFILTER_4) || \ + ((FILTER) == HRTIM_EVENTFILTER_5) || \ + ((FILTER) == HRTIM_EVENTFILTER_6) || \ + ((FILTER) == HRTIM_EVENTFILTER_7) || \ + ((FILTER) == HRTIM_EVENTFILTER_8) || \ + ((FILTER) == HRTIM_EVENTFILTER_9) || \ + ((FILTER) == HRTIM_EVENTFILTER_10) || \ + ((FILTER) == HRTIM_EVENTFILTER_11) || \ + ((FILTER) == HRTIM_EVENTFILTER_12) || \ + ((FILTER) == HRTIM_EVENTFILTER_13) || \ + ((FILTER) == HRTIM_EVENTFILTER_14) || \ + ((FILTER) == HRTIM_EVENTFILTER_15)))) #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) + (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) + (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ + ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) + (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) + (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ + ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) + (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) #define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) + (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ + ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) + (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) + (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) + (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ + ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) + (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) + (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) + (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ + ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) @@ -2750,10 +2751,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) #endif @@ -2782,44 +2783,44 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ + {\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ + }\ } while(0U) @@ -2852,8 +2853,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval None */ -#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) -#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + |= (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + &= ~(__INTERRUPT__)) /** @brief Enables or disables the specified HRTIM Timerx interrupts. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2892,7 +2895,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2907,7 +2911,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2937,7 +2942,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clears the specified HRTIM common pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2967,7 +2973,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag * @retval None */ -#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ + = (__INTERRUPT__)) /** @brief Clears the specified HRTIM Timerx pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2990,7 +2997,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag * @retval None */ -#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) +#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__INTERRUPT__)) /* DMA HANDLING */ /** @brief Enables or disables the specified HRTIM Master timer DMA requests. @@ -3033,14 +3041,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) -#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) -#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) -#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) -#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) +#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ + (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__FLAG__)) /** @brief Sets the HRTIM timer Counter Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3136,16 +3148,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval None */ #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) /** @brief Gets the HRTIM timer Compare Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3161,16 +3173,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval Compare value */ #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) /** * @} @@ -3178,17 +3190,17 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /* Exported functions --------------------------------------------------------*/ /** @addtogroup HRTIM_Exported_Functions -* @{ -*/ + * @{ + */ /** @addtogroup HRTIM_Exported_Functions_Group1 -* @{ -*/ + * @{ + */ /* Initialization and Configuration functions ********************************/ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); @@ -3196,244 +3208,244 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group2 -* @{ -*/ + * @{ + */ /* Simple time base related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group3 -* @{ -*/ + * @{ + */ /* Simple output compare related functions ************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group4 -* @{ -*/ + * @{ + */ /* Simple PWM output related functions ****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group5 -* @{ -*/ + * @{ + */ /* Simple capture related functions *******************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group6 -* @{ -*/ + * @{ + */ /* Simple one pulse related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group7 -* @{ -*/ + * @{ + */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef *pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable); HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group8 -* @{ -*/ + * @{ + */ /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef *pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef *pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef *pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3443,15 +3455,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3459,22 +3471,22 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart); @@ -3503,7 +3515,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferLength); HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -3513,12 +3525,12 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group9 -* @{ -*/ + * @{ + */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); @@ -3526,7 +3538,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); @@ -3547,8 +3559,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group10 -* @{ -*/ + * @{ + */ /* IRQ handler */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); @@ -3565,50 +3577,50 @@ void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); /* Timer events related callback functions */ void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h index 45f6e07d97..45cf33d7f4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h @@ -57,7 +57,7 @@ extern "C" { (HSEM->C1IER |= (__SEM_MASK__)) : \ (HSEM->C2IER |= (__SEM_MASK__))) #else -#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->C1IER |= (__SEM_MASK__)) #endif /* DUAL_CORE */ /** * @brief Disables the specified HSEM interrupts. @@ -69,7 +69,7 @@ extern "C" { (HSEM->C1IER &= ~(__SEM_MASK__)) : \ (HSEM->C2IER &= ~(__SEM_MASK__))) #else -#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->C1IER &= ~(__SEM_MASK__)) #endif /* DUAL_CORE */ /** @@ -80,9 +80,9 @@ extern "C" { #if defined(DUAL_CORE) #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ ((__SEM_MASK__) & HSEM->C1MISR) : \ - ((__SEM_MASK__) & HSEM->C2MISR1)) + ((__SEM_MASK__) & HSEM->C2MISR)) #else -#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1MISR) #endif /* DUAL_CORE */ /** @@ -95,7 +95,7 @@ extern "C" { (__SEM_MASK__) & HSEM->C1ISR : \ (__SEM_MASK__) & HSEM->C2ISR) #else -#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1ISR) #endif /* DUAL_CORE */ /** @@ -108,7 +108,7 @@ extern "C" { (HSEM->C1ICR |= (__SEM_MASK__)) : \ (HSEM->C2ICR |= (__SEM_MASK__))) #else -#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->C1ICR |= (__SEM_MASK__)) #endif /* DUAL_CORE */ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h index 407bf2ccb3..40f321f8e4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h @@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); +/* IO Swap feature */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s); + /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h index 3e792bc9d6..b0df0bd0ac 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h @@ -592,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -625,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * @{ */ /* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h index 50c61f41d1..fecf9fe2af 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h @@ -509,8 +509,8 @@ HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_ HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios); HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); @@ -527,8 +527,8 @@ void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); /** @addtogroup MDIOS_Exported_Functions_Group3 * @{ */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios); +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h index a39cc0d755..fb61178648 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM */ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); @@ -687,8 +687,8 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); * @brief Peripheral State functions * @{ */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h index ed4e5e5ade..3b242bae0e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMC * @{ @@ -121,7 +122,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -135,6 +136,8 @@ typedef struct __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ uint32_t CSD[4U]; /*!< MMC card specific data table */ @@ -276,45 +279,55 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition * @{ */ -#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ /*!< number of transferred bytes does not match the block length */ -#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ /*!< command or if there was an attempt to access a locked card */ -#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ /*!< of erase sequence command was received */ -#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/*!< response results after operating with RPMB partition */ +#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ +#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ +#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ +#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ +#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ +#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ +#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ +#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ +#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} @@ -399,6 +412,19 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); * @} */ +/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types + * @{ + */ +typedef uint32_t HAL_MMC_PartitionTypeDef; + +#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ +#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ +#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ +#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ +/** + * @} + */ + /** * @} */ @@ -686,6 +712,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); /** * @} */ @@ -694,9 +721,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} @@ -705,8 +732,9 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); /** * @} */ @@ -740,6 +768,29 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ + +/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, + uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); + +/** + * @} + */ + /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ @@ -812,6 +863,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h index 215749583f..c610a2bdf1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMCEx * @brief SD HAL extended module driver * @{ @@ -100,6 +100,7 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h index 7290893bd4..b0b31b91bb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h index ef354861f5..cac0948402 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h @@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} @@ -428,7 +428,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop */ /* Peripheral State functions **************************************************/ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h index bfdfb0b456..9aa5e3ab6b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h @@ -342,8 +342,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); /** @@ -353,8 +353,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 /** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions * @{ */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec); -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec); +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h index 9cfa0125e6..221e2af375 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h index 91a905409f..c1d7222366 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -692,7 +692,7 @@ void HAL_PWR_DisableBkUpAccess (void); */ /* Peripheral Control functions **********************************************/ /* PVD configuration */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD (void); void HAL_PWR_DisablePVD (void); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h index 61c76092cd..e8455d8d22 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -544,7 +544,7 @@ void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); #endif /* defined(PWR_CR1_SRDRAMSO) */ /* Wakeup Pins control functions */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams); void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); @@ -599,7 +599,7 @@ uint32_t HAL_PWREx_GetVBATLevel (void); PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); #endif /* PWR_CSR1_MMCVDO */ /* Power AVD configuration functions */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD); void HAL_PWREx_EnableAVD (void); void HAL_PWREx_DisableAVD (void); /* Power PVD/AVD IRQ Handler */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h index 98b2c5cf19..321f05f52b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h @@ -26,6 +26,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined (DLYB_QUADSPI) +#include "stm32h7xx_ll_delayblock.h" +#endif /* DLYB_QUADSPI */ #if defined(QUADSPI) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h index f9444ebc87..b681c8dee6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc); * @brief Error information functions * @{ */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc); /** * @} */ @@ -317,9 +317,9 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); * @brief State and Error Functions * @{ */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc); +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h index 1626c6d050..564a8a09f6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -7968,7 +7968,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h index 2fb1fd2906..d39df84c7a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -3936,7 +3936,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); * @{ */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h index e7dd55a1e1..409ac73bd1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h @@ -178,6 +178,9 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#if defined(RNG_CR_CONDRST) +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ +#endif /* RNG_CR_CONDRST */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h index ee43ec107b..05c83d073a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h index ad0fa135f4..0777b955a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h @@ -181,39 +181,41 @@ typedef struct __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ - void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ - void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ - void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#if defined(RTC_TAMPER2_SUPPORT) + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#endif /* RTC_TAMPER2_SUPPORT */ - void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ #if defined(TAMP) - void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ + void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ - void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ + void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ - void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ + void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ - void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ + void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ - void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ + void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ - void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ + void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ - void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ + void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ #endif /* TAMP */ - void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ @@ -230,7 +232,9 @@ typedef enum HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, /*!< RTC TimeStamp Event Callback ID */ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u, /*!< RTC WakeUp Timer Event Callback ID */ HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, /*!< RTC Tamper 1 Callback ID */ +#if defined(RTC_TAMPER2_SUPPORT) HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, /*!< RTC Tamper 2 Callback ID */ +#endif /* RTC_TAMPER2_SUPPORT */ HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, /*!< RTC Tamper 3 Callback ID */ #if defined(TAMP) HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 12u, /*!< RTC Internal Tamper 1 Callback ID */ @@ -935,9 +939,9 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); /** * @} */ @@ -949,7 +953,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -970,7 +974,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h index bb29abe868..d66729467a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h @@ -56,10 +56,14 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions + This parameter is not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and has been kept for backward compatibility */ - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions + This parameter is not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and has been kept for backward compatibility */ uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ @@ -265,11 +269,17 @@ typedef struct #define RTC_TAMPER_3 TAMP_CR1_TAMP3E #else #define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E +#endif /* RTC_TAMPER2_SUPPORT */ #define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E #endif /* TAMP */ +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3) +#else +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_3) +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ @@ -282,9 +292,13 @@ typedef struct #define RTC_IT_TAMP2 TAMP_IER_TAMP2IE /*!< Enable Tamper 2 Interrupt */ #define RTC_IT_TAMP3 TAMP_IER_TAMP3IE /*!< Enable Tamper 3 Interrupt */ #else +#if defined(RTC_TAMPxIE_SUPPORT) #define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */ #define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */ #define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /*!< Enable Tamper 3 Interrupt */ +#else +#define RTC_IT_TAMP1 RTC_TAFCR_TAMPIE /*!< Enable Tamper Interrupt */ +#endif /* RTC_TAMPxIE_SUPPORT */ #endif /* TAMP */ #if defined(TAMP) @@ -349,13 +363,20 @@ typedef struct #define RTC_TAMPER_3_TRIGGER TAMP_CR2_TAMP3TRG #else #define RTC_TAMPER_1_TRIGGER RTC_TAMPCR_TAMP1TRG +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_2_TRIGGER RTC_TAMPCR_TAMP2TRG +#endif /* RTC_TAMPER2_SUPPORT */ #define RTC_TAMPER_3_TRIGGER RTC_TAMPCR_TAMP3TRG #endif /* TAMP */ +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_X_TRIGGER (RTC_TAMPER_1_TRIGGER |\ RTC_TAMPER_2_TRIGGER |\ RTC_TAMPER_3_TRIGGER) +#else +#define RTC_TAMPER_X_TRIGGER (RTC_TAMPER_1_TRIGGER |\ + RTC_TAMPER_3_TRIGGER) +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ @@ -367,8 +388,15 @@ typedef struct #define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u #define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u #else -#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000u +#if defined(RTC_TAMPNOERASE_SUPPORT) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u #define RTC_TAMPER_ERASE_BACKUP_DISABLE RTC_TAMPCR_TAMP1NOERASE +#else +/*!< These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and have been kept for backward compatibility */ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#endif /* RTC_TAMPNOERASE_SUPPORT */ #endif /* TAMP */ #if defined(TAMP) @@ -376,14 +404,18 @@ typedef struct #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 TAMP_CR2_TAMP2NOERASE #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 TAMP_CR2_TAMP3NOERASE #else +#if defined(RTC_TAMPNOERASE_SUPPORT) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 RTC_TAMPCR_TAMP1NOERASE #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 RTC_TAMPCR_TAMP2NOERASE #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 RTC_TAMPCR_TAMP3NOERASE +#endif /* RTC_TAMPNOERASE_SUPPORT */ #endif /* TAMP */ +#if defined(RTC_TAMPNOERASE_SUPPORT) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK (RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\ RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\ RTC_DISABLE_BKP_ERASE_ON_TAMPER_3) +#endif /* RTC_TAMPNOERASE_SUPPORT */ /** * @} */ @@ -395,8 +427,15 @@ typedef struct #define RTC_TAMPERMASK_FLAG_DISABLE 0x00u #define RTC_TAMPERMASK_FLAG_ENABLE 0x01u #else -#define RTC_TAMPERMASK_FLAG_DISABLE 0x00000000u +#if defined(RTC_TAMPMASKFLAG_SUPPORT) +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u #define RTC_TAMPERMASK_FLAG_ENABLE RTC_TAMPCR_TAMP1MF +#else +/*!< These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 + devices, and have been kept for backward compatibility */ +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ #endif /* TAMP */ #if defined(TAMP) @@ -404,14 +443,18 @@ typedef struct #define RTC_TAMPER_2_MASK_FLAG TAMP_CR2_TAMP2MSK #define RTC_TAMPER_3_MASK_FLAG TAMP_CR2_TAMP3MSK #else +#if defined(RTC_TAMPMASKFLAG_SUPPORT) #define RTC_TAMPER_1_MASK_FLAG RTC_TAMPCR_TAMP1MF #define RTC_TAMPER_2_MASK_FLAG RTC_TAMPCR_TAMP2MF #define RTC_TAMPER_3_MASK_FLAG RTC_TAMPCR_TAMP3MF +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ #endif /* TAMP */ +#if defined(RTC_TAMPMASKFLAG_SUPPORT) #define RTC_TAMPER_X_MASK_FLAG (RTC_TAMPER_1_MASK_FLAG |\ RTC_TAMPER_2_MASK_FLAG |\ RTC_TAMPER_3_MASK_FLAG) +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ /** * @} */ @@ -575,7 +618,9 @@ typedef struct #define RTC_FLAG_TAMP3F TAMP_SR_TAMP3F #else #define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#endif /* RTC_TAMPER2_SUPPORT */ #define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F #endif /* TAMP */ /** @@ -865,7 +910,9 @@ typedef struct #if defined(TAMP) #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E)) #else +#if defined(RTC_TAMPER2_SUPPORT) #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) +#endif /* RTC_TAMPER2_SUPPORT */ #endif /* TAMP */ /** @@ -876,7 +923,9 @@ typedef struct #if defined(TAMP) #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E)) #else +#if defined(RTC_TAMPER2_SUPPORT) #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) +#endif /* RTC_TAMPER2_SUPPORT */ #endif /* TAMP */ /** @@ -908,8 +957,9 @@ typedef struct * This parameter can be any combination of the following values: * @arg RTC_IT_TAMPALL: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) * @arg RTC_IT_TAMP3: Tamper3 interrupt + * (*) Not applicable to all devices. * @retval None */ #if defined(TAMP) @@ -925,8 +975,9 @@ typedef struct * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) * @arg RTC_IT_TAMP3: Tamper3 interrupt + * (*) Not applicable to all devices. * @retval None */ #if defined(TAMP) @@ -942,8 +993,9 @@ typedef struct * This parameter can be: * @arg RTC_IT_TAMPALL: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) * @arg RTC_IT_TAMP3: Tamper3 interrupt + * (*) Not applicable to all devices. * @retval Flag status */ #if defined(TAMP) @@ -958,8 +1010,9 @@ typedef struct * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag (*) * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * (*) Not applicable to all devices. * @retval Flag status */ #if defined(TAMP) @@ -974,8 +1027,9 @@ typedef struct * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag (*) * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * (*) Not applicable to all devices. * @retval None */ #if defined(TAMP) @@ -1658,18 +1712,22 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(RTC_TAMPER2_SUPPORT) HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER2_SUPPORT */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(RTC_TAMPER2_SUPPORT) void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER2_SUPPORT */ void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); #if defined(TAMP) -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); @@ -1679,8 +1737,8 @@ void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed); HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); #endif /* TAMP */ @@ -1700,7 +1758,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1717,8 +1775,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions * @{ */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); /** * @} */ @@ -1742,7 +1800,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); #if defined(TAMP) HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); #endif /* TAMP */ /** * @} @@ -1774,8 +1832,17 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Wakeup event */ /* Masks Definition */ +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)) +#else +#define RTC_TAMPER_X ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_3)) +#endif /* RTC_TAMPER2_SUPPORT */ + +#if defined(RTC_TAMPxIE_SUPPORT) #define RTC_TAMPER_X_INTERRUPT ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)) +#else +#define RTC_TAMPER_X_INTERRUPT RTC_IT_TAMPALL +#endif /* RTC_TAMPxIE_SUPPORT */ /** * @} @@ -1850,7 +1917,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_X) != 0x00U) && \ (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U)) -#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) \ +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) \ ((((__INTERRUPT__) & ( RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL )) != 0x00U) && \ (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL))) == 0x00U)) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h index 83fa74fded..a2536da2de 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h @@ -33,6 +33,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @defgroup SD SD * @brief SD HAL module driver @@ -315,12 +316,12 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ #define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ - /*!< number of transferred bytes does not match the block length */ +/*!< number of transferred bytes does not match the block length */ #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ - /*!< command or if there was an attempt to access a locked card */ +/*!< command or if there was an attempt to access a locked card */ #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -332,7 +333,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ #define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ - /*!< of erase sequence command was received */ +/*!< of erase sequence command was received */ #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -690,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -701,8 +702,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd); /** * @} */ @@ -787,6 +788,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h index 450e7dfad1..050005b0e3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDEx * @brief SD HAL extended module driver @@ -98,6 +99,7 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h new file mode 100644 index 0000000000..77cb250ebd --- /dev/null +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdio.h @@ -0,0 +1,600 @@ +/** + ********************************************************************************************************************** + * @file stm32h7xx_hal_sdio.h + * @author MCD Application Team + * @brief Header file of SDIO HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7xx_HAL_SDIO_H +#define STM32H7xx_HAL_SDIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_ll_sdmmc.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @defgroup SDIO SDIO + * @brief SDIO HAL module driver + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO Exported Types + * @{ + */ + +/** @defgroup SDIO_Exported_Types_Group1 SDIO State enumeration structure + * @{ + + */ +typedef enum +{ + HAL_SDIO_STATE_RESET = 0x00U, /*!< SDIO not yet initialized or disabled */ + HAL_SDIO_STATE_READY = 0x01U, /*!< SDIO initialized and ready for us */ + HAL_SDIO_STATE_BUSY = 0x02U, /*!< SDIO process ongoing */ +} HAL_SDIO_StateTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group2 SDIO Handle and Structure definition + * @{ + */ +/** + * @brief SDIO Card Common Control Register Structure definition + */ +typedef struct +{ + uint8_t sdio_revision; /*!< SDIO revision */ + uint8_t cccr_revision; /*!< CCCR version */ + uint8_t sd_spec_revision; /*!< SD revision */ + uint8_t bus_width_8Bit; /*!< SDIO bus width 8 bit support */ + uint32_t card_capability; /*!< SDIO card capability */ + uint32_t commonCISPointer; /*!< point to common CIS */ +} HAL_SDIO_CCCR_TypeDef; + +/** + * @brief sdio card FBR register(Function Basic Register) + */ +typedef struct +{ + uint8_t flags; /*!< SDIO current IO flags */ + uint8_t ioStdFunctionCode; /*!< SDIO current IO standard function code */ + uint8_t ioExtFunctionCode; /*!< SDIO current IO extended function code */ + uint32_t ioPointerToCIS; /*!< SDIO current IO pointer to CIS */ + uint32_t ioPointerToCSA; /*!< SDIO current IO pointer to CSA */ +} HAL_SDIO_FBR_t; + +/** + * @brief SDIO CMD52 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint8_t ReadAfterWrite; /*!< This is the read after write flag, it is used for write access only. */ + uint8_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_DirectCmd_TypeDef; + +/** + * @brief SDIO CMD53 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint32_t OpCode; /*!< Read/Write operation mode */ + uint32_t Block_Mode; /*!< Bytes or Blocks mode */ + uint32_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_ExtendedCmd_TypeDef; + +#define SDIO_InitTypeDef SDMMC_InitTypeDef +#define SDIO_TypeDef SDMMC_TypeDef + +/** + * @brief SDIO handle Structure definition + */ +typedef struct __SDIO_HandleTypeDef +{ + SDIO_TypeDef *Instance; /*!< SDIO registers base address */ + + SDIO_InitTypeDef Init; /*!< SDIO required parameters */ + + HAL_LockTypeDef Lock; /*!< SDIO locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SDIO Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SDIO Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SDIO Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SDIO Rx Transfer size */ + + uint32_t remaining_data; /*!< Remaining data to transfer */ + + uint32_t next_data_addr; /*!< SDIO Next data address */ + + __IO uint32_t next_reg_addr; /*!< SDIO Next register address */ + + uint16_t block_size; /*!< SDIO Block size */ + + __IO uint32_t Context; /*!< SDIO transfer context */ + + __IO HAL_SDIO_StateTypeDef State; /*!< SDIO card State */ + + __IO uint32_t ErrorCode; /*!< SDIO Card Error codes */ + + uint8_t IOFunctionMask; /*!< SDIO used to record current enabled io interrupt */ + + volatile uint8_t IOInterruptNbr; /*!< SDIO used to record total enabled io interrupt numbers */ + + void (* SDIO_IOFunction_Callback[SDIO_MAX_IO_NUMBER])(struct __SDIO_HandleTypeDef *hsdio, uint32_t func); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* RxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) + void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); + +} SDIO_HandleTypeDef; + +/** + * @} + */ +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** @defgroup SDIO_Exported_Types_Group3 SDIO Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SDIO_TX_CPLT_CB_ID = 0x00U, /*!< SDIO Tx Complete Callback ID */ + HAL_SDIO_RX_CPLT_CB_ID = 0x01U, /*!< SDIO Rx Complete Callback ID */ + HAL_SDIO_ERROR_CB_ID = 0x02U, /*!< SDIO Error Callback ID */ + HAL_SDIO_MSP_INIT_CB_ID = 0x10U, /*!< SDIO MspInit Callback ID */ + HAL_SDIO_MSP_DEINIT_CB_ID = 0x11U /*!< SDIO MspDeInit Callback ID */ +} HAL_SDIO_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group4 SDIO Callback pointer definition + * @{ + */ +typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Constants SDIO Exported Constants + * @{ + */ + +/** @defgroup SDIO_Exported_Constansts_Group1 SDIO Error status Structure definition + * @{ + */ +#define HAL_SDIO_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SDIO_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SDIO_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group2 SDIO context enumeration + * @{ + */ +#define SDIO_CONTEXT_NONE 0x00U /*!< None */ +#define SDIO_CONTEXT_READ_SINGLE_BLOCK 0x01U /*!< Read single block operation */ +#define SDIO_CONTEXT_READ_MULTIPLE_BLOCK 0x02U /*!< Read multiple blocks operation */ +#define SDIO_CONTEXT_WRITE_SINGLE_BLOCK 0x10U /*!< Write single block operation */ +#define SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK 0x20U /*!< Write multiple blocks operation */ +#define SDIO_CONTEXT_IT 0x08U /*!< Process in Interrupt mode */ +#define SDIO_CONTEXT_DMA 0x80U /*!< Process in DMA mode */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group3 SDIO Block mode enumeration + * @{ + */ +#define HAL_SDIO_MODE_BYTE SDMMC_SDIO_MODE_BYTE +#define HAL_SDIO_MODE_BLOCK SDMMC_SDIO_MODE_BLOCK +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group4 SDIO operation code enumeration + * @{ + */ +#define HAL_SDIO_OP_CODE_NO_INC SDMMC_SDIO_NO_INC +#define HAL_SDIO_OP_CODE_AUTO_INC SDMMC_SDIO_AUTO_INC +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group5 SDIO Read After Write(RAW) enumeration + * @{ + */ +#define HAL_SDIO_WRITE_ONLY SDMMC_SDIO_WO /*!< SDIO Write only */ +#define HAL_SDIO_READ_AFTER_WRITE SDMMC_SDIO_RAW /*!< SDIO Read after write */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group6 SDIO wire mode enumeration + * @{ + */ +#define HAL_SDIO_1_WIRE_MODE 0U /*!< SDIO wire support 1 wire */ +#define HAL_SDIO_4_WIRES_MODE 1U /*!< SDIO wire support 4 wires */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group7 SDIO Data block size enumeration + * @{ + */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1BYTE 1U /*!< SDIO data block size 1 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2BYTE 2U /*!< SDIO data block size 2 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_4BYTE 4U /*!< SDIO data block size 4 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_8BYTE 8U /*!< SDIO data block size 8 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_16BYTE 16U /*!< SDIO data block size 16 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_32BYTE 32U /*!< SDIO data block size 32 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_64BYTE 64U /*!< SDIO data block size 64 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_128BYTE 128U /*!< SDIO data block size 128 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_256BYTE 256U /*!< SDIO data block size 256 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_512BYTE 512U /*!< SDIO data block size 512 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE 1024U /*!< SDIO data block size 1024 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE 2048U /*!< SDIO data block size 2048 byte */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration + * @{ + */ +#define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ +#define HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED 1U /*!< SDIO bus width 8 bit is supported */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group9 SDIO Data rate definitions + * @{ + */ +#define HAL_SDIOS_DATA_RATE_SDR12 0U /*!< SDIO Data rate SDR12 */ +#define HAL_SDIOS_DATA_RATE_SDR25 1U /*!< SDIO Data rate SDR25 */ +#define HAL_SDIOS_DATA_RATE_SDR50 2U /*!< SDIO Data rate SDR50 */ +#define HAL_SDIOS_DATA_RATE_DDR50 3U /*!< SDIO Data rate DDR50 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group10 SDIO Functions definitions + * @{ + */ +#define HAL_SDIO_FUNCTION_0 0U /*!< SDIO function 0 */ +#define HAL_SDIO_FUNCTION_1 1U /*!< SDIO function 1 */ +#define HAL_SDIO_FUNCTION_2 2U /*!< SDIO function 2 */ +#define HAL_SDIO_FUNCTION_3 3U /*!< SDIO function 3 */ +#define HAL_SDIO_FUNCTION_4 4U /*!< SDIO function 4 */ +#define HAL_SDIO_FUNCTION_5 5U /*!< SDIO function 5 */ +#define HAL_SDIO_FUNCTION_6 6U /*!< SDIO function 6 */ +#define HAL_SDIO_FUNCTION_7 7U /*!< SDIO function 7 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group11 SDIO FBR definitions + * @{ + */ +#define HAL_SDIO_FBR_SUPPORT_CSA 1U /*!< SDIO function support CSA */ +#define HAL_SDIO_FBR_SUPPORT_POWER_SELECTION 1U /*!< SDIO function support power selection */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_macros SDIO Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** + * @brief Enable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SDIO flag is set or not. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @ref SDMMC_LL_Flags. + * @retval The new state of SDIO FLAG (SET or RESET). + */ +#define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SDIO's pending flags. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of @ref SDMMC_LL_Flags. + * @retval None + */ +#define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SDIO interrupt has occurred or not. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of @ref SDMMC_LL_Interrupt_sources. + * @retval The new state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO interrupt is enabled or not. + * @param __HANDLE__ : SDIO handle. + * @param __INTERRUPT__ : specifies the SDMMC interrupt source to check. + * @retval The state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + __SDMMC_GET_IT_SOURCE((__HANDLE__)->Instance, (__INTERRUPT__)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO Exported Functions + * @{ + */ +/** @defgroup SDIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide); +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed); + +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize); +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate); + +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr); +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group3 Process functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group4 IRQHandler and callback functions + * @{ + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func); +#if (USE_SDIO_TRANSCEIVER != 0U) +/* Callback to switch in 1.8V mode */ +void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); +#endif /* USE_SDIO_TRANSCEIVER */ + +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio); +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group6 Peripheral IO interrupt + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Types SDIO Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines ---------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Defines SDIO Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Variables SDIO Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Constants SDIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Macros SDIO Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions_Prototypes SDIO Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_SDIO_H */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h index cee1ffdd39..e90d546c25 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h @@ -211,7 +211,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); * @{ */ /* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h index 4180c713c3..0a9e11ae26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h @@ -92,7 +92,7 @@ typedef struct SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */ - uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ + const uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */ @@ -122,7 +122,7 @@ typedef struct void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } SWPMI_HandleTypeDef; @@ -145,7 +145,7 @@ typedef enum * @brief SWPMI callback pointer definition */ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} @@ -170,7 +170,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); #define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080) /*!< Transceiver not ready */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) #define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} */ @@ -258,14 +258,14 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @retval None */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) -#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @brief Enable the SWPMI peripheral. @@ -401,7 +401,8 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) +#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__))\ + == (__IT__)) ? SET : RESET) /** * @} @@ -424,14 +425,15 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, pSWPMI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi); HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi); @@ -444,8 +446,8 @@ void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi); /* Peripheral Control and State functions ************************************/ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi); -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi); +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h index c6fced0281..5f0db22055 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h @@ -1233,7 +1233,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1248,8 +1248,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h index 518c0aa35b..28ba1ed155 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h @@ -706,8 +706,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h index 8f2e4dc190..bee4437edb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h index c8f38afa43..8ca787b35c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h @@ -386,12 +386,12 @@ extern "C" { #endif /* ADC_VER_V5_3 */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) +#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) #define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor , temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */ #else -#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */ #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ @@ -2600,7 +2600,7 @@ typedef struct * (1) Available on devices with several ADC instances. * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; @@ -2688,7 +2688,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } @@ -2750,7 +2750,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } @@ -2887,7 +2887,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ @@ -3059,7 +3059,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * (1): Specific to ADC instance: ADC1, ADC2 * (2): Specific to ADC instance: ADC3 */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { #if defined (ADC_VER_V5_3) @@ -3204,7 +3204,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } @@ -3285,7 +3285,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_19 * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected) */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) if (ADCx != ADC3) @@ -3458,7 +3458,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3484,7 +3484,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3526,7 +3526,7 @@ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offset * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(const ADC_TypeDef *ADCx, uint32_t Offsety) { return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL)); } @@ -3581,7 +3581,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -3649,7 +3649,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3713,7 +3713,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3787,7 +3787,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); if (ADCx == ADC3) @@ -3898,7 +3898,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); @@ -3925,7 +3925,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } @@ -3960,7 +3960,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } @@ -4105,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } @@ -4160,7 +4160,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } @@ -4354,7 +4354,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); @@ -4400,7 +4400,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } @@ -4438,7 +4438,7 @@ __STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx) CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN); } -__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL); } @@ -4515,7 +4515,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t D * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(const ADC_TypeDef *ADCx) { if (ADCx == ADC3) { @@ -4544,7 +4544,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @arg @ref LL_ADC_REG_DFSDM_TRANSFER */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT)); } @@ -4584,7 +4584,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } @@ -4685,7 +4685,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); @@ -4712,7 +4712,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } @@ -4747,7 +4747,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } @@ -4794,7 +4794,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } @@ -4827,7 +4827,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } @@ -4962,7 +4962,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) @@ -5014,7 +5014,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } @@ -5075,7 +5075,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMo * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } @@ -5491,7 +5491,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); @@ -5623,7 +5623,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_19 * @retval 0: channel in single-ended mode, else: channel in differential mode */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); @@ -5910,7 +5910,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1. */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); @@ -6085,7 +6085,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -6245,7 +6245,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { if (ADCx == ADC3) { @@ -6318,7 +6318,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } @@ -6364,7 +6364,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } @@ -6441,7 +6441,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { #if defined(ADC_VER_V5_V90) if(ADCx==ADC3) @@ -6478,7 +6478,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -6536,7 +6536,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) * @param ADCx ADC instance * @retval 0: Boost disabled 1: Boost enabled */ -__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(const ADC_TypeDef *ADCx) { if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */ { @@ -6598,7 +6598,7 @@ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint3 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } @@ -6689,7 +6689,7 @@ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF)); } @@ -6767,7 +6767,7 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C * (6) Parameter available only if ADC resolution is 12 bits. * (7) Parameter available only if ADC resolution is 16 or 14 bits. */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } @@ -6829,7 +6829,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } @@ -6878,7 +6878,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -6938,7 +6938,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -6949,7 +6949,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -7003,7 +7003,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t Calibra * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -7070,7 +7070,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -7081,7 +7081,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -7095,7 +7095,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7110,7 +7110,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7125,7 +7125,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7140,7 +7140,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7155,7 +7155,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7170,7 +7170,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7195,7 +7195,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) @@ -7265,7 +7265,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } @@ -7276,7 +7276,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } @@ -7298,7 +7298,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7325,7 +7325,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7352,7 +7352,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7379,7 +7379,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7406,7 +7406,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7433,7 +7433,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7459,7 +7459,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -7470,7 +7470,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -7481,7 +7481,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -7492,7 +7492,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -7503,7 +7503,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -7514,7 +7514,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } @@ -7525,7 +7525,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } @@ -7536,7 +7536,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } @@ -7547,7 +7547,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); } @@ -7558,7 +7558,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -7569,7 +7569,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -7580,7 +7580,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -7716,7 +7716,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } @@ -7728,7 +7728,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } @@ -7740,7 +7740,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7752,7 +7752,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7764,7 +7764,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } @@ -7776,7 +7776,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } @@ -7788,7 +7788,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } @@ -7800,7 +7800,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } @@ -7812,7 +7812,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } @@ -7824,7 +7824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } @@ -7836,7 +7836,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } @@ -7848,7 +7848,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } @@ -7860,7 +7860,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } @@ -7872,7 +7872,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } @@ -7884,7 +7884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } @@ -7896,7 +7896,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } @@ -7908,7 +7908,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } @@ -7920,7 +7920,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } @@ -7932,7 +7932,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } @@ -7944,7 +7944,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } @@ -7956,7 +7956,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } @@ -8230,7 +8230,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -8242,7 +8242,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -8254,7 +8254,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -8266,7 +8266,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -8278,7 +8278,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -8290,7 +8290,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } @@ -8302,7 +8302,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } @@ -8314,7 +8314,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } @@ -8326,7 +8326,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -8338,7 +8338,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -8350,7 +8350,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -8365,7 +8365,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h index 8db1b7cc6f..72b747a64e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h @@ -132,7 +132,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX2_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ @@ -499,7 +499,7 @@ LL_BDMA_CHANNEL_7) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -521,7 +521,7 @@ __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -543,7 +543,7 @@ __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -584,7 +584,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_BDMA_ConfigTransfer(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -613,7 +613,7 @@ __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -640,7 +640,7 @@ __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint3 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -668,7 +668,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, u * @arg @ref LL_BDMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_BDMA_SetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -693,7 +693,7 @@ __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint * @arg @ref LL_BDMA_MODE_NORMAL * @arg @ref LL_BDMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -719,7 +719,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -744,7 +744,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_PERIPH_INCREMENT * @arg @ref LL_BDMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -770,7 +770,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -795,7 +795,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_MEMORY_INCREMENT * @arg @ref LL_BDMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -822,7 +822,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_BDMA_SetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD * @arg @ref LL_BDMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -875,7 +875,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_BDMA_SetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -901,7 +901,7 @@ __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD * @arg @ref LL_BDMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -929,7 +929,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -956,7 +956,7 @@ __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_PRIORITY_HIGH * @arg @ref LL_BDMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -982,7 +982,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, ui * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_BDMA_SetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1007,7 +1007,7 @@ __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1033,7 +1033,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) +__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1057,7 +1057,7 @@ __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t C * @arg @ref LL_BDMA_CURRENTTARGETMEM0 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1101,7 +1101,7 @@ __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_ * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1123,7 +1123,7 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { register uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1154,7 +1154,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_BDMA_ConfigAddresses(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1191,7 +1191,7 @@ __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Chann * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1216,7 +1216,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_BDMA_SetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1239,7 +1239,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1262,7 +1262,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1287,7 +1287,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1312,7 +1312,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1358,7 +1358,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1381,7 +1381,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) +__STATIC_INLINE void LL_BDMA_SetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1403,7 +1403,7 @@ __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1449,7 +1449,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_BDMA_SetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) { UNUSED(BDMAx); MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Chan * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel) { UNUSED(BDMAx); return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -1513,7 +1513,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); } @@ -1524,7 +1524,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1535,7 +1535,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1546,7 +1546,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1557,7 +1557,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1568,7 +1568,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1579,7 +1579,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1590,7 +1590,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); } @@ -1611,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1622,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1633,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1644,7 +1644,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1655,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1677,7 +1677,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1688,7 +1688,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1710,7 +1710,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1721,7 +1721,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1743,7 +1743,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1754,7 +1754,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1765,7 +1765,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1776,7 +1776,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); } @@ -1787,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1798,7 +1798,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1809,7 +1809,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1820,7 +1820,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1831,7 +1831,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1842,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -2264,7 +2264,7 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2286,7 +2286,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2308,7 +2308,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2330,7 +2330,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2352,7 +2352,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2374,7 +2374,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2396,7 +2396,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2418,7 +2418,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2440,7 +2440,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h index 44fd717d1c..0a0ba77701 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h @@ -341,7 +341,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * @arg @ref LL_COMP_WINDOWMODE_DISABLE * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { return (uint32_t)(READ_BIT(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE)); } @@ -378,7 +378,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_PWRMODE)); } @@ -480,7 +480,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { #if defined (COMP_CFGRx_INP2SEL) return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL)); @@ -549,7 +549,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 * @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)); } @@ -580,7 +580,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_HYST)); } @@ -615,7 +615,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_POLARITY)); } @@ -660,7 +660,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_BLANKING)); } @@ -685,7 +685,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_AF_PK2 * @retval None */ -__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uint32_t CompAFx) +__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(const COMP_TypeDef *COMPx, uint32_t CompAFx) { MODIFY_REG(COMP12->OR, 0x7FFUL, (COMPx == COMP1) ? ((~CompAFx) & 0x7FFUL) : CompAFx); } @@ -706,7 +706,7 @@ __STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uin * @arg @ref LL_COMP_AF_PI4 * @arg @ref LL_COMP_AF_PK2 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(COMP_TypeDef *COMPx ) +__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(const COMP_TypeDef *COMPx ) { return (uint32_t) ((COMPx == COMP1) ? ((~COMP12->OR) & 0x7FFUL) : (COMP12->OR & 0x7FFUL)); } @@ -751,7 +751,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_EN) == (COMP_CFGRx_EN)) ? 1UL : 0UL); } @@ -778,7 +778,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_LOCK) == (COMP_CFGRx_LOCK)) ? 1UL : 0UL); } @@ -803,7 +803,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -829,7 +829,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -847,7 +847,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval None */ -__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -895,7 +895,7 @@ __STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h index fe1f6f9efc..f36ebfc0ef 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h index c05815a94f..5195c3b7e6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -140,7 +140,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX1_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ @@ -486,7 +486,7 @@ typedef struct * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -508,7 +508,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -530,7 +530,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -571,7 +571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 *@retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -599,7 +599,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -624,7 +624,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -651,7 +651,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_MODE_PFCTRL * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -677,7 +677,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t * @arg @ref LL_DMA_MODE_CIRCULAR * @arg @ref LL_DMA_MODE_PFCTRL */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -702,7 +702,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_PERIPH_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -726,7 +726,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @arg @ref LL_DMA_PERIPH_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_MEMORY_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -775,7 +775,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -801,7 +801,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -826,7 +826,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -877,7 +877,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 * @retval None */ -__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_OFFSETSIZE_PSIZE * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 */ -__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -953,7 +953,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -979,7 +979,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1001,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1023,7 +1023,7 @@ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_ * @param NbData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1072,7 +1072,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1396,7 +1396,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream) { return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1421,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t St * @arg @ref LL_DMA_MBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1447,7 +1447,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_MBURST_INC8 * @arg @ref LL_DMA_MBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1500,7 +1500,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_PBURST_INC8 * @arg @ref LL_DMA_PBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1525,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1549,7 +1549,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 * @arg @ref LL_DMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1615,9 +1615,9 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); } @@ -1643,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_FIFOSTATUS_EMPTY * @arg @ref LL_DMA_FIFOSTATUS_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1665,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1687,7 +1687,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1714,7 +1714,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1740,7 +1740,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1801,7 +1801,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1837,7 +1837,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param PeriphAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1885,7 +1885,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1908,7 +1908,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1933,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Str * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1981,7 +1981,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2004,7 +2004,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2027,7 +2027,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Str * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2049,7 +2049,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t St * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); } @@ -2081,7 +2081,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); } @@ -2092,7 +2092,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); } @@ -2103,7 +2103,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); } @@ -2114,7 +2114,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); } @@ -2125,7 +2125,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); } @@ -2136,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); } @@ -2147,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); } @@ -2158,7 +2158,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); } @@ -2169,7 +2169,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); } @@ -2180,7 +2180,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); } @@ -2191,7 +2191,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); } @@ -2202,7 +2202,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); } @@ -2213,7 +2213,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); } @@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); } @@ -2257,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); } @@ -2268,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); } @@ -2279,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); } @@ -2290,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); } @@ -2301,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); } @@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); } @@ -2323,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); } @@ -2334,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); } @@ -2345,7 +2345,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); } @@ -2356,7 +2356,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); } @@ -2367,7 +2367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); } @@ -2378,7 +2378,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); } @@ -2389,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); } @@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); } @@ -2411,7 +2411,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); } @@ -2422,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); } @@ -2433,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); } @@ -2444,7 +2444,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); } @@ -2455,7 +2455,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); } @@ -2466,7 +2466,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); } @@ -2477,7 +2477,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); } @@ -2488,7 +2488,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); } @@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); } @@ -2967,7 +2967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2989,7 +2989,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3011,7 +3011,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3055,7 +3055,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3077,7 +3077,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3099,7 +3099,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3121,7 +3121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3143,7 +3143,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3165,7 +3165,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3187,7 +3187,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3209,7 +3209,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3231,7 +3231,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3253,7 +3253,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3275,7 +3275,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h index daea475843..905cbc7eaf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h @@ -582,7 +582,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } @@ -619,7 +619,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } @@ -644,7 +644,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } @@ -679,7 +679,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); } @@ -712,7 +712,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); } @@ -739,7 +739,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_ * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); } @@ -766,7 +766,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } @@ -794,7 +794,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); } @@ -821,7 +821,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); } @@ -844,7 +844,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @param DMA2Dx DMA2D Instance * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); } @@ -867,7 +867,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint * @param DMA2Dx DMA2D Instance * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); } @@ -890,7 +890,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO * @param DMA2Dx DMA2D Instance * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); } @@ -913,7 +913,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O * @param DMA2Dx DMA2D Instance * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); } @@ -934,8 +934,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) { - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); + WRITE_REG(DMA2Dx->OCOLR, OutputColor); } /** @@ -950,7 +949,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out * @param DMA2Dx DMA2D Instance * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); @@ -974,7 +973,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L * @param DMA2Dx DMA2D Instance * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); } @@ -997,7 +996,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi * @param DMA2Dx DMA2D Instance * @retval Dead time value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); } @@ -1030,7 +1029,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } @@ -1057,7 +1056,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); } @@ -1079,7 +1078,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } @@ -1124,7 +1123,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); } @@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); } @@ -1176,7 +1175,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); } @@ -1203,7 +1202,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); } @@ -1230,7 +1229,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); } @@ -1253,7 +1252,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); } @@ -1293,7 +1292,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); } @@ -1316,7 +1315,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); } @@ -1339,7 +1338,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); } @@ -1362,7 +1361,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); } @@ -1385,7 +1384,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); } @@ -1412,7 +1411,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); } @@ -1441,7 +1440,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint * @arg @ref LL_DMA2D_CSS_422 * @arg @ref LL_DMA2D_CSS_420 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); } @@ -1471,7 +1470,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); } @@ -1493,7 +1492,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } @@ -1538,7 +1537,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); } @@ -1567,7 +1566,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); } @@ -1590,7 +1589,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); } @@ -1617,7 +1616,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); } @@ -1644,7 +1643,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); } @@ -1667,7 +1666,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); } @@ -1707,7 +1706,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); } @@ -1730,7 +1729,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); } @@ -1753,7 +1752,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); } @@ -1776,7 +1775,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); } @@ -1799,7 +1798,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); } @@ -1826,7 +1825,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); } @@ -1850,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } @@ -1861,7 +1860,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } @@ -1872,7 +1871,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } @@ -1883,7 +1882,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } @@ -1894,7 +1893,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } @@ -1905,7 +1904,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } @@ -2122,7 +2121,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } @@ -2133,7 +2132,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } @@ -2144,7 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } @@ -2155,7 +2154,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } @@ -2166,7 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } @@ -2177,7 +2176,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2193,16 +2192,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) * @{ */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h index bf4cffa0bc..be9b2fc40f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h @@ -726,7 +726,7 @@ extern "C" { * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -919,7 +919,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -950,7 +950,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -980,7 +980,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1015,7 +1015,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1109,7 +1109,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1169,7 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1199,7 +1199,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1229,7 +1229,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1284,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1338,7 +1338,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1360,7 +1360,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1400,7 +1400,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1427,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1453,7 +1453,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1477,7 +1477,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1561,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1607,7 +1607,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1628,7 +1628,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1641,7 +1641,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1654,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1667,7 +1667,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1680,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1693,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1706,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1719,7 +1719,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1758,7 +1758,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1784,7 +1784,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1797,7 +1797,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1810,7 +1810,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1823,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1836,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1849,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1875,7 +1875,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1901,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1914,7 +1914,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1927,7 +1927,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1940,7 +1940,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1966,7 +1966,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1979,7 +1979,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1992,7 +1992,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2005,7 +2005,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2018,7 +2018,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2057,7 +2057,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2083,7 +2083,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2109,7 +2109,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2122,7 +2122,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2135,7 +2135,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2148,7 +2148,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2161,7 +2161,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2174,7 +2174,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2187,7 +2187,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2200,7 +2200,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2226,7 +2226,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2239,7 +2239,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2277,7 +2277,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2307,7 +2307,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2337,7 +2337,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2359,7 +2359,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2381,7 +2381,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2403,7 +2403,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h index 8e92c3d4d1..5edb287d86 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h index 3d34898e39..7509bcedbf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h @@ -190,61 +190,62 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ } FMC_NORSRAM_InitTypeDef; /** @@ -288,7 +289,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; /** @@ -1056,11 +1057,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -1086,11 +1087,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1101,7 +1102,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -1117,9 +1118,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1131,7 +1132,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h index b51f9d3bf9..b099741d98 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h @@ -309,7 +309,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); } @@ -377,7 +377,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); } @@ -515,7 +515,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); } @@ -591,7 +591,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); @@ -669,7 +669,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * @@ -741,7 +741,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -752,7 +752,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -771,7 +771,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -800,7 +800,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -823,7 +823,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -954,7 +954,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h index d3f3608fe1..741d758b9d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h @@ -1972,7 +1972,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT { uint32_t shift = ((3U * ADCTrig) & 0x1FU); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); } @@ -2247,7 +2247,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2464,7 +2464,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -3138,7 +3138,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3158,7 +3158,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3178,7 +3178,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3209,7 +3209,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3238,7 +3238,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3268,7 +3268,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3290,7 +3290,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3313,7 +3313,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3335,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3358,7 +3358,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3380,7 +3380,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3405,7 +3405,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3429,7 +3429,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3454,7 +3454,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3478,7 +3478,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3503,7 +3503,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3527,7 +3527,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3552,7 +3552,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3576,7 +3576,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3663,7 +3663,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3743,7 +3743,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3763,7 +3763,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3783,7 +3783,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3871,7 +3871,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -3957,7 +3957,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -3977,7 +3977,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -3997,7 +3997,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4017,7 +4017,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -4062,7 +4062,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4103,7 +4103,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4124,7 +4124,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4145,7 +4145,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4165,7 +4165,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4195,7 +4195,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4225,7 +4225,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4255,7 +4255,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -4277,7 +4277,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4442,7 +4442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeD { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4464,7 +4464,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4524,7 +4524,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4581,7 +4581,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4627,7 +4627,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4670,7 +4670,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4704,7 +4704,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4733,7 +4733,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4761,7 +4761,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4782,7 +4782,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4802,7 +4802,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4825,7 +4825,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4847,7 +4847,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4868,7 +4868,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4888,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4911,7 +4911,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -4933,7 +4933,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -4953,7 +4953,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -4973,7 +4973,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -4993,7 +4993,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5013,7 +5013,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5049,7 +5049,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5089,7 +5089,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5125,7 +5125,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5157,7 +5157,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5185,7 +5185,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5224,7 +5224,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5260,7 +5260,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5389,7 +5389,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5509,7 +5509,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5630,7 +5630,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5750,7 +5750,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5793,7 +5793,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5823,7 +5823,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5851,7 +5851,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5881,7 +5881,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -5909,7 +5909,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5940,7 +5940,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5968,7 +5968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6001,7 +6001,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6031,7 +6031,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6061,7 +6061,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6089,7 +6089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6119,7 +6119,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6147,7 +6147,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6176,7 +6176,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -6214,7 +6214,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6242,7 +6242,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -6323,7 +6323,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6363,7 +6363,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6401,7 +6401,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6440,7 +6440,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6476,7 +6476,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6516,7 +6516,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6554,7 +6554,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6587,7 +6587,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6618,7 +6618,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6770,7 +6770,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6799,7 +6799,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6824,8 +6824,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6853,7 +6853,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6878,8 +6878,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6921,7 +6921,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6960,8 +6960,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7017,7 +7017,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7041,7 +7041,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7065,7 +7065,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7089,7 +7089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -7765,7 +7765,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7787,7 +7787,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -7810,7 +7810,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -7833,7 +7833,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -7856,7 +7856,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7878,7 +7878,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -7901,7 +7901,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -7923,7 +7923,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -7946,7 +7946,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -7991,7 +7991,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8013,7 +8013,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -8034,7 +8034,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8054,7 +8054,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -8075,7 +8075,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8095,7 +8095,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -8116,7 +8116,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8136,7 +8136,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -8157,7 +8157,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8177,7 +8177,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -8198,7 +8198,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8218,7 +8218,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -8239,7 +8239,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8259,7 +8259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -8280,7 +8280,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8300,7 +8300,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -8321,7 +8321,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8341,7 +8341,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } @@ -8636,7 +8636,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8658,7 +8658,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8680,7 +8680,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); } @@ -8703,7 +8703,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8725,7 +8725,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8747,7 +8747,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); } @@ -8770,7 +8770,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8792,7 +8792,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8814,7 +8814,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); } @@ -8837,7 +8837,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8859,7 +8859,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8881,7 +8881,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); } @@ -8904,7 +8904,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8926,7 +8926,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8948,7 +8948,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); } @@ -8971,7 +8971,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -8993,7 +8993,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9015,7 +9015,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); } @@ -9036,7 +9036,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9056,7 +9056,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9076,7 +9076,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); } @@ -9097,7 +9097,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9117,7 +9117,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9137,7 +9137,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); } @@ -9158,7 +9158,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9178,7 +9178,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9198,7 +9198,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); } @@ -9219,7 +9219,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9239,7 +9239,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9259,7 +9259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); } @@ -9280,7 +9280,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9300,7 +9300,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9320,7 +9320,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); } @@ -9341,7 +9341,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9361,7 +9361,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9381,7 +9381,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); } @@ -9402,7 +9402,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9422,7 +9422,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9442,7 +9442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); } @@ -9463,7 +9463,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9483,7 +9483,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9503,7 +9503,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); } @@ -9567,7 +9567,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9589,7 +9589,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9611,7 +9611,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); } @@ -9634,7 +9634,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9656,7 +9656,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9678,7 +9678,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); } @@ -9701,7 +9701,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9723,7 +9723,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9745,7 +9745,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); } @@ -9768,7 +9768,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9790,7 +9790,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9812,7 +9812,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); } @@ -9835,7 +9835,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9857,7 +9857,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9879,7 +9879,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); } @@ -9902,7 +9902,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9924,7 +9924,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9946,7 +9946,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); } @@ -9967,7 +9967,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -9987,7 +9987,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10007,7 +10007,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); } @@ -10028,7 +10028,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10048,7 +10048,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10068,7 +10068,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); } @@ -10089,7 +10089,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10109,7 +10109,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10129,7 +10129,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); } @@ -10150,7 +10150,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10170,7 +10170,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10190,7 +10190,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); } @@ -10211,7 +10211,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10231,7 +10231,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10251,7 +10251,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); } @@ -10272,7 +10272,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10292,7 +10292,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10312,7 +10312,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); } @@ -10333,7 +10333,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10353,7 +10353,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10373,7 +10373,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); } @@ -10394,7 +10394,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10414,7 +10414,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10434,7 +10434,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); } @@ -10447,7 +10447,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions * @{ */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx); /** * @} */ @@ -10473,4 +10473,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif /* STM32H7xx_LL_HRTIM_H */ - diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h index cff88b5cd5..689b7e57e8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h @@ -163,7 +163,7 @@ extern "C" { * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); } @@ -178,7 +178,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_COREID_CPU1 * @arg @ref LL_HSEM_COREID_CPU2 */ -__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); } @@ -190,7 +190,7 @@ __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval Process number. Value between Min_Data=0 and Max_Data=255 */ -__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); } @@ -236,7 +236,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ -__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); } @@ -261,7 +261,7 @@ __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 0 semaphore is free, 1 semaphore is locked */ -__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) * @param HSEMx HSEM Instance. * @retval key to unlock all semaphore from the same core */ -__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) { return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -586,7 +586,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -736,7 +736,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_ * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -827,7 +827,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -872,7 +872,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h index d34acc2622..743c91730e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h index fe66becb5b..2f362a4e74 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h @@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h index 8b80c7d811..a55cb82897 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h @@ -688,7 +688,7 @@ typedef struct * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -718,7 +718,7 @@ __STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -748,7 +748,7 @@ __STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -778,7 +778,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_GenerateSWRequest(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -814,7 +814,7 @@ __STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE or @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -881,7 +881,7 @@ __STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -914,7 +914,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -947,7 +947,7 @@ __STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -980,7 +980,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1013,7 +1013,7 @@ __STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1083,7 +1083,7 @@ __STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1143,7 +1143,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, ui * @param BufferXferLength This parameter can be a value Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) +__STATIC_INLINE void LL_MDMA_ConfigTransfer(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1174,7 +1174,7 @@ __STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1204,7 +1204,7 @@ __STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1234,7 +1234,7 @@ __STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1267,7 +1267,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) +__STATIC_INLINE void LL_MDMA_SetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1300,7 +1300,7 @@ __STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) +__STATIC_INLINE void LL_MDMA_SetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1370,7 +1370,7 @@ __STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) +__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1469,7 +1469,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1529,7 +1529,7 @@ __STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1560,7 +1560,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t * @param Length Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) +__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1592,7 +1592,7 @@ __STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32 * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1631,7 +1631,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) +__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1670,7 +1670,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) +__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1748,7 +1748,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1783,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1818,7 +1818,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1923,7 +1923,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) +__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1993,7 +1993,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) +__STATIC_INLINE void LL_MDMA_SetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2028,7 +2028,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2062,7 +2062,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) +__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2130,7 +2130,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) +__STATIC_INLINE void LL_MDMA_SetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2164,7 +2164,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2197,7 +2197,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2230,7 +2230,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Cha * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_SetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2261,7 +2261,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2292,7 +2292,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t * @param BlockRepeatCount Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2324,7 +2324,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Cha * @retval Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2358,7 +2358,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2393,7 +2393,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2426,7 +2426,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2459,7 +2459,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2492,7 +2492,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2526,7 +2526,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) +__STATIC_INLINE void LL_MDMA_ConfigAddresses(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2557,7 +2557,7 @@ __STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Chann * @param SrcAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) +__STATIC_INLINE void LL_MDMA_SetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2588,7 +2588,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2619,7 +2619,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t * @param DestAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) +__STATIC_INLINE void LL_MDMA_SetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2650,7 +2650,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2684,7 +2684,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint * @param DestAdrUpdateValue Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2716,7 +2716,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @param DestAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2748,7 +2748,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, u * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2779,7 +2779,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMA * @param SrcAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2810,7 +2810,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2841,7 +2841,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx * @param LinkAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) +__STATIC_INLINE void LL_MDMA_SetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2872,7 +2872,7 @@ __STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2906,7 +2906,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI or @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2941,7 +2941,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) +__STATIC_INLINE void LL_MDMA_SetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2974,7 +2974,7 @@ __STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3007,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) +__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3040,7 +3040,7 @@ __STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3108,7 +3108,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_ * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) +__STATIC_INLINE void LL_MDMA_SetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3176,7 +3176,7 @@ __STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3207,7 +3207,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Chan * @param MaskAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) +__STATIC_INLINE void LL_MDMA_SetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3238,7 +3238,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3269,7 +3269,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @param MaskData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) +__STATIC_INLINE void LL_MDMA_SetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3300,7 +3300,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3333,7 +3333,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Chann * @arg @ref LL_MDMA_WRITE_ERROR * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3364,7 +3364,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3402,7 +3402,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(const MDMA_TypeDef *MDMAx, uint32_t Channel) { return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } @@ -3430,7 +3430,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3460,7 +3460,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3490,7 +3490,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3520,7 +3520,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3550,7 +3550,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3580,7 +3580,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3610,7 +3610,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3640,7 +3640,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3670,7 +3670,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3700,7 +3700,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3730,7 +3730,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3760,7 +3760,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3790,7 +3790,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3820,7 +3820,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3850,7 +3850,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3888,7 +3888,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3918,7 +3918,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3948,7 +3948,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3978,7 +3978,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4008,7 +4008,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4038,7 +4038,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4068,7 +4068,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4098,7 +4098,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4128,7 +4128,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4158,7 +4158,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4188,7 +4188,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4218,7 +4218,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4248,7 +4248,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4278,7 +4278,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4308,7 +4308,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h index 03ab42c701..abd81e3e43 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h @@ -392,7 +392,7 @@ __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode) * @arg @ref LL_OPAMP_MODE_FUNCTIONAL * @arg @ref LL_OPAMP_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON)); } @@ -434,7 +434,7 @@ __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS * @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS */ -__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL)); } @@ -469,7 +469,7 @@ __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)); } @@ -498,7 +498,7 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power * @arg @ref LL_OPAMP_POWERMODE_NORMAL * @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) { uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM)); @@ -536,7 +536,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL)); } @@ -572,7 +572,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *OPAMPx) { uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); @@ -611,7 +611,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t Tr * @arg @ref LL_OPAMP_TRIMMING_FACTORY * @arg @ref LL_OPAMP_TRIMMING_USER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM)); } @@ -658,7 +658,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin * using two trimming steps (one with each transistors differential * pair NMOS and PMOS) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *OPAMPx) { uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); @@ -675,7 +675,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT)?1UL:0UL); } @@ -728,7 +728,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P * @arg @ref LL_OPAMP_TRIMMING_PMOS * @retval 0x0...0x1F */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); @@ -779,7 +779,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN))?1UL:0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h index 62039d0e6b..cf1ab84f12 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h @@ -680,7 +680,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h index 85e6fadda7..d792373e92 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h @@ -252,7 +252,9 @@ typedef struct #define LL_RTC_ISR_ITSF RTC_ISR_ITSF #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#endif /* RTC_TAMPER2_SUPPORT */ #define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F #define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF #define LL_RTC_ISR_TSF RTC_ISR_TSF @@ -280,9 +282,11 @@ typedef struct #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE #if !defined(TAMP) +#if defined(RTC_TAMPxIE_SUPPORT) #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE +#endif /* RTC_TAMPxIE_SUPPORT */ #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE #endif /* !TAMP */ /** @@ -527,13 +531,17 @@ typedef struct * @{ */ #define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ +#endif /* RTC_TAMPER2_SUPPORT */ #define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ /** * @} */ /** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @note These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 devices, + * and have been kept for backward compatibility. * @{ */ #define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ @@ -544,6 +552,8 @@ typedef struct */ /** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @note These values are not applicable to the STM32H723/33, STM32H725/35 and STM32H730 devices, + * and have been kept for backward compatibility. * @{ */ #define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ @@ -903,7 +913,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -935,7 +945,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -992,7 +1002,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); } @@ -1078,7 +1088,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1112,7 +1122,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } @@ -1173,7 +1183,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1184,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1376,7 +1386,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1411,7 +1421,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1446,7 +1456,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1481,7 +1491,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1535,7 +1545,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1575,7 +1585,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } @@ -1617,7 +1627,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1674,7 +1684,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1713,7 +1723,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1767,7 +1777,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1797,7 +1807,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1865,7 +1875,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1944,7 +1954,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1994,7 +2004,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -2031,7 +2041,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -2058,7 +2068,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -2086,7 +2096,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2114,7 +2124,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2142,7 +2152,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2214,7 +2224,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2237,7 +2247,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2310,7 +2320,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2360,7 +2370,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2397,7 +2407,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2424,7 +2434,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2452,7 +2462,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2480,7 +2490,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2508,7 +2518,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2580,7 +2590,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2603,7 +2613,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2689,7 +2699,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2702,7 +2712,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2715,7 +2725,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2728,7 +2738,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2741,7 +2751,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2759,7 +2769,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2778,7 +2788,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2803,7 +2813,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2816,7 +2826,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2833,7 +2843,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2844,7 +2854,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -2916,13 +2926,14 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) /** * @brief Enable RTC_TAMPx input detection * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable - * TAMPCR TAMP2E LL_RTC_TAMPER_Enable + * TAMPCR TAMP2E LL_RTC_TAMPER_Enable (*) * TAMPCR TAMP3E LL_RTC_TAMPER_Enable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_2 (*) * @arg @ref LL_RTC_TAMPER_3 + * (*) Not applicable to all devices. * * @retval None */ @@ -2934,13 +2945,14 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) /** * @brief Clear RTC_TAMPx input detection * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable - * TAMPCR TAMP2E LL_RTC_TAMPER_Disable + * TAMPCR TAMP2E LL_RTC_TAMPER_Disable (*) * TAMPCR TAMP3E LL_RTC_TAMPER_Disable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_2 (*) * @arg @ref LL_RTC_TAMPER_3 + * (*) Not applicable to all devices. * * @retval None */ @@ -2951,6 +2963,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) /** * @brief Enable Tamper mask flag + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @note Associated Tamper IT must not enabled when tamper mask is set. * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask @@ -2970,6 +2984,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Disable Tamper mask flag + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask @@ -2988,6 +3004,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Enable backup register erase after Tamper event detection + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP @@ -3006,6 +3024,8 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta /** * @brief Disable backup register erase after Tamper event detection + * @note This API shall not be used with STM32H723/33, STM32H725/35 and STM32H730 devices, + * and has been kept for backward compatibility. * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP @@ -3070,7 +3090,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); } @@ -3101,7 +3121,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); } @@ -3140,7 +3160,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); } @@ -3148,13 +3168,14 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) /** * @brief Enable Active level for Tamper input * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel - * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel + * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel (*) * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * (*) Not applicable to all devices. * * @retval None */ @@ -3166,13 +3187,14 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t /** * @brief Disable Active level for Tamper input * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel - * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel + * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel (*) * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * (*) Not applicable to all devices. * * @retval None */ @@ -3490,7 +3512,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } @@ -3527,7 +3549,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3551,7 +3573,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3656,7 +3678,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR31 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3707,7 +3729,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -3805,7 +3827,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3832,7 +3854,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } @@ -3865,7 +3887,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3890,7 +3912,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3911,7 +3933,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL); } @@ -3922,7 +3944,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); } @@ -3933,21 +3955,23 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL); } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Get RTC_TAMP2 detection flag * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2 * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Get RTC_TAMP1 detection flag @@ -3955,7 +3979,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); } @@ -3966,7 +3990,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); } @@ -3977,7 +4001,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); } @@ -3988,7 +4012,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); } @@ -3999,7 +4023,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); } @@ -4010,7 +4034,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); } @@ -4037,6 +4061,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Clear RTC_TAMP2 detection flag * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2 @@ -4047,6 +4072,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) { WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Clear RTC_TAMP1 detection flag @@ -4120,7 +4146,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); } @@ -4131,7 +4157,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); } @@ -4153,7 +4179,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); } @@ -4164,7 +4190,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); } @@ -4175,7 +4201,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); } @@ -4186,7 +4212,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); } @@ -4197,7 +4223,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } @@ -4706,6 +4732,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) } #if !defined(TAMP) +#if defined(RTC_TAMPxIE_SUPPORT) /** * @brief Enable Tamper 3 interrupt * @rmtoll TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3 @@ -4728,6 +4755,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Enable Tamper 2 interrupt * @rmtoll TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2 @@ -4749,6 +4777,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Enable Tamper 1 interrupt @@ -4771,6 +4800,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); } +#endif /* RTC_TAMPxIE_SUPPORT */ /** * @brief Enable all Tamper Interrupt @@ -4801,7 +4831,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } @@ -4812,7 +4842,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } @@ -4823,7 +4853,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } @@ -4834,19 +4864,20 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } #if !defined(TAMP) +#if defined(RTC_TAMPxIE_SUPPORT) /** * @brief Check if Tamper 3 interrupt is enabled or not * @rmtoll TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3 * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); } @@ -4857,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); @@ -4869,10 +4900,11 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); } +#endif /* RTC_TAMPxIE_SUPPORT */ /** * @brief Check if all the TAMPER interrupts are enabled or not @@ -4880,7 +4912,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h index 6e12084e4b..9887fe0ec6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDMMC_LL * @{ */ @@ -61,10 +61,10 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ -#if (USE_SD_TRANSCEIVER != 0U) +#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ -#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ } SDMMC_InitTypeDef; @@ -160,84 +160,128 @@ typedef struct #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +/** + * @brief Masks for R5 Response + */ +/** this is the reserved for future use in spec RFU */ +#define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) +/** Out of range error */ +#define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) +/** Invalid function number */ +#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) +/** General or an unknown error */ +#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) +/** SDIO Card current state + * 00=DIS (card not selected) + * 01=CMD (data line free) + * 10=TRN (transfer on data lines) */ +#define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) +/** Illegal command error */ +#define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) +/** CRC check of previous cmd failed */ +#define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ + SDMMC_SDIO_R5_ILLEGAL_CMD | \ + SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ + SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ + SDMMC_SDIO_R5_OUT_OF_RANGE) +/** + * @brief SDIO_CMD53_MODE + */ +#define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ +#define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ + +/** + * @brief SDIO_CMD53_OP_CODE + */ +#define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ +#define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ + +/** + * @brief SDIO_CMD53_RAW + */ +#define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ +#define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ + /** * @brief SDMMC Commands Index */ -#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ -#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ -#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ /*!< for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are MMC Specific commands. */ -#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) -#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) -#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) -#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) -#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) -#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) -#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U /** * @brief Masks for errors Card Status R1 (OCR Register) @@ -291,9 +335,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -303,6 +352,8 @@ typedef struct #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) +/* SDMMC FIFO Size */ +#define SDMMC_FIFO_SIZE 32U /** * @brief Command Class supported */ @@ -543,9 +594,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} @@ -657,6 +710,82 @@ typedef struct * @} */ +/** @defgroup SDMMC_SDIO_CCCR_Registers + * @{ + */ +/*-------------------------------- CCCR0 ----------------------------------*/ +#define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ + +/*-------------------------------- CCCR4 ----------------------------------*/ +#define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ + +/*-------------------------------- CCCR8 ----------------------------------*/ +#define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ + +/*-------------------------------- CCCR12 ---------------------------------*/ +#define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ + +/*-------------------------------- CCCR16 ---------------------------------*/ +#define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ + +/*-------------------------------- CCCR20 ---------------------------------*/ +#define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ + +/*-------------------------------- F1BR0 ----------------------------------*/ +#define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ + +/*-------------------------------- F1BR8 ----------------------------------*/ +#define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ + +/*-------------------------------- F1BR12 ---------------------------------*/ +#define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ + +/*-------------------------------- F1BR16 ---------------------------------*/ +#define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ +/** + * @} + */ + /** * @} */ @@ -871,6 +1000,38 @@ typedef struct */ #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +/** + * @brief Checks the source of specified interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) + /** * @brief Clears the SDMMC's interrupt pending bits. * @param __INSTANCE__ Pointer to SDMMC register base @@ -1009,7 +1170,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); /** @addtogroup HAL_SDMMC_LL_Group2 * @{ */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); /** * @} @@ -1022,17 +1183,17 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); @@ -1073,6 +1234,10 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); /** * @} */ @@ -1084,6 +1249,8 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @@ -1106,7 +1273,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** * @} */ - +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h index c2b31d604f..06568c7b10 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h @@ -63,24 +63,30 @@ typedef struct uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetVoltageClass. */ uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. - This parameter must be a number between Min_Data=0 and Max_Data=255U. + This parameter must be a number between Min_Data=0 + and Max_Data=255U. - The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER + The value can be calculated thanks to helper + macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetBitRatePrescaler. */ uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetTransmissionMode. */ uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetReceptionMode. */ } LL_SWPMI_InitTypeDef; /** @@ -266,7 +272,7 @@ __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t R * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); } @@ -294,7 +300,7 @@ __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_ * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); } @@ -351,7 +357,7 @@ __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL); } @@ -381,7 +387,7 @@ __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); } @@ -428,7 +434,7 @@ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_ * @param SWPMIx SWPMI Instance * @retval A number between Min_Data=0 and Max_Data=255U */ -__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); } @@ -455,7 +461,7 @@ __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t Vo * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B */ -__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); } @@ -474,7 +480,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); } @@ -485,7 +491,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); } @@ -496,7 +502,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); } @@ -507,7 +513,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); } @@ -518,7 +524,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); } @@ -530,7 +536,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); } @@ -542,7 +548,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); } @@ -554,7 +560,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); } @@ -566,7 +572,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); } @@ -577,7 +583,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); } @@ -588,7 +594,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); } @@ -599,7 +605,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL); } @@ -926,7 +932,7 @@ __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL); } @@ -937,7 +943,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); } @@ -948,7 +954,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); } @@ -959,7 +965,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); } @@ -970,7 +976,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); } @@ -981,7 +987,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); } @@ -992,7 +998,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); } @@ -1003,7 +1009,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); } @@ -1014,7 +1020,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); } @@ -1025,7 +1031,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); } @@ -1066,7 +1072,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); } @@ -1099,7 +1105,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); } @@ -1114,19 +1120,19 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef *SWPMIx, uint32_t Direction) { uint32_t data_reg_addr; if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->TDR); + data_reg_addr = (uint32_t) &(SWPMIx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->RDR); + data_reg_addr = (uint32_t) &(SWPMIx->RDR); } return data_reg_addr; @@ -1146,7 +1152,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t * @param SWPMIx SWPMI Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); } @@ -1210,8 +1216,8 @@ __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) * @{ */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx); +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct); void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h index eef033dd61..a8625e967b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html index 02124608f5..4e0c79d1d9 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html @@ -40,10 +40,159 @@

Purpose

Update History

- +

Main Changes

    +
  • HAL PWR +
      +
    • Add a note to the HAL_PWREx_ConfigSupply() API documentation to clarify that this API comes obsolete after deploying "how to exit from Run* recommended sequence.
      • +
    • +
  • HAL QSPI +
      +
    • Fix possible race condition with QSPI data transfer when using DMA.
      • +
    • +
  • HAL/LL RTC +
      +
    • Alignment with new RTC TAMPER register and bitfields naming in the CMSIS.
      • +
    • Add new restrictions to manage specific Tamper features.
      • +
    • +
  • HAL HSEM +
      +
    • Update __HAL_HSEM_ENABLE_IT(), __HAL_HSEM_DISABLE_IT(), __HAL_HSEM_GET_IT(), __HAL_HSEM_GET_FLAG() and __HAL_HSEM_CLEAR_FLAG() macros to be aligned with registers’ names in the CMSIS.
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers.
    • +
  • General updates to fix known defects and enhancements implementation.
    • +
  • HAL Generic +
      +
    • Add new REV_ID_x to cover all supported STM32H7 device revisions.
      • +
    • +
  • HAL ADC +
      +
    • Fix Misra-C 2012 Rule-12.1 related issues.
      • +
    • +
  • HAL DAC +
      +
    • Fix HAL DAC calibration procedure (HAL_DACEx_SelfCalibrate() API) to manage case of calibration factor equal to range maximum value (previously, in this case calibration factor was reset, leading to voltage accuracy not optimal).
      • +
    • +
  • LL DMA +
      +
    • Remove deprecated ‘register’ storage class specifier from LL_DMA_IsEnabledDoubleBufferMode() API to fix GCC compiler issue.
      • +
    • +
  • HAL CRYP +
      +
    • Update CRYP HAL driver to fix the issue of writing out the outputbuffer when the size is not multiple of 4.
      • +
    • +
  • HAL HASH +
      +
    • Update the HAL HASH driver to support data in case of buffer smaller than 4 bytes in mode IT.
      • +
    • +
  • HAL RNG +
      +
    • Update the HAL RNG driver to support error coming from RecoverSeedError.
      • +
    • +
  • HAL HRTIM +
      +
    • Correct the typo in the “HRTIMInterruptRequests” structure member and add the legacy define in the stm32_hal_legacy.h file.
      • +
    • +
  • HAL USART +
      +
    • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
      • +
    • Improve the visibility of the SPI API support in HAL USART description.
      • +
    • +
  • HAL SWPMI +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL/LL UART +
      +
    • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
      • +
    • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
      • +
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.
      • +
    • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.
      • +
    • Add LL LPUART API allowing TX FIFO flush request.
      • +
    • +
  • HAL/LL SWPMI driver +
      +
    • Fix incorrect word ‘surcharged’ in functions headers.
      • +
    • +
  • HAL SDMMC driver +
      +
    • Add new HAL SDIO driver.
      • +
    • +
  • HAL I2C +
      +
    • Add a temporary variable to get the value to check before comparison.
      • +
    • Add abort memory management to HAL_I2C_Master_Abort_IT() API.
      • +
    • Move the prefetch process in HAL_I2C_Slave_Transmit() API.
      • +
    • Move variable tmp declaration at the beginning in I2C_TransferCofig function.
      • +
    • Update function HAL_I2C_IsDeviceReady() API to take into account the number of trials.
      • +
    • +
  • HAL I2S +
      +
    • Add HAL IOSwap APIs: +
        +
      • HAL_I2S_EnableIOSwap()to enable the SDO/SDI alternate functions inversion feature.
        • +
      • HAL_I2S_DisableIOSwap() to disable the SDO/SDI alternate functions inversion feature.
        • +
      • HAL_I2S_IsEnabledIOSwap() to retrieve the SDO/SDI alternate functions inversion feature.
        • +
      • +
    • +
  • HAL ETH +
      +
    • Fix undefined Macro usage in ETH DMA Status Flags.
      • +
    • Fix the calculation of the tail pointer so that it points to the last updated descriptor.
      • +
    • Add new API HAL_ETH_GetTxBuffersNumber() to get Buffers in use number.
      • +
    • +
  • HAL SPI +
      +
    • Add protection against wrong transfer size during transmission.
      • +
    • Check coherence between data size and DMA TX configuration.
      • +
    • +
  • HAL OSPI +
      +
    • Fix wrong parameters passed to HAL_MDMA_Start_IT() API.
      • +
    • +
  • HAL QSPI +
      +
    • Clear AR register after CCR to avoid new transfer when address is not needed.
      • +
    • +
  • HAL USB +
      +
    • Fix MisraC 2012 Rule-10.7 related issues.
      • +
    • hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
  • HAL Generic
      @@ -54,7 +203,6 @@

      Main Changes

    • HAL PWR
      • Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘Regulator’.
        • -
      • Update HAL_PWREx_PVD_AVD_IRQHandle() API to call right callbacks before performing the clear.
    • HAL GPIO
        @@ -232,11 +380,11 @@

        Main Changes

      • Fix a note about Ticks parameter.
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward compatibility

    +

    Backward compatibility

    • None
    @@ -245,18 +393,18 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • HAL ETH
      • Update on Rx descriptor Tail pointer management to avoid race condition.
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward compatibility

    +

    Backward compatibility

    • None
    @@ -265,7 +413,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • General updates to fix known defects and implementation enhancements.
    • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
      • @@ -351,6 +499,20 @@

      Main Changes

      • Change argument order in SPI_WaitOnFlagUntilTimeout to be aligned with declaration.
      • Fix dereferencing pointer warning on GNU compiler inside LL_SPI_ReceiveData16() function.
        • +
      • Add SuspendCallback(), useful to avoid data overrun in case transfer is interrupted. +
          +
        • NOTE: SuspendCallback() is called only when MasterReceiverAutoSusp is enabled and EOT interrupt is activated.
          • +
        • +
      • Add support of Simplex Transmitter and Simplex Receiver modes.
        • +
      • Remove the call to HAL_SPI_TransmitReceive() from HAL_SPI_Receive(). +
          +
        • NOTES: +
            +
          • When the HAL_SPI_Receive() is called in Master mode, only the RX Line is active.
            • +
          • In case of a Master using the Full-Duplex mode, HAL_SPI_TransmitReceive() shall be called instead of HAL_SPI_Receive() at user application level.
            • +
          • +
        • +
      • Clear EOT and SUSP flags in the HAL_SPI_Abort_IT().
    • HAL ETH
        @@ -378,11 +540,11 @@

        Main Changes

      • Remove redundant word from @note of HAL_InitTick() header description, which may cause confusion when reading the note.
    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward compatibility

    +

    Backward compatibility

    • None
    @@ -391,7 +553,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • General updates to fix known defects and implementation enhancements.
    • The following changes done on the HAL drivers require an update of the application code based on older HAL versions @@ -474,11 +636,11 @@

      Main Changes

    • Fix USB BCD data contact timeout
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Compatibility break with HAL ETH driver V1.10.0 available within STM32CubeFW_H7 V1.9.0
@@ -487,7 +649,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
    • @@ -646,14 +808,14 @@

    Main Changes

  • Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).
-

Known Limitations

+

Known Limitations

  • HAL/ETH
    • A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP
-

Backward compatibility

+

Backward compatibility

  • None
@@ -662,7 +824,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements

  • Fix minor issues related to English typo in comments

    • @@ -948,14 +1110,14 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL/ETH
    • A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP
-

Backward compatibility

+

Backward compatibility

  • None
@@ -964,7 +1126,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of the STM32CubeH7 Firmware Package supporting STM32H72x/3x new devices
  • General updates to fix known defects and implementation enhancements
    • @@ -1558,11 +1720,11 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)
@@ -1571,7 +1733,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements
  • HAL: generic @@ -1805,7 +1967,7 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL I2S:
      @@ -1815,7 +1977,7 @@

      Known Limitations

-

Backward compatibility

+

Backward compatibility

  • None
@@ -1824,7 +1986,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Official release with support of STM32H7A3/B3xx/B0xx new devices
    • @@ -2379,7 +2541,7 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL I2S:
      @@ -2393,7 +2555,7 @@

      Known Limitations

    • New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.
-

Backward compatibility

+

Backward compatibility

  • HAL I2S:
      @@ -2417,7 +2579,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements
      • HAL: generic @@ -2692,11 +2854,11 @@

        Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • HAL TIM:
      @@ -2714,7 +2876,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements
      • Add support for VOS0 power regulator voltage scaling with 480MHz over clock
        • @@ -3184,7 +3346,7 @@

        Main Changes

      • Update LL_Init1msTick and LL_SetSystemCoreClock description for DUAL CORE lines
    -

    Known Limitations

    +

    Known Limitations

    • HAL SD:
        @@ -3198,7 +3360,7 @@

        Known Limitations

      • Full duplex Transmit/receive feature not available
    -

    Backward compatibility

    +

    Backward compatibility

    • HAL ADC:
        @@ -3250,7 +3412,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • General updates to fix known defects and implementation enhancements
        • Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG
          • @@ -3519,7 +3681,7 @@

          Main Changes

        • Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled
      -

      Known Limitations

      +

      Known Limitations

      • HAL I2S:
          @@ -3527,7 +3689,7 @@

          Known Limitations

        • A new version of this driver will be available in next release with full features tested
      -

      Backward compatibility

      +

      Backward compatibility

      • HAL ADC:
          @@ -3567,7 +3729,7 @@

          Backward compatibility

          -

          Main Changes

          +

          Main Changes

          • Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers
          • HAL Cortex: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15
            • @@ -3579,7 +3741,7 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • General updates to fix known defects and enhancements implementation
            • HAL SPI: Driver reworked to fix critical issues
              • @@ -3590,7 +3752,7 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • General updates to fix known defects and enhancements implementation
              • HAL FLASH: Add Mass Erase for both banks
                • @@ -3605,7 +3767,7 @@

                Main Changes

                -

                Main Changes

                +

                Main Changes

                • First official release for STM32H743xx/753xx devices
                diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c index 468fd83a0e..6ddbeee45b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -51,7 +51,7 @@ */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ -#define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x05UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c index 74cf03aec0..855ea82de4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c @@ -2341,7 +2341,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3022,11 +3022,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Set sampling time of the selected ADC channel */ - /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), - sConfig->SamplingTime); + /* Set ADC channel preselection of corresponding negative channel */ + LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel)); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ @@ -3494,7 +3491,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3508,7 +3505,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c index 749473f773..b2dc363b89 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c @@ -197,7 +197,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1016,7 +1016,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; @@ -1277,7 +1277,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; @@ -1323,7 +1323,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; @@ -2296,8 +2296,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + /* Set ADC channel preselection of corresponding negative channel */ + LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfigInjected->InjectedChannel)); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c index 165c09e37c..621a0a05d0 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c @@ -1148,7 +1148,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1201,7 +1201,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ if(hcomp == NULL) @@ -1221,7 +1221,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c index 7eea29cb6c..da6b810bb7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c index e272cfc2db..5c158d532b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c @@ -327,7 +327,7 @@ void HAL_MPU_DisableRegion(uint32_t RegionNumber) * the initialization and configuration information. * @retval None */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c index b4ba3de352..c814b28715 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c index 61d732e4be..942c1e0138 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c @@ -74,7 +74,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -1741,7 +1741,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * the configuration information for the CRYP IP * @retval CRYP error code */ -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp) { return hcryp->ErrorCode; } @@ -1752,7 +1752,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module. * @retval HAL state */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp) { return hcryp->State; } @@ -4434,7 +4434,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; + const uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; /***************************** Header phase for GCM/GMAC or CCM *********************************/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c index ddce86e43b..5dee88e2f8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c @@ -108,7 +108,7 @@ * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout) { uint32_t tickstart; uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ @@ -274,7 +274,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; uint32_t ctr0 [4] = {0}; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c index a5e6225186..0207677006 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c @@ -1065,6 +1065,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c index 15d998a430..e2b8e6aea5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c @@ -666,8 +666,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -713,8 +713,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -787,8 +791,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c index e1549e2473..980270258f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c @@ -914,7 +914,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } @@ -925,7 +925,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) * the configuration information for DCMI. * @retval DCMI Error Code */ -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c index dada223e62..8714741055 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -174,7 +174,7 @@ typedef struct */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); @@ -1733,7 +1733,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * the configuration information for the specified DMA Stream. * @retval HAL state */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) { return hdma->State; } @@ -1744,7 +1744,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @retval DMA Error Code */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } @@ -1893,7 +1893,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @retval HAL status */ -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c index 520841c9f3..e85122ce71 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c @@ -323,7 +323,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U) { /* Abort DMA2D transfer if any */ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) @@ -1013,7 +1013,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); @@ -1067,7 +1068,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ @@ -1770,7 +1771,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - DMA2D_LayerCfgTypeDef *pLayerCfg; + const DMA2D_LayerCfgTypeDef *pLayerCfg; uint32_t regMask; uint32_t regValue; @@ -2062,7 +2063,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t * the configuration information for the DMA2D. * @retval HAL state */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->State; } @@ -2073,7 +2074,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) * the configuration information for DMA2D. * @retval DMA2D Error Code */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c index 9f122a49bd..3b9b85a202 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c @@ -948,7 +948,7 @@ __weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts) * @param hdts DTS handle * @retval HAL state */ -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts) +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts) { /* Check the DTS handle allocation */ if (hdts == NULL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c index 2536a73b12..b9e26fa7b7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c @@ -1081,7 +1081,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + /* Get the Frame Length of the received packet */ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; /* Check if last descriptor */ @@ -1209,7 +1209,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT; /* DMB instruction to avoid race condition */ __DMB(); @@ -1429,7 +1429,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) #ifdef HAL_ETH_USE_PTP /* Disable Ptp transmission */ - CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) @@ -1506,6 +1506,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT return HAL_ERROR; } + /* Mask the Timestamp Trigger interrupt */ + CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE); + tmpTSCR = ptpconfig->Timestamp | ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | @@ -1539,8 +1542,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT } } - /* Ptp Init */ - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } /* Set PTP Configuration done */ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; @@ -1552,6 +1558,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT HAL_ETH_PTP_SetTime(heth, &time); + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Return function status */ return HAL_OK; } @@ -2491,7 +2500,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ ((uint32_t)pFilterConfig->HashMulticast << 2) | ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) | ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | @@ -2524,7 +2533,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; @@ -2772,6 +2781,16 @@ uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) return heth->MACWakeUpEvent; } +/** + * @brief Returns the ETH Tx Buffers in use number + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Tx Buffers in use number + */ +uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth) +{ + return heth->TxDescList.BuffersInUse; +} /** * @} */ @@ -3056,7 +3075,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept + * @param ItMode: Enable or disable Tx EOT interrupt * @retval Status */ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c index fe54a0374f..07825da414 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param hexti Exti handle. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -682,7 +682,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @param hexti Exti handle. * @retval none. */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -734,9 +734,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) * This parameter is kept for compatibility with other series. * @retval 1 if interrupt is pending else 0. */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -785,7 +785,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * This parameter is kept for compatibility with other series. * @retval None. */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; @@ -827,7 +827,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @param hexti Exti handle. * @retval None. */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c index bed7b5e753..7a1e2d76fd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -1020,26 +1020,26 @@ void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) */ void HAL_FLASHEx_BusFault_IRQHandler(void) { - /* Check if the ECC double error occured*/ + /* Check if the ECC double error occurred*/ if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0) { /* FLASH ECC detection user callback */ HAL_FLASHEx_EccDetectionCallback(); /* Clear Bank 1 ECC double detection error flag - note : this step will clear all the informations related to the flash ECC detection + note : this step will clear all the information related to the flash ECC detection */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1); } #if defined (DUAL_BANK) - /* Check if the ECC double error occured*/ + /* Check if the ECC double error occurred*/ if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0) { /* FLASH ECC detection user callback */ HAL_FLASHEx_EccDetectionCallback(); /* Clear Bank 2 ECC double detection error flag - note : this step will clear all the informations related to the flash ECC detection + note : this step will clear all the information related to the flash ECC detection */ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c index f4cebd05d9..306073b601 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c @@ -204,7 +204,6 @@ not defined, the callback registration feature is not available and weak callbacks are used. - @endverbatim * */ @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -1203,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1222,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1239,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ @@ -2410,7 +2417,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2516,11 +2522,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c index 7e771a7925..f6961785f0 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c @@ -518,7 +518,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @param Address Start address of LUT in flash. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address) @@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber) { @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, * @param lutLine LUT line parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) { HAL_StatusTypeDef status = HAL_OK; @@ -841,7 +841,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) * @param hgfxmmu GFXMMU handle. * @retval GFXMMU state. */ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) { /* Return GFXMMU handle state */ return hgfxmmu->State; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c index 3580f78a5b..7133e81e73 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -162,7 +162,7 @@ * the configuration information for the specified GPIO peripheral. * @retval None */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00U; uint32_t iocurrent; @@ -386,7 +386,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c index 8bc984da55..27513cfa76 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,8 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +791,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +806,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +823,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +850,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +865,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +913,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +937,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +951,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +967,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +992,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1006,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1079,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1109,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1166,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1186,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1229,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1247,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1254,7 +1258,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ - /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @brief HMAC processing functions using DMA modes. * @@ -1297,7 +1300,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1325,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1369,7 +1372,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @param hhash HASH handle. * @retval HAL HASH state */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) { return hhash->State; } @@ -1382,7 +1385,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @param hhash HASH handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash) { return hhash->Status; } @@ -1400,7 +1403,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1441,7 +1444,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) * beforehand). * @retval None */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1620,7 +1623,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code */ -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ return hhash->ErrorCode; @@ -1821,7 +1824,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1917,8 +1920,8 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB if ((Size % 4U) == 3U) { tmp = *(uint8_t *)inputaddr; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U; HASH->DIN = tmp; } @@ -1927,7 +1930,6 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB { HASH->DIN = *(uint32_t *)inputaddr; } - /*hhash->HashInCount += 4U;*/ } @@ -1940,7 +1942,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2005,7 +2007,6 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) } - /** * @brief Handle HASH processing Timeout. * @param hhash HASH handle. @@ -2491,10 +2492,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2526,7 +2528,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2542,7 +2544,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2550,7 +2552,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2628,9 +2630,10 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2662,7 +2665,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2673,7 +2676,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2731,7 +2734,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2841,7 +2845,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff } - /** * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest in interruption mode. @@ -2853,7 +2856,8 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2902,6 +2906,19 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } + else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U)) + { + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + } + } else { initialization_skipped = 1; /* info user later on in case of multi-buffer */ @@ -3011,7 +3028,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3188,7 +3206,8 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3252,7 +3271,6 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint } - /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then * read the computed digest in interruption mode. @@ -3266,7 +3284,8 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3361,7 +3380,6 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u } - /** * @brief Initialize the HASH peripheral in HMAC mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -3377,7 +3395,8 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c index 86b7030c59..00c4340c98 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c @@ -86,8 +86,6 @@ #include "stm32h7xx_hal.h" - - /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -148,7 +146,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +187,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +204,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +288,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +312,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +326,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +367,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +381,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -422,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin */ - - /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer * to feed the input buffer to the Peripheral. @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -507,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest. @@ -521,7 +518,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +537,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -570,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest in interrupt mode. @@ -583,7 +579,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,15 +597,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } - - /** * @} */ @@ -639,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -659,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c index 17f99edb5b..e1fbd00433 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c @@ -1693,6 +1693,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c index 2e11610e89..65efda0016 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c @@ -83,7 +83,6 @@ any restriction. HRTIM waveform modes are managed through the set of functions named HAL_HRTIM_Waveform -============================================================================== ##### How to use this driver ##### ============================================================================== [..] @@ -423,62 +422,62 @@ static uint32_t TimerIdxToTimerId[] = /** @defgroup HRTIM_Private_Functions HRTIM Private Functions * @{ */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg); +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event); -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg); -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma); -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma); @@ -497,7 +496,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); */ /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions @verbatim =============================================================================== ##### Initialization and Time Base Configuration functions ##### @@ -518,20 +517,20 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim) { uint8_t timer_idx; uint32_t hrtim_mcr; /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance)); - assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests)); + assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests)); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) if (hhrtim->State == HAL_HRTIM_STATE_RESET) @@ -660,10 +659,10 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim) { /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } @@ -696,7 +695,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -711,7 +710,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -743,16 +742,16 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio)); assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Set the HRTIM state */ @@ -780,7 +779,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions - * @brief Simple time base mode functions. + * @brief Simple time base mode functions. @verbatim =============================================================================== ##### Simple time base mode functions ##### @@ -812,10 +811,10 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -847,10 +846,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -883,10 +882,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -929,10 +928,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -978,24 +977,24 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @param Length The length of data items (data size) to be transferred * from source to destination */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1013,12 +1012,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA transfer completed callback */ @@ -1036,14 +1035,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer repetition DMA request */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) @@ -1080,10 +1079,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1098,7 +1097,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP); @@ -1119,12 +1118,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hdma) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP); - } + } } /* Disable the timer counter */ @@ -1135,11 +1134,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -1148,7 +1147,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions - * @brief Simple output compare functions + * @brief Simple output compare functions @verbatim =============================================================================== ##### Simple output compare functions ##### @@ -1202,10 +1201,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, * Inactive: SETxy =0, RSTxy = CMPy * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -1217,9 +1216,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1231,27 +1230,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { CompareUnit = HRTIM_COMPAREUNIT_1; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { CompareUnit = HRTIM_COMPAREUNIT_2; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -1262,9 +1261,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ @@ -1277,7 +1276,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, switch (pSimpleOCChannelCfg->Mode) { - case HRTIM_BASICOCMODE_TOGGLE: + case HRTIM_BASICOCMODE_TOGGLE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1291,7 +1290,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_ACTIVE: + case HRTIM_BASICOCMODE_ACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1305,7 +1304,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_INACTIVE: + case HRTIM_BASICOCMODE_INACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1319,7 +1318,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1333,9 +1332,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } HRTIM_OutputConfig(hhrtim, @@ -1376,11 +1375,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1426,11 +1425,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1481,13 +1480,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset interrupt is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1540,13 +1539,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1607,26 +1606,26 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset DMA request is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; uint32_t dma_request; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1639,7 +1638,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Process Locked */ __HAL_LOCK(hhrtim); - /* Enable the timer output */ + /* Enable the timer output */ hhrtim->Instance->sCommonRegs.OENR |= OCChannel; /* Get the DMA request to enable */ @@ -1650,12 +1649,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -1666,14 +1665,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request); @@ -1714,9 +1713,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t dma_request; @@ -1765,7 +1764,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions - * @brief Simple PWM output functions + * @brief Simple PWM output functions @verbatim =============================================================================== ##### Simple PWM output functions ##### @@ -1822,10 +1821,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, * enabled (otherwise the behavior is not guaranteed). * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -1836,9 +1835,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1849,28 +1848,28 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1884,14 +1883,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1); - OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1); + OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; @@ -1940,11 +1939,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -1990,11 +1989,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2041,11 +2040,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2059,27 +2058,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2090,9 +2089,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2131,11 +2130,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2149,27 +2148,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2180,9 +2179,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2225,25 +2224,25 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -2280,39 +2279,39 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2323,9 +2322,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2364,9 +2363,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); @@ -2394,27 +2393,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2425,9 +2424,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2446,7 +2445,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions - * @brief Simple input capture functions + * @brief Simple input capture functions @verbatim =============================================================================== ##### Simple input capture functions ##### @@ -2488,10 +2487,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * edges on event channel. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -2505,9 +2504,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event, pSimpleCaptureChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2559,11 +2558,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr * units. It can be used directly and is active as soon as the timing * unit counter is enabled. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2575,19 +2574,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2598,9 +2597,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2630,14 +2629,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2649,19 +2648,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2672,9 +2671,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2712,11 +2711,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2728,7 +2727,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2737,7 +2736,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2746,7 +2745,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2757,9 +2756,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2790,15 +2789,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2810,7 +2809,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2819,7 +2818,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2828,7 +2827,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2839,9 +2838,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2883,16 +2882,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2906,12 +2905,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -2922,18 +2921,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2942,7 +2941,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2952,7 +2951,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2961,11 +2960,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2996,9 +2995,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; @@ -3017,17 +3016,17 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3037,7 +3036,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3047,7 +3046,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3058,9 +3057,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3086,7 +3085,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions - * @brief Simple one pulse functions + * @brief Simple one pulse functions @verbatim =============================================================================== ##### Simple one pulse functions ##### @@ -3143,10 +3142,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, * second call will override the reset event related configuration data * provided in the first call. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3163,9 +3162,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event, pSimpleOnePulseChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3176,29 +3175,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh /* Configure timer compare unit */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -3212,13 +3211,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ - OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); + OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; @@ -3235,7 +3234,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F); EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1); - EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS); + EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS); EventCfg.Source = HRTIM_EVENTSRC_1; HRTIM_EventConfig(hhrtim, @@ -3279,7 +3278,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel) { @@ -3329,9 +3328,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3380,9 +3379,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3398,27 +3397,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3429,9 +3428,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3470,9 +3469,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3488,27 +3487,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3519,9 +3518,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -3540,7 +3539,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions - * @brief HRTIM configuration functions + * @brief HRTIM configuration functions @verbatim =============================================================================== ##### HRTIM configuration functions ##### @@ -3567,8 +3566,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the burst mode * controller */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) +HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3579,9 +3578,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3647,9 +3646,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3659,9 +3658,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3692,15 +3691,15 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3734,9 +3733,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * enabling faults inputs * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef *pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; @@ -3748,9 +3747,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3764,7 +3763,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P); @@ -3774,7 +3773,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P); @@ -3784,7 +3783,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P); @@ -3792,9 +3791,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F); hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK); break; - } + } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P); @@ -3804,7 +3803,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P); @@ -3814,7 +3813,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3825,9 +3824,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers except LOCK bit */ @@ -3835,8 +3834,8 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK))); /* Update the HRTIM registers LOCK bit */ - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -3859,15 +3858,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer and before * enabling faults inputs */ -HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3902,9 +3901,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled * @retval None */ -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, - uint32_t Faults, - uint32_t Enable) +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, + uint32_t Faults, + uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Faults)); @@ -3946,9 +3945,9 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg) { uint32_t hrtim_cr1; @@ -3956,9 +3955,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3971,7 +3970,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, switch (ADCTrigger) { - case HRTIM_ADCTRIGGER_1: + case HRTIM_ADCTRIGGER_1: { hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC); hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC); @@ -3981,7 +3980,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_2: + case HRTIM_ADCTRIGGER_2: { hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC); @@ -3991,7 +3990,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_3: + case HRTIM_ADCTRIGGER_3: { hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC); @@ -4001,7 +4000,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_4: + case HRTIM_ADCTRIGGER_4: { hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC); @@ -4011,7 +4010,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4022,9 +4021,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers */ @@ -4044,7 +4043,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions - * @brief HRTIM timer configuration and control functions + * @brief HRTIM timer configuration and control functions @verbatim =============================================================================== ##### HRTIM timer configuration and control functions ##### @@ -4098,9 +4097,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4114,9 +4113,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4199,10 +4198,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -4211,9 +4210,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4224,75 +4223,85 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt /* Configure timer event filtering capabilities */ switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1); CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2); break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4302,9 +4311,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4329,9 +4338,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -4345,9 +4354,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4368,9 +4377,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, /* Update the HRTIM registers */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, ( - HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | - HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | - HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); + HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | + HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | + HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4394,9 +4403,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before configuring the timer output(s) */ -HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg) { uint32_t hrtim_chpr; @@ -4406,9 +4415,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle)); assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4471,16 +4480,16 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4491,44 +4500,44 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the burst DMA timer update register */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate; break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4538,9 +4547,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4578,17 +4587,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef *pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4602,43 +4611,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, switch (CompareUnit) { case HRTIM_COMPAREUNIT_1: - { + { hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_2: - { + { hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_3: - { + { hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_4: - { + { hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; break; - } + } default: - { + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); break; - } + } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } } @@ -4646,14 +4655,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, { switch (CompareUnit) { - case HRTIM_COMPAREUNIT_1: + case HRTIM_COMPAREUNIT_1: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_2: + case HRTIM_COMPAREUNIT_2: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4688,17 +4697,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } - break; + break; } - case HRTIM_COMPAREUNIT_3: + case HRTIM_COMPAREUNIT_3: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_4: + case HRTIM_COMPAREUNIT_4: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4733,24 +4742,24 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } - break; + break; } - default: - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + default: + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - break; - } - } + break; + } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return HAL_ERROR; - } + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) + { + return HAL_ERROR; + } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4779,18 +4788,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef *pCaptureCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4801,19 +4810,19 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure the capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4824,9 +4833,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } @@ -4865,10 +4874,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before configuring the timer and after * configuring the deadtime insertion feature (if required). */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -4879,9 +4888,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4933,7 +4942,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, * @note The 'software set/reset trigger' bit in the output set/reset registers * is automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel) @@ -4942,9 +4951,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4955,16 +4964,16 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, /* Force timer output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { /* Force output to its active state */ - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST); } else { @@ -4974,11 +4983,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { @@ -4993,7 +5002,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -5004,9 +5013,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5035,10 +5044,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStart)); /* Process Locked */ @@ -5075,10 +5084,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStop)); /* Process Locked */ @@ -5111,8 +5120,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5148,8 +5157,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5188,8 +5197,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, * function. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5202,7 +5211,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Enable HRTIM interrupts (if required) */ - __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Enable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5232,7 +5241,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - return HAL_OK;} + return HAL_OK; +} /** * @brief Stop the counter of the designated timer(s) operating in waveform mode @@ -5250,8 +5260,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* ++ WA */ __IO uint32_t delai = (uint32_t)(0x17FU); @@ -5268,7 +5278,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Disable HRTIM interrupts (if required) */ - __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Disable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5322,18 +5332,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * size of each DMA transfer are specified at timer configuration time * (see HAL_HRTIM_WaveformTimerConfig) */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -5344,29 +5354,29 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) && (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { - /* Set the DMA error callback */ - hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; + /* Set the DMA error callback */ + hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; - /* Set the DMA transfer completed callback */ - hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; + /* Set the DMA transfer completed callback */ + hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } - /* Enable the timer DMA request */ - __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + /* Enable the timer DMA request */ + __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; @@ -5374,7 +5384,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -5389,7 +5399,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, return HAL_ERROR; } - /* Set the DMA error callback */ + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; /* Set the DMA transfer completed callback */ @@ -5397,17 +5407,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - hhrtim->TimerParam[timer_idx].DMASrcAddress, - hhrtim->TimerParam[timer_idx].DMADstAddress, - hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->TimerParam[timer_idx].DMASrcAddress, + hhrtim->TimerParam[timer_idx].DMADstAddress, + hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, @@ -5443,8 +5453,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related DMA requests are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5459,14 +5469,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } else { - hhrtim->State = HAL_HRTIM_STATE_READY; - /* Disable the DMA request(s) */ - __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + hhrtim->State = HAL_HRTIM_STATE_READY; + /* Disable the DMA request(s) */ + __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } } @@ -5500,11 +5510,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -5518,15 +5528,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called after starting the timer(s) */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_BURSTMODECTL(Enable)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5552,9 +5562,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim) { - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5591,7 +5601,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim * @note The 'software capture' bit in the capure configuration register is * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5599,9 +5609,9 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5612,32 +5622,32 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, /* Force a software capture on concerned capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - break; + break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5663,15 +5673,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5705,15 +5715,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERRESET(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5761,18 +5771,18 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferAddress, uint32_t BurstBufferLength) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U)) { return HAL_ERROR; } @@ -5806,17 +5816,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - BurstBufferAddress, - (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR), - BurstBufferLength) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + BurstBufferAddress, + (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR), + BurstBufferLength) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5841,9 +5851,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers) + uint32_t Timers) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); /* Process Locked */ @@ -5860,7 +5870,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @brief Disable the transfer from preload to active registers for one @@ -5896,14 +5906,14 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @} */ /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions - * @brief Peripheral State functions + * @brief Peripheral State functions @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -5928,7 +5938,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -5950,7 +5960,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5963,21 +5973,21 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR; break; } - default: - { - captured_value = 0xFFFFFFFFUL; + default: + { + captured_value = 0xFFFFFFFFUL; break; } @@ -6013,7 +6023,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6025,11 +6035,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, /* Read the output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET) { @@ -6039,14 +6049,14 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, { output_level = HRTIM_OUTPUTLEVEL_INACTIVE; } - break; + break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET) { @@ -6059,7 +6069,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { output_level = 0xFFFFFFFFUL; break; @@ -6093,7 +6103,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6109,67 +6119,67 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, /* Set output state according to output control status and output disable status */ switch (Output) { - case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TA1: { output_bit = HRTIM_OENR_TA1OEN; break; } - case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TA2: { output_bit = HRTIM_OENR_TA2OEN; break; } - case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TB1: { output_bit = HRTIM_OENR_TB1OEN; break; } - case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TB2: { output_bit = HRTIM_OENR_TB2OEN; break; } - case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TC1: { output_bit = HRTIM_OENR_TC1OEN; break; } - case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TC2: { output_bit = HRTIM_OENR_TC2OEN; break; } - case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TD1: { output_bit = HRTIM_OENR_TD1OEN; break; } - case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TD2: { output_bit = HRTIM_OENR_TD2OEN; break; } - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TE1: { output_bit = HRTIM_OENR_TE1OEN; break; } - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TE2: { output_bit = HRTIM_OENR_TE2OEN; break; } - default: + default: { output_bit = 0UL; break; @@ -6195,7 +6205,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, } } - return(output_state); + return (output_state); } /** @@ -6223,7 +6233,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6235,11 +6245,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim /* Read the delayed protection status */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET) { @@ -6254,11 +6264,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET) { @@ -6273,7 +6283,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - default: + default: { delayed_protection_status = 0xFFFFFFFFUL; break; @@ -6288,7 +6298,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim) { uint32_t burst_mode_status; @@ -6311,7 +6321,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -6339,7 +6349,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -6358,24 +6368,24 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling - * @brief Functions called when HRTIM generates an interrupt - * 7 interrupts can be generated by the master timer: - * - Master timer registers update - * - Synchronization event received - * - Master timer repetition event - * - Master Compare 1 to 4 event - * 14 interrupts can be generated by each timing unit: - * - Delayed protection triggered - * - Counter reset or roll-over event - * - Output 1 and output 2 reset (transition active to inactive) - * - Output 1 and output 2 set (transition inactive to active) - * - Capture 1 and 2 events - * - Timing unit registers update - * - Repetition event - * - Compare 1 to 4 event - * 7 global interrupts are generated for the whole HRTIM: - * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) - * - Burst mode period completed + * @brief Functions called when HRTIM generates an interrupt + * 7 interrupts can be generated by the master timer: + * - Master timer registers update + * - Synchronization event received + * - Master timer repetition event + * - Master Compare 1 to 4 event + * 14 interrupts can be generated by each timing unit: + * - Delayed protection triggered + * - Counter reset or roll-over event + * - Output 1 and output 2 reset (transition active to inactive) + * - Output 1 and output 2 set (transition inactive to active) + * - Capture 1 and 2 events + * - Timing unit registers update + * - Repetition event + * - Compare 1 to 4 event + * 7 global interrupts are generated for the whole HRTIM: + * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) + * - Burst mode period completed @verbatim =============================================================================== ##### HRTIM interrupts handling ##### @@ -6424,7 +6434,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * This parameter can be any value of HRTIM_Timer_Index * @retval None */ -void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* HRTIM interrupts handling */ @@ -6450,7 +6460,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None * @retval None */ -__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6465,7 +6475,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6480,7 +6490,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6495,7 +6505,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6510,7 +6520,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6525,7 +6535,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6540,7 +6550,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6555,7 +6565,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6578,7 +6588,7 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6603,7 +6613,7 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6629,8 +6639,8 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6655,8 +6665,8 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E */ -__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6681,8 +6691,8 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6707,8 +6717,8 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6731,8 +6741,8 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6755,8 +6765,8 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6780,8 +6790,8 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6805,8 +6815,8 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6829,8 +6839,8 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6853,8 +6863,8 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6877,8 +6887,8 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6901,8 +6911,8 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6926,7 +6936,7 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6973,7 +6983,7 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim) * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback) { @@ -7102,7 +7112,7 @@ HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_MSPDEINIT_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7114,79 +7124,79 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, { switch (CallbackID) { - case HAL_HRTIM_FAULT1CALLBACK_CB_ID : - hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; - break; + case HAL_HRTIM_FAULT1CALLBACK_CB_ID : + hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; + break; - case HAL_HRTIM_FAULT2CALLBACK_CB_ID : - hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; - break; + case HAL_HRTIM_FAULT2CALLBACK_CB_ID : + hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; + break; - case HAL_HRTIM_FAULT3CALLBACK_CB_ID : - hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; - break; + case HAL_HRTIM_FAULT3CALLBACK_CB_ID : + hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; + break; - case HAL_HRTIM_FAULT4CALLBACK_CB_ID : - hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; - break; + case HAL_HRTIM_FAULT4CALLBACK_CB_ID : + hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; + break; - case HAL_HRTIM_FAULT5CALLBACK_CB_ID : - hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; - break; + case HAL_HRTIM_FAULT5CALLBACK_CB_ID : + hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; + break; - case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : - hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; - break; + case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : + hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; + break; - case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : - hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; - break; + case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : + hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; + break; - case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : - hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; - break; + case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : + hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; + break; - case HAL_HRTIM_ERRORCALLBACK_CB_ID : - hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; - break; + case HAL_HRTIM_ERRORCALLBACK_CB_ID : + hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; + break; - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_HRTIM_STATE_RESET == hhrtim->State) { switch (CallbackID) { - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -7227,7 +7237,7 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback) { @@ -7308,7 +7318,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = pCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7354,7 +7364,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7426,7 +7436,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7468,8 +7478,8 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -7497,9 +7507,9 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -7526,8 +7536,8 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg) +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -7580,9 +7590,9 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -7662,11 +7672,11 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, Delayed Idle is available whatever the timer operating mode (regular, push-pull) Balanced Idle is only available in push-pull mode */ - if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) + if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)) - || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) + || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) { - hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); + hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN); hrtim_timoutr |= pTimerCfg->DelayedProtectionMode; } @@ -7676,43 +7686,43 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Set the timer burst mode */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 1U); break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 2U); break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 3U); break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 4U); break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 5U); break; } - default: - break; + default: + break; } /* Update the HRTIM registers */ @@ -7731,7 +7741,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param Event Event reference * @retval None */ -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event) @@ -7740,86 +7750,86 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; break; } - default: - break; + default: + break; } switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger; break; } - default: - break; + default: + break; } } @@ -7831,10 +7841,10 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, * @param pOutputCfg pointer to the output configuration data structure * @retval None */ -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef *pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -7846,11 +7856,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; @@ -7858,11 +7868,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; @@ -7871,15 +7881,15 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } /* Clear output config */ hrtim_outr &= ~((HRTIM_OUTR_POL1 | HRTIM_OUTR_IDLM1 | - HRTIM_OUTR_IDLES1| - HRTIM_OUTR_FAULT1| + HRTIM_OUTR_IDLES1 | + HRTIM_OUTR_FAULT1 | HRTIM_OUTR_CHP1 | HRTIM_OUTR_DIDL1) << shift); @@ -7922,7 +7932,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, * @param pEventCfg pointer to the event channel configuration data structure * @retval None */ -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { @@ -7937,7 +7947,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR1 = 0U; @@ -7946,7 +7956,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC); @@ -7960,7 +7970,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC); @@ -7974,7 +7984,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC); @@ -7988,7 +7998,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC); @@ -8002,7 +8012,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC); @@ -8016,7 +8026,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC); @@ -8030,7 +8040,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC); @@ -8044,21 +8054,21 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC); hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL); hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS); hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F ); + hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC); @@ -8072,7 +8082,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC); @@ -8086,8 +8096,8 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } } @@ -8098,74 +8108,74 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @param Event Event channel identifier * @retval None */ -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event) { switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; break; } - default: - break; + default: + break; } } @@ -8188,7 +8198,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8198,13 +8208,13 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8217,29 +8227,29 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8252,24 +8262,24 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return interrupt; @@ -8294,7 +8304,7 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8304,13 +8314,13 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8323,29 +8333,29 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8358,81 +8368,81 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; + DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL; switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hdma = hhrtim->hdmaMaster; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hdma = hhrtim->hdmaTimerA; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hdma = hhrtim->hdmaTimerB; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hdma = hhrtim->hdmaTimerC; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hdma = hhrtim->hdmaTimerD; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hdma = hhrtim->hdmaTimerE; break; } - default: - break; + default: + break; } return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma) { uint32_t timed_idx = 0xFFFFFFFFU; @@ -8474,49 +8484,49 @@ static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, * @param TimerIdx Timer index * @retval None */ -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; break; } - default: - break; + default: + break; } } @@ -8526,15 +8536,15 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); /* Fault 1 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -8548,9 +8558,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -8564,9 +8574,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -8580,9 +8590,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -8596,9 +8606,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -8612,9 +8622,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -8629,11 +8639,11 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /** -* @brief Master timer interrupts service routine -* @param hhrtim pointer to HAL HRTIM handle -* @retval None -*/ -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) + * @brief Master timer interrupts service routine + * @param hhrtim pointer to HAL HRTIM handle + * @retval None + */ +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); @@ -8641,9 +8651,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); /* Burst mode period event */ - if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -8657,9 +8667,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -8673,9 +8683,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -8689,9 +8699,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -8705,9 +8715,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -8721,9 +8731,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -8737,9 +8747,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -8753,9 +8763,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -8780,17 +8790,17 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None -*/ -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) + */ +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); /* Timer compare 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -8804,9 +8814,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -8820,9 +8830,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -8836,9 +8846,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -8852,9 +8862,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -8868,9 +8878,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -8884,9 +8894,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -8900,9 +8910,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -8916,9 +8926,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -8932,9 +8942,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -8948,9 +8958,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -8964,9 +8974,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -8980,9 +8990,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -8996,9 +9006,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); @@ -9019,7 +9029,7 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) { @@ -9092,11 +9102,11 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) { uint8_t timer_idx; - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma); - if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;} + if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;} if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET) { @@ -9217,16 +9227,16 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) } /** -* @brief DMA error callback -* @param hdma pointer to DMA handle. -* @retval None -*/ + * @brief DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->ErrorCallback(hrtim); + hrtim->ErrorCallback(hrtim); #else HAL_HRTIM_ErrorCallback(hrtim); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ @@ -9239,10 +9249,10 @@ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) */ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); + hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #else HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c index 39b2d68dd5..665cab0631 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1407,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1428,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1439,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1451,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -3255,6 +3267,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3312,37 +3326,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -4552,7 +4593,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4561,7 +4602,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -7284,15 +7327,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c index d449267694..0cd61d309b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c @@ -1835,6 +1835,107 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) return errorcode; } +/** + * @brief Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature enabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Enable IO Swap feature */ + SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature disabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Disable the IO Swap feature */ + CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx. + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null. + */ +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return 0; + } + + return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + /** * @brief This function handles I2S interrupt request. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c index 2ec2829876..23955db40f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c @@ -127,7 +127,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c index ac257fab62..662519a8a4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c @@ -279,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); /* Set Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); tmp = (hltdc->Init.HorizontalSync << 16U); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); /* Set Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); tmp = (hltdc->Init.AccumulatedHBP << 16U); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); /* Set Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); tmp = (hltdc->Init.AccumulatedActiveW << 16U); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); /* Set Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); tmp = (hltdc->Init.TotalWidth << 16U); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); @@ -916,11 +912,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx) { uint32_t tmp; uint32_t counter; - uint32_t *pcolorlut = pCLUT; + const uint32_t *pcolorlut = pCLUT; /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -2092,7 +2089,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * the configuration information for the LTDC. * @retval HAL state */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc) { return hltdc->State; } @@ -2103,7 +2100,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval LTDC Error Code */ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) { return hltdc->ErrorCode; } @@ -2154,9 +2151,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | - LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -2167,8 +2162,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); /* Configure the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c index dc7b722acf..50b04a985a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c @@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum * @param hmdios: mdios handle * @retval bit map of written registers addresses */ -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios) { return hmdios->Instance->WRFR; } @@ -645,7 +645,7 @@ uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval bit map of read registers addresses */ -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios) { return hmdios->Instance->RDFR; } @@ -916,7 +916,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval mdios error code */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios) { /* return the error code */ return hmdios->ErrorCode; @@ -927,7 +927,7 @@ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval HAL state */ -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios) { /* Return MDIOS state */ return hmdios->State; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c index 089d9fbb1d..064949bc54 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -708,7 +708,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD * * @retval HAL status */ -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode) +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode) { MDMA_LinkNodeTypeDef *pNode; uint32_t counter = 0, nodeInserted = 0; @@ -1719,7 +1719,7 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) * the configuration information for the specified MDMA Channel. * @retval HAL state */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma) { return hmdma->State; } @@ -1730,7 +1730,7 @@ HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) * the configuration information for the specified MDMA Channel. * @retval MDMA Error Code */ -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma) { return hmdma->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c index 0aa5d66313..b67bdef9a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization - *** MMC Card Initialization and configuration *** ================================================ [..] @@ -93,6 +92,7 @@ (#) Select the corresponding MMC Card according to the address read with the step 2. (#) Configure the MMC Card in wide bus mode: 4-bits data. + (#) Select the MMC Card partition using HAL_MMC_SwitchPartition() *** MMC Card Read operation *** ============================== @@ -169,6 +169,64 @@ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. Some of the CID parameters are useful for card initialization and identification. + *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation *** + ============================== + [..] + (+) You can program the authentication key of RPMB area in polling mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can program the authentication key of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey_IT(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) write counter operation *** + ============================== + [..] + (+) You can get the write counter value of RPMB area in polling mode by using function + HAL_MMC_RPMB_GetWriteCounter(). + (+) You can get the write counter value of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_GetWriteCounter_IT(). + + *** MMC Card Reply Protected Memory Block (RPMB) write operation *** + ============================== + [..] + (+) You can write to the RPMB area of MMC card in polling mode by using function + HAL_MMC_WriteBlocks(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can write to the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_WriteBlocks_IT(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) read operation *** + ============================== + [..] + (+) You can read from the RPMB area of MMC card in polling mode by using function + HAL_MMC_RPMB_ReadBlocks(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + (+) You can read from the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_RPMB_ReadBlocks_IT(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + *** MMC HAL driver macros list *** ================================== [..] @@ -204,7 +262,7 @@ and a pointer to the user callback function. Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. (+) ErrorCallback : callback when error occurs. @@ -218,9 +276,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + reset to the legacy weak (overridden) functions in the HAL_MMC_Init and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -235,7 +293,7 @@ When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -253,6 +311,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -290,6 +349,12 @@ /* Frequencies used in the driver for clock divider calculation */ #define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ + +/* The Data elements' postitions in the frame Frame for RPMB area */ +#define MMC_RPMB_KEYMAC_POSITION 196U +#define MMC_RPMB_DATA_POSITION 228U +#define MMC_RPMB_NONCE_POSITION 484U +#define MMC_RPMB_WRITE_COUNTER_POSITION 500U /** * @} */ @@ -538,7 +603,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) return HAL_OK; } - /** * @brief Initializes the MMC MSP. * @param hmmc: Pointer to MMC handle @@ -655,7 +719,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -697,10 +761,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -712,7 +776,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -850,7 +914,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -892,10 +956,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -907,7 +971,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD tempbuff++; (void)SDMMC_WriteFIFO(hmmc->Instance, &data); } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -1044,7 +1108,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1157,7 +1221,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1271,7 +1335,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1386,7 +1450,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1504,8 +1568,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - start_add *= 512U; - end_add *= 512U; + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; } /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ @@ -1793,7 +1857,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) * @param hmmc: Pointer to mmc handle * @retval HAL state */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc) { return hmmc->State; } @@ -1804,7 +1868,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) * the configuration information. * @retval MMC Error Code */ -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc) { return hmmc->ErrorCode; } @@ -1872,7 +1936,7 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /** * @brief Register a User MMC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID * and HAL_MMC_MSP_DEINIT_CB_ID. @@ -1977,7 +2041,7 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call /** * @brief Unregister a User MMC Callback - * MMC Callback is redirected to the weak (surcharged) predefined callback + * MMC Callback is redirected to the weak (overridden) predefined callback * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID * and HAL_MMC_MSP_DEINIT_CB_ID. @@ -2099,7 +2163,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2185,14 +2249,14 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); - hmmc->MmcCard.LogBlockSize = 512U; + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / MMC_BLOCKSIZE); + hmmc->MmcCard.LogBlockSize = MMC_BLOCKSIZE; } else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) { hmmc->MmcCard.BlockNbr = block_nbr; hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; - hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.BlockSize = MMC_BLOCKSIZE; hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; } else @@ -2250,7 +2314,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -2300,7 +2364,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512U; + config.DataLength = MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -2326,7 +2390,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); tmp_buf++; @@ -2707,7 +2771,8 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /*we will send the CMD12 in all cases in order to stop the data transfers*/ - /*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer just finished, the external memory will not respond + and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/ /*Other scenario will return HAL_ERROR*/ @@ -2723,40 +2788,40 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) { if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } } else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } else @@ -2764,13 +2829,15 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /* Nothing to do*/ } - /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */ - /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */ + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result + in next SDMMC read/write operation to fail */ /*SDMMC ready for clear data flags*/ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - /* If IDMA Context, disable Internal DMA */ + /* If IDMA Context, disable Internal DMA */ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; hmmc->State = HAL_MMC_STATE_READY; @@ -2902,8 +2969,8 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT /* In case of low capacity card, the address is not block number but bytes */ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - start_add *= 512U; - end_add *= 512U; + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; } /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */ @@ -3562,7 +3629,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) * @{ */ - /** * @brief Initializes the mmc card. * @param hmmc: Pointer to MMC handle @@ -3646,7 +3712,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode |= errorstate; } - /* Get Extended CSD parameters */ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) { @@ -3789,7 +3854,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512U; + config.DataLength = MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3814,7 +3879,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { tmp_data = SDMMC_ReadFIFO(hmmc->Instance); /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ @@ -3896,10 +3961,10 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pRxBuffPtr; - if (hmmc->RxXferSize >= 32U) + if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3913,7 +3978,7 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) } hmmc->pRxBuffPtr = tmp; - hmmc->RxXferSize -= 32U; + hmmc->RxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3931,10 +3996,10 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pTxBuffPtr; - if (hmmc->TxXferSize >= 32U) + if (hmmc->TxXferSize >= SDMMC_FIFO_SIZE) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tmp); tmp++; @@ -3948,7 +4013,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) } hmmc->pTxBuffPtr = tmp; - hmmc->TxXferSize -= 32U; + hmmc->TxXferSize -= SDMMC_FIFO_SIZE; } } @@ -4276,6 +4341,1553 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 return errorstate; } +/** + * @brief Used to select the partition. + * @param hmmc: Pointer to MMC handle + * @param Partition: Partition type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) +{ + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + uint32_t tickstart = HAL_GetTick(); + uint32_t arg = Partition | 0x03B30000U; + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Index : 179 - Value : partition */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Allows to program the authentication key within the RPMB partition + * @param hmmc: Pointer to MMC handle + * @param pKey: pointer to the authentication key (32 bytes) + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + + tail_pack[11] = 0x01; + + if (NULL == pKey) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x80000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pKey; + } + else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \ + (byte_count >= MMC_RPMB_DATA_POSITION)) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to get the value of write counter within the RPMB partition. + * @param hmmc: Pointer to MMC handle + * @param pNonce: pointer to the value of nonce (16 bytes) + * @param Timeout: Specify timeout value + * @retval write counter value. + */ +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint8_t *tempbuff = zero_pack; + + tail_pack[11] = 0x02; + + if (NULL == pNonce) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = (uint8_t *)pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + + return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \ + ((uint32_t)tail_pack[0] << 24)); + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } +} + +/** + * @brief Allows to write block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout) +{ + + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08 + }; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0x80000000U; + uint32_t offset = 0; + + if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if ((NULL == pData) || (NULL == pMAC)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + tail_pack[11] = 0x02; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = local_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (local_nonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } + tail_pack[11] = 0x03; + tail_pack[10] = 0x00; + tail_pack[7] = (uint8_t)(NumberOfBlocks) & 0xFFU; + tail_pack[6] = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + + rtempbuff = zero_pack; + byte_count = 0; + arg |= NumberOfBlocks; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pMAC; + } + if (byte_count == MMC_RPMB_DATA_POSITION) + { + rtempbuff = &pData[offset]; + } + if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \ + (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)) + { + rtempbuff = zero_pack; + } + if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + offset += (uint32_t)256U; + byte_count = 0; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Response Packet */ + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to read block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pNonce: Pointer to the buffer that will contain the nonce to transmit + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint32_t dataremaining; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0; + uint32_t offset = 0; + + arg |= NumberOfBlocks; + + tail_pack[11] = 0x04; + tail_pack[10] = 0x00; + tail_pack[7] = 0x00; + tail_pack[6] = 0x00; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + tail_pack[3] = 0x00; + tail_pack[2] = 0x00; + tail_pack[1] = 0x00; + tail_pack[0] = 0x00; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = (uint8_t *)pMAC; + } + else if (byte_count == MMC_RPMB_DATA_POSITION) + { + tempbuff = &pData[offset]; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + byte_count = 0; + offset += (uint32_t)256U; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + + /** * @brief Read DMA Buffer 0 Transfer completed callbacks * @param hmmc: MMC handle @@ -4341,6 +5953,7 @@ __weak void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc) */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c index 10acaf3610..8723867067 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c @@ -45,6 +45,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -59,7 +60,6 @@ */ - /** @addtogroup MMCEx_Exported_Functions_Group1 * @brief Multibuffer functions * @@ -333,7 +333,6 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D return HAL_OK; } - /** * @} */ @@ -343,6 +342,7 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c index 87c492d0f1..370d123d52 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c index 688ff3e7af..5bb8080317 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c @@ -902,10 +902,10 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp) * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available * */ -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) { HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; - __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + __IO const uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ @@ -1122,7 +1122,7 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL * @param hopamp OPAMP handle * @retval HAL state */ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp) { /* Check the OPAMP handle allocation */ if(hopamp == NULL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c index 46474bfe11..332f08082e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c @@ -1177,7 +1177,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1270,7 +1271,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1597,7 +1599,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } /* Enable the transmit MDMA Channel */ - if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize, 1) == \ + if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == \ HAL_OK) { /* Enable the transfer error interrupt */ @@ -2581,8 +2583,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c index af78206b19..f34f396116 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c @@ -69,11 +69,11 @@ The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions HAL_OTFDEC_RegisterCallback() + Use Functions @ref HAL_OTFDEC_RegisterCallback() to register an interrupt callback. [..] - Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks: + Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : OTFDEC error callback (+) MspInitCallback : OTFDEC Msp Init callback (+) MspDeInitCallback : OTFDEC Msp DeInit callback @@ -81,11 +81,11 @@ and a pointer to the user callback function. [..] - Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default + Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default weak function. [..] - HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, + @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : OTFDEC error callback @@ -93,27 +93,27 @@ (+) MspDeInitCallback : OTFDEC Msp DeInit callback [..] - By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET + By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET all callbacks are set to the corresponding weak functions: - example HAL_OTFDEC_ErrorCallback(). + example @ref HAL_OTFDEC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when + reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit() + If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only. + Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state, + in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit() - or HAL_OTFDEC_Init() function. + using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit() + or @ref HAL_OTFDEC_Init() function. [..] When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or @@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) { OTFDEC_Region_TypeDef *region; uint32_t address; @@ -753,16 +753,16 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_ * @param pKey pointer at set of keys * @retval CRC value */ -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey) { uint8_t crc7_poly = 0x7; - uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; + const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; uint8_t i; uint8_t crc = 0; uint32_t j; uint32_t keyval; uint32_t k; - uint32_t *temp = pKey; + const uint32_t *temp = pKey; for (j = 0U; j < 4U; j++) { @@ -901,7 +901,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 * the configuration information for OTFDEC module * @retval HAL state */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec) { return hotfdec->State; } @@ -914,9 +914,9 @@ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) * @param RegionIndex index of region the keys CRC of which is read * @retval Key CRC */ -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef *region; + const OTFDEC_Region_TypeDef *region; uint32_t address; uint32_t keycrc; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c index 221cdfc082..a50cac24be 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c @@ -1453,7 +1453,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1766,7 +1766,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1781,7 +1781,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; if (ep->is_in != 0U) @@ -2101,6 +2101,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; @@ -2331,13 +2332,11 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /** * @} */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c index 60fb841d8b..4262725490 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -412,7 +412,7 @@ void HAL_PWR_DisableBkUpAccess (void) * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD) { /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c index 4b1a86e7c5..6faff7386c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -308,6 +308,10 @@ * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. + * @note This API is deprecated and is kept only for backward compatibility's sake. + * The power supply configuration is handled as part of the system initialization + * process during startup. + * For more details, please refer to the power control chapter in the reference manual * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) @@ -1299,7 +1303,7 @@ void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) * Cortex-M4. * @retval None. */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams) { uint32_t pinConfig; uint32_t regMask; @@ -1973,7 +1977,7 @@ PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD) { /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c index 1d8fa10e68..48554f57a3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c @@ -1325,21 +1325,24 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat status = HAL_ERROR; } + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Use DMAEN bit with no impact on H7 HW to record MDMA transfer request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Enable the QSPI transmit MDMA */ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" - but no impact on H7 HW and it minimize the cost in the footprint */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } else { + /* Clear DMAEN bit with no impact on H7 HW to cancel MDMA transfer request */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + status = HAL_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; hqspi->State = HAL_QSPI_STATE_READY; @@ -1440,21 +1443,23 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Use DMAEN bit with no impact on H7 HW to record MDMA transfer request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Enable the MDMA */ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" - but no impact on H7 HW and it minimize the cost in the footprint */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } else { + /* Clear DMAEN bit with no impact on H7 HW to cancel MDMA transfer request */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + status = HAL_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; hqspi->State = HAL_QSPI_STATE_READY; @@ -2550,6 +2555,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2577,6 +2585,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } @@ -2611,6 +2622,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2640,6 +2654,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c index d59992a95f..ec1e1f34a7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c @@ -613,7 +613,7 @@ __weak void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing address offset. */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -629,7 +629,7 @@ uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing data low. */ -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -645,7 +645,7 @@ uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing data high. */ -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -661,7 +661,7 @@ uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Hamming bits injected. */ -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -677,7 +677,7 @@ uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval State of bit (1 or 0). */ -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -693,7 +693,7 @@ uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval State of bit (1 or 0). */ -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -734,7 +734,7 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC state. */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc) +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC state */ return hramecc->State; @@ -747,7 +747,7 @@ HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC error code. */ -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC error code */ return hramecc->ErrorCode; @@ -760,7 +760,7 @@ uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC error code detected. */ -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC error code detected*/ return hramecc->RAMECCErrorCode; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c index 8c987ac8ef..dad88545fd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -919,7 +919,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { HAL_StatusTypeDef halstatus; uint32_t tickstart; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c index 96517ce083..b619c4ae5e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -58,8 +58,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider); /* Exported functions --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions @@ -3379,7 +3379,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) { uint32_t value; @@ -3690,7 +3690,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { uint32_t tickstart; @@ -3795,7 +3795,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c index ef602992f4..7f5142d28d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c @@ -116,9 +116,9 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} @@ -216,7 +216,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -257,12 +257,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -673,6 +673,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c index 70c5540524..0bcb1add39 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -45,16 +45,16 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -66,11 +66,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -283,7 +283,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -320,6 +320,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c index 140826c0fd..0216e438db 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c @@ -112,10 +112,20 @@ (+) TimeStampEventCallback : RTC TimeStamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. (*) (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Callback ID (*) + (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Callback ID (*) + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Callback ID (*) + (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Callback ID (*) + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Callback ID (*) + (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Callback ID (*) + (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Callback ID (*) (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. + + (*) Not applicable to all devices. + This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -129,11 +139,20 @@ (+) TimeStampEventCallback : RTC TimeStamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. (*) (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Callback ID (*) + (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Callback ID (*) + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Callback ID (*) + (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Callback ID (*) + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Callback ID (*) + (+) InternalTamper6EventCallback : RTC Internal Tamper 6 Callback ID (*) + (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Callback ID (*) (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. + (*) Not applicable to all devices. + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions : examples AlarmAEventCallback(), WakeUpTimerEventCallback(). @@ -254,7 +273,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#if defined(RTC_TAMPER2_SUPPORT) hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#endif /* RTC_TAMPER2_SUPPORT */ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ #if defined(TAMP) @@ -483,17 +504,18 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID (*) * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID (*) * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * (*) Not applicable to all devices. * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -533,9 +555,11 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call hrtc->Tamper1EventCallback = pCallback; break; +#if defined(RTC_TAMPER2_SUPPORT) case HAL_RTC_TAMPER2_EVENT_CB_ID : hrtc->Tamper2EventCallback = pCallback; break; +#endif /* RTC_TAMPER2_SUPPORT */ case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = pCallback; @@ -626,17 +650,18 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID (*) * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID - * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID (*) + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID (*) * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * (*) Not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -670,9 +695,11 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ break; +#if defined(RTC_TAMPER2_SUPPORT) case HAL_RTC_TAMPER2_EVENT_CB_ID : hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ break; +#endif /* RTC_TAMPER2_SUPPORT */ case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ @@ -920,7 +947,7 @@ HAL_StatusTypeDef status; * to ensure consistency between the time and date values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; @@ -1052,7 +1079,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * Reading RTC current time locks the values in calendar shadow registers until Current date is read. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1604,7 +1631,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { uint32_t tmpreg; uint32_t subsecondtmpreg; @@ -1883,7 +1910,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) { /* Return RTC handle state */ return hrtc->State; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c index 252dce91b8..aef0524bc7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c @@ -115,7 +115,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(TAMP) #define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) +#endif /* TAMP */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -469,7 +471,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -537,7 +539,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -576,6 +578,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); } +#if defined(RTC_TAMPNOERASE_SUPPORT) /* Configure the tamper backup registers erasure bit */ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { @@ -607,7 +610,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); } } +#endif /* RTC_TAMPNOERASE_SUPPORT */ +#if defined(RTC_TAMPMASKFLAG_SUPPORT) /* Configure the tamper flags masking bit */ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { @@ -639,6 +644,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); } } +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ /* Clearing remaining fields before setting them */ tmpreg &= ~(RTC_TAMPERFILTER_MASK | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ @@ -671,7 +677,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -748,7 +754,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -788,6 +794,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); } +#if defined(RTC_TAMPNOERASE_SUPPORT) /* Configure the tamper backup registers erasure bit */ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { @@ -819,7 +826,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); } } +#endif /* RTC_TAMPNOERASE_SUPPORT */ +#if defined(RTC_TAMPMASKFLAG_SUPPORT) /* Configure the tamper flags masking bit */ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { @@ -851,6 +860,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); } } +#endif /* RTC_TAMPMASKFLAG_SUPPORT */ /* Clearing remaining fields before setting them */ tmpreg &= ~(RTC_TAMPERFILTER_MASK | RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ @@ -933,8 +943,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t * @param Tamper Selected tamper pin. * This parameter can be any combination of the following values: * @arg RTC_TAMPER_1 - * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_2 (*) * @arg RTC_TAMPER_3 + * (*) Not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t Tamper) @@ -949,21 +960,28 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t /* Disable the selected Tamper pin */ hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); +#if defined(RTC_TAMPxIE_SUPPORT) /* Disable the selected Tamper interrupt */ if ((Tamper & RTC_TAMPER_1) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); } +#if defined(RTC_TAMPER2_SUPPORT) if ((Tamper & RTC_TAMPER_2) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); } +#endif /* RTC_TAMPER2_SUPPORT */ if ((Tamper & RTC_TAMPER_3) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); } +#else + /* Disable the Tamper interrupt */ + hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP); +#endif /* RTC_TAMPxIE_SUPPORT */ hrtc->State = HAL_RTC_STATE_READY; @@ -981,7 +999,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper) { /* Check the parameters */ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); @@ -1007,7 +1025,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_Inter * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper) { /* Check the parameters */ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); @@ -1063,7 +1081,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui * @param sAllTamper Pointer to active Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper) +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper) { uint32_t IER, CR1, CR2, ATCR1, CR, i, tickstart; @@ -1177,7 +1195,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active * @param pSeed Pointer to active tamper seed values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed) +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed) { uint32_t i, tickstart; @@ -1295,6 +1313,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } +#if defined(RTC_TAMPER2_SUPPORT) /* Check Tamper 2 status */ if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) { @@ -1306,6 +1325,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_Tamper2EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } +#endif /* RTC_TAMPER2_SUPPORT */ /* Check Tamper 3 status */ if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) @@ -1442,7 +1462,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } /* Get the Tamper 1 interrupt source enable status */ +#if defined(RTC_TAMPxIE_SUPPORT) if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) +#else + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) +#endif /* RTC_TAMPxIE_SUPPORT */ { /* Get the pending status of the Tamper 1 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) @@ -1460,7 +1484,12 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } /* Get the Tamper 2 interrupt source enable status */ +#if defined(RTC_TAMPER2_SUPPORT) +#if defined(RTC_TAMPxIE_SUPPORT) if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) +#else + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) +#endif /* RTC_TAMPxIE_SUPPORT */ { /* Get the pending status of the Tamper 2 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) @@ -1476,9 +1505,14 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } +#endif /* RTC_TAMPER2_SUPPORT */ /* Get the Tamper 3 interrupts source enable status */ +#if defined(RTC_TAMPxIE_SUPPORT) if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) +#else + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) +#endif /* RTC_TAMPxIE_SUPPORT */ { /* Get the pending status of the Tamper 3 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) @@ -1540,6 +1574,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef * hrtc) */ } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Tamper 2 callback. * @param hrtc RTC handle @@ -1554,6 +1589,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef * hrtc) the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Tamper 3 callback. @@ -1768,6 +1804,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Handle Tamper2 Polling. * @param hrtc RTC handle @@ -1799,6 +1836,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @brief Handle Tamper3 Polling. @@ -2129,7 +2167,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval Counter value */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc) { /* Get the counter value */ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); @@ -2273,7 +2311,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef * hrtc, ui * @param Data Data to be written in the specified Backup data register. * @retval None */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data) +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -2282,9 +2320,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint /* Point on address of first backup register */ #if defined(TAMP) - tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); + tmp = (uint32_t) &(((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); #else - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); #endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2302,7 +2340,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint * specify the register. * @retval Read value */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) { uint32_t tmp; @@ -2311,9 +2349,9 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) /* Point on address of first backup register */ #if defined(TAMP) - tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); + tmp = (uint32_t) &(((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); #else - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); #endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2709,7 +2747,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef * hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + hrtc->Instance->CR |= (uint32_t)RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2741,7 +2779,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef * hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BYPSHAD); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2784,7 +2822,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, * @param Counter monotonic counter value * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance) +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance) { UNUSED(hrtc); UNUSED(Instance); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c index fea0680856..ae33c68277 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - *** SD Card Initialization and configuration *** ================================================ [..] @@ -211,7 +210,7 @@ respectively HAL_SD_RegisterTransceiverCallback(). Use function HAL_SD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. (+) ErrorCallback : callback when error occurs. @@ -227,9 +226,9 @@ respectively HAL_SD_UnRegisterTransceiverCallback(). By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SD_Init + reset to the legacy weak (overridden) functions in the HAL_SD_Init and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -244,7 +243,7 @@ When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -261,6 +260,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -439,7 +439,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -607,7 +607,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Initializes the SD MSP. * @param hsd: Pointer to SD handle @@ -704,7 +703,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -746,10 +745,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 dataremaining = config.DataLength; while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -761,7 +760,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -889,7 +888,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -932,10 +931,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -947,7 +946,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData tempbuff++; (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -1074,7 +1073,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1169,7 +1168,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pD if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1266,7 +1265,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1310,7 +1309,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - return HAL_OK; } else @@ -1365,7 +1363,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1377,7 +1375,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; @@ -1474,8 +1471,8 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Get start and end block for high capacity cards */ if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - start_add *= 512U; - end_add *= 512U; + start_add *= BLOCKSIZE; + end_add *= BLOCKSIZE; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ @@ -1765,7 +1762,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) * @param hsd: Pointer to sd handle * @retval HAL state */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd) { return hsd->State; } @@ -1776,7 +1773,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) * the configuration information. * @retval SD Error Code */ -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd) { return hsd->ErrorCode; } @@ -1860,7 +1857,7 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /** * @brief Register a User SD Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID * and HAL_SD_MSP_DEINIT_CB_ID. @@ -1965,7 +1962,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback /** * @brief Unregister a User SD Callback - * SD Callback is redirected to the weak (surcharged) predefined callback + * SD Callback is redirected to the weak (overridden) predefined callback * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID * and HAL_SD_MSP_DEINIT_CB_ID. @@ -2062,7 +2059,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba #if (USE_SD_TRANSCEIVER != 0U) /** * @brief Register a User SD Transceiver Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hsd : SD handle * @param pCallback : pointer to the Callback function * @retval status @@ -2100,7 +2097,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ /** * @brief Unregister a User SD Transceiver Callback - * SD Callback is redirected to the weak (surcharged) predefined callback + * SD Callback is redirected to the weak (overridden) predefined callback * @param hsd : SD handle * @retval status */ @@ -2157,7 +2154,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2236,8 +2233,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); - hsd->SdCard.LogBlockSize = 512U; + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / BLOCKSIZE); + hsd->SdCard.LogBlockSize = BLOCKSIZE; } else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) { @@ -2246,7 +2243,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; - hsd->SdCard.BlockSize = 512U; + hsd->SdCard.BlockSize = BLOCKSIZE; hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; } else @@ -2363,7 +2360,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } - return status; } @@ -2374,7 +2370,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); @@ -2404,6 +2400,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2833,7 +2830,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2893,11 +2890,12 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /*we will send the CMD12 in all cases in order to stop the data transfers*/ - /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer just finished , the external memory will not respond + and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/ /*Other scenario will return HAL_ERROR*/ @@ -2913,40 +2911,40 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { if (hsd->ErrorCode == HAL_SD_ERROR_NONE) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } } else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } else @@ -2962,7 +2960,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /*SDMMC ready for clear data flags*/ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END); __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - /* If IDMA Context, disable Internal DMA */ + /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; hsd->State = HAL_SD_STATE_READY; @@ -2973,7 +2971,6 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -3031,7 +3028,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ - /** * @brief Initializes the sd card. * @param hsd: Pointer to SD handle @@ -3237,7 +3233,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check to CKSTOP */ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3267,7 +3263,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check VSWEND Flag */ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3375,7 +3371,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } } - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3403,7 +3399,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3538,7 +3534,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) } } - /** * @brief Finds the SD card SCR register value. * @param hsd: Pointer to SD handle @@ -3593,8 +3588,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) index++; } - - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3624,11 +3618,11 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24U)); scr++; - *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24U)); } @@ -3649,10 +3643,10 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) tmp = hsd->pRxBuffPtr; - if (hsd->RxXferSize >= 32U) + if (hsd->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3666,7 +3660,7 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) } hsd->pRxBuffPtr = tmp; - hsd->RxXferSize -= 32U; + hsd->RxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3684,10 +3678,10 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) tmp = hsd->pTxBuffPtr; - if (hsd->TxXferSize >= 32U) + if (hsd->TxXferSize >= SDMMC_FIFO_SIZE) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tmp); tmp++; @@ -3701,7 +3695,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) } hsd->pTxBuffPtr = tmp; - hsd->TxXferSize -= 32U; + hsd->TxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3750,7 +3744,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3768,8 +3761,7 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) } loop ++; } - - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -3885,7 +3877,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeed loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4015,7 +4007,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4142,12 +4134,12 @@ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd) */ } - /** * @} */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c index 1cc19e3135..aa50d0bf39 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c @@ -44,6 +44,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -303,6 +304,7 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c new file mode 100644 index 0000000000..ddde94eb91 --- /dev/null +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdio.c @@ -0,0 +1,2877 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_sdio.c + * @author MCD Application Team + * @brief SDIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital Input Output (SDIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this SDIO card. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_SDIO_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with SDIO cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implementing the HAL_SDIO_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for SDIO card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) NVIC configuration if you need to use interrupt process (HAL_SDIO_ReadExtended_DMA() + and HAL_SDIO_WriteExtended_DMA() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SDIO_ENABLE_IT() + and __HAL_SDIO_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SDIO_GET_IT(). + (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used. + + (#) At this stage, you can perform SDIO read/write/erase operations after SDIO card initialization. + + *** SDIO Card Initialization and configuration *** + ================================================ + [..] + To initialize the SDIO Card, use the HAL_SDIO_Init() function. It Initializes + SDMMC Peripheral(STM32 side) and the SDIO Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SDIO Card initialization process at 400KHz. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SDIO Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) + + In initialization mode and according to the SDIO Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the SDIO card. The API used is HAL_SDIO_Init(). + This phase allows the card initialization and identification. + + (#) Configure the SDIO Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field by the API HAL_SDIO_ConfigFrequency(). + + (#) Configure the SDIO Card in wide bus mode: 4-bits data by the API HAL_SDIO_SetDataBusWidth(). + + (#) Configure the SDIO Card data block size by the API : HAL_SDIO_SetBlockSize(). + + (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode(). + + (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback + function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function. + + *** SDIO Card Read operation *** + ============================== + [..] + (+) You can read from SDIO card in polling mode by using function HAL_SDIO_ReadExtended(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + + (+) You can read from SDIO card in DMA mode by using function HAL_SDIO_ReadExtended_DMA(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + After this, you have to ensure that the transfer is done correctly. + You could also check the DMA transfer process through the SDIO Rx interrupt event. + + *** SDIO Card Write operation *** + =============================== + [..] + (+) You can write to SDIO card in polling mode by using function HAL_SDIO_WriteExtended(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + + (+) You can write to SDIO card in DMA mode by using function HAL_SDIO_WriteExtended_DMA(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + You could also check the DMA transfer process through the SDIO Tx interrupt event. + + + *** SDIO card common control register (CCCR) *** + ====================== + [..] + (+) The SDIO CCCR allow for quick host checking and control of an IO card's enable and interrupts on a per card and + per function basis. + To get the Card common control registers field, you can use the API HAL_SDIO_GetCardCommonControlRegister(). + + *** SDIO card Function basic register (FBR) *** + =========================== + [..] + (+) The SDIO card function basic register are used to allow the host to quickly determine the abilities and + requirements of each function. + (+) To get the SDIO function basic register information, you can use the API HAL_SDIO_GetCardFBRRegister(). + + *** SDIO HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SDIO HAL driver. + + (+) __HAL_SDIO_ENABLE_IT: Enable the SDIO device interrupt + (+) __HAL_SDIO_DISABLE_IT: Disable the SDIO device interrupt + (+) __HAL_SDIO_GET_FLAG: Check whether the specified SDIO flag is set or not + (+) __HAL_SDIO_CLEAR_FLAG: Clear the SDIO's pending flags + (+) __HAL_SDIO_GET_IT: Check whether the specified SDIO interrupt has occurred or not + (+) __HAL_SDIO_GET_IT_SOURCE: Checks whether the specified SDIO interrupt is enabled or not + + (@) You can refer to the SDIO HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SDIO_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) MspInitCallback : SDIO MspInit. + (+) MspDeInitCallback : SDIO MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + For specific callbacks TransceiverCallback use dedicated register callbacks: + respectively HAL_SDIO_RegisterTransceiverCallback(). + + Use function HAL_SDIO_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) MspInitCallback : SDIO MspInit. + (+) MspDeInitCallback : SDIO MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + For specific callbacks TransceiverCallback use dedicated unregister callbacks: + respectively HAL_SDIO_UnRegisterTransceiverCallback(). + + By default, after the HAL_SDIO_Init and if the state is HAL_SDIO_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SDIO_Init + and HAL_SDIO_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDIO_Init and HAL_SDIO_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SDIO_RegisterCallback before calling HAL_SDIO_DeInit + or HAL_SDIO_Init function. + + When The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + *** SDIO peripheral IO interrupt *** + ============================================= + [..] + (+) Below the list of most used SDIO function to check and control the IO card's enable and interrupts on a per + functions basis. + + (+) HAL_SDIO_EnableIOFunctionInterrupt: Enable SDIO IO interrupt. + (+) HAL_SDIO_DisableIOFunctionInterrupt: Disable SDIO IO interrupt. + (+) HAL_SDIO_EnableIOFunction: Enable Function number(0-7) + (+) HAL_SDIO_DisableIOFunction: Disable Function number(0-7) + (+) HAL_SDIO_SelectIOFunction: Select a function number(0-7) + (+) HAL_SDIO_AbortIOFunction: Abort an IO read or write operation and free the SDIO bus. + (+) HAL_SDIO_EnableIOAsynInterrupt: Enable Bit of asynchronous interrupt + (+) HAL_SDIO_DisableIOAsynInterrupt: Disable Bit of asynchronous interrupt + + @endverbatim + ****************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_SDIO_MODULE_ENABLED + +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @addtogroup SDIO_Private_Defines + * @{ + */ +#define SDIO_INIT_FREQ 400000U /*!< Initialization phase : 400 kHz max */ +#define SDIO_TIMEOUT 1000U /*!< SDIO timeout millisecond */ + +#define SDIO_FUNCTION_0 0x00U /*!< SDIO_Functions 0 */ +#define SDIO_FUNCTION_1 0x01U /*!< SDIO_Functions 1 */ + +#define SDIO_READ 0x0U /*!< Read flag for cmd52 and cmd53 */ +#define SDIO_WRITE 0x1U /*!< Write flag for cmd52 and cmd53 */ + +#define SDIO_BUS_SPEED_SDR12 0x00U /*!< SDIO bus speed mode SDR12 */ +#define SDIO_BUS_SPEED_SDR25 0x02U /*!< SDIO bus speed mode SDR25 */ +#define SDIO_BUS_SPEED_SDR50 0x04U /*!< SDIO bus speed mode SDR50 */ +#define SDIO_BUS_SPEED_DDR50 0x08U /*!< SDIO bus speed mode DDR50 */ + +#define SDIO_CCCR_REG_NUMBER 0x16U /*!< SDIO card cccr register number */ + +#define SDIO_OCR_VDD_32_33 (1U << 20U) +#define SDIO_OCR_SDIO_S18R (1U << 24U) +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +#define IS_SDIO_RAW_FLAG(ReadAfterWrite) (((ReadAfterWrite) == HAL_SDIO_WRITE_ONLY) || \ + ((ReadAfterWrite) == HAL_SDIO_READ_AFTER_WRITE)) + +#define IS_SDIO_FUNCTION(FN) (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7)) + +#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ +static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio); +static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, + uint8_t *pData); +static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, + uint8_t *pData); +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, + uint8_t *pData, uint16_t Size_byte); +static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size); +static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDIO_Exported_Functions + * @{ + */ +/** @addtogroup SDIO_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SDIO + device to be ready for use. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the SDIO according to the specified parameters in the + SDIO_HandleTypeDef and create the associated handle. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) +{ + SDIO_InitTypeDef Init; + uint32_t sdmmc_clk; + uint8_t data; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hsdio->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsdio->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hsdio->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsdio->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hsdio->Init.ClockDiv)); + + /* Check the SDIO handle allocation */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_RESET) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SDIO_STATE_RESET only */ + hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback; + hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback; + hsdio->ErrorCallback = HAL_SDIO_ErrorCallback; +#if (USE_SDIO_TRANSCEIVER != 0U) + if (hsdio->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback; + } +#endif /* USE_SDIO_TRANSCEIVER */ + + if (hsdio->MspInitCallback == NULL) + { + hsdio->MspInitCallback = HAL_SDIO_MspInit; + } + /* Init the low level hardware */ + hsdio->MspInitCallback(hsdio); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SDIO_MspInit(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk == 0U) + { + hsdio->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * SDIO_INIT_FREQ); + /* Initialize SDMMC peripheral interface with default configuration */ + (void)SDMMC_Init(hsdio->Instance, Init); + + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hsdio->Instance); + + /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */ + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + + if (hsdio->SDIO_IdentifyCard == NULL) + { + hsdio->SDIO_IdentifyCard = SDIO_InitCard; + } + /* SDIO enumeration sequence */ + if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK) + { + hsdio->State = HAL_SDIO_STATE_RESET; + return HAL_ERROR; + } + + /* Configure the SDMMC user parameters */ + Init.ClockEdge = hsdio->Init.ClockEdge; + Init.ClockPowerSave = hsdio->Init.ClockPowerSave; + Init.BusWide = hsdio->Init.BusWide; + Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; + Init.ClockDiv = hsdio->Init.ClockDiv; + (void)SDMMC_Init(hsdio->Instance, Init); + + data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->Context = SDIO_CONTEXT_NONE; + hsdio->State = HAL_SDIO_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initializes the SDIO device. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio) +{ + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance)); + + /* Check the SDIO handle allocation */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hsdio->Instance); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + if (hsdio->MspDeInitCallback == NULL) + { + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdio->MspDeInitCallback(hsdio); +#else + /* De-Initialize the MSP layer */ + HAL_SDIO_MspDeInit(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the SDIO MSP. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SDIO MSP. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_MspDeInit could be implemented in the user file + */ +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group2 + * @brief + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to re-configure the SDIO peripheral. + +@endverbatim + * @{ + */ +/** + * @brief Enables wide bus operation for the requested card if supported by card. + * @param hsdio: Pointer to SDIO handle + * @param BusWide: Specifies the SDIO card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide) +{ + uint8_t data; + HAL_StatusTypeDef error_state = HAL_OK; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + data = (BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_WIDBUS, + (BusWide == HAL_SDIO_4_WIRES_MODE) ? SDMMC_BUS_WIDE_4B : SDMMC_BUS_WIDE_1B); + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + error_state = HAL_ERROR; + } + } + else + { + error_state = HAL_ERROR; + } + + return error_state; +} + +/** + * @brief Update the SDIO Clock. + * @param hsdio: Pointer to SDIO handle. + * @param ClockSpeed: SDIO Clock speed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed) +{ + uint32_t ClockDiv; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)) / (2U * ClockSpeed); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_CLKDIV, ClockDiv); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set the SDIO block size. + * @param hsdio: Pointer to SDIO handle + * @param function_nbr: Specifies the SDIO function number. + * @param BlockSize: Specifies the SDIO Block size to set. + * This parameter can be one of the following values @ref SDIO_Exported_Constansts_Group7. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize) +{ + HAL_SDIO_ExtendedCmd_TypeDef cmd53; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(function_nbr)); + assert_param(IS_SDIO_SUPPORTED_BLOCK_SIZE(BlockSize)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /* Set SDIO F1 block size */ + cmd53.IOFunctionNbr = SDIO_FUNCTION_0; + cmd53.OpCode = HAL_SDIO_OP_CODE_AUTO_INC; + cmd53.Block_Mode = HAL_SDIO_MODE_BYTE; + cmd53.Reg_Addr = (function_nbr * 0x100UL) + 0x10UL; + if (SDIO_WriteExtended(hsdio, &cmd53, (uint8_t *)(&BlockSize), 2U) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->block_size = BlockSize; + + return HAL_OK; +} + +/** + * @brief Configure the data rate. + * @param hsdio: Pointer to SDIO handle + * @param DataRate: Specifies the SDIO data rate to set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate) +{ + HAL_StatusTypeDef errorstate = HAL_OK; + uint8_t data; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + switch (DataRate) + { + case HAL_SDIOS_DATA_RATE_SDR25: + data = SDIO_BUS_SPEED_SDR25; + errorstate = SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR16_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + break; + + case HAL_SDIOS_DATA_RATE_SDR50: + data = SDIO_BUS_SPEED_SDR50; + errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2U) | (SDIO_FUNCTION_0 << 1U) | (SDIO_FUNCTION_0 << 14U) + | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED, SDMMC_CLKCR_BUSSPEED); + break; + + case HAL_SDIOS_DATA_RATE_DDR50: + data = SDIO_BUS_SPEED_DDR50; + errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | + SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED, + SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED); + break; + default: /* SDR12 */ + break; + } + + return (errorstate != HAL_OK) ? HAL_ERROR : HAL_OK; +} + +/** + * @brief Reset SDIO Card + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio) +{ + uint8_t data = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /** To reset the SDIO module by CMD52 with writing to RES in CCCR or send CMD0 the card shall change the speed mode + * default speed mode. + * The reset cmd (cmd0) is only used for memory. In order to reset an I/O card or the I/O portion of a combo card, + * Use CMD52 to write 1 to the RES bit in the CCC(bit3 of register 6). + */ + if (SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | + SDMMC_SDIO_CCCR4_SD_BYTE2), + HAL_SDIO_WRITE_ONLY, + 0U, + &data) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->State = HAL_SDIO_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Get Card Common Control register (CCCR). + * @param hsdio: Pointer to SDIO handle. + * @param pCccr: Pointer to Cccr register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr) +{ + uint8_t tempBuffer[256] = {0U}; + uint32_t count; + + assert_param(hsdio != NULL); + assert_param(pCccr != NULL); + + if ((hsdio == NULL) || (pCccr == NULL)) + { + return HAL_ERROR; + } + + for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++) + { + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0 + count, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != + HAL_OK) + { + return HAL_ERROR; + } + } + + pCccr->cccr_revision = tempBuffer[0] & 0x0FU; + pCccr->sdio_revision = (tempBuffer[0] & 0xF0U) >> 4U; + pCccr->sd_spec_revision = tempBuffer[0x01U] & 0x0FU; + pCccr->bus_width_8Bit = ((tempBuffer[0x07U] & 0x04U) != 0U) ? HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED + : HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED; + pCccr->card_capability = (tempBuffer[0x08U] & 0xDFUL); + /* common CIS pointer */ + pCccr->commonCISPointer = tempBuffer[0x09U] | ((uint32_t)tempBuffer[(uint32_t)0x09U + 1U] << 8U) | + ((uint32_t)tempBuffer[(uint32_t)0x09U + 2U] << 16U); + + return HAL_OK; +} + +/** + * @brief Get Card Function Basic register(FBR). + * @param hsdio: Pointer to SDIO handle. + * @param pFbr: Pointer to Fbr register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr) +{ + uint8_t tempBuffer[256] = {0U}; + uint32_t count; + uint8_t func_idx; + + assert_param(hsdio != NULL); + assert_param(pFbr != NULL); + + if ((hsdio == NULL) || (pFbr == NULL)) + { + return HAL_ERROR; + } + + for (func_idx = 2U; func_idx <= SDIO_MAX_IO_NUMBER; func_idx++) + { + for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++) + { + if (SDIO_ReadDirect(hsdio, (((uint32_t)SDMMC_SDIO_F1BR0 * (uint32_t)func_idx) + count), + HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != HAL_OK) + { + return HAL_ERROR; + } + } + pFbr[(uint32_t)func_idx - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + pFbr[(uint32_t)func_idx - 1U].ioExtFunctionCode = tempBuffer[1U]; + pFbr[(uint32_t)func_idx - 1U].ioPointerToCIS = tempBuffer[9U] | ((uint32_t)tempBuffer[10U] << 8U) | + ((uint32_t)tempBuffer[11U] << 16U); + pFbr[(uint32_t)func_idx - 1U].ioPointerToCSA = tempBuffer[12U] | ((uint32_t)tempBuffer[13U] << 8U) | + ((uint32_t)tempBuffer[14U] << 16U); + if ((tempBuffer[2U] & 0x01U) != 0U) + { + pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_POWER_SELECTION; + } + if ((tempBuffer[0U] & 0x40U) != 0U) + { + pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_CSA; + } + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group3 + * @brief + * +@verbatim + ============================================================================== + ##### Data management functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data transfer from/to SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief Read data from a specified address using the direct mode through cmd52. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Specifies the SDIO Argument. + * @param pData: pointer to the buffer that will contain the received data. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData) +{ + uint32_t cmd; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite)); + + if ((hsdio == NULL) || (Argument == NULL) || (NULL == pData)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + cmd = SDIO_READ << 31U; + cmd |= (((uint32_t)Argument->IOFunctionNbr) << 28U); + cmd |= (((uint32_t)Argument->ReadAfterWrite) << 27U); + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= 0U; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData); + + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + + +/** + * @brief Read data from a specified address using the direct mode through cmd52. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Specifies the SDIO Argument. + * @param Data: pointer to the buffer that will contain the received data. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data) +{ + uint32_t cmd; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite)); + + if ((hsdio == NULL) || (Argument == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + cmd = SDIO_WRITE << 31U; + cmd |= ((uint32_t)Argument->IOFunctionNbr) << 28U; + cmd |= ((uint32_t)Argument->ReadAfterWrite) << 27U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= Data; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &Data); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Read data from a specified address using extended mode through cmd53. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: size to read. + * @param Timeout_Ms: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint8_t *tempbuff = pData; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */ + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */ + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Correspond to the write or read bit of the CMD argument */ + /* Read */ + hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK : + SDIO_CONTEXT_READ_SINGLE_BLOCK; + cmd = SDIO_READ << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (Size_byte & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + { + /* Read data from SDMMC Rx FIFO */ + for (regCount = 0U; regCount < 8U; regCount++) + { + data = SDMMC_ReadFIFO(hsdio->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + } + dataremaining -= 32U; + } + else if (dataremaining < 32U) + { + while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE))) + { + data = SDMMC_ReadFIFO(hsdio->Instance); + for (byteCount = 0U; byteCount < 4U; byteCount++) + { + if (dataremaining > 0U) + { + *tempbuff = (uint8_t)((data >> (byteCount * 8U)) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + } + } + else + { + /* Nothing to do */ + } + if ((HAL_GetTick() - tickstart) >= Timeout_Ms) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + /* Get error state */ + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_RX_OVERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Write data from a specified address using extended mode through cmd53. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @param Timeout_Ms: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint8_t *u32tempbuff = pData; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Correspond to the write or read bit of the CMD argument */ + hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK; + cmd = SDIO_WRITE << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (Size_byte & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + { + /* Read data from SDMMC Rx FIFO */ + for (regCount = 0U; regCount < 8U; regCount++) + { + hsdio->Instance->FIFO = *u32tempbuff; + u32tempbuff++; + } + dataremaining -= 32U; + } + else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + { + uint8_t *u8buff = (uint8_t *)u32tempbuff; + while (dataremaining > 0U) + { + data = 0U; + for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++) + { + data |= ((uint32_t)(*u8buff) << (byteCount << 3U)); + u8buff++; + dataremaining--; + } + hsdio->Instance->FIFO = data; + } + } + if (((HAL_GetTick() - tickstart) >= Timeout_Ms)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + /* Get error state */ + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Read data from a specified address using extended mode through cmd53 in DMA mode. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint8_t *p_dma_buffer; + uint32_t cmd; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + p_dma_buffer = (uint8_t *)pData; + hsdio->pRxBuffPtr = (uint8_t *)pData; + hsdio->RxXferSize = Size_byte; + hsdio->next_data_addr = (uint32_t)pData; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + if (nbr_of_block != 0U) + { + hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block)); + hsdio->next_reg_addr = (Argument->Reg_Addr) | ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) + | ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U); + hsdio->next_data_addr += (nbr_of_block * hsdio->block_size); + } + else + { + hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte : + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + if (hsdio->remaining_data != 0U) + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + hsdio->next_reg_addr += (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \ + (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE + 1U) : (Size_byte + 1U); + } + } + + /* DMA configuration (use single buffer) */ + hsdio->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsdio->Instance->IDMABASE0 = (uint32_t)p_dma_buffer; + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ; + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Read */ + hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK : + SDIO_CONTEXT_READ_SINGLE_BLOCK) | SDIO_CONTEXT_DMA; + + cmd = SDIO_READ << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= ((nbr_of_block == 0U) ? Size_byte : nbr_of_block) & 0x1FFU; + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Enable interrupt */ + __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Write data from a specified address using extended mode through cmd53 in DMA mode. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint8_t *p_dma_buffer; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + p_dma_buffer = (uint8_t *)pData; + hsdio->pTxBuffPtr = (uint8_t *)pData; + hsdio->TxXferSize = Size_byte; + hsdio->next_data_addr = (uint32_t)pData; + + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + if (nbr_of_block != 0U) + { + hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block)); + if (hsdio->block_size <= 128U) + { + hsdio->next_reg_addr = (Argument->Reg_Addr) | + ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) | + ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U); + } + else + { + hsdio->next_reg_addr = (nbr_of_block * hsdio->block_size) >> 1U; + } + hsdio->next_data_addr += (nbr_of_block * hsdio->block_size); + } + else + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + if (hsdio->remaining_data != 0U) + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + hsdio->next_reg_addr += ((Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \ + (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE >> 1U) : (Size_byte >> 1U)) | + (((hsdio->remaining_data > 0U) ? 0U : 1U)); + } + hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte : + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + } + + /* DMA configuration (use single buffer) */ + hsdio->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsdio->Instance->IDMABASE0 = (uint32_t)p_dma_buffer; + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK + : SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Write */ + hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? + SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK) | SDIO_CONTEXT_DMA; + cmd = SDIO_WRITE << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= ((nbr_of_block == 0U) ? ((Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte) : nbr_of_block) & 0x1FFU; + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Enable interrupt */ + __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group4 + * @brief + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set callback functions allowing to manage the data transfer from/to SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief This function handles SDIO device interrupt request. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio) +{ + HAL_SDIO_ExtendedCmd_TypeDef CMD53_desc; + HAL_StatusTypeDef errorstate; + uint32_t ctx = hsdio->Context; + uint32_t flags; + + flags = READ_REG(((SDMMC_TypeDef *)((uint32_t)(hsdio)->Instance))->STA); + + if (READ_BIT(flags, SDMMC_FLAG_SDIOIT) != 0U) + { + (void)SDIO_IOFunction_IRQHandler(hsdio); + } + + if (READ_BIT(flags, SDMMC_FLAG_DATAEND) != 0U) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_FLAG_DATAEND); + + hsdio->State = HAL_SDIO_STATE_READY; + + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | + SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF); + + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + if ((ctx & SDIO_CONTEXT_DMA) != 0U) + { + hsdio->Instance->DLEN = 0; + hsdio->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + hsdio->Context = SDIO_CONTEXT_NONE; + hsdio->State = HAL_SDIO_STATE_READY; + } + + if (hsdio->remaining_data != 0U) + { + CMD53_desc.Block_Mode = HAL_SDIO_MODE_BYTE; + CMD53_desc.Reg_Addr = hsdio->next_reg_addr; + CMD53_desc.IOFunctionNbr = 1; + CMD53_desc.OpCode = 1; + if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + hsdio->pRxBuffPtr = (uint8_t *)hsdio->next_data_addr; + errorstate = HAL_SDIO_ReadExtended_DMA(hsdio, &CMD53_desc, hsdio->pRxBuffPtr, hsdio->remaining_data); + } + else + { + hsdio->pTxBuffPtr = (uint8_t *)hsdio->next_data_addr; + errorstate = HAL_SDIO_WriteExtended_DMA(hsdio, &CMD53_desc, hsdio->pTxBuffPtr, hsdio->remaining_data); + } + if (errorstate != HAL_OK) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1) + hsdio->ErrorCallback(hsdio); +#else + HAL_SDIO_ErrorCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + } + else if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + hsdio->RxCpltCallback(hsdio); +#else + HAL_SDIO_RxCpltCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + hsdio->TxCpltCallback(hsdio); +#else + HAL_SDIO_TxCpltCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + } + + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR)) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1) + hsdio->ErrorCallback(hsdio); +#else + HAL_SDIO_ErrorCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsdio: Pointer SDIO handle + * @retval None + */ +__weak void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SDIO error callbacks + * @param hsdio: Pointer SDIO handle + * @retval None + */ +__weak void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief SDIO IO Function complete callback + * @param hsdio: Pointer SDIO handle + * @param func: SDIO IO Function + * @retval None + */ +__weak void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + UNUSED(func); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_ErrorCallback can be implemented in the user file + */ +} + +#if (USE_SDIO_TRANSCEIVER != 0U) +/** + * @brief Enable/Disable the SDIO Transceiver 1.8V Mode Callback. + * @param hsdio: Pointer SDIO handle + * @param status: Voltage Switch State + * @retval None + */ +__weak void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + UNUSED(status); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_EnableTransceiver could be implemented in the user file + */ +} +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SDIO Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDIO_TX_CPLT_CB_ID SDIO Tx Complete Callback ID + * @arg @ref HAL_SDIO_RX_CPLT_CB_ID SDIO Rx Complete Callback ID + * @arg @ref HAL_SDIO_ERROR_CB_ID SDIO Error Callback ID + * @arg @ref HAL_SDIO_MSP_INIT_CB_ID SDIO MspInit Callback ID + * @arg @ref HAL_SDIO_MSP_DEINIT_CB_ID SDIO MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + switch (CallbackID) + { + case HAL_SDIO_TX_CPLT_CB_ID : + hsdio->TxCpltCallback = pCallback; + break; + case HAL_SDIO_RX_CPLT_CB_ID : + hsdio->RxCpltCallback = pCallback; + break; + case HAL_SDIO_ERROR_CB_ID : + hsdio->ErrorCallback = pCallback; + break; + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = pCallback; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdio->State == HAL_SDIO_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = pCallback; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDIO Callback + * SDIO Callback is redirected to the weak (overridden) predefined callback. + * @note The HAL_SDIO_UnRegisterCallback() may be called before HAL_SDIO_Init() in + * HAL_SDIO_STATE_RESET to register callbacks for HAL_SDIO_MSP_INIT_CB_ID + * and HAL_SDIO_MSP_DEINIT_CB_ID. + * @param hsdio : SDIO handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values @ref SDIO_Exported_Types_Group3. + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + switch (CallbackID) + { + case HAL_SDIO_TX_CPLT_CB_ID : + hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback; + break; + case HAL_SDIO_RX_CPLT_CB_ID : + hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback; + break; + case HAL_SDIO_ERROR_CB_ID : + hsdio->ErrorCallback = HAL_SDIO_ErrorCallback; + break; + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = HAL_SDIO_MspInit; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + break; + default : + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hsdio->State == HAL_SDIO_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = HAL_SDIO_MspInit; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + break; + default : + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +/** + * @brief Register a User SDIO Transceiver Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->DriveTransceiver_1_8V_Callback = pCallback; + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDIO Transceiver Callback + * SDIO Callback is redirected to the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback; + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_SDIO_TRANSCEIVER */ + +/** + * @brief Register a User SDIO Identification Callback + * @param hsdio: Pointer to SDIO handle + * @param pCallback: pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + hsdio->SDIO_IdentifyCard = pCallback; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group5 + * @brief + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDIO card operations. + +@endverbatim + * @{ + */ +/** + * @brief return the SDIO state + * @param hsdio: Pointer to SDIO handle + * @retval HAL state + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio) +{ + return hsdio->State; +} + +/** + * @brief Return the SDIO error code + * @param hsdio : Pointer to a SDIO_HandleTypeDef structure that contains the configuration information. + * @retval SDIO Error Code + */ +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio) +{ + return hsdio->ErrorCode; +} + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group6 + * @brief + * +@verbatim + ============================================================================== + ##### Peripheral IO interrupt ##### + ============================================================================== + [..] + This subsection provides a set functions allowing to enable/disable IO functions interrupt features + on the SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief Enable SDIO IO interrupt. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t intEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if ((((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) && ((intEn & 0x01U) != 0U)) + { + return HAL_OK; + } + else + { + intEn |= (1U << (uint32_t)IOFunction) | 0x01U; + hsdio->IOInterruptNbr++; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, + &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + __HAL_SDIO_ENABLE_IT(hsdio, SDMMC_IT_SDIOIT); + + /* Enable host SDIO interrupt operations */ + __SDMMC_OPERATION_ENABLE(hsdio->Instance); + + return HAL_OK; +} + +/** + * @brief Enable SDIO IO interrupt. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t intEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already disable , do not need enable again */ + if (((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U) + { + return HAL_OK; + } + else + { + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + if (hsdio->IOInterruptNbr > 1U) + { + hsdio->IOInterruptNbr--; + } + else + { + hsdio->IOInterruptNbr = 0U; + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_SDIOIT); + } + return HAL_OK; +} + +/** + * @brief Enable SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t ioEn = 0U; + uint8_t ioReady = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need to enable again */ + if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) + { + return HAL_OK; + } + else + { + ioEn |= (1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioReady) != HAL_OK) + { + return HAL_ERROR; + } + /* check if IO ready */ + if ((ioReady & (1U << (uint32_t)IOFunction)) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Disable SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t ioEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U) + { + return HAL_OK; + } + else + { + ioEn &= ~(1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Select SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR12_SD_BYTE1, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + (uint8_t *)&IOFunction) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort IO transfer. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction IO number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + (uint8_t *)&IOFunction) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Enable Assynchrone interrupt. + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) +{ + uint8_t enable_asyn_it = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it) + != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if ((enable_asyn_it & 0x02U) == 0x02U) + { + return HAL_OK; + } + else + { + enable_asyn_it |= 0x02U; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &enable_asyn_it) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable Assynchrone interrupt. + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) +{ + uint8_t enable_asyn_it = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it) + != HAL_OK) + { + return HAL_ERROR; + } + + /* if already disable , do not need disable again */ + if ((enable_asyn_it & 0x02U) == 0x00U) + { + return HAL_OK; + } + else + { + enable_asyn_it &= (uint8_t) ~(0x02U); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &enable_asyn_it) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief sdio set io IRQ handler. + * @param hsdio Pointer to SDIO handle + * @param IOFunction IO function io number. + * @param Callback io IRQ handler. + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback; + hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction); + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private function --------------------------------------------------------------------------------------------------*/ +/** @addtogroup SDIO_Private_Functions + * @{ + */ +/** + * @brief Initializes the SDIO device. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) +{ + uint32_t errorstate; + uint32_t timeout = 0U; + uint16_t sdio_rca = 1U; + uint32_t Resp4; + uint32_t nbr_of_func; + + /* Identify card operating voltage */ + errorstate = SDMMC_CmdGoIdleState(hsdio->Instance); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + /* Check the power State */ + if (SDMMC_GetPowerState(hsdio->Instance) == 0U) + { + return HAL_ERROR; + } + + /* Send CMD5 */ + errorstate = SDMMC_CmdSendOperationcondition(hsdio->Instance, 0U, &Resp4); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + nbr_of_func = ((Resp4 & 0x70000000U) >> 28U); + /* Check if Nbr of function > 0 and OCR valid */ + if (nbr_of_func > 0U) + { + /* Send CMD5 with arg= S18R, WV*/ + if (SDMMC_CmdSendOperationcondition(hsdio->Instance, (SDIO_OCR_VDD_32_33 | SDIO_OCR_SDIO_S18R), &Resp4) + != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + /* Check if IORDY = 1 and S18A = 1 */ + if ((((Resp4 & 0x80000000U) >> 31U) != 0U) && (((Resp4 & 0x1000000U) >> 24U) != 0U)) + { + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsdio->Instance); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + } + else + { + /* S18A is not supported */ + } + } + + /** Cmd3 is sent while response is SDMMC_ERROR_ILLEGAL_CMD, due to the partial init test done before + * (sending cmd0 after the sequence cmd0/cmd3 is sent is considered illegal). + */ + do + { + errorstate = SDMMC_CmdSetRelAdd(hsdio->Instance, &sdio_rca); + timeout++; + HAL_Delay(1); + } while ((errorstate == SDMMC_ERROR_ILLEGAL_CMD) && (timeout != SDIO_TIMEOUT)); + + if ((timeout == SDIO_TIMEOUT) || (errorstate != HAL_SDIO_ERROR_NONE)) + { + return HAL_ERROR; + } + + /* Select the Card ( Sending CMD7)*/ + errorstate = SDMMC_CmdSelDesel(hsdio->Instance, (uint32_t)(((uint32_t)sdio_rca) << 16U)); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read 1 byte data. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted CMD52 structure + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, + uint32_t function_nbr, uint8_t *pData) +{ + uint32_t errorstate; + uint32_t cmd; + + cmd = SDIO_READ << 31U; + cmd |= function_nbr << 28U; + cmd |= raw << 27U; + cmd |= (addr & 0x1FFFFU) << 9U; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Write 1 byte data. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted CMD52 structure + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, + uint32_t function_nbr, uint8_t *pData) +{ + uint32_t errorstate; + uint32_t cmd; + uint8_t response; + + cmd = SDIO_WRITE << 31U; + cmd |= function_nbr << 28U; + cmd |= raw << 27U; + cmd |= (addr & 0x1FFFFU) << 9U; + cmd |= ((uint32_t) * pData & 0x000000FFU); + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &response); + + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Write multiple data with a single command. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted cmd53 structure + * @param Size_byte: block size if CMD53 defined in HAL_SDIO_MODE_BLOCK + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, + uint8_t *pData, uint16_t Size_byte) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData; + SDMMC_TypeDef *SDMMCx; + uint32_t cmd; + uint32_t nbr_of_block; + + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (((uint32_t)Size_byte & ~((uint32_t)hsdio->block_size & 1U))) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = Size_byte; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + hsdio->Context = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK; + cmd = SDIO_WRITE << 31U; + cmd |= cmd_arg->IOFunctionNbr << 28U; + cmd |= cmd_arg->Block_Mode << 27U; + cmd |= cmd_arg->OpCode << 26U; + cmd |= (cmd_arg->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->ErrorCode |= errorstate; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + + SDMMCx = hsdio->Instance; + dataremaining = config.DataLength; + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + { + for (regCount = 8U; regCount > 0U; regCount--) + { + SDMMCx->FIFO = *u32tempbuff; + u32tempbuff++; + } + dataremaining -= 32U; + } + else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + { + uint8_t *u8buff = (uint8_t *)u32tempbuff; + while (dataremaining > 0U) + { + data = 0U; + for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++) + { + data |= ((uint32_t)(*u8buff) << (byteCount << 3U)); + u8buff++; + dataremaining--; + } + SDMMCx->FIFO = data; + } + } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Allows to convert a block size in the according SDMMC value for configuring the SDMMC when doing a CMD53 + * @param hsdio: Pointer to the SDIO handle. + * @param block_size: block size in bytes + * @retval block size as DBLOCKSIZE[3:0] bits format + */ +static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size) +{ + UNUSED(hsdio); + + uint8_t most_bit = (uint8_t)__CLZ(__RBIT(block_size)); + /*(1 << most_bit) - 1) is the mask used for blocksize*/ + if (((uint8_t)block_size & ((1U << most_bit) - 1U)) != 0U) + { + return (uint8_t)SDMMC_DATABLOCK_SIZE_4B; + } + return most_bit << SDMMC_DCTRL_DBLOCKSIZE_Pos; +} + +/*! + * @brief SDIO card io pending interrupt handle function. + * @note This function is used to handle the pending io interrupt. + * To register a IO IRQ handler, Use HAL_SDIO_EnableIOInterrupt and HAL_SDIO_SetIOIRQHandler + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio) +{ + uint8_t count; + uint8_t pendingInt; + + if (hsdio->IOInterruptNbr == 1U) + { + if ((hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U]) != NULL) + { + (hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U])(hsdio, hsdio->IOFunctionMask - 1U); + } + } + else if ((hsdio->IOInterruptNbr > 1U) && (hsdio->IOFunctionMask != 0U)) + { + /* Get pending int firstly */ + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE1, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &pendingInt) != + HAL_OK) + { + return HAL_ERROR; + } + + if ((pendingInt != 0U) && (hsdio->IOFunctionMask != 0U)) + { + for (count = 1; count <= SDIO_MAX_IO_NUMBER; count++) + { + if (((pendingInt & (1U << count)) != 0U) && (((1U << count) & hsdio->IOFunctionMask) != 0U)) + { + if ((hsdio->SDIO_IOFunction_Callback[count - 1U]) != NULL) + { + (hsdio->SDIO_IOFunction_Callback[count - 1U])(hsdio, count); + } + } + } + } + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} +/** + * @} + */ +#endif /* HAL_SDIO_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c index 8859a08cdd..d376e44631 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c @@ -1214,7 +1214,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) * the configuration information for SDRAM module. * @retval HAL state */ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram) { return hsdram->State; } @@ -1237,6 +1237,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) */ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1259,6 +1260,7 @@ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1281,6 +1283,7 @@ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c index 4641fc2c9e..d8742f742b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c @@ -2408,7 +2408,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c index 354966a13e..6149a5f1e3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c index 932eb3fb3d..e0571e0d96 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c @@ -2235,7 +2235,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if (hspi->State != HAL_SPI_STATE_READY) { __HAL_UNLOCK(hspi); @@ -2418,9 +2417,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ - (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)))) + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD) || \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + (((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ + ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c index 7cf5fb343f..fac9ba50d7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c index 94d93ca06d..b3ad7f7071 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c @@ -1040,6 +1040,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1062,6 +1063,7 @@ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1084,6 +1086,7 @@ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c index 0cf0c1c42f..22fafc585d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c @@ -131,7 +131,7 @@ and a pointer to the user callback function. [..] Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: @@ -144,10 +144,10 @@ (+) MspDeInitCallback : SWPMI MspDeInit. [..] By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init + reset to the legacy weak functions in the HAL_SWPMI_Init and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -162,7 +162,7 @@ [..] When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -208,7 +208,8 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, + uint32_t Timeout); /* Exported functions --------------------------------------------------------*/ @@ -276,7 +277,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SWPMI_MspInit(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } hswpmi->State = HAL_SWPMI_STATE_BUSY; @@ -302,7 +303,8 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Enable the SWPMI transceiver */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN); /* Wait on RDYF flag to activate SWPMI */ - if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) + if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, + SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } @@ -365,7 +367,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) hswpmi->MspDeInitCallback(hswpmi); #else HAL_SWPMI_MspDeInit(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; hswpmi->State = HAL_SWPMI_STATE_RESET; @@ -410,7 +412,7 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) /** * @brief Register a user SWPMI callback - * to be used instead of the weak predefined callback. + * To be used to override the weak predefined callback. * @param hswpmi SWPMI handle. * @param CallbackID ID of the callback to be registered. * This parameter can be one of the following values: @@ -503,7 +505,7 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, /** * @brief Unregister a user SWPMI callback. - * SWPMI callback is redirected to the weak predefined callback. + * Callback is redirected to the weak predefined callback. * @param hswpmi SWPMI handle. * @param CallbackID ID of the callback to be unregistered. * This parameter can be one of the following values: @@ -651,12 +653,13 @@ HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpm * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - uint32_t *ptmp_data; + const uint32_t *ptmp_data; uint32_t tmp_size; if ((pData == NULL) || (Size == 0U)) @@ -713,8 +716,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pDat } } } - } - while (tmp_size != 0U); + } while (tmp_size != 0U); /* Wait on TXBEF flag to be able to start a second transfer */ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) @@ -789,7 +791,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; /* Disable any receiver interrupts */ - CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); + CLEAR_BIT(hswpmi->Instance->IER, + SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); /* Enable SWPMI peripheral if not */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); @@ -822,8 +825,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData } } } - } - while (tmp_size != 0U); + } while (tmp_size != 0U); if (status == HAL_OK) { @@ -868,7 +870,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; @@ -998,7 +1000,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; @@ -1044,7 +1046,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; /* Enable the SWPMI transmit DMA stream */ - if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, + (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1130,7 +1133,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, + (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1271,8 +1275,8 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) */ /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks - * @brief SWPMI IRQ handler. - * + * @brief SWPMI IRQ handler. + * @verbatim ============================================================================== ##### SWPMI IRQ handler and callbacks ##### @@ -1363,7 +1367,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1375,7 +1379,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1408,7 +1412,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1420,7 +1424,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } } @@ -1555,19 +1559,19 @@ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) * @param hswpmi SWPMI handle * @retval HAL state */ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi) +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi) { /* Return SWPMI handle state */ return hswpmi->State; } /** -* @brief Return the SWPMI error code. -* @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains + * @brief Return the SWPMI error code. + * @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for the specified SWPMI. -* @retval SWPMI Error Code -*/ -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi) + * @retval SWPMI Error Code + */ +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi) { return hswpmi->ErrorCode; } @@ -1642,7 +1646,7 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1668,7 +1672,7 @@ static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) hswpmi->RxCpltCallback(hswpmi); #else HAL_SWPMI_RxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1759,7 +1763,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } else { @@ -1778,7 +1782,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } /* DMA Circular mode */ @@ -1788,7 +1792,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } @@ -1805,7 +1809,7 @@ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) hswpmi->TxHalfCpltCallback(hswpmi); #else HAL_SWPMI_TxHalfCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } @@ -1841,7 +1845,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hswpmi->RxCpltCallback(hswpmi); #else HAL_SWPMI_RxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1857,7 +1861,7 @@ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) hswpmi->RxHalfCpltCallback(hswpmi); #else HAL_SWPMI_RxHalfCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1879,7 +1883,7 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1900,7 +1904,7 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1911,7 +1915,8 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, + uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c index 1020295267..c0a36edfe7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -6955,8 +6955,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -6969,16 +6967,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c index 3465d29cca..55f1c5835e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c @@ -1078,6 +1078,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) reception services: (+) HAL_UARTEx_RxEventCallback() + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -2425,6 +2428,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3842,7 +3867,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4513,6 +4537,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4677,6 +4702,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c index 6e5c0b20d7..bb45995e96 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c @@ -576,7 +576,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c index 85ccef27e3..6c77f25fad 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -225,8 +225,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -238,7 +238,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -657,11 +657,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -2910,7 +2909,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c index b1a916da86..8fa72eeaa8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c index 4eed817e5d..676b9c2eb8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c @@ -51,17 +51,17 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values (case of STM32H74x/5x devices): (++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 40.96us + max timeout before reset: approximately 40.96µs (++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 335.54ms (+) Typical values (case of STM32H7Ax/Bx devices): (++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 29.25us + max timeout before reset: approximately 29.25µs (++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 239.67ms (+) Typical values (case of STM32H72x/3x devices): (++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 32.76us + max timeout before reset: approximately 32.76µs (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 268.43ms @@ -131,7 +131,6 @@ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c index 86ef0277a2..2ecaf6ccb6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c @@ -352,7 +352,7 @@ * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c index e79d451964..c1767ab034 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c @@ -136,7 +136,7 @@ * - SUCCESS: DMA2D registers are de-initialized * - ERROR: DMA2D registers are not de-initialized */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx) { ErrorStatus status = SUCCESS; @@ -150,7 +150,6 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) /* Release reset of DMA2D clock */ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_DMA2D); - } else { @@ -439,7 +438,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -483,7 +482,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -527,7 +526,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -571,7 +570,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c index eab7ae8ca0..fca256ff01 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c index b9fa468f1a..27aadb10e1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c @@ -61,7 +61,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -188,7 +188,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -322,7 +322,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -338,13 +338,14 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) @@ -370,7 +371,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -515,7 +516,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -548,7 +549,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -562,10 +563,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -579,7 +580,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -593,10 +594,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -700,7 +701,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -739,7 +740,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ - /** @defgroup FMC_LL_SDRAM * @brief SDRAM Controller functions * @@ -786,7 +786,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -849,7 +849,7 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -979,7 +979,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c index 67015f0e60..e37e28dcf2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c @@ -101,7 +101,7 @@ * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c index 1ee8c0a112..2abc2b1d28 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c @@ -53,7 +53,7 @@ * - SUCCESS: HRTIMx registers are de-initialized * - ERROR: invalid HRTIMx instance */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx) +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx) { ErrorStatus result = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c index 02981e2c45..192cc90a9c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c @@ -112,7 +112,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c index 38e7697ed6..dd39836dec 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c @@ -162,7 +162,8 @@ * @{ */ -#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) +#if defined (SDMMC1) || defined (SDMMC2) +#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) || defined (HAL_SDIO_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -248,7 +249,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx) { /* Read data from Rx FIFO */ return (SDMMCx->FIFO); @@ -335,7 +336,7 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) * - 0x02: Power UP * - 0x03: Power ON */ -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); } @@ -348,7 +349,7 @@ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -378,7 +379,7 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef * @param SDMMCx: Pointer to SDMMC register base * @retval Command index of the last command response received */ -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx) { return (uint8_t)(SDMMCx->RESPCMD); } @@ -395,7 +396,7 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) * @arg SDMMC_RESP4: Response Register 4 * @retval The Corresponding response register value */ -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) { uint32_t tmp; @@ -416,7 +417,7 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -451,7 +452,7 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef * @param SDMMCx: Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->DCOUNT); } @@ -461,7 +462,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) * @param SDMMCx: Pointer to SDMMC register base * @retval Data received */ -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->FIFO); } @@ -529,6 +530,30 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) return errorstate; } +/** + * @brief Send the Data Block number command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockCount; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCK_COUNT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Read Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base @@ -1231,6 +1256,78 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) return errorstate; } +/** + * @brief Execute a cmd52 to write single byte data and read single byte data if needed + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @param pData: pointer to read response if needed + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_DIRECT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_DIRECT, pResponse); + + return errorstate; +} + +/** + * @brief Execute a cmd53 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_EXTENDED; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_EXTENDED, NULL); + + return errorstate; +} + +/** + * @brief Execute a cmd5 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_SEN_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp4(SDMMCx, pResp); + + return errorstate; +} /** * @} */ @@ -1466,6 +1563,138 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_NONE; } +/** + * @brief Checks for error conditions for R4 response. + * @param SDMMCx: Pointer to SDMMC register base + * @param pResp: pointer to response + * @retval error state + */ +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp) +{ + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + *pResp = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R5 (cmd52/cmd53) response. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDIO_CMD: The sent command index + * @param pData: pointer to the read/write buffer needed for cmd52 + * @retval SDIO Card error state + */ +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData) +{ + uint32_t response_r5; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if (SDMMC_GetCommandResponse(SDMMCx) != SDIO_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r5 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if ((response_r5 & SDMMC_SDIO_R5_ERRORBITS) == SDMMC_ALLZERO) + { + /* we only want 8 bit read or write data and the 8 bit response flags are masked in the data pointer */ + if (pData != NULL) + { + *pData = (uint8_t)(response_r5 & 0xFFU); + } + + return SDMMC_ERROR_NONE; + } + else if ((response_r5 & SDMMC_SDIO_R5_OUT_OF_RANGE) == SDMMC_SDIO_R5_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if ((response_r5 & SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) == SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + else if ((response_r5 & SDMMC_SDIO_R5_ILLEGAL_CMD) == SDMMC_SDIO_R5_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if ((response_r5 & SDMMC_SDIO_R5_COM_CRC_FAILED) == SDMMC_SDIO_R5_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + /** * @brief Checks for error conditions for R6 (RCA) response. * @param hsd: SD handle @@ -1635,6 +1864,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) */ #endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c index 20c2c5e1a0..50d2377d26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c @@ -20,11 +20,11 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_ll_swpmi.h" #include "stm32h7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -46,13 +46,13 @@ #define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U)) #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \ - || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) + || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) #define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \ - || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI)) + || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI)) #define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \ - || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B)) + || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B)) /** * @} @@ -76,7 +76,7 @@ * - SUCCESS: SWPMI registers are de-initialized * - ERROR: Not applicable */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx) { ErrorStatus status = SUCCESS; @@ -108,7 +108,7 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) * - SUCCESS: SWPMI registers are initialized * - ERROR: SWPMI registers are not initialized */ -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct) +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c index ed2ca0f04a..54ff752e94 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c @@ -777,17 +777,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -1314,8 +1314,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 8d2e2ead00..a81cc7785e 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -10,7 +10,7 @@ * STM32G0: 1.4.6 * STM32G4: 1.2.5 * STM32H5: 1.4.0 - * STM32H7: 1.11.3 + * STM32H7: 1.11.5 * STM32L0: 1.10.6 * STM32L1: 1.4.5 * STM32L4: 1.13.5 From a3faf96d522a5efceb4cd526d349ead15f11b4a7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 17:09:18 +0100 Subject: [PATCH 2/6] system(H7): update STM32H7xx CMSIS Drivers to v1.10.6 Included in STM32CubeH7 FW v1.12.1 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32H7xx/Include/stm32h723xx.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h725xx.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h730xx.h | 427 +++++++++++------ .../ST/STM32H7xx/Include/stm32h730xxq.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h733xx.h | 429 ++++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h735xx.h | 427 +++++++++++------ .../Device/ST/STM32H7xx/Include/stm32h742xx.h | 292 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h743xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h745xg.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h745xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h747xg.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h747xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h750xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h753xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h755xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h757xx.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7a3xx.h | 296 ++++++++---- .../ST/STM32H7xx/Include/stm32h7a3xxq.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7b0xx.h | 296 ++++++++---- .../ST/STM32H7xx/Include/stm32h7b0xxq.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7b3xx.h | 296 ++++++++---- .../ST/STM32H7xx/Include/stm32h7b3xxq.h | 296 ++++++++---- .../Device/ST/STM32H7xx/Include/stm32h7xx.h | 7 +- .../ST/STM32H7xx/Include/system_stm32h7xx.h | 1 + .../Device/ST/STM32H7xx/Release_Notes.html | 77 +++- .../gcc/linker/stm32h745xg_flash_CM7.ld | 10 + .../gcc/linker/stm32h745xx_flash_CM7.ld | 10 + .../gcc/linker/stm32h747xg_flash_CM7.ld | 10 + .../gcc/linker/stm32h747xx_flash_CM7.ld | 10 + .../gcc/linker/stm32h755xx_flash_CM7.ld | 10 + .../gcc/linker/stm32h757xx_flash_CM7.ld | 10 + .../Templates/gcc/startup_stm32h723xx.s | 2 + .../Templates/gcc/startup_stm32h725xx.s | 2 + .../Templates/gcc/startup_stm32h730xx.s | 2 + .../Templates/gcc/startup_stm32h730xxq.s | 2 + .../Templates/gcc/startup_stm32h733xx.s | 2 + .../Templates/gcc/startup_stm32h735xx.s | 2 + .../Templates/gcc/startup_stm32h742xx.s | 2 + .../Templates/gcc/startup_stm32h743xx.s | 2 + .../Templates/gcc/startup_stm32h745xg.s | 2 + .../Templates/gcc/startup_stm32h745xx.s | 2 + .../Templates/gcc/startup_stm32h747xg.s | 2 + .../Templates/gcc/startup_stm32h747xx.s | 2 + .../Templates/gcc/startup_stm32h750xx.s | 2 + .../Templates/gcc/startup_stm32h753xx.s | 2 + .../Templates/gcc/startup_stm32h755xx.s | 2 + .../Templates/gcc/startup_stm32h757xx.s | 2 + .../Templates/gcc/startup_stm32h7a3xx.s | 2 + .../Templates/gcc/startup_stm32h7a3xxq.s | 2 + .../Templates/gcc/startup_stm32h7b0xx.s | 2 + .../Templates/gcc/startup_stm32h7b0xxq.s | 2 + .../Templates/gcc/startup_stm32h7b3xx.s | 2 + .../Templates/gcc/startup_stm32h7b3xxq.s | 2 + .../Source/Templates/system_stm32h7xx.c | 120 ++++- .../system_stm32h7xx_dualcore_boot_cm4_cm7.c | 120 ++++- ...stem_stm32h7xx_dualcore_bootcm4_cm7gated.c | 122 ++++- ...stem_stm32h7xx_dualcore_bootcm7_cm4gated.c | 121 ++++- .../Templates/system_stm32h7xx_singlecore.c | 122 ++++- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 59 files changed, 5674 insertions(+), 2418 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h index 4c8a9d0d37..de1ce9482f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h @@ -1321,7 +1321,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -11785,101 +11785,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -16876,7 +16973,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -16904,49 +17098,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -21641,7 +21798,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h index 56eb393881..c99cb32ca7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h @@ -1322,7 +1322,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -11786,101 +11786,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -16888,7 +16985,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -16916,49 +17110,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -21653,7 +21810,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h index 2b2cea29cf..241f231e7d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h @@ -1324,7 +1324,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -12039,101 +12039,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -17363,7 +17460,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17391,49 +17585,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -22128,7 +22285,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h index 01c6a27ff1..bb2b15818a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h @@ -1325,7 +1325,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -12040,101 +12040,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -17375,7 +17472,104 @@ typedef struct #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17403,49 +17597,12 @@ typedef struct #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) @@ -22140,7 +22297,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h index 218232730b..dea34817ca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h @@ -1324,7 +1324,7 @@ typedef struct __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -11981,7 +11981,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!Release Notes for  STM32H7xx C

                Update History

                - +

                Main Changes

                  +
                • system_stm32h7xx.c template files +
                    +
                  • Fix computed frequencies returned by the HAL_RCC_GetHCLKFreq(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq() APIs.
                    • +
                  • Enable FMC clock to ensure effective write access to FMC Bank1 registers in the SystemInit() API.
                    • +
                  • +
                • STM32H723/H725/H730/H733/H735 devices header files +
                    +
                  • Align the RTC TAMPER register and bitfields naming with the terminology used in the Reference Manual (RM0468).
                    • +
                  • +
                • STM32H742/H743/H745/H747/H750/H753/H755/H757/H7A3/H7B0/H7B3 device header files +
                    +
                  • Define new RTC macros to manage specific supported Tamper features: +
                      +
                    • RTC_TAMPER2_SUPPORT to manage Tamper 2 support
                      • +
                    • RTC_TAMPMASKFLAG_SUPPORT to manage Tamper Event Masking support
                      • +
                    • RTC_TAMPNOERASE_SUPPORT to manage Backup Registers erasure upon Tamper Event support
                      • +
                    • RTC_TAMPxIE_SUPPORT to manage selective TAMPERx interrupt enable support.
                      • +
                    • +
                  • +
                +
                +
                +
                + +
                +

                Main Changes

                +
                  +
                • Update startup files to safely exit from Run* mode. +
                    +
                  • Deploy the recommended “how to exit from Run* mode” configuration sequence available within product documentation.
                    • +
                  • +
                • Update DBGMCU_APB1HFZ1_DBG_TIM24_Pos and FMC_SDCMR_MODE_2 macros with the new values.
                  • +
                • Align GPIO MODER defines with naming used in reference manual. +
                    +
                  • Rename “GPIO_MODER_MODExx” to “GPIO_MODER_MODERxx”.
                    • +
                  • +
                • Add alignment statements ALIGN(4) to Flash sections in gcc template linker files.
                  • +
                +
                +
                +
                + +
                +

                Main Changes

                +
                • Update the values of the sensor calibration temperatures for H742, H743, and H753 part numbers.
                • Remove the unsupported MDMA BASE channel.
                • Align CMSIS with IP spec and product reference manual by adding missing bit fields definition.
                  • @@ -47,7 +92,7 @@

                  Main Changes

                  -

                  Main Changes

                  +

                  Main Changes

                  • General updates to fix known defects and implementation enhancements
                  • Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.
                    • @@ -58,7 +103,7 @@

                    Main Changes

                    -

                    Main Changes

                    +

                    Main Changes

                    • General updates to fix known defects and implementation enhancements
                    • Add support for ADC LDO output voltage ready bit.
                      • @@ -73,7 +118,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • General updates to fix known defects and implementation enhancements
                      • All source files: update disclaimer to add reference to the new license agreement.
                        • @@ -99,7 +144,7 @@

                        Main Changes

                        -

                        Main Changes

                        +

                        Main Changes

                        • Fix minor issues related to English typo in comments of registers and fields description
                        • Update STM32H7 devices header files to add GPV registers definition, base address and instance
                          • @@ -117,7 +162,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
                              @@ -175,7 +220,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • General updates to align Bits and registers definitions with the STM32H7 reference manual
                              • Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero
                                • @@ -196,7 +241,7 @@

                                Main Changes

                                -

                                Main Changes

                                +

                                Main Changes

                                • General updates to align Bit and registers definition with the STM32H7 reference manual

                                • Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -226,7 +271,7 @@

                                  Main Changes

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  • Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices
                                  • Add definition of “ART” instance: pointer to “ART_TypeDef” structure
                                    • @@ -241,7 +286,7 @@

                                    Main Changes

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • General updates to align Bit and registers definition with the STM32H7 reference manual
                                    • Updates to aligned with STM32H7xx rev.V devices
                                      • @@ -305,7 +350,7 @@

                                      Main Changes

                                      -

                                      Main Changes

                                      +

                                      Main Changes

                                      • Patch Release on top of V1.3.0
                                      • Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -318,7 +363,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • STM32H7xx include files:
                                            @@ -363,7 +408,7 @@

                                            Main Changes

                                            -

                                            Main Changes

                                            +

                                            Main Changes

                                            • Add support for stm32h750xx value line devices:
                                                @@ -376,7 +421,7 @@

                                                Main Changes

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                • Update FDCAN bit definition
                                                • Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access
                                                  • @@ -386,7 +431,7 @@

                                                  Main Changes

                                                  -

                                                  Main Changes

                                                  +

                                                  Main Changes

                                                  • Update USB OTG bit definition
                                                  • Adjust PLL fractional computation
                                                    • @@ -396,7 +441,7 @@

                                                    Main Changes

                                                    -

                                                    Main Changes

                                                    +

                                                    Main Changes

                                                    • First official release for STM32H743xx/753xx devices
                                                    diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld index ef62d8e234..f599d60c81 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld index a6efc45a33..2b251bd2c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld index ef62d8e234..f599d60c81 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld index a6efc45a33..2b251bd2c7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld @@ -87,34 +87,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld index 176419e978..6e88dcf91a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld @@ -86,34 +86,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld index 176419e978..6e88dcf91a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld @@ -86,34 +86,44 @@ SECTIONS .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); } >FLASH .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; + . = ALIGN(4); } >FLASH .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); } >FLASH .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); } >FLASH .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { + . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); } >FLASH /* used by the startup to initialize data */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s index caca6333a8..9c653fb358 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s index 2e13d98887..662c166634 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s index dcbe73896e..85c1de7cf6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s index e21d2a22f7..194d5dde29 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s index 131288012f..55a2c133ca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s index fe3c52b4b8..5745795c66 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s index e4c4df33b1..e25ddd4877 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s index 26eb214793..2663d53d89 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s index 5ecfcdf7e3..ef1a75d46e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s index 98cd733f50..c04b81cb9f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s index 9729c5c145..5b730883be 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s index 4c55c0598c..9374976871 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s index dc7c0fd066..0290118da9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s index 3dec8aeb21..1c9d6918a3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s index 677907814f..5fce5289f0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s index 7f03e9aa6e..81f80f0b88 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s index e7b5946074..8c9d0c70d5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s index be2331d7df..0f2dc095a8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s index 29d1f09b0a..66fda946e6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s index 7deecf0a1d..9a74c15a8e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s index 5c15c5705b..f41cf1ece1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s index 80a4252091..ebc1743429 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s @@ -60,6 +60,8 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode /* Call the clock system initialization function.*/ bl SystemInit diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c index 86e678475c..197d15ceac 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c @@ -6,6 +6,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -285,12 +290,21 @@ void SystemInit (void) #endif /* USER_VECT_TAB_ADDRESS */ #else - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -301,7 +315,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -436,6 +450,98 @@ void SystemCoreClockUpdate (void) #endif /* DUAL_CORE && CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 2d0b59ead1..8641d8bcd4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -9,6 +9,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -266,12 +271,21 @@ void SystemInit (void) #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -284,7 +298,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -406,6 +420,98 @@ void SystemCoreClockUpdate (void) #endif /* CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index dc86d254a9..fe008aba56 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c @@ -12,6 +12,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -258,13 +263,21 @@ void SystemInit (void) /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } - - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -276,7 +289,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -398,6 +411,99 @@ void SystemCoreClockUpdate (void) #endif /* DUAL_CORE && CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index f3f3406415..241e937788 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c @@ -12,6 +12,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -264,12 +269,21 @@ void SystemInit (void) #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -282,7 +296,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -404,6 +418,99 @@ void SystemCoreClockUpdate (void) #endif /* CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c index 6ab8cc2de9..9823d88300 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c @@ -8,6 +8,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -262,13 +267,21 @@ void SystemInit (void) tmpreg = RCC->AHB2ENR; (void) tmpreg; #endif /* DATA_IN_D2_SRAM */ - - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) @@ -277,7 +290,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -401,6 +414,99 @@ void SystemCoreClockUpdate (void) #endif } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 08c80c7f56..e7e12952c8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -10,7 +10,7 @@ * STM32G0: 1.4.4 * STM32G4: 1.2.5 * STM32H5: 1.3.1 - * STM32H7: 1.10.4 + * STM32H7: 1.10.6 * STM32L0: 1.9.3 * STM32L1: 2.3.3 * STM32L4: 1.7.4 From 361fdbab894dc28a7429368a77d44f5107d42bf1 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 17:09:21 +0100 Subject: [PATCH 3/6] core(H7): update wrapped files Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c index 2a9e696c39..c07176b297 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32U5xx +#ifdef STM32H7xx + #include "stm32h7xx_hal_sdio.c" +#elif STM32U5xx #include "stm32u5xx_hal_sdio.c" #endif #pragma GCC diagnostic pop From cc79807898976d8d574116a1a0ccebc292cfd633 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Dec 2024 14:32:08 +0100 Subject: [PATCH 4/6] system(h7): update STM32H7xx hal default config Signed-off-by: Frederic Pillon --- system/STM32H7xx/stm32h7xx_hal_conf_default.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/system/STM32H7xx/stm32h7xx_hal_conf_default.h b/system/STM32H7xx/stm32h7xx_hal_conf_default.h index 0df8a95db6..5dc9afa366 100644 --- a/system/STM32H7xx/stm32h7xx_hal_conf_default.h +++ b/system/STM32H7xx/stm32h7xx_hal_conf_default.h @@ -88,6 +88,7 @@ extern "C" { #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SDIO_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -148,8 +149,8 @@ extern "C" { #if !defined (LSI_VALUE) #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz -The real value may vary depending on the variations -in voltage and temperature.*/ + The real value may vary depending on the variations + in voltage and temperature.*/ /** * @brief External clock source for I2S peripheral @@ -157,7 +158,7 @@ in voltage and temperature.*/ * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE 12288000L /*!< Value of the External clock in Hz*/ +#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -185,7 +186,12 @@ in voltage and temperature.*/ #if !defined (USE_FLASH_ECC) #define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */ #endif - +#if !defined (USE_SDIO_TRANSCEIVER) +#define USE_SDIO_TRANSCEIVER 0U +#endif +#if !defined (SDIO_MAX_IO_NUMBER) +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ +#endif #if !defined(USE_HAL_ADC_REGISTER_CALLBACKS) #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ @@ -551,6 +557,10 @@ in voltage and temperature.*/ #include "stm32h7xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h7xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32h7xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ From 6a68ecb5892d918e66970c960f003e21914ff520 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 2 Dec 2024 14:50:40 +0100 Subject: [PATCH 5/6] system(h7): update STM32H7xx system Signed-off-by: Frederic Pillon --- system/STM32H7xx/system_stm32h7xx.c | 119 ++++++++++++++++++++++++++-- 1 file changed, 113 insertions(+), 6 deletions(-) diff --git a/system/STM32H7xx/system_stm32h7xx.c b/system/STM32H7xx/system_stm32h7xx.c index 950ff938a7..dca15c1b7e 100644 --- a/system/STM32H7xx/system_stm32h7xx.c +++ b/system/STM32H7xx/system_stm32h7xx.c @@ -6,6 +6,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -265,12 +270,21 @@ void SystemInit (void) #endif /* DATA_IN_D2_SRAM */ #if !defined(DUAL_CORE) || defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; +if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } #endif /* !DUAL_CORE || CORE_CM7 */ /* Configure the Vector Table location add offset address for cortex-M7 or for cortex-M4 ------------------*/ @@ -413,6 +427,99 @@ void SystemCoreClockUpdate (void) } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ From 574f1f6d1bbd646a4d56002102ff26e52b525585 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 17 Dec 2024 16:42:57 +0100 Subject: [PATCH 6/6] system(h7): define system Power Supply Used by exit Run* mode to configure the system Power Supply Signed-off-by: Frederic Pillon --- .../H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h | 2 ++ .../variant_DAISY_PATCH_SM.h | 2 ++ .../variant_DAISY_PETAL_SM.h | 2 ++ .../variant_DAISY_SEED.h | 2 ++ .../variant_DevEBoxH7xx.h | 2 ++ .../variant_WeActMiniH7xx.h | 2 ++ .../variant_STM32H747I_DISCO.h | 1 + .../variant_NUCLEO_H743ZI.h | 2 ++ .../variant_NUCLEO_H753ZI.h | 2 ++ 9 files changed, 17 insertions(+) diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h index 7105d7b416..75bbacbc3d 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.h @@ -269,6 +269,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h index 446c9c7fad..fe99fca2fa 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h +++ b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PATCH_SM.h @@ -257,6 +257,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h index f506c369dc..8408c25f95 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h +++ b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_PETAL_SM.h @@ -145,6 +145,8 @@ #define HAL_DAC_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h index fdfeddaf0a..37ba4323d0 100644 --- a/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h +++ b/variants/STM32H7xx/H742I(G-I)K_H743I(G-I)K_H750IBK_H753IIK/variant_DAISY_SEED.h @@ -140,6 +140,8 @@ #define HAL_DAC_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h index 19efcedec2..10430f322d 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.h @@ -243,6 +243,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h index cdb8fa423d..a74c67cdd7 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.h @@ -242,6 +242,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h index 43c21a3f4e..da40f465bf 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/variant_STM32H747I_DISCO.h @@ -326,6 +326,7 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_DIRECT_SMPS_SUPPLY /*---------------------------------------------------------------------------- * Arduino objects - C++ only diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h index 6813eb16fc..90896259cd 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H743ZI.h @@ -382,6 +382,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h index bb4424b7ec..d6b999ed68 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/variant_NUCLEO_H753ZI.h @@ -254,6 +254,8 @@ #define HAL_SD_MODULE_ENABLED #endif +#define USE_PWR_LDO_SUPPLY + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/