[Z9332F] Why some 100G ports seems to be assigned with 3 lanes instead of 2 in "sai_postinit_cmd.soc"?

[gechiang]

We noticed that in the following file some 100G ports gets assigned with 3 lanes while some gets one lane only... my understanding is that each 100G port should have 2 lanes and 400G ports should have 8 lanes.
Can DELL team please comment what is the purpose of the "sai_postinit_cmd.soc" for and if this strange behavior was intentional??

You can see the following where ce17 got assigned with 3 lanes while ce19 only onelane?

local port ce17
#*** lane 2 ***
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=4
phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1E4
phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x70
phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1E8
phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1

#*** lane 3 ***
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=4
phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1E4
phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x70
phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1E8
phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1

#*** lane 4 ***
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP0_COEFF=0
phy $port TXFIR_TAP_CTL1r.4 TXFIR_TAP1_COEFF=0x1E8
phy $port TXFIR_TAP_CTL2r.4 TXFIR_TAP2_COEFF=0x88
phy $port TXFIR_TAP_CTL3r.4 TXFIR_TAP3_COEFF=0x1F8
phy $port TXFIR_TAP_CTL4r.4 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.4 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.4 TXFIR_TAP_LOAD=0x1


local port ce18
#*** lane 5 ***
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP0_COEFF=0
phy $port TXFIR_TAP_CTL1r.5 TXFIR_TAP1_COEFF=0x1E8
phy $port TXFIR_TAP_CTL2r.5 TXFIR_TAP2_COEFF=0x90
phy $port TXFIR_TAP_CTL3r.5 TXFIR_TAP3_COEFF=0
phy $port TXFIR_TAP_CTL4r.5 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.5 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.5 TXFIR_TAP_LOAD=0x1

#*** lane 6 ***
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP0_COEFF=0
phy $port TXFIR_TAP_CTL1r.6 TXFIR_TAP1_COEFF=0x1E8
phy $port TXFIR_TAP_CTL2r.6 TXFIR_TAP2_COEFF=0x88
phy $port TXFIR_TAP_CTL3r.6 TXFIR_TAP3_COEFF=0x1F8
phy $port TXFIR_TAP_CTL4r.6 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.6 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.6 TXFIR_TAP_LOAD=0x1

local port ce19
#*** lane 7 ***
phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP0_COEFF=4
phy $port TXFIR_TAP_CTL1r.7 TXFIR_TAP1_COEFF=0x1E4
phy $port TXFIR_TAP_CTL2r.7 TXFIR_TAP2_COEFF=0x70
phy $port TXFIR_TAP_CTL3r.7 TXFIR_TAP3_COEFF=0x1E8
phy $port TXFIR_TAP_CTL4r.7 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.7 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.7 TXFIR_TAP_LOAD=0x1

delay 10


#***
#*** Port CE20-CE23 Preemphasis setting ***
#***

local port ce20
#*** lane 0 ***
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1E8
phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x90
phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0
phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1

#*** lane 1 ***
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1E8
phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x84
phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1

Similar issue with ce46 which got assigned with 3 lanes while ce47 only one lane:
https://github.com/Azure/sonic-buildimage/blob/8a00ad73fd071e6e5f13319587f7f2432acd4acf/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-M-O16C64/sai_postinit_cmd.soc#L977

Please investigate and if this is a bug please help fix it.

[gechiang]

@aravindmani-1 Can you please help investigate and answer my question?
Thanks!

[aravindmani-1]

100G ports should be assigned to two lanes only. Will raise PR to fix this issue. Thanks.