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Interrupt is not implemented after 'duh-export-scala' #71

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RyanSangdeokPark opened this issue Feb 19, 2020 · 0 comments
Open

Interrupt is not implemented after 'duh-export-scala' #71

RyanSangdeokPark opened this issue Feb 19, 2020 · 0 comments

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@RyanSangdeokPark
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I describe interrupt component to the duh document, but it's not implemented after chisel wrapper generation using 'duh-export-scala' command. to be more precise, interrupt wiring is not executed.

this is what I described interrupt component in the json5
......
"intr": {
name: "irq",
interfaceMode: "master",
busType: {vendor: "sifive.com", version: "0.1.0", library: "free", name: "interrupts"},
abstractionTypes: [
{
viewRef: "RTLview",
portMaps: [
'hightemp_int',
]
}
],
},
......

this is a part of the generated chisel wrapper (*-base.scala)
......
class LmifBaseImp extends LazyRawModuleImp(this) {
...
// interface wiring
val irq0 = irqNode.out(0)._1
...
// wiring for irq of type interrupts
// ["hightemp_int"]
...
}
......

I think below line is should be include in the generated chisel wrapper.
......
// wiring for irq of type interrupts
// ["hightemp_int"]
irq0(0) := blackbox.io.hightemp_int
......

@drom drom transferred this issue from sifive/duhportinf Mar 6, 2020
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