From a3f6821c84eda8c7a038439d07e891ac3cc22da8 Mon Sep 17 00:00:00 2001
From: Henri Lunnikivi <heggggxa@gmail.com>
Date: Sat, 5 Oct 2024 11:52:05 +0300
Subject: [PATCH] Update tests/ui/abi/riscv32e-registers.rs

Co-authored-by: Jubilee <workingjubilee@gmail.com>
---
 tests/ui/abi/riscv32e-registers.rs | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tests/ui/abi/riscv32e-registers.rs b/tests/ui/abi/riscv32e-registers.rs
index 937c6c70f5ee3..4b34f188efb1f 100644
--- a/tests/ui/abi/riscv32e-registers.rs
+++ b/tests/ui/abi/riscv32e-registers.rs
@@ -22,8 +22,7 @@ macro_rules! asm {
 #[lang = "sized"]
 trait Sized {}
 
-// Check that loads to registers x1..=x16 will be generated but loads to registers x17..=x31 will
-// not.
+// Verify registers x1..=x15 are addressable on riscv32e, but registers x16..=x31 are not.
 #[no_mangle]
 pub unsafe fn registers() {
     asm!("li x1, 0");