From 9d0b3565b53250f7ab770f61a86de5e3e756618a Mon Sep 17 00:00:00 2001 From: Paul Buxton Date: Mon, 29 Jul 2024 14:42:01 +0100 Subject: [PATCH] Reword the ASR description to clarify Zstid register behaviour. (#335) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The thread id registers introduced in Zstid differ in behaviour with other registers in that they have different behaviour for reads than writes, and the utidc register is treated as privileged for the purposes of ASR checking. Try and clarify this more. --------- Co-authored-by: Andrés Amaya Garcia --- src/cap-description.adoc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/cap-description.adoc b/src/cap-description.adoc index d108eb15..cfa4d619 100644 --- a/src/cap-description.adoc +++ b/src/cap-description.adoc @@ -120,10 +120,11 @@ Execute Permission (X):: Allow instruction execution. [#asr_perm,reftext="ASR-permission"] Access System Registers Permission (ASR):: Allow read and write access to all -privileged (M-mode and S-mode) CSRs with the following exceptions: -. <>, <>, <>, <>, <>, <> all require ASR -access for writing and not for reading, as well as having a suitable privileged -execution mode. +privileged (M-mode and S-mode) CSRs. +If {tid_ext_name} is supported the <>, <>, <>, <>, <>, +<> registers are all considered privileged for the purposes of writing +and unprivileged for reading, and thus require ASR-permission for writes but not reads. +In all cases a suitable privilege mode is required for access. [#cap_permissions_encoding] ===== Permission Encoding