From 17530cb714a28a4981b9c4f677cbff05efc04498 Mon Sep 17 00:00:00 2001 From: Jason Yu Date: Fri, 4 Oct 2024 22:56:54 +0800 Subject: [PATCH] Chapter 3 note about the relationship between privileged and unprivileged components (#321) Related to discussions in #317 This adds a note at the beginning of chapter 3 to clarify the split privileged/unprivileged design that mirrors the base RISC-V ISA. --- src/riscv-integration.adoc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 81aca480..37deee38 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -15,6 +15,14 @@ NOTE: The changes described in this specification also ensure that NOTE: RV128 is not currently supported by any CHERI extension. +NOTE: In line with the base RISC-V ISA, the unprivileged component +with its corresponding {cheri_base_ext_name} changes +as described in this chapter can be used with +an entirely different privileged-level design. The changes for the privileged +component described in this chapter are designed to support existing +popular operating systems, and assume the standard +privileged architecture specified in the RISC-V ISA. + === Memory A hart supporting {cheri_base_ext_name} has a single byte-addressable address