From 560904fdf0f5870f0ffa8b4c9ea661feca9e3198 Mon Sep 17 00:00:00 2001 From: Flex Software Development Robot Date: Tue, 6 Oct 2020 01:01:37 +0000 Subject: [PATCH] Release v2.0.0 --- README.md | 18 +- ra/board/ra6m4_ek/board.h | 62 + .../ra6m4_ek/board_ethernet_phy.h} | 64 +- ra/board/ra6m4_ek/board_init.c | 62 + .../ra6m4_ek/board_init.h} | 62 +- ra/board/ra6m4_ek/board_leds.c | 71 + ra/board/ra6m4_ek/board_leds.h | 75 + ra/fsp/inc/api/bsp_api.h | 2 +- ra/fsp/inc/api/r_adc_api.h | 14 + ra/fsp/inc/api/r_ble_api.h | 114 +- ra/fsp/inc/api/r_cac_api.h | 13 + ra/fsp/inc/api/r_can_api.h | 13 + ra/fsp/inc/api/r_cgc_api.h | 21 +- ra/fsp/inc/api/r_ctsu_api.h | 13 + ra/fsp/inc/api/r_doc_api.h | 14 + ra/fsp/inc/api/r_external_irq_api.h | 16 + ra/fsp/inc/api/r_flash_api.h | 13 + ra/fsp/inc/api/r_i2c_master_api.h | 18 +- ra/fsp/inc/api/r_i2c_slave_api.h | 20 +- ra/fsp/inc/api/r_i2s_api.h | 14 + ra/fsp/inc/api/r_ioport_api.h | 4 + ra/fsp/inc/api/r_lpm_api.h | 142 +- ra/fsp/inc/api/r_lvd_api.h | 14 + ra/fsp/inc/api/r_poeg_api.h | 13 + ra/fsp/inc/api/r_rtc_api.h | 13 + ra/fsp/inc/api/r_sdmmc_api.h | 13 + ra/fsp/inc/api/r_spi_api.h | 23 + ra/fsp/inc/api/r_spi_flash_api.h | 44 +- ra/fsp/inc/api/r_three_phase_api.h | 14 + ra/fsp/inc/api/r_timer_api.h | 14 + ra/fsp/inc/api/r_uart_api.h | 14 + ra/fsp/inc/api/r_usb_hhid_api.h | 9 + ra/fsp/inc/api/r_wdt_api.h | 13 + ra/fsp/inc/api/rm_block_media_api.h | 16 + ra/fsp/inc/api/rm_touch_api.h | 41 +- ra/fsp/inc/api/rm_vee_api.h | 13 + ra/fsp/inc/fsp_common_api.h | 11 +- ra/fsp/inc/fsp_features.h | 1 + ra/fsp/inc/fsp_version.h | 10 +- ra/fsp/inc/instances/r_adc.h | 19 +- ra/fsp/inc/instances/r_agt.h | 19 +- ra/fsp/inc/instances/r_cac.h | 15 + ra/fsp/inc/instances/r_can.h | 31 +- ra/fsp/inc/instances/r_cgc.h | 15 +- ra/fsp/inc/instances/r_ctsu.h | 74 +- ra/fsp/inc/instances/r_doc.h | 13 + ra/fsp/inc/instances/r_ether.h | 2 - ra/fsp/inc/instances/r_flash_hp.h | 22 +- ra/fsp/inc/instances/r_flash_lp.h | 4 + ra/fsp/inc/instances/r_gpt.h | 30 +- ra/fsp/inc/instances/r_gpt_three_phase.h | 4 + ra/fsp/inc/instances/r_icu.h | 18 +- ra/fsp/inc/instances/r_iic_master.h | 15 + ra/fsp/inc/instances/r_iic_slave.h | 15 + ra/fsp/inc/instances/r_iwdt.h | 10 + ra/fsp/inc/instances/r_lvd.h | 13 + ra/fsp/inc/instances/r_ospi.h | 179 + ra/fsp/inc/instances/r_poeg.h | 17 +- ra/fsp/inc/instances/r_rtc.h | 18 +- ra/fsp/inc/instances/r_sci_i2c.h | 15 + ra/fsp/inc/instances/r_sci_spi.h | 15 + ra/fsp/inc/instances/r_sci_uart.h | 13 + ra/fsp/inc/instances/r_sdhi.h | 8 + ra/fsp/inc/instances/r_spi.h | 15 + ra/fsp/inc/instances/r_ssi.h | 16 +- ra/fsp/inc/instances/r_usb_hhid.h | 1 + ra/fsp/inc/instances/r_wdt.h | 9 + ra/fsp/inc/instances/rm_block_media_sdmmc.h | 11 +- ra/fsp/inc/instances/rm_block_media_usb.h | 5 + ra/fsp/inc/instances/rm_touch.h | 76 +- ra/fsp/inc/instances/rm_vee_flash.h | 11 + ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a | Bin 1479368 -> 1480626 bytes .../lib/r_ble/cm4_ac6/all_freertos/libr_ble.a | Bin 1480768 -> 1481650 bytes ra/fsp/lib/r_ble/cm4_gcc/all/libr_ble.a | Bin 1128076 -> 1128594 bytes .../lib/r_ble/cm4_gcc/all_freertos/libr_ble.a | Bin 1129188 -> 1129426 bytes ra/fsp/lib/r_ble/cm4_iar/all/libr_ble.a | Bin 2515634 -> 2518234 bytes .../lib/r_ble/cm4_iar/all_freertos/libr_ble.a | Bin 2534070 -> 2536488 bytes .../Device/RENESAS/Include/base_addresses.h | 521 + .../cmsis/Device/RENESAS/Include/renesas.h | 23061 +-- .../src/bsp/cmsis/Device/RENESAS/SVD/RA.svd | 121089 ++++++++------- .../bsp/cmsis/Device/RENESAS/Source/startup.c | 4 +- .../bsp/cmsis/Device/RENESAS/Source/system.c | 186 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.c | 422 +- ra/fsp/src/bsp/mcu/all/bsp_clocks.h | 54 +- ra/fsp/src/bsp/mcu/all/bsp_common.h | 32 +- ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h | 35 +- ra/fsp/src/bsp/mcu/all/bsp_group_irq.c | 4 +- ra/fsp/src/bsp/mcu/all/bsp_group_irq.h | 2 + .../mcu/all/bsp_guard.c} | 52 +- .../mcu/all/bsp_guard.h} | 44 +- ra/fsp/src/bsp/mcu/all/bsp_io.h | 18 +- ra/fsp/src/bsp/mcu/all/bsp_irq.c | 42 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+ .../rm_block_media_sdmmc.c | 152 +- .../rm_block_media_usb/rm_block_media_usb.c | 42 +- .../rm_freertos_plus_tcp/NetworkInterface.c | 13 +- .../src/rm_littlefs_flash/rm_littlefs_flash.c | 4 +- ra/fsp/src/rm_psa_crypto/aes_alt_process.c | 52 +- ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c | 1591 + ra/fsp/src/rm_psa_crypto/ecdsa_alt.c | 175 +- ra/fsp/src/rm_psa_crypto/ecp_alt_process.c | 202 +- ra/fsp/src/rm_psa_crypto/inc/aes_alt.h | 5 +- .../src/rm_psa_crypto/inc/asymmetric_vendor.h | 42 +- ra/fsp/src/rm_psa_crypto/inc/ctr_drbg_alt.h | 575 + ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h | 1 - ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h | 62 +- ra/fsp/src/rm_psa_crypto/platform_alt.c | 32 +- ra/fsp/src/rm_psa_crypto/rsa_alt_process.c | 108 +- .../ra/CMSIS_Driver/Driver_Flash.c | 609 + .../ra/CMSIS_Driver/Driver_QSPI_Flash.c | 176 + .../ra/CMSIS_Driver/Driver_USART.c | 279 + .../rm_tfm_port/ra/Device/Config/device_cfg.h | 33 + .../src/rm_tfm_port/ra/Device/Include/cmsis.h | 71 + .../ra/Device/Include/platform_base_address.h | 34 + .../ra/Device/Include/platform_description.h | 25 + .../ra/Device/Include/platform_irq.h | 39 + .../ra/Device/Include/platform_pins.h | 27 + .../ra/Device/Include/platform_regs.h | 23 + .../ra/Device/Include/system_core_init.h | 39 + .../ra/Device/Source/system_core_init.c | 89 + .../ra/Native_Driver/mpu_armv8m_drv.c | 152 + .../ra/Native_Driver/mpu_armv8m_drv.h | 143 + ra/fsp/src/rm_tfm_port/ra/attest_hal.c | 134 + ra/fsp/src/rm_tfm_port/ra/boot_hal.c | 180 + ra/fsp/src/rm_tfm_port/ra/crypto_keys.c | 118 + ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h | 33 + ra/fsp/src/rm_tfm_port/ra/nv_counters.c | 197 + .../rm_tfm_port/ra/partition/flash_layout.h | 200 + .../rm_tfm_port/ra/partition/region_defs.h | 137 + .../ra/services/include/tfm_ioctl_api.h | 310 + .../ra/services/src/tfm_ioctl_s_api.c | 308 + .../ra/services/src/tfm_platform_system.c | 142 + ra/fsp/src/rm_tfm_port/ra/spm_hal.c | 297 + ra/fsp/src/rm_tfm_port/ra/target_cfg.c | 140 + ra/fsp/src/rm_tfm_port/ra/target_cfg.h | 98 + .../ra/tfm_initial_attestation_key_material.c | 83 + .../src/rm_tfm_port/ra/tfm_peripherals_def.h | 39 + ra/fsp/src/rm_tfm_port/tfm_common_config.h | 26 + ra/fsp/src/rm_touch/rm_touch.c | 880 +- ra/fsp/src/rm_tz_context/tz_context.c | 224 + ra/fsp/src/rm_vee_flash/rm_vee_flash.c | 122 +- .../rm_wifi_onchip_silex/aws_secure_sockets.c | 203 +- 348 files changed, 153447 insertions(+), 67124 deletions(-) create mode 100644 ra/board/ra6m4_ek/board.h rename ra/{fsp/src/r_sce/ra2/SC324_p02.prc.c => board/ra6m4_ek/board_ethernet_phy.h} (56%) create mode 100644 ra/board/ra6m4_ek/board_init.c rename ra/{fsp/src/r_sce/ra4_sce5/SC327_p99.prc.c => board/ra6m4_ek/board_init.h} (58%) create mode 100644 ra/board/ra6m4_ek/board_leds.c create mode 100644 ra/board/ra6m4_ek/board_leds.h create mode 100644 ra/fsp/inc/instances/r_ospi.h create mode 100644 ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h rename ra/fsp/src/{r_sce/ra2/SC324_p99.prc.c => bsp/mcu/all/bsp_guard.c} (64%) rename ra/fsp/src/{r_sce/ra2/SC324_SoftReset.prc.c => bsp/mcu/all/bsp_guard.h} (68%) create mode 100644 ra/fsp/src/bsp/mcu/all/bsp_security.c rename ra/fsp/src/{r_sce/ra2/SC324_p01.prc.c => bsp/mcu/all/bsp_security.h} (59%) create mode 100644 ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h create mode 100644 ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h create mode 100644 ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h create mode 100644 ra/fsp/src/r_ospi/r_ospi.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_RSA_adapt.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c create mode 100644 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ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h create mode 100644 ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h create mode 100644 ra/fsp/src/r_sce/ra2/SC324_utils.c create mode 100644 ra/fsp/src/r_sce/ra2/SCE_module.h create mode 100644 ra/fsp/src/r_sce/ra4_sce5/SC327_utils.c create mode 100644 ra/fsp/src/r_sce/ra4_sce5/SCE_module.h create mode 100644 ra/fsp/src/r_sce/ra6_sce7/SC32_utils.c create mode 100644 ra/fsp/src/r_sce/ra6_sce7/SCE_module.h create mode 100644 ra/fsp/src/rm_bl2_port/tfm_common_config.h create mode 100644 ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c create mode 100644 ra/fsp/src/rm_psa_crypto/inc/ctr_drbg_alt.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_Flash.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_QSPI_Flash.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_USART.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Config/device_cfg.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/cmsis.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_base_address.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_description.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_irq.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_pins.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_regs.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Include/system_core_init.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/Device/Source/system_core_init.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/attest_hal.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/boot_hal.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/crypto_keys.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/nv_counters.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/partition/flash_layout.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/services/src/tfm_ioctl_s_api.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/services/src/tfm_platform_system.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/spm_hal.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/target_cfg.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/target_cfg.h create mode 100644 ra/fsp/src/rm_tfm_port/ra/tfm_initial_attestation_key_material.c create mode 100644 ra/fsp/src/rm_tfm_port/ra/tfm_peripherals_def.h create mode 100644 ra/fsp/src/rm_tfm_port/tfm_common_config.h create mode 100644 ra/fsp/src/rm_tz_context/tz_context.c diff --git a/README.md b/README.md index cece93d4d..01a4f8bd5 100644 --- a/README.md +++ b/README.md @@ -1,16 +1,17 @@ - ## Overview + Flexible Software Package (FSP) for Renesas RA MCU Family FSP is the next generation Arm® MCU software package from Renesas, that enables secure devices and IoT connectivity through production ready peripheral drivers, FreeRTOS, and portable middleware stacks. FSP includes best-in-class HAL drivers with high performance and low memory footprint. Middleware stacks with FreeRTOS integration are included to ease implementation of complex modules like communication and security. -The e² studio ISDE provides support with intuitive configurators and intelligent code generation to make programming and debugging easier and faster. +The e² studio ISDE provides support with intuitive configurators and intelligent code generation to make programming and debugging easier and faster. -FSP uses an open software ecosystem and provides flexibility in using your preferred RTOS, legacy code, and third-party ecosystem solutions. +FSP uses an open software ecosystem and provides flexibility in using your preferred RTOS, legacy code, and third-party ecosystem solutions. Download the latest FSP version from the [Releases page](https://github.com/renesas/fsp/releases). ### Supported RA MCU Kits + - EK-RA2A1 - EK-RA4M1 - EK-RA4W1 @@ -18,14 +19,18 @@ Download the latest FSP version from the [Releases page](https://github.com/rene - EK-RA6M2 - EK-RA6M3 - EK-RA6M3G +- EK-RA6M4 ### Setup Instructions #### For existing users that are using FSP with e² studio +FSP versions of 2.0.0 and later require a minimum e² studio version of 2020-10. + If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, and an installer version, FSP_Packs_\.exe. #### For new users that are using FSP with e² studio + 1. Download the FSP with e² studio Installer from the Assets section of the [latest release](https://github.com/renesas/fsp/releases). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. @@ -34,9 +39,12 @@ If you have already installed a previous FSP release that included e² studio th 1. See [RA SC User Guide for MDK and IAR](https://renesas.github.io/fsp/_s_t_a_r_t__d_e_v.html#RASC-MDK-IAR-user-guide). ### Starting Development -1. Open e² studio and click File > New > RA C/C++ Project. + +1. Open e² studio and click File > New > C/C++ Project. +2. In the window that pops up, choose Renesas RA in the left pane. ### Related Links + FSP Releases : https://github.com/renesas/fsp/releases FSP Documentation : https://renesas.github.io/fsp @@ -53,4 +61,4 @@ Example Projects : www.renesas.com/ra/example-projects Knowledge Base: https://en-support.renesas.com/knowledgeBase/category/31087 -Support: www.renesas.com/support +Support: www.renesas.com/support diff --git a/ra/board/ra6m4_ek/board.h b/ra/board/ra6m4_ek/board.h new file mode 100644 index 000000000..3135cd3b1 --- /dev/null +++ b/ra/board/ra6m4_ek/board.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RA6M4_EK BSP for the RA6M4-EK board + * @brief BSP for the RA6M4-EK Board + * + * The RA6M4_EK is a development kit for the Renesas R7FA6M4AF3CFB microcontroller in a LQFP144 package. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RA6M4_EK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BOARD_RA6M4_EK) */ + +#endif diff --git a/ra/fsp/src/r_sce/ra2/SC324_p02.prc.c b/ra/board/ra6m4_ek/board_ethernet_phy.h similarity index 56% rename from ra/fsp/src/r_sce/ra2/SC324_p02.prc.c rename to ra/board/ra6m4_ek/board_ethernet_phy.h index acd27b043..a9d666b73 100644 --- a/ra/fsp/src/r_sce/ra2/SC324_p02.prc.c +++ b/ra/board/ra6m4_ek/board_ethernet_phy.h @@ -18,31 +18,43 @@ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. **********************************************************************************************************************/ -///////////////////////////////////////////////////////////////////////////////////////// -// // -// Procedure number: 02 // -// File name : SC324_p02.prc // -// State Diagram : main(FSM1) // -// Start State : main01 // -// End State : Pass :main03, Retry :main01 // -// Input Data : void // -// Output Data : void // -// Return value : Pass, Retry, Resource_Conflict // -// -------------------------------------------------------------------------------------// -// total cycle : polling + write access + read access // -// polling : cycle // -// polling access : times // -// write access : times // -// read access : times // -///////////////////////////////////////////////////////////////////////////////////////// - -#include "hw_sce_private.h" -#include "fsp_common_api.h" - /*******************************************************************************************************************//** - * TSIP Initialization2 - * @retval FSP_SUCCESS The operation completed successfully. + * @ingroup BOARD_RA6M4_EK + * @defgroup BOARD_RA6M4_EK_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RA6M4_EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_PHY_TYPE (1) +#define BOARD_PHY_REF_CLK (1) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions **********************************************************************************************************************/ -fsp_err_t HW_SCE_Initialization2 () { - return FSP_SUCCESS; -} + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6M4_EK_ETHERNET_PHY) */ diff --git a/ra/board/ra6m4_ek/board_init.c b/ra/board/ra6m4_ek/board_init.c new file mode 100644 index 000000000..188fd9a5b --- /dev/null +++ b/ra/board/ra6m4_ek/board_init.c @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M4_EK + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RA6M4_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RA6M4_EK) */ diff --git a/ra/fsp/src/r_sce/ra4_sce5/SC327_p99.prc.c b/ra/board/ra6m4_ek/board_init.h similarity index 58% rename from ra/fsp/src/r_sce/ra4_sce5/SC327_p99.prc.c rename to ra/board/ra6m4_ek/board_init.h index c2dfd11c0..20a6ac4b3 100644 --- a/ra/fsp/src/r_sce/ra4_sce5/SC327_p99.prc.c +++ b/ra/board/ra6m4_ek/board_init.h @@ -18,31 +18,41 @@ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. **********************************************************************************************************************/ -////////////////////////////////////////////////////////////////////////// -// // -// Procedure number: 99 // -// File name : SC327_p99.prc // -// State Diagram : main(FSM1) // -// Start State : main02 // -// End State : main03 // -// Input Data : void // -// Output Data : void // -// Return value : Pass, Resource_Conflict // -// ----------------------------------------------------------------------// -// total cycle : polling + write access + read access // -// polling : TBD // -// polling access : TBD // -// write access : TBD // -// read access : TBD // -////////////////////////////////////////////////////////////////////////// - -#include "SCE_ProcCommon.h" -#include "hw_sce_private.h" - /*******************************************************************************************************************//** - * Secure Boot procedure - * @retval FSP_SUCCESS The operation completed successfully. + * @addtogroup BOARD_RA6M4_EK + * @brief Board specific code for the RA6M4-EK Board + * + * This include file is specific to the RA6M4-EK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) **********************************************************************************************************************/ -fsp_err_t HW_SCE_secureBoot (void) { - return FSP_SUCCESS; -} +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end addtogroup BOARD_RA6M4_EK) */ diff --git a/ra/board/ra6m4_ek/board_leds.c b/ra/board/ra6m4_ek/board_leds.c new file mode 100644 index 000000000..a1b3b0bc5 --- /dev/null +++ b/ra/board/ra6m4_ek/board_leds.c @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RA6M4_EK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RA6M4_EK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint16_t g_bsp_prv_leds[] = +{ + (uint16_t) BSP_IO_PORT_04_PIN_15, ///< LED1 + (uint16_t) BSP_IO_PORT_04_PIN_04, ///< LED2 + (uint16_t) BSP_IO_PORT_04_PIN_00, ///< LED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))), + .p_leds = &g_bsp_prv_leds[0] +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RA6M4_EK_LEDS) */ diff --git a/ra/board/ra6m4_ek/board_leds.h b/ra/board/ra6m4_ek/board_leds.h new file mode 100644 index 000000000..dd536e87a --- /dev/null +++ b/ra/board/ra6m4_ek/board_leds.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RA6M4_EK + * @defgroup BOARD_RA6M4_EK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the EK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_LED1, ///< LED1 + BSP_LED_LED2, ///< LED2 + BSP_LED_LED3, ///< LED3 +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RA6M4_EK_LEDS) */ diff --git a/ra/fsp/inc/api/bsp_api.h b/ra/fsp/inc/api/bsp_api.h index 54e0465e8..50a91d586 100644 --- a/ra/fsp/inc/api/bsp_api.h +++ b/ra/fsp/inc/api/bsp_api.h @@ -62,13 +62,13 @@ #include "../../src/bsp/mcu/all/bsp_group_irq.h" #include "../../src/bsp/mcu/all/bsp_clocks.h" #include "../../src/bsp/mcu/all/bsp_module_stop.h" +#include "../../src/bsp/mcu/all/bsp_security.h" /* Factory MCU information. */ #include "../../inc/fsp_features.h" /* BSP Common Includes (Other than bsp_common.h) */ #include "../../src/bsp/mcu/all/bsp_delay.h" - #include "../../src/bsp/mcu/all/bsp_mcu_api.h" /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ diff --git a/ra/fsp/inc/api/r_adc_api.h b/ra/fsp/inc/api/r_adc_api.h index 843026d10..795c90dc4 100644 --- a/ra/fsp/inc/api/r_adc_api.h +++ b/ra/fsp/inc/api/r_adc_api.h @@ -295,6 +295,20 @@ typedef struct st_adc_api */ fsp_err_t (* offsetSet)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_ADC_CallbackSet() + * + * @param[in] p_ctrl Pointer to the ADC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(adc_ctrl_t * const p_api_ctrl, void (* p_callback)(adc_callback_args_t *), + void const * const p_context, adc_callback_args_t * const p_callback_memory); + /** Close the specified ADC unit by ending any scan in progress, disabling interrupts, and removing power to the * specified A/D unit. * @par Implemented as diff --git a/ra/fsp/inc/api/r_ble_api.h b/ra/fsp/inc/api/r_ble_api.h index 61cbae149..77163ddef 100644 --- a/ra/fsp/inc/api/r_ble_api.h +++ b/ra/fsp/inc/api/r_ble_api.h @@ -50,7 +50,7 @@ FSP_HEADER /********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BLE_API_VERSION_MAJOR (1U) +#define BLE_API_VERSION_MAJOR (2U) #define BLE_API_VERSION_MINOR (0U) /* =================================================== Main Macro =================================================== */ @@ -59,13 +59,13 @@ FSP_HEADER * @def BLE_VERSION_MAJOR * BLE Module Major Version. */ -#define BLE_VERSION_MAJOR (0x0000) +#define BLE_VERSION_MAJOR (0x0002) /** * @def BLE_VERSION_MINOR * BLE Module Minor Version. */ -#define BLE_VERSION_MINOR (0x0009) +#define BLE_VERSION_MINOR (0x0000) /** * @def BLE_LIB_ALL_FEATS @@ -550,37 +550,37 @@ enum RBLE_STATUS_enum * @def BLE_GAP_LIST_ADD_DEV * @brief Add the device to the list. */ -#define BLE_GAP_LIST_ADD_DEV (0x01) +#define BLE_GAP_LIST_ADD_DEV (0x01) /** * @def BLE_GAP_LIST_REM_DEV * @brief Delete the device from the list. */ -#define BLE_GAP_LIST_REM_DEV (0x02) +#define BLE_GAP_LIST_REM_DEV (0x02) /** * @def BLE_GAP_LIST_CLR * @brief Clear the list. */ -#define BLE_GAP_LIST_CLR (0x03) +#define BLE_GAP_LIST_CLR (0x03) /** * @def BLE_GAP_WHITE_LIST_MAX_ENTRY * @brief The maximum entry number of White List. */ -#define BLE_GAP_WHITE_LIST_MAX_ENTRY (0x04) +#define BLE_GAP_WHITE_LIST_MAX_ENTRY (0x04) /** * @def BLE_GAP_RSLV_LIST_MAX_ENTRY * @brief The maximum entry number of Resolving List. */ -#define BLE_GAP_RSLV_LIST_MAX_ENTRY (0x08) +#define BLE_GAP_RSLV_LIST_MAX_ENTRY (0x08) /** * @def BLE_GAP_PERD_LIST_MAX_ENTRY * @brief The maximum entry number of Periodic Advertiser List. */ -#define BLE_GAP_PERD_LIST_MAX_ENTRY (0x04) +#define BLE_GAP_PERD_LIST_MAX_ENTRY (0x04) /* Set Address Resolution */ @@ -588,13 +588,13 @@ enum RBLE_STATUS_enum * @def BLE_GAP_RPA_DISABLED * @brief Disable RPA generation/resolution. */ -#define BLE_GAP_RPA_DISABLED (0x00) +#define BLE_GAP_RPA_DISABLED (0x00) /** * @def BLE_GAP_RPA_ENABLED * @brief Enable RPA generation/resolution. */ -#define BLE_GAP_RPA_ENABLED (0x01) +#define BLE_GAP_RPA_ENABLED (0x01) /* Set Local IRK type */ @@ -602,13 +602,13 @@ enum RBLE_STATUS_enum * @def BLE_GAP_RL_LOC_KEY_ALL_ZERO * @brief All-zero IRK. */ -#define BLE_GAP_RL_LOC_KEY_ALL_ZERO (0x00) +#define BLE_GAP_RL_LOC_KEY_ALL_ZERO (0x00) /** * @def BLE_GAP_RL_LOC_KEY_REGISTERED * @brief The IRK registered by R_BLE_GAP_SetLocIdInfo(). */ -#define BLE_GAP_RL_LOC_KEY_REGISTERED (0x01) +#define BLE_GAP_RL_LOC_KEY_REGISTERED (0x01) /* Number of advertising set supported */ @@ -616,7 +616,11 @@ enum RBLE_STATUS_enum * @def BLE_MAX_NO_OF_ADV_SETS_SUPPORTED * @brief The maximum number of advertising set for the Abstraction API. */ -#define BLE_MAX_NO_OF_ADV_SETS_SUPPORTED (BLE_ABS_CFG_RF_ADVERTISING_SET_MAXIMUM) +#if (BLE_CFG_LIBRARY_TYPE == 0) + #define BLE_MAX_NO_OF_ADV_SETS_SUPPORTED (4) +#else /* (BLE_CFG_LIB_TYPE == 0) */ + #define BLE_MAX_NO_OF_ADV_SETS_SUPPORTED (1) +#endif /* (BLE_CFG_LIB_TYPE == 0) */ /* Advertising Properties */ /* Legacy Advertising PDU */ @@ -9660,6 +9664,18 @@ typedef struct void * p_param; } st_ble_vs_evt_data_t; +/******************************************************************************************************************//** + * @struct st_ble_vs_get_scan_ch_map_comp_evt_t + * @brief This structure notifies that current scan channel map. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The result of current scan channel map. + */ + uint8_t ch_map; +} st_ble_vs_get_scan_ch_map_comp_evt_t; + /******************************************************************************************************************//** * @typedef ble_vs_app_cb_t * @brief ble_vs_app_cb_t is the Vendor Specific Event callback function type. @@ -9993,6 +10009,50 @@ typedef enum */ BLE_VS_EVENT_FAIL_DETECT = 0x800D, + /** + * @brief This event notifies that scan channel map has been set by R_BLE_VS_SetScanChMap(). + * + * ## Event Code: 0x800E + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The ch_map parameter specified by R_BLE_VS_SetScanChMap() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SET_SCAN_CH_MAP = 0x800E, + + /** + * @brief This event notifies that scan channel map has been retrieved by R_BLE_VS_GetScanChMap(). + * + * ## Event Code: 0x800F + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_get_scan_ch_map_comp_evt_t + */ + BLE_VS_EVENT_GET_SCAN_CH_MAP = 0x800F, + /** * @brief Invalid VS Event. * @@ -12564,6 +12624,32 @@ ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num); **********************************************************************************************************************/ ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm); +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetScanChMap(uint16_t ch_map) + * @brief This function sets the scan channel map. + * @details Set specify the scan channel for use.\n + * At least one channel must be enabled. + * @note Calling this API while Scan is already running will not change the channel map. + * @param[in] ch_map Specify the channel map for use. + * | bit | description | + * |:-------------- |:-------------------------------------------------- | + * | bit0 | Enable channel 37 for use (0:disable, 1:enable) | + * | bit1 | Enable channel 38 for use (0:disable, 1:enable) | + * | bit2 | Enable channel 39 for use (0:disable, 1:enable) | + * | All other bits | Reserved for future use. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The ch_map parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetScanChMap(uint16_t ch_map); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetScanChMap(void) + * @brief This function gets currently scan channel map. + * @details The result of this API call is notified in BLE_VS_EVENT_GET_SCAN_CH_MAP event. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetScanChMap(void); + /*@}*/ /*******************************************************************************************************************//** diff --git a/ra/fsp/inc/api/r_cac_api.h b/ra/fsp/inc/api/r_cac_api.h index ae0cc793e..c57952b62 100644 --- a/ra/fsp/inc/api/r_cac_api.h +++ b/ra/fsp/inc/api/r_cac_api.h @@ -195,6 +195,19 @@ typedef struct st_cac_api */ fsp_err_t (* read)(cac_ctrl_t * const p_ctrl, uint16_t * const p_counter); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_CAC_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref cac_api_t::open call + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(cac_ctrl_t * const p_api_ctrl, void (* p_callback)(cac_callback_args_t *), + void const * const p_context, cac_callback_args_t * const p_callback_memory); + /** Close function for CAC device. * @param[in] p_ctrl Pointer to CAC device control. */ diff --git a/ra/fsp/inc/api/r_can_api.h b/ra/fsp/inc/api/r_can_api.h index 34c96e0b7..6d1fb94db 100644 --- a/ra/fsp/inc/api/r_can_api.h +++ b/ra/fsp/inc/api/r_can_api.h @@ -319,6 +319,19 @@ typedef struct st_can_api */ fsp_err_t (* infoGet)(can_ctrl_t * const p_ctrl, can_info_t * const p_info); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_CAN_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref can_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(can_ctrl_t * const p_api_ctrl, void (* p_callback)(can_callback_args_t *), + void const * const p_context, can_callback_args_t * const p_callback_memory); + /** Version get function for CAN device * @par Implemented as * - R_CAN_VersionGet() diff --git a/ra/fsp/inc/api/r_cgc_api.h b/ra/fsp/inc/api/r_cgc_api.h index 6e86d0e2f..0e2933195 100644 --- a/ra/fsp/inc/api/r_cgc_api.h +++ b/ra/fsp/inc/api/r_cgc_api.h @@ -87,6 +87,7 @@ typedef enum e_cgc_clock CGC_CLOCK_MAIN_OSC = 3, ///< The main oscillator CGC_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator CGC_CLOCK_PLL = 5, ///< The PLL oscillator + CGC_CLOCK_PLL2 = 6, ///< The PLL2 oscillator } cgc_clock_t; /** PLL divider values */ @@ -219,6 +220,7 @@ typedef void cgc_ctrl_t; typedef struct s_cgc_cfg { void (* p_callback)(cgc_callback_args_t * p_args); + void const * p_context; } cgc_cfg_t; /** Clock configuration */ @@ -226,12 +228,14 @@ typedef struct st_cgc_clocks_cfg { cgc_clock_t system_clock; ///< System clock source enumeration cgc_pll_cfg_t pll_cfg; ///< PLL configuration structure + cgc_pll_cfg_t pll2_cfg; ///< PLL2 configuration structure cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure cgc_clock_change_t loco_state; ///< State of LOCO cgc_clock_change_t moco_state; ///< State of MOCO cgc_clock_change_t hoco_state; ///< State of HOCO cgc_clock_change_t mainosc_state; ///< State of Main oscillator cgc_clock_change_t pll_state; ///< State of PLL + cgc_clock_change_t pll2_state; ///< State of PLL2 } cgc_clocks_cfg_t; /** CGC functions implemented at the HAL layer follow this API. */ @@ -258,7 +262,8 @@ typedef struct * - @ref R_CGC_ClockStart() * @param[in] p_ctrl Pointer to instance control block * @param[in] clock_source Clock source to start - * @param[in] p_pll_cfg Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL + * @param[in] p_pll_cfg Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL or + * CGC_CLOCK_PLL2 */ fsp_err_t (* clockStart)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const * const p_pll_cfg); @@ -323,6 +328,20 @@ typedef struct */ fsp_err_t (* oscStopStatusClear)(cgc_ctrl_t * const p_ctrl); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_CGC_CallbackSet() + * + * @param[in] p_ctrl Pointer to the CGC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(cgc_ctrl_t * const p_api_ctrl, void (* p_callback)(cgc_callback_args_t *), + void const * const p_context, cgc_callback_args_t * const p_callback_memory); + /** Close the CGC driver. * @par Implemented as * - @ref R_CGC_Close() diff --git a/ra/fsp/inc/api/r_ctsu_api.h b/ra/fsp/inc/api/r_ctsu_api.h index 0da8035df..58f6132e7 100644 --- a/ra/fsp/inc/api/r_ctsu_api.h +++ b/ra/fsp/inc/api/r_ctsu_api.h @@ -231,6 +231,19 @@ typedef struct st_ctsu_api */ fsp_err_t (* dataGet)(ctsu_ctrl_t * const p_ctrl, uint16_t * p_data); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_CTSU_CallbackSet() + * + * @param[in] p_ctrl Pointer to the CTSU control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(ctsu_ctrl_t * const p_api_ctrl, void (* p_callback)(ctsu_callback_args_t *), + void const * const p_context, ctsu_callback_args_t * const p_callback_memory); + /** Close driver. * @par Implemented as * - @ref R_CTSU_Close() diff --git a/ra/fsp/inc/api/r_doc_api.h b/ra/fsp/inc/api/r_doc_api.h index b155a6c17..8d814ab38 100644 --- a/ra/fsp/inc/api/r_doc_api.h +++ b/ra/fsp/inc/api/r_doc_api.h @@ -145,6 +145,20 @@ typedef struct st_doc_api * @param[out] p_version Code and API version used. */ fsp_err_t (* versionGet)(fsp_version_t * const p_version); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_DOC_CallbackSet() + * + * @param[in] p_ctrl Pointer to the DOC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(doc_ctrl_t * const p_api_ctrl, void (* p_callback)(doc_callback_args_t *), + void const * const p_context, doc_callback_args_t * const p_callback_memory); } doc_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/api/r_external_irq_api.h b/ra/fsp/inc/api/r_external_irq_api.h index 604616768..ce6c17807 100644 --- a/ra/fsp/inc/api/r_external_irq_api.h +++ b/ra/fsp/inc/api/r_external_irq_api.h @@ -136,6 +136,22 @@ typedef struct st_external_irq_api */ fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_ICU_ExternalIrqCallbackSet() + * + * @param[in] p_ctrl Pointer to the Extneral IRQ control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)(external_irq_callback_args_t *), + void const * const p_context, + external_irq_callback_args_t * const p_callback_memory); + /** Allow driver to be reconfigured. May reduce power consumption. * @par Implemented as * - @ref R_ICU_ExternalIrqClose() diff --git a/ra/fsp/inc/api/r_flash_api.h b/ra/fsp/inc/api/r_flash_api.h index 417985d95..07895dae2 100644 --- a/ra/fsp/inc/api/r_flash_api.h +++ b/ra/fsp/inc/api/r_flash_api.h @@ -330,6 +330,19 @@ typedef struct st_flash_api fsp_err_t (* startupAreaSelect)(flash_ctrl_t * const p_ctrl, flash_startup_area_swap_t swap_type, bool is_temporary); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_FLASH_HP_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref flash_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(flash_ctrl_t * const p_api_ctrl, void (* p_callback)(flash_callback_args_t *), + void const * const p_context, flash_callback_args_t * const p_callback_memory); + /** Get Flash driver version. * @par Implemented as * - @ref R_FLASH_LP_VersionGet() diff --git a/ra/fsp/inc/api/r_i2c_master_api.h b/ra/fsp/inc/api/r_i2c_master_api.h index 547bed12f..76eaae95e 100644 --- a/ra/fsp/inc/api/r_i2c_master_api.h +++ b/ra/fsp/inc/api/r_i2c_master_api.h @@ -84,8 +84,8 @@ typedef enum e_i2c_master_event /** I2C callback parameter definition */ typedef struct st_i2c_master_callback_args { - void const * const p_context; ///< Pointer to user-provided context - i2c_master_event_t const event; ///< Event code + void const * p_context; ///< Pointer to user-provided context + i2c_master_event_t event; ///< Event code } i2c_master_callback_args_t; /** I2C configuration block */ @@ -175,6 +175,20 @@ typedef struct st_i2c_master_api fsp_err_t (* slaveAddressSet)(i2c_master_ctrl_t * const p_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_IIC_MASTER_CallbackSet() + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_master_ctrl_t * const p_api_ctrl, void (* p_callback)(i2c_master_callback_args_t *), + void const * const p_context, i2c_master_callback_args_t * const p_callback_memory); + /** Closes the driver and releases the I2C Master device. * @par Implemented as * - @ref R_IIC_MASTER_Close() diff --git a/ra/fsp/inc/api/r_i2c_slave_api.h b/ra/fsp/inc/api/r_i2c_slave_api.h index eee758e0f..8757a4c73 100644 --- a/ra/fsp/inc/api/r_i2c_slave_api.h +++ b/ra/fsp/inc/api/r_i2c_slave_api.h @@ -88,9 +88,9 @@ typedef enum e_i2c_slave_event /** I2C callback parameter definition */ typedef struct st_i2c_slave_callback_args { - void const * const p_context; ///< Pointer to user-provided context - uint32_t const bytes; ///< Number of received/transmitted bytes in buffer - i2c_slave_event_t const event; ///< Event code + void const * p_context; ///< Pointer to user-provided context + uint32_t bytes; ///< Number of received/transmitted bytes in buffer + i2c_slave_event_t event; ///< Event code } i2c_slave_callback_args_t; /** I2C configuration block */ @@ -155,6 +155,20 @@ typedef struct st_i2c_slave_api */ fsp_err_t (* write)(i2c_slave_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_IIC_SLAVE_CallbackSet() + * + * @param[in] p_ctrl Pointer to the IIC Slave control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_slave_ctrl_t * const p_api_ctrl, void (* p_callback)(i2c_slave_callback_args_t *), + void const * const p_context, i2c_slave_callback_args_t * const p_callback_memory); + /** Closes the driver and releases the I2C Slave device. * @par Implemented as * - @ref R_IIC_SLAVE_Close() diff --git a/ra/fsp/inc/api/r_i2s_api.h b/ra/fsp/inc/api/r_i2s_api.h index 3c62708ed..4cbda86f7 100644 --- a/ra/fsp/inc/api/r_i2s_api.h +++ b/ra/fsp/inc/api/r_i2s_api.h @@ -261,6 +261,20 @@ typedef struct st_i2s_api * @param[out] p_version Code and API version used. */ fsp_err_t (* versionGet)(fsp_version_t * const p_version); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_SSI_CallbackSet() + * + * @param[in] p_ctrl Pointer to the I2S control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2s_ctrl_t * const p_api_ctrl, void (* p_callback)(i2s_callback_args_t *), + void const * const p_context, i2s_callback_args_t * const p_callback_memory); } i2s_api_t; /** This structure encompasses everything that is needed to use an instance of this interface. */ diff --git a/ra/fsp/inc/api/r_ioport_api.h b/ra/fsp/inc/api/r_ioport_api.h index 245774889..472f959f6 100644 --- a/ra/fsp/inc/api/r_ioport_api.h +++ b/ra/fsp/inc/api/r_ioport_api.h @@ -145,6 +145,9 @@ typedef enum e_ioport_peripheral /** Pin will function as a debug trace peripheral pin */ IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + /** Pin will function as a OSPI peripheral pin */ + IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + /** Marks end of enum - used by parameter checking */ IOPORT_PERIPHERAL_END } ioport_peripheral_t; @@ -177,6 +180,7 @@ typedef enum e_ioport_cfg_options IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge diff --git a/ra/fsp/inc/api/r_lpm_api.h b/ra/fsp/inc/api/r_lpm_api.h index c22a7d934..8b48db6e7 100644 --- a/ra/fsp/inc/api/r_lpm_api.h +++ b/ra/fsp/inc/api/r_lpm_api.h @@ -69,47 +69,51 @@ typedef enum e_lpm_mode /** Snooze request sources */ typedef enum e_lpm_snooze_request { - LPM_SNOOZE_REQUEST_RXD0_FALLING = 0x00000000U, ///< Enable RXD0 falling edge snooze request - LPM_SNOOZE_REQUEST_IRQ0 = 0x00000001U, ///< Enable IRQ0 pin snooze request - LPM_SNOOZE_REQUEST_IRQ1 = 0x00000002U, ///< Enable IRQ1 pin snooze request - LPM_SNOOZE_REQUEST_IRQ2 = 0x00000004U, ///< Enable IRQ2 pin snooze request - LPM_SNOOZE_REQUEST_IRQ3 = 0x00000008U, ///< Enable IRQ3 pin snooze request - LPM_SNOOZE_REQUEST_IRQ4 = 0x00000010U, ///< Enable IRQ4 pin snooze request - LPM_SNOOZE_REQUEST_IRQ5 = 0x00000020U, ///< Enable IRQ5 pin snooze request - LPM_SNOOZE_REQUEST_IRQ6 = 0x00000040U, ///< Enable IRQ6 pin snooze request - LPM_SNOOZE_REQUEST_IRQ7 = 0x00000080U, ///< Enable IRQ7 pin snooze request - LPM_SNOOZE_REQUEST_IRQ8 = 0x00000100U, ///< Enable IRQ8 pin snooze request - LPM_SNOOZE_REQUEST_IRQ9 = 0x00000200U, ///< Enable IRQ9 pin snooze request - LPM_SNOOZE_REQUEST_IRQ10 = 0x00000400U, ///< Enable IRQ10 pin snooze request - LPM_SNOOZE_REQUEST_IRQ11 = 0x00000800U, ///< Enable IRQ11 pin snooze request - LPM_SNOOZE_REQUEST_IRQ12 = 0x00001000U, ///< Enable IRQ12 pin snooze request - LPM_SNOOZE_REQUEST_IRQ13 = 0x00002000U, ///< Enable IRQ13 pin snooze request - LPM_SNOOZE_REQUEST_IRQ14 = 0x00004000U, ///< Enable IRQ14 pin snooze request - LPM_SNOOZE_REQUEST_IRQ15 = 0x00008000U, ///< Enable IRQ15 pin snooze request - LPM_SNOOZE_REQUEST_KEY = 0x00020000U, ///< Enable KR snooze request - LPM_SNOOZE_REQUEST_ACMPHS0 = 0x00400000U, ///< Enable High-speed analog comparator 0 snooze request - LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000U, ///< Enable RTC alarm snooze request - LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000U, ///< Enable RTC period snooze request - LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000U, ///< Enable AGT1 underflow snooze request - LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000U, ///< Enable AGT1 compare match A snooze request - LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000U, ///< Enable AGT1 compare match B snooze request + LPM_SNOOZE_REQUEST_RXD0_FALLING = 0x00000000ULL, ///< Enable RXD0 falling edge snooze request + LPM_SNOOZE_REQUEST_IRQ0 = 0x00000001ULL, ///< Enable IRQ0 pin snooze request + LPM_SNOOZE_REQUEST_IRQ1 = 0x00000002ULL, ///< Enable IRQ1 pin snooze request + LPM_SNOOZE_REQUEST_IRQ2 = 0x00000004ULL, ///< Enable IRQ2 pin snooze request + LPM_SNOOZE_REQUEST_IRQ3 = 0x00000008ULL, ///< Enable IRQ3 pin snooze request + LPM_SNOOZE_REQUEST_IRQ4 = 0x00000010ULL, ///< Enable IRQ4 pin snooze request + LPM_SNOOZE_REQUEST_IRQ5 = 0x00000020ULL, ///< Enable IRQ5 pin snooze request + LPM_SNOOZE_REQUEST_IRQ6 = 0x00000040ULL, ///< Enable IRQ6 pin snooze request + LPM_SNOOZE_REQUEST_IRQ7 = 0x00000080ULL, ///< Enable IRQ7 pin snooze request + LPM_SNOOZE_REQUEST_IRQ8 = 0x00000100ULL, ///< Enable IRQ8 pin snooze request + LPM_SNOOZE_REQUEST_IRQ9 = 0x00000200ULL, ///< Enable IRQ9 pin snooze request + LPM_SNOOZE_REQUEST_IRQ10 = 0x00000400ULL, ///< Enable IRQ10 pin snooze request + LPM_SNOOZE_REQUEST_IRQ11 = 0x00000800ULL, ///< Enable IRQ11 pin snooze request + LPM_SNOOZE_REQUEST_IRQ12 = 0x00001000ULL, ///< Enable IRQ12 pin snooze request + LPM_SNOOZE_REQUEST_IRQ13 = 0x00002000ULL, ///< Enable IRQ13 pin snooze request + LPM_SNOOZE_REQUEST_IRQ14 = 0x00004000ULL, ///< Enable IRQ14 pin snooze request + LPM_SNOOZE_REQUEST_IRQ15 = 0x00008000ULL, ///< Enable IRQ15 pin snooze request + LPM_SNOOZE_REQUEST_KEY = 0x00020000ULL, ///< Enable KR snooze request + LPM_SNOOZE_REQUEST_ACMPHS0 = 0x00400000ULL, ///< Enable High-speed analog comparator 0 snooze request + LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000ULL, ///< Enable RTC alarm snooze request + LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000ULL, ///< Enable RTC period snooze request + LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000ULL, ///< Enable AGT1 underflow snooze request + LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000ULL, ///< Enable AGT1 compare match A snooze request + LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000ULL, ///< Enable AGT1 compare match B snooze request + LPM_SNOOZE_REQUEST_AGT3_UNDERFLOW = 0x100000000ULL, ///< Enable AGT3 underflow snooze request + LPM_SNOOZE_REQUEST_AGT3_COMPARE_A = 0x200000000ULL, ///< Enable AGT3 compare match A snooze request + LPM_SNOOZE_REQUEST_AGT3_COMPARE_B = 0x400000000ULL, ///< Enable AGT3 compare match B snooze request } lpm_snooze_request_t; /** Snooze end control */ typedef enum e_lpm_snooze_end { - LPM_SNOOZE_END_STANDBY_WAKE_SOURCES = 0x00U, ///< Transition from Snooze to Normal mode directly - LPM_SNOOZE_END_AGT1_UNDERFLOW = 0x01U, ///< AGT1 underflow - LPM_SNOOZE_END_DTC_TRANS_COMPLETE = 0x02U, ///< Last DTC transmission completion - LPM_SNOOZE_END_DTC_TRANS_COMPLETE_NEGATED = 0x04U, ///< Not Last DTC transmission completion - LPM_SNOOZE_END_ADC0_COMPARE_MATCH = 0x08U, ///< ADC Channel 0 compare match - LPM_SNOOZE_END_ADC0_COMPARE_MISMATCH = 0x10U, ///< ADC Channel 0 compare mismatch - LPM_SNOOZE_END_ADC1_COMPARE_MATCH = 0x20U, ///< ADC 1 compare match - LPM_SNOOZE_END_ADC1_COMPARE_MISMATCH = 0x40U, ///< ADC 1 compare mismatch - LPM_SNOOZE_END_SCI0_ADDRESS_MATCH = 0x80U, ///< SCI0 address mismatch + LPM_SNOOZE_END_STANDBY_WAKE_SOURCES = 0x00U, ///< Transition from Snooze to Normal mode directly + LPM_SNOOZE_END_AGT1_UNDERFLOW = 0x01U, ///< AGT1 underflow + LPM_SNOOZE_END_DTC_TRANS_COMPLETE = 0x02U, ///< Last DTC transmission completion + LPM_SNOOZE_END_DTC_TRANS_COMPLETE_NEGATED = 0x04U, ///< Not Last DTC transmission completion + LPM_SNOOZE_END_ADC0_COMPARE_MATCH = 0x08U, ///< ADC Channel 0 compare match + LPM_SNOOZE_END_ADC0_COMPARE_MISMATCH = 0x10U, ///< ADC Channel 0 compare mismatch + LPM_SNOOZE_END_ADC1_COMPARE_MATCH = 0x20U, ///< ADC 1 compare match + LPM_SNOOZE_END_ADC1_COMPARE_MISMATCH = 0x40U, ///< ADC 1 compare mismatch + LPM_SNOOZE_END_SCI0_ADDRESS_MATCH = 0x80U, ///< SCI0 address mismatch + LPM_SNOOZE_END_AGT3_UNDERFLOW = 0x100U, ///< AGT3 underflow } lpm_snooze_end_t; -typedef uint8_t lpm_snooze_end_bits_t; +typedef uint16_t lpm_snooze_end_bits_t; /** Snooze cancel control */ typedef enum e_lpm_snooze_cancel @@ -140,40 +144,43 @@ typedef enum e_lpm_snooze_dtc /** Wake from standby mode sources, does not apply to sleep or deep standby modes */ typedef enum e_lpm_standby_wake_source { - LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001U, ///< IRQ0 - LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002U, ///< IRQ1 - LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004U, ///< IRQ2 - LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008U, ///< IRQ3 - LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010U, ///< IRQ4 - LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020U, ///< IRQ5 - LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040U, ///< IRQ6 - LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080U, ///< IRQ7 - LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100U, ///< IRQ8 - LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200U, ///< IRQ9 - LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400U, ///< IRQ10 - LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800U, ///< IRQ11 - LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000U, ///< IRQ12 - LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000U, ///< IRQ13 - LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000U, ///< IRQ14 - LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000U, ///< IRQ15 - LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000U, ///< Independent watchdog interrupt - LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000U, ///< Key interrupt - LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000U, ///< Low Voltage Detection 1 interrupt - LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000U, ///< Low Voltage Detection 2 interrupt - LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000U, ///< VBATT Monitor interrupt - LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000U, ///< Analog Comparator High-speed 0 interrupt - LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000U, ///< Analog Comparator Low-speed 0 interrupt - LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000U, ///< RTC Alarm interrupt - LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000U, ///< RTC Period interrupt - LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000U, ///< USB High-speed interrupt - LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000U, ///< USB Full-speed interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000U, ///< AGT1 underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000U, ///< AGT1 compare match A interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000U, ///< AGT1 compare match B interrupt - LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000U, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 compare match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 compare match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 compare match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 compare match B interrupt } lpm_standby_wake_source_t; -typedef uint32_t lpm_standby_wake_source_bits_t; +typedef uint64_t lpm_standby_wake_source_bits_t; /** I/O port state after Deep Software Standby mode */ typedef enum e_lpm_io_port @@ -248,6 +255,8 @@ typedef enum e_lpm_deep_standby_cancel_edge LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_FALLING = 0U, ///< IRQ13-DS Pin Falling Edge LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_RISING = 0x00004000U, ///< IRQ14-DS Pin Rising Edge LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_FALLING = 0U, ///< IRQ14-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_RISING = 0x00008000U, ///< IRQ14-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_FALLING = 0U, ///< IRQ14-DS Pin Falling Edge LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_RISING = 0x00010000U, ///< LVD1 Rising Slope LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_FALLING = 0U, ///< LVD1 Falling Slope @@ -280,6 +289,7 @@ typedef enum e_lpm_deep_standby_cancel_source LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12 = 0x00001000U, ///< IRQ12 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13 = 0x00002000U, ///< IRQ13 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14 = 0x00004000U, ///< IRQ14 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15 = 0x00008000U, ///< IRQ15 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1 = 0x00010000U, ///< LVD1 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2 = 0x00020000U, ///< LVD2 diff --git a/ra/fsp/inc/api/r_lvd_api.h b/ra/fsp/inc/api/r_lvd_api.h index a2df03353..4ea830ed1 100644 --- a/ra/fsp/inc/api/r_lvd_api.h +++ b/ra/fsp/inc/api/r_lvd_api.h @@ -244,6 +244,20 @@ typedef struct st_lvd_api **/ fsp_err_t (* statusClear)(lvd_ctrl_t * const p_ctrl); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_LVD_CallbackSet() + * + * @param[in] p_ctrl Pointer to the LVD control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(lvd_ctrl_t * const p_api_ctrl, void (* p_callback)(lvd_callback_args_t *), + void const * const p_context, lvd_callback_args_t * const p_callback_memory); + /** Disables the LVD peripheral. * Closes the driver instance. * @par Implemented as diff --git a/ra/fsp/inc/api/r_poeg_api.h b/ra/fsp/inc/api/r_poeg_api.h index a2ccad36c..6b7ba5cd8 100644 --- a/ra/fsp/inc/api/r_poeg_api.h +++ b/ra/fsp/inc/api/r_poeg_api.h @@ -163,6 +163,19 @@ typedef struct st_poeg_api */ fsp_err_t (* statusGet)(poeg_ctrl_t * const p_ctrl, poeg_status_t * p_status); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_POEG_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref poeg_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(poeg_ctrl_t * const p_api_ctrl, void (* p_callback)(poeg_callback_args_t *), + void const * const p_context, poeg_callback_args_t * const p_callback_memory); + /** Disables GPT output pins by software request. * @par Implemented as * - @ref R_POEG_OutputDisable() diff --git a/ra/fsp/inc/api/r_rtc_api.h b/ra/fsp/inc/api/r_rtc_api.h index 7feef6836..e4f9a1a57 100644 --- a/ra/fsp/inc/api/r_rtc_api.h +++ b/ra/fsp/inc/api/r_rtc_api.h @@ -258,6 +258,19 @@ typedef struct st_rtc_api */ fsp_err_t (* errorAdjustmentSet)(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_RTC_CallbackSet() + * + * @param[in] p_ctrl Pointer to the RTC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated + */ + fsp_err_t (* callbackSet)(rtc_ctrl_t * const p_ctrl, void (* p_callback)(rtc_callback_args_t *), + void const * const p_context, rtc_callback_args_t * const p_callback_memory); + /** Return the currently configure clock source for the RTC * * @par Implemented as diff --git a/ra/fsp/inc/api/r_sdmmc_api.h b/ra/fsp/inc/api/r_sdmmc_api.h index a5ad00996..c953f8f84 100644 --- a/ra/fsp/inc/api/r_sdmmc_api.h +++ b/ra/fsp/inc/api/r_sdmmc_api.h @@ -468,6 +468,19 @@ typedef struct st_sdmmc_api */ fsp_err_t (* erase)(sdmmc_ctrl_t * const p_ctrl, uint32_t const start_sector, uint32_t const sector_count); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_SDHI_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref sdmmc_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(sdmmc_ctrl_t * const p_api_ctrl, void (* p_callback)(sdmmc_callback_args_t *), + void const * const p_context, sdmmc_callback_args_t * const p_callback_memory); + /** Close open SD/MMC device. * * @par Implemented as diff --git a/ra/fsp/inc/api/r_spi_api.h b/ra/fsp/inc/api/r_spi_api.h index 6083eaa20..acca1d447 100644 --- a/ra/fsp/inc/api/r_spi_api.h +++ b/ra/fsp/inc/api/r_spi_api.h @@ -124,6 +124,15 @@ typedef struct st_spi_callback_args void const * p_context; ///< Context provided to user during callback } spi_callback_args_t; +/** Non-secure arguments for write-read guard function */ +typedef struct st_spi_write_read_guard_args +{ + void const * p_src; + void * p_dest; + uint32_t const length; + spi_bit_width_t const bit_width; +} spi_write_read_guard_args_t; + /** SPI interface configuration */ typedef struct st_spi_cfg { @@ -217,6 +226,20 @@ typedef struct st_spi_api fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length, spi_bit_width_t const bit_width); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_SCI_SPI_CallbackSet() + * + * @param[in] p_ctrl Pointer to the SPI control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *), + void const * const p_context, spi_callback_args_t * const p_callback_memory); + /** Remove power to the SPI channel designated by the handle and disable the associated interrupts. * @par Implemented as * - @ref R_SPI_Close() diff --git a/ra/fsp/inc/api/r_spi_flash_api.h b/ra/fsp/inc/api/r_spi_flash_api.h index 571f70975..931676d92 100644 --- a/ra/fsp/inc/api/r_spi_flash_api.h +++ b/ra/fsp/inc/api/r_spi_flash_api.h @@ -26,6 +26,9 @@ * @section SPI_FLASH_API_SUMMARY Summary * The SPI flash API provides an interface that configures, writes, and erases sectors in SPI flash devices. * + * Implemented by: + * - @ref OSPI + * - @ref QSPI * @{ **********************************************************************************************************************/ @@ -72,6 +75,12 @@ typedef enum e_spi_flash_protocol /** QPI mode (commands on 4 lines). Note that the application must ensure the device is in QPI mode. */ SPI_FLASH_PROTOCOL_QPI = 2, + + /** SOPI mode (command and data on 8 lines). Note that the application must ensure the device is in SOPI mode. */ + SPI_FLASH_PROTOCOL_SOPI = 3, + + /** DOPI mode (command and data on 8 lines, dual data rate). Note that the application must ensure the device is in DOPI mode. */ + SPI_FLASH_PROTOCOL_DOPI = 4, } spi_flash_protocol_t; /** Number of bytes in the address. */ @@ -118,13 +127,31 @@ typedef enum e_spi_flash_dummy_clocks SPI_FLASH_DUMMY_CLOCKS_17, ///< 17 dummy clocks } spi_flash_dummy_clocks_t; +/** Direct Read and Write direction */ +typedef enum e_spi_flash_direct_transfer_dir_option +{ + SPI_FLASH_DIRECT_TRANSFER_DIR_READ = 0x0, + SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE = 0x1 +} spi_flash_direct_transfer_dir_t; + /** Structure to define an erase command and associated erase size. */ typedef struct st_spi_flash_erase_command { - uint8_t command; ///< Erase command + uint16_t command; ///< Erase command uint32_t size; ///< Size of erase for associated command, set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE for chip erase } spi_flash_erase_command_t; +typedef struct st_spi_flash_direct_transfer +{ + uint32_t address; + uint32_t data; + uint16_t command; + uint8_t dummy_cycles; + uint8_t command_length; + uint8_t address_length; + uint8_t data_length; +} spi_flash_direct_transfer_t; + /** User configuration structure used by the open function */ typedef struct st_spi_flash_cfg { @@ -136,11 +163,13 @@ typedef struct st_spi_flash_cfg /** Number of lines used to send address for page program command. This should either be 1 or match the number of lines used in * the selected read mode. */ spi_flash_data_lines_t page_program_address_lines; + uint8_t write_status_bit; ///< Which bit determines write status + uint8_t write_enable_bit; ///< Which bit determines write status uint32_t page_size_bytes; ///< Page size in bytes (maximum number of bytes for page program) uint8_t page_program_command; ///< Page program command uint8_t write_enable_command; ///< Command to enable write or erase, typically 0x06 uint8_t status_command; ///< Command to read the write status - uint8_t write_status_bit; ///< Which bit determines write status + uint8_t read_command; ///< Read command - OSPI SPI mode only uint8_t xip_enter_command; ///< Command to enter XIP mode uint8_t xip_exit_command; ///< Command to exit XIP mode uint8_t erase_command_list_length; ///< Length of erase command list @@ -199,6 +228,17 @@ typedef struct st_spi_flash_api **/ fsp_err_t (* directRead)(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + /** Direct Read/Write raw data to the SPI flash. + * @par Implemented as + * - @ref R_OSPI_DirectTransfer() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_data Pointer to command, address and data values and lengths + * @param[in] direction Direct Read/Write + **/ + fsp_err_t (* directTransfer)(spi_flash_ctrl_t * p_ctrl, spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); + /** Change the SPI protocol in the driver. The application must change the SPI protocol on the device. * @par Implemented as * - @ref R_QSPI_SpiProtocolSet() diff --git a/ra/fsp/inc/api/r_three_phase_api.h b/ra/fsp/inc/api/r_three_phase_api.h index 10a72d5a9..75ad003a4 100644 --- a/ra/fsp/inc/api/r_three_phase_api.h +++ b/ra/fsp/inc/api/r_three_phase_api.h @@ -94,6 +94,7 @@ typedef struct st_three_phase_cfg /* Pointers to GPT instance structs */ timer_instance_t const * p_timer_instance[3]; ///< Pointer to the timer instance structs + three_phase_channel_t callback_ch; ///< Channel to enable callback when using three_phase_api_t::callbackSet uint32_t channel_mask; ///< Bitmask of timer channels used by this module @@ -149,6 +150,19 @@ typedef struct st_three_phase_api */ fsp_err_t (* dutyCycleSet)(three_phase_ctrl_t * const p_ctrl, three_phase_duty_cycle_t * const p_duty_cycle); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_GPT_THREE_PHASE_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref three_phase_api_t::open call. + * @param[in] p_callback Callback function to register with GPT U-channel + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(three_phase_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *), + void const * const p_context, timer_callback_args_t * const p_callback_memory); + /** Allows driver to be reconfigured and may reduce power consumption. * @par Implemented as * - @ref R_GPT_THREE_PHASE_Close() diff --git a/ra/fsp/inc/api/r_timer_api.h b/ra/fsp/inc/api/r_timer_api.h index 570336621..76ef0e2b9 100644 --- a/ra/fsp/inc/api/r_timer_api.h +++ b/ra/fsp/inc/api/r_timer_api.h @@ -284,6 +284,20 @@ typedef struct st_timer_api */ fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_GPT_CallbackSet() + * - @ref R_AGT_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(timer_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *), + void const * const p_context, timer_callback_args_t * const p_callback_memory); + /** Allows driver to be reconfigured and may reduce power consumption. * @par Implemented as * - @ref R_GPT_Close() diff --git a/ra/fsp/inc/api/r_uart_api.h b/ra/fsp/inc/api/r_uart_api.h index 6d4e7e7bf..6fff23076 100644 --- a/ra/fsp/inc/api/r_uart_api.h +++ b/ra/fsp/inc/api/r_uart_api.h @@ -237,6 +237,20 @@ typedef struct st_uart_api */ fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_SCI_Uart_CallbackSet() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *), + void const * const p_context, uart_callback_args_t * const p_callback_memory); + /** Close UART device. * @par Implemented as * - @ref R_SCI_UART_Close() diff --git a/ra/fsp/inc/api/r_usb_hhid_api.h b/ra/fsp/inc/api/r_usb_hhid_api.h index a2c407506..0ed4ed624 100644 --- a/ra/fsp/inc/api/r_usb_hhid_api.h +++ b/ra/fsp/inc/api/r_usb_hhid_api.h @@ -39,6 +39,7 @@ * Includes , "Project Includes" ******************************************************************************/ #include "r_usb_hhid_cfg.h" +#include "r_usb_basic_api.h" /****************************************************************************** * Macro definitions @@ -98,6 +99,14 @@ typedef struct st_usb_hhid_api fsp_err_t (* maxPacketSizeGet)(usb_ctrl_t * const p_api_ctrl, uint16_t * p_size, uint8_t direction, uint8_t device_address); } usb_hhid_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_usb_hhid_instance +{ + usb_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + usb_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + usb_hhid_api_t const * p_api; ///< Pointer to the API structure for this instance +} usb_hhid_instance_t; #endif /* USB_HHID_API_H */ /*******************************************************************************************************************//** diff --git a/ra/fsp/inc/api/r_wdt_api.h b/ra/fsp/inc/api/r_wdt_api.h index 1152d4f1c..cf698348d 100644 --- a/ra/fsp/inc/api/r_wdt_api.h +++ b/ra/fsp/inc/api/r_wdt_api.h @@ -223,6 +223,19 @@ typedef struct st_wdt_api */ fsp_err_t (* timeoutGet)(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_WDT_CallbackSet() + * + * @param[in] p_ctrl Pointer to the WDT control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(wdt_ctrl_t * const p_api_ctrl, void (* p_callback)(wdt_callback_args_t *), + void const * const p_context, wdt_callback_args_t * const p_callback_memory); + /** Return the version of the driver. * @par Implemented as * - @ref R_WDT_VersionGet() diff --git a/ra/fsp/inc/api/rm_block_media_api.h b/ra/fsp/inc/api/rm_block_media_api.h index 3c3fa9600..70b334abb 100644 --- a/ra/fsp/inc/api/rm_block_media_api.h +++ b/ra/fsp/inc/api/rm_block_media_api.h @@ -75,6 +75,7 @@ typedef struct st_rm_block_media_info uint32_t sector_size_bytes; ///< Sector size in bytes uint32_t num_sectors; ///< Total number of sectors bool reentrant; ///< True if connected block media driver is reentrant + bool write_protected; ///< True if connected block media device is write protected } rm_block_media_info_t; /** Callback function parameter data */ @@ -170,6 +171,21 @@ typedef struct st_rm_block_media_api */ fsp_err_t (* erase)(rm_block_media_ctrl_t * const p_ctrl, uint32_t const block_address, uint32_t const num_blocks); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref RM_BLOCK_MEDIA_SDMMC_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref rm_block_media_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)(rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory); + /** Get status of connected device. * * @par Implemented as diff --git a/ra/fsp/inc/api/rm_touch_api.h b/ra/fsp/inc/api/rm_touch_api.h index a81f94c09..46fa554c6 100644 --- a/ra/fsp/inc/api/rm_touch_api.h +++ b/ra/fsp/inc/api/rm_touch_api.h @@ -87,6 +87,19 @@ typedef struct st_touch_wheel_cfg_t uint16_t threshold; ///< Position calculation start threshold value. } touch_wheel_cfg_t; +/** Configuration of each pads */ +typedef struct st_touch_pad_cfg_t +{ + uint8_t const * p_elem_index_rx; ///< RX of element number arrays used by this pad. + uint8_t const * p_elem_index_tx; ///< TX of element number arrays used by this pad. + uint8_t num_elements; ///< Number of elements used by this pad. + uint16_t threshold; ///< Coordinate calculation threshold value. + uint16_t rx_pixel; ///< rx coordinate resolution + uint16_t tx_pixel; ///< tx coordinate resolution + uint8_t max_touch; ///< Maximum number of touch judgments used by the pad. + uint8_t num_drift; ///< Number of pad drift. +} touch_pad_cfg_t; + /** Callback function parameter data */ typedef struct st_ctsu_callback_args touch_callback_args_t; @@ -96,6 +109,7 @@ typedef struct st_touch_cfg touch_button_cfg_t const * p_buttons; ///< Pointer to array of button configuration. touch_slider_cfg_t const * p_sliders; ///< Pointer to array of slider configuration. touch_wheel_cfg_t const * p_wheels; ///< Pointer to array of wheel configuration. + touch_pad_cfg_t const * p_pad; ///< Pointer of pad configuration. uint8_t num_buttons; ///< Number of buttons. uint8_t num_sliders; ///< Number of sliders. uint8_t num_wheels; ///< Number of wheels. @@ -135,13 +149,38 @@ typedef struct st_touch_api * - @ref RM_TOUCH_DataGet() * * @param[in] p_ctrl Pointer to control structure. - * @param[out] p_buton_status Pointer to get data bitmap. + * @param[out] p_button_status Pointer to get data bitmap. * @param[out] p_slider_position Pointer to get data array. * @param[out] p_wheel_position Pointer to get data array. */ fsp_err_t (* dataGet)(touch_ctrl_t * const p_ctrl, uint64_t * p_button_status, uint16_t * p_slider_position, uint16_t * p_wheel_position); + /** pad data get. + * @par Implemented as + * - @ref RM_TOUCH_PadDataGet() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_pad_rx_coordinate Pointer to get coordinate of receiver side. + * @param[out] p_pad_tx_coordinate Pointer to get coordinate of transmitter side. + * @param[out] p_pad_num_touch Pointer to get touch count. + */ + fsp_err_t (* padDataGet)(touch_ctrl_t * const p_ctrl, uint16_t * p_pad_rx_coordinate, + uint16_t * p_pad_tx_coordinate, uint8_t * p_pad_num_touch); + + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref RM_TOUCH_CallbackSet() + * + * @param[in] p_ctrl Pointer to the CTSU control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(touch_ctrl_t * const p_api_ctrl, void (* p_callback)(touch_callback_args_t *), + void const * const p_context, touch_callback_args_t * const p_callback_memory); + /** Close driver. * @par Implemented as * - @ref RM_TOUCH_Close() diff --git a/ra/fsp/inc/api/rm_vee_api.h b/ra/fsp/inc/api/rm_vee_api.h index 01613318d..46734320a 100644 --- a/ra/fsp/inc/api/rm_vee_api.h +++ b/ra/fsp/inc/api/rm_vee_api.h @@ -180,6 +180,19 @@ typedef struct st_rm_vee_api */ fsp_err_t (* format)(rm_vee_ctrl_t * const p_ctrl, uint8_t const * const p_ref_data); + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref RM_VEE_FLASH_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref rm_vee_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(rm_vee_ctrl_t * const p_api_ctrl, void (* p_callback)(rm_vee_callback_args_t *), + void const * const p_context, rm_vee_callback_args_t * const p_callback_memory); + /** Closes the module and lower level storage device. * @par Implemented as * - @ref RM_VEE_FLASH_Close diff --git a/ra/fsp/inc/fsp_common_api.h b/ra/fsp/inc/fsp_common_api.h index c4d566e82..52fd68ba7 100644 --- a/ra/fsp/inc/fsp_common_api.h +++ b/ra/fsp/inc/fsp_common_api.h @@ -58,8 +58,12 @@ #endif /** FSP Header and Footer definitions */ -#define FSP_HEADER FSP_CPP_HEADER -#define FSP_FOOTER FSP_CPP_FOOTER +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) /********************************************************************************************************************** * Typedef definitions @@ -103,6 +107,7 @@ typedef enum e_fsp_err FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback /* Start of RTOS only error codes */ FSP_ERR_INTERNAL = 100, ///< Internal error @@ -303,6 +308,8 @@ typedef enum e_fsp_err FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, /* Start of SF_CRYPTO specific */ FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened diff --git a/ra/fsp/inc/fsp_features.h b/ra/fsp/inc/fsp_features.h index c9a791823..9f6af3eef 100644 --- a/ra/fsp/inc/fsp_features.h +++ b/ra/fsp/inc/fsp_features.h @@ -113,6 +113,7 @@ typedef enum e_fsp_ip FSP_IP_JPEG = 69, ///< JPEG FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter FSP_IP_USBHS = 71, ///< USB High Speed + FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface } fsp_ip_t; /** Signals that can be mapped to an interrupt. */ diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index a75d71e49..1e1ea659e 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -38,22 +38,22 @@ **********************************************************************************************************************/ /** FSP pack major version. */ -#define FSP_VERSION_MAJOR (1U) +#define FSP_VERSION_MAJOR (2U) /** FSP pack minor version. */ -#define FSP_VERSION_MINOR (3U) +#define FSP_VERSION_MINOR (0U) /** FSP pack patch version. */ -#define FSP_VERSION_PATCH (1U) +#define FSP_VERSION_PATCH (0U) /** FSP pack version build number (currently unused). */ #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ -#define FSP_VERSION_STRING ("1.3.1") +#define FSP_VERSION_STRING ("2.0.0") /** Unique FSP version ID. */ -#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 1.3.1") +#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 2.0.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_adc.h b/ra/fsp/inc/instances/r_adc.h index 192b330a7..63ee7619c 100644 --- a/ra/fsp/inc/instances/r_adc.h +++ b/ra/fsp/inc/instances/r_adc.h @@ -215,11 +215,20 @@ typedef struct st_adc_channel_cfg /** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */ typedef struct { - R_ADC0_Type * p_reg; // Base register for this unit + R_ADC0_Type * p_reg; // Base register for this unit adc_cfg_t const * p_cfg; - uint32_t opened; // Boolean to verify that the Unit has been initialized - uint32_t scan_mask; // Scan mask used for Normal scan. + uint32_t opened; // Boolean to verify that the Unit has been initialized + uint32_t scan_mask; // Scan mask used for Normal scan. uint16_t scan_start_adcsr; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs. + adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; } adc_instance_ctrl_t; /********************************************************************************************************************** @@ -248,6 +257,10 @@ fsp_err_t R_ADC_Close(adc_ctrl_t * p_ctrl); fsp_err_t R_ADC_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset); fsp_err_t R_ADC_Calibrate(adc_ctrl_t * const p_ctrl, void * const p_extend); fsp_err_t R_ADC_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_ADC_CallbackSet(adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void const * const p_context, + adc_callback_args_t * const p_callback_memory); /*******************************************************************************************************************//** * @} (end defgroup ADC) diff --git a/ra/fsp/inc/instances/r_agt.h b/ra/fsp/inc/instances/r_agt.h index a57bc248a..09afed5a2 100644 --- a/ra/fsp/inc/instances/r_agt.h +++ b/ra/fsp/inc/instances/r_agt.h @@ -119,10 +119,17 @@ typedef enum e_agt_pin_cfg /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ typedef struct st_agt_instance_ctrl { - uint32_t open; ///< Whether or not channel is open - const timer_cfg_t * p_cfg; ///< Pointer to initial configurations - R_AGT0_Type * p_reg; ///< Base register for this channel - uint32_t period; ///< Current timer period (counts) + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + R_AGT0_Type * p_reg; // Base register for this channel + uint32_t period; // Current timer period (counts) + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. + timer_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void const * p_context; // Pointer to context to be passed into callback function } agt_instance_ctrl_t; /** Optional AGT extension data structure.*/ @@ -171,6 +178,10 @@ fsp_err_t R_AGT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info fsp_err_t R_AGT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); fsp_err_t R_AGT_Stop(timer_ctrl_t * const p_ctrl); fsp_err_t R_AGT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_AGT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory); fsp_err_t R_AGT_VersionGet(fsp_version_t * const p_version); /*******************************************************************************************************************//** diff --git a/ra/fsp/inc/instances/r_cac.h b/ra/fsp/inc/instances/r_cac.h index f4efcb272..591cd86fa 100644 --- a/ra/fsp/inc/instances/r_cac.h +++ b/ra/fsp/inc/instances/r_cac.h @@ -51,6 +51,17 @@ typedef struct st_cac_instance_ctrl { uint32_t open; // Set to "CAC" once API has been successfully opened. cac_cfg_t const * p_cfg; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(cac_callback_args_t *); + cac_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; } cac_instance_ctrl_t; /********************************************************************************************************************** @@ -73,6 +84,10 @@ fsp_err_t R_CAC_Read(cac_ctrl_t * const p_ctrl, uint16_t * const p_counter); fsp_err_t R_CAC_Reset(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_Close(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_CAC_CallbackSet(cac_ctrl_t * const p_ctrl, + void ( * p_callback)(cac_callback_args_t *), + void const * const p_context, + cac_callback_args_t * const p_callback_memory); /*******************************************************************************************************************//** * @} (end addtogroup CAC) diff --git a/ra/fsp/inc/instances/r_can.h b/ra/fsp/inc/instances/r_can.h index 5b9fe7b86..7b8fe8764 100644 --- a/ra/fsp/inc/instances/r_can.h +++ b/ra/fsp/inc/instances/r_can.h @@ -50,16 +50,23 @@ FSP_HEADER typedef struct st_can_instance_ctrl { /* Parameters to control CAN peripheral device */ - can_cfg_t const * p_cfg; // Pointer to the configuration structure - R_CAN0_Type * p_reg; // Pointer to register base address - uint32_t open; // Open status of channel. - can_operation_mode_t operation_mode; // Can operation mode. - can_test_mode_t test_mode; // Can operation mode. - can_id_mode_t id_mode; // Standard or Extended ID mode. - uint32_t mailbox_count; // Number of mailboxes. - can_mailbox_t * p_mailbox; // Pointer to mailboxes. - can_message_mode_t message_mode; // Overwrite message or overrun. - can_clock_source_t clock_source; // Clock source. CANMCLK or PCLKB. + can_cfg_t const * p_cfg; // Pointer to the configuration structure + R_CAN0_Type * p_reg; // Pointer to register base address + uint32_t open; // Open status of channel. + can_operation_mode_t operation_mode; // Can operation mode. + can_test_mode_t test_mode; // Can operation mode. + can_id_mode_t id_mode; // Standard or Extended ID mode. + uint32_t mailbox_count; // Number of mailboxes. + can_mailbox_t * p_mailbox; // Pointer to mailboxes. + can_message_mode_t message_mode; // Overwrite message or overrun. + can_clock_source_t clock_source; // Clock source. CANMCLK or PCLKB. + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(can_callback_args_t *); // Pointer to callback + can_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } can_instance_ctrl_t; /* CAN clock configuration and mailbox mask to be pointed to by p_extend. */ @@ -89,6 +96,10 @@ fsp_err_t R_CAN_ModeTransition(can_ctrl_t * const p_api_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode); fsp_err_t R_CAN_InfoGet(can_ctrl_t * const p_api_ctrl, can_info_t * const p_info); +fsp_err_t R_CAN_CallbackSet(can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void const * const p_context, + can_callback_args_t * const p_callback_memory); fsp_err_t R_CAN_VersionGet(fsp_version_t * const version); /*******************************************************************************************************************//** diff --git a/ra/fsp/inc/instances/r_cgc.h b/ra/fsp/inc/instances/r_cgc.h index 79a99f356..8230d8915 100644 --- a/ra/fsp/inc/instances/r_cgc.h +++ b/ra/fsp/inc/instances/r_cgc.h @@ -49,9 +49,16 @@ FSP_HEADER /** CGC private control block. DO NOT MODIFY. Initialization occurs when R_CGC_Open() is called. */ typedef struct st_cgc_instance_ctrl { - uint32_t open; + uint32_t open; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + cgc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void (* p_callback)(cgc_callback_args_t * p_args); // Pointer to callback that is called when a cgc_event_t occurs. + + /** Placeholder for user data. Passed to the user callback in ::cgc_callback_args_t. */ void const * p_context; - void (* p_callback)(cgc_callback_args_t * p_args); } cgc_instance_ctrl_t; /********************************************************************************************************************** @@ -81,6 +88,10 @@ fsp_err_t R_CGC_SystemClockGet(cgc_ctrl_t * const p_ctrl, fsp_err_t R_CGC_OscStopDetectEnable(cgc_ctrl_t * const p_ctrl); fsp_err_t R_CGC_OscStopDetectDisable(cgc_ctrl_t * const p_ctrl); fsp_err_t R_CGC_OscStopStatusClear(cgc_ctrl_t * const p_ctrl); +fsp_err_t R_CGC_CallbackSet(cgc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(cgc_callback_args_t *), + void const * const p_context, + cgc_callback_args_t * const p_callback_memory); fsp_err_t R_CGC_Close(cgc_ctrl_t * const p_ctrl); fsp_err_t R_CGC_VersionGet(fsp_version_t * version); diff --git a/ra/fsp/inc/instances/r_ctsu.h b/ra/fsp/inc/instances/r_ctsu.h index 2ffeeb98a..ca14b391b 100644 --- a/ra/fsp/inc/instances/r_ctsu.h +++ b/ra/fsp/inc/instances/r_ctsu.h @@ -130,9 +130,13 @@ typedef struct st_ctsu_correction_info volatile ctsu_self_buf_t scanbuf; ///< Correction scan buffer #if (BSP_FEATURE_CTSU_VERSION == 2) #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + uint16_t tscap_voltage; ///< TSCAP Voltage by ADC + #endif uint16_t scan_index; ///< Scan point index uint16_t update_counter; ///< Coefficient update counter uint16_t ex_base_value; ///< Value of external registance measurement + uint8_t suadj0; ///< Stored SUADJ0 value #endif uint16_t base_value[CTSU_RANGE_NUM]; ///< Value of internal registance measurement uint16_t error_rate[CTSU_RANGE_NUM]; ///< Error rate of base vs DAC @@ -171,39 +175,43 @@ typedef struct st_ctsu_corrcfc_info /** CTSU private control block. DO NOT MODIFY. Initialization occurs when R_CTSU_Open() is called. */ typedef struct st_ctsu_instance_ctrl { - uint32_t open; ///< Whether or not driver is open. - ctsu_state_t state; ///< CTSU run state. - ctsu_tuning_t tuning; ///< CTSU Initial offset tuning status. - uint16_t num_elements; ///< Number of elements to scan - uint16_t wr_index; ///< Word index into ctsuwr register array. - uint16_t rd_index; ///< Word index into scan data buffer. - uint8_t * p_tuning_complete; ///< Pointer to tuning completion flag of each element. g_ctsu_tuning_complete[] is set by Open API. - int32_t * p_tuning_diff; ///< Pointer to difference from base value of each element. g_ctsu_tuning_diff[] is set by Open API. - uint16_t average; ///< CTSU Moving average counter. - uint16_t num_moving_average; ///< Copy from config by Open API. - uint8_t ctsucr1; ///< Copy from (atune1 << 3, md << 6) by Open API. CLK, ATUNE0, CSW, and PON is set by HAL driver. - ctsu_ctsuwr_t * p_ctsuwr; ///< CTSUWR write register value. g_ctsu_ctsuwr[] is set by Open API. - ctsu_self_buf_t * p_self_raw; ///< Pointer to Self raw data. g_ctsu_self_raw[] is set by Open API. - uint16_t * p_self_work; ///< Pointer to Self work buffer. g_ctsu_self_work[] is set by Open API. - uint16_t * p_self_data; ///< Pointer to Self moving average data. g_ctsu_self_data[] is set by Open API. - ctsu_mutual_buf_t * p_mutual_raw; ///< Pointer to Mutual raw data. g_ctsu_mutual_raw[] is set by Open API. - uint16_t * p_mutual_pri_work; ///< Pointer to Mutual primary work buffer. g_ctsu_mutual_pri_work[] is set by Open API. - uint16_t * p_mutual_snd_work; ///< Pointer to Mutual secondary work buffer. g_ctsu_mutual_snd_work[] is set by Open API. - uint16_t * p_mutual_pri_data; ///< Pointer to Mutual primary moving average data. g_ctsu_mutual_pri_data[] is set by Open API. - uint16_t * p_mutual_snd_data; ///< Pointer to Mutual secondary moving average data. g_ctsu_mutual_snd_data[] is set by Open API. - ctsu_correction_info_t * p_correction_info; ///< Pointer to correction info + uint32_t open; ///< Whether or not driver is open. + ctsu_state_t state; ///< CTSU run state. + ctsu_tuning_t tuning; ///< CTSU Initial offset tuning status. + uint16_t num_elements; ///< Number of elements to scan + uint16_t wr_index; ///< Word index into ctsuwr register array. + uint16_t rd_index; ///< Word index into scan data buffer. + uint8_t * p_tuning_count; ///< Pointer to tuning count of each element. g_ctsu_tuning_count[] is set by Open API. + int32_t * p_tuning_diff; ///< Pointer to difference from base value of each element. g_ctsu_tuning_diff[] is set by Open API. + uint16_t average; ///< CTSU Moving average counter. + uint16_t num_moving_average; ///< Copy from config by Open API. + uint8_t ctsucr1; ///< Copy from (atune1 << 3, md << 6) by Open API. CLK, ATUNE0, CSW, and PON is set by HAL driver. + ctsu_ctsuwr_t * p_ctsuwr; ///< CTSUWR write register value. g_ctsu_ctsuwr[] is set by Open API. + ctsu_self_buf_t * p_self_raw; ///< Pointer to Self raw data. g_ctsu_self_raw[] is set by Open API. + uint16_t * p_self_work; ///< Pointer to Self work buffer. g_ctsu_self_work[] is set by Open API. + uint16_t * p_self_data; ///< Pointer to Self moving average data. g_ctsu_self_data[] is set by Open API. + ctsu_mutual_buf_t * p_mutual_raw; ///< Pointer to Mutual raw data. g_ctsu_mutual_raw[] is set by Open API. + uint16_t * p_mutual_pri_work; ///< Pointer to Mutual primary work buffer. g_ctsu_mutual_pri_work[] is set by Open API. + uint16_t * p_mutual_snd_work; ///< Pointer to Mutual secondary work buffer. g_ctsu_mutual_snd_work[] is set by Open API. + uint16_t * p_mutual_pri_data; ///< Pointer to Mutual primary moving average data. g_ctsu_mutual_pri_data[] is set by Open API. + uint16_t * p_mutual_snd_data; ///< Pointer to Mutual secondary moving average data. g_ctsu_mutual_snd_data[] is set by Open API. + ctsu_correction_info_t * p_correction_info; ///< Pointer to correction info #if (BSP_FEATURE_CTSU_VERSION == 2) - ctsu_range_t range; ///< According to atune12. (20uA : 0, 40uA : 1, 80uA : 2, 160uA : 3) - uint8_t ctsucr2; ///< Copy from (posel, atune1, md) by Open API. FCMODE and SDPSEL and LOAD is set by HAL driver. - uint64_t cfc_rx_bitmap; ///< Bitmap of CFC receive terminal. - ctsu_corrcfc_info_t * p_corrcfc_info; ///< pointer to CFC correction info + ctsu_range_t range; ///< According to atune12. (20uA : 0, 40uA : 1, 80uA : 2, 160uA : 3) + uint8_t ctsucr2; ///< Copy from (posel, atune1, md) by Open API. FCMODE and SDPSEL and LOAD is set by HAL driver. + uint64_t cfc_rx_bitmap; ///< Bitmap of CFC receive terminal. + ctsu_corrcfc_info_t * p_corrcfc_info; ///< pointer to CFC correction info #endif - ctsu_cfg_t const * p_ctsu_cfg; ///< Pointer to initial configurations. - IRQn_Type write_irq; ///< Copy from config by Open API. CTSU_CTSUWR interrupt vector - IRQn_Type read_irq; ///< Copy from config by Open API. CTSU_CTSURD interrupt vector - IRQn_Type end_irq; ///< Copy from config by Open API. CTSU_CTSUFN interrupt vector - void const * p_context; ///< Placeholder for user data. - void (* p_callback)(ctsu_callback_args_t * p_args); ///< Callback provided when a CTSUFN occurs. + ctsu_cfg_t const * p_ctsu_cfg; ///< Pointer to initial configurations. + IRQn_Type write_irq; ///< Copy from config by Open API. CTSU_CTSUWR interrupt vector + IRQn_Type read_irq; ///< Copy from config by Open API. CTSU_CTSURD interrupt vector + IRQn_Type end_irq; ///< Copy from config by Open API. CTSU_CTSUFN interrupt vector +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; ///< If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(ctsu_callback_args_t *); ///< Callback provided when a CTSUFN occurs. + ctsu_callback_args_t * p_callback_memory; ///< Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void const * p_context; ///< Placeholder for user data. } ctsu_instance_ctrl_t; /********************************************************************************************************************** @@ -222,6 +230,10 @@ extern const ctsu_api_t g_ctsu_on_ctsu; fsp_err_t R_CTSU_Open(ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cfg); fsp_err_t R_CTSU_ScanStart(ctsu_ctrl_t * const p_ctrl); fsp_err_t R_CTSU_DataGet(ctsu_ctrl_t * const p_ctrl, uint16_t * p_data); +fsp_err_t R_CTSU_CallbackSet(ctsu_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ctsu_callback_args_t *), + void const * const p_context, + ctsu_callback_args_t * const p_callback_memory); fsp_err_t R_CTSU_Close(ctsu_ctrl_t * const p_ctrl); fsp_err_t R_CTSU_VersionGet(fsp_version_t * const p_version); diff --git a/ra/fsp/inc/instances/r_doc.h b/ra/fsp/inc/instances/r_doc.h index 0e1f8745d..36569dd0b 100644 --- a/ra/fsp/inc/instances/r_doc.h +++ b/ra/fsp/inc/instances/r_doc.h @@ -46,6 +46,15 @@ typedef struct st_doc_instance_ctrl { doc_cfg_t const * p_cfg; // Pointer to the configuration structure uint32_t open; ///< Used by driver to check if the control structure is valid + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(doc_callback_args_t *); + doc_callback_args_t * p_callback_memory; + void const * p_context; ///< User defined context passed into callback function } doc_instance_ctrl_t; /********************************************************************************************************************** @@ -66,6 +75,10 @@ fsp_err_t R_DOC_Close(doc_ctrl_t * const p_api_ctrl); fsp_err_t R_DOC_StatusGet(doc_ctrl_t * const p_api_ctrl, doc_status_t * p_status); fsp_err_t R_DOC_Write(doc_ctrl_t * const p_api_ctrl, uint16_t data); fsp_err_t R_DOC_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_DOC_CallbackSet(doc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(doc_callback_args_t *), + void const * const p_context, + doc_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_ether.h b/ra/fsp/inc/instances/r_ether.h index 7c9a83657..7cd088858 100644 --- a/ra/fsp/inc/instances/r_ether.h +++ b/ra/fsp/inc/instances/r_ether.h @@ -174,8 +174,6 @@ fsp_err_t R_ETHER_BufferRelease(ether_ctrl_t * const p_ctrl); fsp_err_t R_ETHER_Write(ether_ctrl_t * const p_ctrl, void * const p_buffer, uint32_t const frame_length); -fsp_err_t R_ETHER_LinkStatusCheck(ether_ctrl_t * const p_ctrl); - fsp_err_t R_ETHER_LinkProcess(ether_ctrl_t * const p_ctrl); fsp_err_t R_ETHER_WakeOnLANEnable(ether_ctrl_t * const p_ctrl); diff --git a/ra/fsp/inc/instances/r_flash_hp.h b/ra/fsp/inc/instances/r_flash_hp.h index 9185804bf..607d7952c 100644 --- a/ra/fsp/inc/instances/r_flash_hp.h +++ b/ra/fsp/inc/instances/r_flash_hp.h @@ -44,13 +44,6 @@ FSP_HEADER #define FLASH_HP_CODE_VERSION_MAJOR (1U) #define FLASH_HP_CODE_VERSION_MINOR (1U) -/* RA6M3, RA6M2 and RA6M1 MCUs uses RV40F Phase 2 Flash technology. */ -/* This macro will eventually be migrated to bsp_feature.h. */ -#if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M2) || defined(BSP_MCU_GROUP_RA6M1) || \ - defined(BSP_MCU_GROUP_RA6T1) - #define FLASH_HP_VERSION_PHASE_2 -#endif - /* If Code Flash programming is enabled, then all API functions must execute out of RAM. */ #if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) #if defined(__ICCARM__) @@ -81,8 +74,7 @@ typedef enum e_flash_bgo_operation /** Flash HP instance control block. DO NOT INITIALIZE. */ typedef struct st_flash_hp_instance_ctrl { - uint32_t opened; ///< To check whether api has been opened or not. - void (* p_callback)(flash_callback_args_t * p_args); /// User Callback function. + uint32_t opened; ///< To check whether api has been opened or not. flash_cfg_t const * p_cfg; uint32_t timeout_write_cf; uint32_t timeout_write_df; @@ -95,7 +87,13 @@ typedef struct st_flash_hp_instance_ctrl uint32_t source_start_address; uint32_t dest_end_address; uint32_t operations_remaining; - flash_bgo_operation_t current_operation; ///< Operation in progress, for example, FLASH_OPERATION_CF_ERASE + flash_bgo_operation_t current_operation; ///< Operation in progress, for example, FLASH_OPERATION_CF_ERASE +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(flash_callback_args_t *); // Pointer to callback + flash_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } flash_hp_instance_ctrl_t; /********************************************************************************************************************** @@ -142,6 +140,10 @@ fsp_err_t R_FLASH_HP_UpdateFlashClockFreq(flash_ctrl_t * const p_api_ctrl); fsp_err_t R_FLASH_HP_StartUpAreaSelect(flash_ctrl_t * const p_api_ctrl, flash_startup_area_swap_t swap_type, bool is_temporary); +fsp_err_t R_FLASH_HP_CallbackSet(flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void const * const p_context, + flash_callback_args_t * const p_callback_memory); fsp_err_t R_FLASH_HP_VersionGet(fsp_version_t * const p_version); fsp_err_t R_FLASH_HP_InfoGet(flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info); diff --git a/ra/fsp/inc/instances/r_flash_lp.h b/ra/fsp/inc/instances/r_flash_lp.h index d66a22db7..8a3a7b8f6 100644 --- a/ra/fsp/inc/instances/r_flash_lp.h +++ b/ra/fsp/inc/instances/r_flash_lp.h @@ -122,6 +122,10 @@ fsp_err_t R_FLASH_LP_Reset(flash_ctrl_t * const p_api_ctrl); fsp_err_t R_FLASH_LP_StartUpAreaSelect(flash_ctrl_t * const p_api_ctrl, flash_startup_area_swap_t swap_type, bool is_temporary); +fsp_err_t R_FLASH_LP_CallbackSet(flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void const * const p_context, + flash_callback_args_t * const p_callback_memory); fsp_err_t R_FLASH_LP_UpdateFlashClockFreq(flash_ctrl_t * const p_api_ctrl); fsp_err_t R_FLASH_LP_VersionGet(fsp_version_t * const p_version); fsp_err_t R_FLASH_LP_InfoGet(flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info); diff --git a/ra/fsp/inc/instances/r_gpt.h b/ra/fsp/inc/instances/r_gpt.h index 0348d328d..3dd3b5bd3 100644 --- a/ra/fsp/inc/instances/r_gpt.h +++ b/ra/fsp/inc/instances/r_gpt.h @@ -60,14 +60,11 @@ typedef enum e_gpt_pin_level GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high } gpt_pin_level_t; -/** GPT PWM shortest pin level */ +/* DEPRECATED - Do not use. */ typedef enum e_gpt_shortest_level { - /** 1 extra PCLK in ON time. Minimum ON time will be limited to 2 PCLK raw counts. */ GPT_SHORTEST_LEVEL_OFF = 0, - - /** 1 extra PCLK in OFF time. Minimum ON time will be limited to 1 PCLK raw counts. */ - GPT_SHORTEST_LEVEL_ON = 1, + GPT_SHORTEST_LEVEL_ON = 1, } gpt_shortest_level_t; /** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent @@ -257,11 +254,18 @@ typedef enum e_gpt_interrupt_skip_adc /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ typedef struct st_gpt_instance_ctrl { - uint32_t open; // Whether or not channel is open - const timer_cfg_t * p_cfg; // Pointer to initial configurations - R_GPT0_Type * p_reg; // Base register for this channel - uint32_t channel_mask; // Channel bitmask - timer_variant_t variant; // Timer variant + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + R_GPT0_Type * p_reg; // Base register for this channel + uint32_t channel_mask; // Channel bitmask + timer_variant_t variant; // Timer variant + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(timer_callback_args_t *); // Pointer to callback + timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } gpt_instance_ctrl_t; /** GPT extension for advanced PWM features. */ @@ -288,7 +292,7 @@ typedef struct st_gpt_extended_cfg { gpt_output_pin_t gtioca; ///< Configuration for GPT I/O pin A gpt_output_pin_t gtiocb; ///< Configuration for GPT I/O pin B - gpt_shortest_level_t shortest_pwm_signal; ///< Shortest PWM signal level + gpt_shortest_level_t shortest_pwm_signal; // DEPRECATED - Do not use gpt_source_t start_source; ///< Event sources that trigger the timer to start gpt_source_t stop_source; ///< Event sources that trigger the timer to stop gpt_source_t clear_source; ///< Event sources that trigger the timer to clear @@ -345,6 +349,10 @@ fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, gpt_adc_compare_match_t which_compare_match, uint32_t compare_match_value); +fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory); fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); fsp_err_t R_GPT_VersionGet(fsp_version_t * const p_version); diff --git a/ra/fsp/inc/instances/r_gpt_three_phase.h b/ra/fsp/inc/instances/r_gpt_three_phase.h index 416a1fa4a..119f8e51d 100644 --- a/ra/fsp/inc/instances/r_gpt_three_phase.h +++ b/ra/fsp/inc/instances/r_gpt_three_phase.h @@ -74,6 +74,10 @@ fsp_err_t R_GPT_THREE_PHASE_Start(three_phase_ctrl_t * const p_ctrl); fsp_err_t R_GPT_THREE_PHASE_Reset(three_phase_ctrl_t * const p_ctrl); fsp_err_t R_GPT_THREE_PHASE_DutyCycleSet(three_phase_ctrl_t * const p_ctrl, three_phase_duty_cycle_t * const p_duty_cycle); +fsp_err_t R_GPT_THREE_PHASE_CallbackSet(three_phase_ctrl_t * const p_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory); fsp_err_t R_GPT_THREE_PHASE_Close(three_phase_ctrl_t * const p_ctrl); fsp_err_t R_GPT_THREE_PHASE_VersionGet(fsp_version_t * const p_version); diff --git a/ra/fsp/inc/instances/r_icu.h b/ra/fsp/inc/instances/r_icu.h index 0089ebb22..4d4c54740 100644 --- a/ra/fsp/inc/instances/r_icu.h +++ b/ra/fsp/inc/instances/r_icu.h @@ -48,12 +48,15 @@ FSP_HEADER /** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ typedef struct st_icu_instance_ctrl { - uint32_t open; ///< Used to determine if channel control block is in use - IRQn_Type irq; ///< NVIC interrupt number - uint8_t channel; ///< Channel + uint32_t open; ///< Used to determine if channel control block is in use + IRQn_Type irq; ///< NVIC interrupt number + uint8_t channel; ///< Channel - /** Callback provided when a external IRQ ISR occurs. Set to NULL for no CPU interrupt. */ - void (* p_callback)(external_irq_callback_args_t * p_args); +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) + external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +#endif + void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin. /** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */ void const * p_context; @@ -80,6 +83,11 @@ fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl); fsp_err_t R_ICU_ExternalIrqVersionGet(fsp_version_t * const p_version); +fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)(external_irq_callback_args_t *), + void const * const p_context, + external_irq_callback_args_t * const p_callback_memory); + fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl); /*******************************************************************************************************************//** diff --git a/ra/fsp/inc/instances/r_iic_master.h b/ra/fsp/inc/instances/r_iic_master.h index c4e80ddf3..20eca30a5 100644 --- a/ra/fsp/inc/instances/r_iic_master.h +++ b/ra/fsp/inc/instances/r_iic_master.h @@ -89,6 +89,17 @@ typedef struct st_iic_master_instance_ctrl volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt volatile bool address_restarted; // Tracks whether the restart condition is send on 10 bit read iic_master_timeout_mode_t timeout_mode; // Holds the timeout mode value. i.e short mode or long mode + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; } iic_master_instance_ctrl_t; /** R_IIC extended configuration */ @@ -127,6 +138,10 @@ fsp_err_t R_IIC_MASTER_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_addr_mode_t const addr_mode); fsp_err_t R_IIC_MASTER_Close(i2c_master_ctrl_t * const p_api_ctrl); fsp_err_t R_IIC_MASTER_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_IIC_MASTER_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void const * const p_context, + i2c_master_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_iic_slave.h b/ra/fsp/inc/instances/r_iic_slave.h index c4f5b259b..264bfa9d5 100644 --- a/ra/fsp/inc/instances/r_iic_slave.h +++ b/ra/fsp/inc/instances/r_iic_slave.h @@ -75,6 +75,17 @@ typedef struct st_iic_slave_instance_ctrl volatile bool do_dummy_read; // Tracks whether a dummy read is issued on the first RX volatile bool start_interrupt_enabled; // Tracks whether the start interrupt is enabled volatile bool transaction_completed; // Tracks whether previous transaction restarted + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_slave_callback_args_t *); + i2c_slave_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; } iic_slave_instance_ctrl_t; /** R_IIC_SLAVE extended configuration */ @@ -102,6 +113,10 @@ fsp_err_t R_IIC_SLAVE_Read(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const fsp_err_t R_IIC_SLAVE_Write(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes); fsp_err_t R_IIC_SLAVE_Close(i2c_slave_ctrl_t * const p_api_ctrl); fsp_err_t R_IIC_SLAVE_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_IIC_SLAVE_CallbackSet(i2c_slave_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_slave_callback_args_t *), + void const * const p_context, + i2c_slave_callback_args_t * const p_callback_memory); #endif // R_IIC_SLAVE_H diff --git a/ra/fsp/inc/instances/r_iwdt.h b/ra/fsp/inc/instances/r_iwdt.h index a89f84a99..173917557 100644 --- a/ra/fsp/inc/instances/r_iwdt.h +++ b/ra/fsp/inc/instances/r_iwdt.h @@ -50,7 +50,12 @@ typedef struct st_iwdt_instance_ctrl uint32_t wdt_open; ///< Indicates whether the open() API has been successfully called. void const * p_context; ///< Placeholder for user data. Passed to the user callback in wdt_callback_args_t. R_IWDT_Type * p_reg; ///< Pointer to register base address. + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS). +#endif void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT NMI ISR occurs. + wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. } iwdt_instance_ctrl_t; /********************************************************************************************************************** @@ -74,6 +79,11 @@ fsp_err_t R_IWDT_CounterGet(wdt_ctrl_t * const p_api_ctrl, uint32_t * const p_co fsp_err_t R_IWDT_TimeoutGet(wdt_ctrl_t * const p_api_ctrl, wdt_timeout_values_t * const p_timeout); +fsp_err_t R_IWDT_CallbackSet(wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void const * const p_context, + wdt_callback_args_t * const p_callback_memory); + fsp_err_t R_IWDT_VersionGet(fsp_version_t * const p_data); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/instances/r_lvd.h b/ra/fsp/inc/instances/r_lvd.h index 9f9ea676d..f94f9da91 100644 --- a/ra/fsp/inc/instances/r_lvd.h +++ b/ra/fsp/inc/instances/r_lvd.h @@ -51,6 +51,15 @@ typedef struct st_lvd_instance_ctrl { uint32_t open; lvd_cfg_t const * p_cfg; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(lvd_callback_args_t *); // Pointer to callback that is called when lvd_current_state_t changes. + lvd_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; } lvd_instance_ctrl_t; /********************************************************************************************************************** @@ -71,6 +80,10 @@ fsp_err_t R_LVD_Close(lvd_ctrl_t * const p_api_ctrl); fsp_err_t R_LVD_StatusGet(lvd_ctrl_t * const p_api_ctrl, lvd_status_t * p_lvd_status); fsp_err_t R_LVD_StatusClear(lvd_ctrl_t * const p_api_ctrl); fsp_err_t R_LVD_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_LVD_CallbackSet(lvd_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lvd_callback_args_t *), + void const * const p_context, + lvd_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_ospi.h b/ra/fsp/inc/instances/r_ospi.h new file mode 100644 index 000000000..1d0c731a3 --- /dev/null +++ b/ra/fsp/inc/instances/r_ospi.h @@ -0,0 +1,179 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup OSPI + * @{ + **********************************************************************************************************************/ + +#ifndef R_OSPI_H +#define R_OSPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_ospi_cfg.h" +#include "r_spi_flash_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define OSPI_CODE_VERSION_MAJOR (1U) +#define OSPI_CODE_VERSION_MINOR (0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* OSPI Flash device chip select */ +typedef enum e_ospi_device_number +{ + OSPI_DEVICE_NUMBER_0, ///< Device connected to Chip-Select 0 + OSPI_DEVICE_NUMBER_1, ///< Device connected to Chip-Select 1 +} ospi_device_number_t; + +/* OSPI command to command interval in single continuous read/write mode + * Unit: OCTACLK + */ +typedef enum e_ospi_command_interval_clocks +{ + OSPI_COMMAND_INTERVAL_CLOCKS_2, + OSPI_COMMAND_INTERVAL_CLOCKS_5, + OSPI_COMMAND_INTERVAL_CLOCKS_7, + OSPI_COMMAND_INTERVAL_CLOCKS_9, + OSPI_COMMAND_INTERVAL_CLOCKS_11, + OSPI_COMMAND_INTERVAL_CLOCKS_13, + OSPI_COMMAND_INTERVAL_CLOCKS_15, + OSPI_COMMAND_INTERVAL_CLOCKS_17 +} ospi_command_interval_clocks_t; + +/* OSPI chip select de-assertion duration after last command in single continuous read/write mode + * Unit: OCTACLK + */ +typedef enum e_ospi_cs_pullup_clocks +{ + OSPI_COMMAND_CS_PULLUP_CLOCKS_2, ///< 1.5 clocks DOPI mode; 2 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_3, ///< 2.5 clocks DOPI mode; 3 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_4, ///< 3.5 clocks DOPI mode; 4 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_5, ///< 4.5 clocks DOPI mode; 5 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_6, ///< 5.5 clocks DOPI mode; 6 Clocks all other modes; Unsupported for DOPI Read + OSPI_COMMAND_CS_PULLUP_CLOCKS_7, ///< 6.5 clocks DOPI mode; 7 Clocks all other modes + OSPI_COMMAND_CS_PULLUP_CLOCKS_8, ///< 7.5 clocks DOPI mode; 8 Clocks all other modes + OSPI_COMMAND_CS_PULLUP_CLOCKS_9 ///< 8.5 clocks DOPI mode; 9 Clocks all other modes +} ospi_command_cs_pullup_clocks_t; + +/* OSPI chip select assertion duration before first command in single continuous read/write mode + * Unit: OCTACLK + */ +typedef enum e_ospi_cs_pulldown_clocks +{ + OSPI_COMMAND_CS_PULLDOWN_CLOCKS_3 = 1, ///< 2.5 clocks DOPI mode; 3 Clocks all other modes + OSPI_COMMAND_CS_PULLDOWN_CLOCKS_4, ///< 3.5 clocks DOPI mode; 4 Clocks all other modes + OSPI_COMMAND_CS_PULLDOWN_CLOCKS_5 ///< 4.5 clocks DOPI mode; 5 Clocks all other modes +} ospi_command_cs_pulldown_clocks_t; + +/* Memory mapped timing */ +typedef struct st_ospi_timing_setting +{ + ospi_command_interval_clocks_t command_to_command_interval; ///< Interval between 2 consecutive commands + ospi_command_cs_pullup_clocks_t cs_pullup_lag; ///< Duration to de-assert CS line after the last command + ospi_command_cs_pulldown_clocks_t cs_pulldown_lead; ///< Duration to assert CS line before the first command +} ospi_timing_setting_t; + +/* This command set is used only with OPI mode set under ospi_extended_cfg_t. spi_flash_cfg_t holds commands for SPI mode. */ +typedef struct st_ospi_opi_command_set +{ + uint16_t dual_read_command; ///< Dual data Read command, valid only in DOPI mode + uint16_t page_program_command; ///< Page program command + uint16_t write_enable_command; ///< Command to enable write or erase, typically 0x06 + uint16_t status_command; ///< Command to read the write status + uint16_t read_command; ///< Read command + uint8_t command_bytes; ///< Command Bytes +} ospi_opi_command_set_t; + +/* Extended configuration. */ +typedef struct st_ospi_extended_cfg +{ + ospi_device_number_t channel; ///< Device number to be used for memory device + uint32_t memory_size; ///< Size of memory device + uint8_t data_latch_delay_clocks; ///< Specify delay between OM_DQS and OM_DQS Strobe. Set to 0 to auto-callibrate. Typical value is 0x80. + uint8_t single_continuous_mode_read_idle_time; ///< Mode idle time duration in PCLKA + uint8_t single_continuous_mode_write_idle_time; ///< Mode idle time duration in PCLKA + ospi_timing_setting_t const * p_mem_mapped_read_timing_settings; ///< Memory mapped read mode settings + ospi_timing_setting_t const * p_mem_mapped_write_timing_settings; ///< Memory mapped write mode settings + ospi_timing_setting_t const * p_timing_settings; ///< Memory mapped write mode settings + ospi_opi_command_set_t const * p_opi_commands; ///< If OPI commands are not used set this to NULL + uint8_t opi_mem_read_dummy_cycles; ///< Dummy cycles to be inserted for memory mapped reads + uint8_t * p_autocalibration_preamble_pattern_addr; ///< OctaFlash memory address holding the preamble pattern +} ospi_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ +typedef struct st_ospi_instance_ctrl +{ + spi_flash_cfg_t const * p_cfg; // Pointer to initial configuration + ospi_device_number_t channel; // Device number to be used for memory device + spi_flash_protocol_t spi_protocol; // Current SPI protocol selected + uint32_t open; // Whether or not driver is open +} ospi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_flash_api_t g_ospi_on_spi_flash; + +/** @endcond */ + +fsp_err_t R_OSPI_Open(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg); +fsp_err_t R_OSPI_Close(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_OSPI_DirectWrite(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +fsp_err_t R_OSPI_DirectRead(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_OSPI_DirectTransfer(spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); +fsp_err_t R_OSPI_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol); +fsp_err_t R_OSPI_XipEnter(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_OSPI_XipExit(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_OSPI_Write(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); +fsp_err_t R_OSPI_Erase(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); +fsp_err_t R_OSPI_StatusGet(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status); +fsp_err_t R_OSPI_BankSet(spi_flash_ctrl_t * p_ctrl, uint32_t bank); +fsp_err_t R_OSPI_VersionGet(fsp_version_t * const p_version); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup OSPI) + **********************************************************************************************************************/ diff --git a/ra/fsp/inc/instances/r_poeg.h b/ra/fsp/inc/instances/r_poeg.h index 2caeb3032..b93b27c04 100644 --- a/ra/fsp/inc/instances/r_poeg.h +++ b/ra/fsp/inc/instances/r_poeg.h @@ -48,9 +48,16 @@ FSP_HEADER /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref poeg_api_t::open is called. */ typedef struct st_poeg_instance_ctrl { - uint32_t open; // Whether or not channel is open - const poeg_cfg_t * p_cfg; // Pointer to initial configurations - R_GPT_POEG0_Type * p_reg; // Base register for this channel + uint32_t open; // Whether or not channel is open + const poeg_cfg_t * p_cfg; // Pointer to initial configurations + R_GPT_POEG0_Type * p_reg; // Base register for this channel + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(poeg_callback_args_t *); // Pointer to callback + poeg_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } poeg_instance_ctrl_t; /********************************************************************************************************************** @@ -68,6 +75,10 @@ extern const poeg_api_t g_poeg_on_poeg; **********************************************************************************************************************/ fsp_err_t R_POEG_Open(poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cfg); fsp_err_t R_POEG_StatusGet(poeg_ctrl_t * const p_ctrl, poeg_status_t * const p_status); +fsp_err_t R_POEG_CallbackSet(poeg_ctrl_t * const p_ctrl, + void ( * p_callback)(poeg_callback_args_t *), + void const * const p_context, + poeg_callback_args_t * const p_callback_memory); fsp_err_t R_POEG_OutputDisable(poeg_ctrl_t * const p_ctrl); fsp_err_t R_POEG_Reset(poeg_ctrl_t * const p_ctrl); fsp_err_t R_POEG_Close(poeg_ctrl_t * const p_ctrl); diff --git a/ra/fsp/inc/instances/r_rtc.h b/ra/fsp/inc/instances/r_rtc.h index a8cc8c753..836bd506b 100644 --- a/ra/fsp/inc/instances/r_rtc.h +++ b/ra/fsp/inc/instances/r_rtc.h @@ -52,9 +52,17 @@ FSP_HEADER /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref rtc_api_t::open is called */ typedef struct st_rtc_ctrl { - uint32_t open; ///< Whether or not driver is open - const rtc_cfg_t * p_cfg; ///< Pointer to initial configurations - volatile bool carry_isr_triggered; ///< Was the carry isr triggered + uint32_t open; ///< Whether or not driver is open + const rtc_cfg_t * p_cfg; ///< Pointer to initial configurations + volatile bool carry_isr_triggered; ///< Was the carry isr triggered + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(rtc_callback_args_t *); // Pointer to callback that is called when a rtc_event_t occurs. + rtc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + void const * p_context; // Pointer to context to be passed into callback function } rtc_instance_ctrl_t; /********************************************************************************************************************** @@ -80,6 +88,10 @@ fsp_err_t R_RTC_PeriodicIrqRateSet(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_s fsp_err_t R_RTC_ErrorAdjustmentSet(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); fsp_err_t R_RTC_InfoGet(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); fsp_err_t R_RTC_VersionGet(fsp_version_t * version); +fsp_err_t R_RTC_CallbackSet(rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void const * const p_context, + rtc_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_sci_i2c.h b/ra/fsp/inc/instances/r_sci_i2c.h index 3e0aeacdd..cdd24232e 100644 --- a/ra/fsp/inc/instances/r_sci_i2c.h +++ b/ra/fsp/inc/instances/r_sci_i2c.h @@ -86,6 +86,17 @@ typedef struct st_sci_i2c_instance_ctrl volatile bool do_dummy_read; // Tracks whether a dummy read is issued on the first RX */ volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt */ volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt */ + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; } sci_i2c_instance_ctrl_t; /** SCI I2C extended configuration */ @@ -122,6 +133,10 @@ fsp_err_t R_SCI_I2C_Abort(i2c_master_ctrl_t * const p_api_ctrl); fsp_err_t R_SCI_I2C_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_SCI_I2C_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void const * const p_context, + i2c_master_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_sci_spi.h b/ra/fsp/inc/instances/r_sci_spi.h index 7c3bfe8c2..42488999e 100644 --- a/ra/fsp/inc/instances/r_sci_spi.h +++ b/ra/fsp/inc/instances/r_sci_spi.h @@ -69,6 +69,17 @@ typedef struct st_sci_spi_instance_ctrl uint32_t tx_count; uint32_t rx_count; uint32_t count; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; } sci_spi_instance_ctrl_t; /********************************************************************************************************************** @@ -101,6 +112,10 @@ fsp_err_t R_SCI_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, fsp_err_t R_SCI_SPI_Close(spi_ctrl_t * const p_api_ctrl); fsp_err_t R_SCI_SPI_VersionGet(fsp_version_t * p_version); fsp_err_t R_SCI_SPI_CalculateBitrate(uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr); +fsp_err_t R_SCI_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_sci_uart.h b/ra/fsp/inc/instances/r_sci_uart.h index 4cc59a175..c307beaa7 100644 --- a/ra/fsp/inc/instances/r_sci_uart.h +++ b/ra/fsp/inc/instances/r_sci_uart.h @@ -92,6 +92,15 @@ typedef struct st_sci_uart_instance_ctrl /* Base register for this channel */ R_SCI0_Type * p_reg; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; } sci_uart_instance_ctrl_t; /** Receive FIFO trigger configuration. */ @@ -183,6 +192,10 @@ fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate, bool bitrate_modulation, uint32_t baud_rate_error_x_1000, baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory); /*******************************************************************************************************************//** * @} (end addtogroup SCI_UART) diff --git a/ra/fsp/inc/instances/r_sdhi.h b/ra/fsp/inc/instances/r_sdhi.h index d354dd862..59a65b55c 100644 --- a/ra/fsp/inc/instances/r_sdhi.h +++ b/ra/fsp/inc/instances/r_sdhi.h @@ -104,6 +104,10 @@ typedef struct st_sdmmc_instance_ctrl uint32_t transfer_block_current; uint32_t transfer_block_size; uint32_t aligned_buff[SDHI_MAX_BLOCK_SIZE / sizeof(uint32_t)]; + + void (* p_callback)(sdmmc_callback_args_t *); // Pointer to callback + sdmmc_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } sdhi_instance_ctrl_t; /********************************************************************************************************************** @@ -156,6 +160,10 @@ fsp_err_t R_SDHI_WriteIoExt(sdmmc_ctrl_t * const p_api_ctrl, fsp_err_t R_SDHI_IoIntEnable(sdmmc_ctrl_t * const p_api_ctrl, bool enable); fsp_err_t R_SDHI_StatusGet(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_status_t * const p_status); fsp_err_t R_SDHI_Erase(sdmmc_ctrl_t * const p_api_ctrl, uint32_t const start_sector, uint32_t const sector_count); +fsp_err_t R_SDHI_CallbackSet(sdmmc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(sdmmc_callback_args_t *), + void const * const p_context, + sdmmc_callback_args_t * const p_callback_memory); fsp_err_t R_SDHI_Close(sdmmc_ctrl_t * const p_api_ctrl); fsp_err_t R_SDHI_VersionGet(fsp_version_t * const p_version); diff --git a/ra/fsp/inc/instances/r_spi.h b/ra/fsp/inc/instances/r_spi.h index 208989e23..0132d00e4 100644 --- a/ra/fsp/inc/instances/r_spi.h +++ b/ra/fsp/inc/instances/r_spi.h @@ -146,6 +146,17 @@ typedef struct st_spi_instance_ctrl uint32_t rx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; } spi_instance_ctrl_t; /********************************************************************************************************************** @@ -184,6 +195,10 @@ fsp_err_t R_SPI_Close(spi_ctrl_t * const p_api_ctrl); fsp_err_t R_SPI_VersionGet(fsp_version_t * p_version); fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, rspck_div_setting_t * spck_div); +fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory); /*******************************************************************************************************************//** * @} (end ingroup SPI) diff --git a/ra/fsp/inc/instances/r_ssi.h b/ra/fsp/inc/instances/r_ssi.h index 03b920031..3bfefc870 100644 --- a/ra/fsp/inc/instances/r_ssi.h +++ b/ra/fsp/inc/instances/r_ssi.h @@ -48,7 +48,8 @@ FSP_HEADER typedef enum e_ssi_audio_clock { SSI_AUDIO_CLOCK_EXTERNAL = 0, ///< Audio clock source is the AUDIO_CLK input pin - SSI_AUDIO_CLOCK_GTIOC1A = 1, ///< Audio clock source is internal connection to GPT channel 1 output + SSI_AUDIO_CLOCK_GTIOC1A = 1, // Audio clock source is internal connection to GPT channel 1 output (Deprecated) + SSI_AUDIO_CLOCK_INTERNAL = 1, ///< Audio clock source is internal connection to a MCU specific GPT channel output } ssi_audio_clock_t; /** Bit clock division ratio. Bit clock frequency = audio clock frequency / bit clock division ratio. */ @@ -88,6 +89,15 @@ typedef struct st_ssi_instance_ctrl /* Size of destination buffer used to fill from hardware FIFO in receive ISR. */ uint32_t rx_dest_samples; transfer_size_t fifo_access_size; // Access the FIFO as 1 byte, 2 bytes, or 4 bytes + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2s_callback_args_t *); + i2s_callback_args_t * p_callback_memory; + void const * p_context; // < User defined context passed into callback function } ssi_instance_ctrl_t; /** SSI configuration extension. This extension is optional. */ @@ -120,6 +130,10 @@ fsp_err_t R_SSI_WriteRead(i2s_ctrl_t * const p_ctrl, void const * const p_src, v fsp_err_t R_SSI_Mute(i2s_ctrl_t * const p_ctrl, i2s_mute_t const mute_enable); fsp_err_t R_SSI_Close(i2s_ctrl_t * const p_ctrl); fsp_err_t R_SSI_VersionGet(fsp_version_t * const p_version); +fsp_err_t R_SSI_CallbackSet(i2s_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2s_callback_args_t *), + void const * const p_context, + i2s_callback_args_t * const p_callback_memory); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_usb_hhid.h b/ra/fsp/inc/instances/r_usb_hhid.h index 8d27947f4..a4ad9441d 100644 --- a/ra/fsp/inc/instances/r_usb_hhid.h +++ b/ra/fsp/inc/instances/r_usb_hhid.h @@ -35,6 +35,7 @@ * Includes , "Project Includes" ******************************************************************************/ #include "r_usb_hhid_cfg.h" +#include "r_usb_basic_api.h" /****************************************************************************** * Exported global functions (to be accessed by other files) diff --git a/ra/fsp/inc/instances/r_wdt.h b/ra/fsp/inc/instances/r_wdt.h index 3d30438a6..ec6820c30 100644 --- a/ra/fsp/inc/instances/r_wdt.h +++ b/ra/fsp/inc/instances/r_wdt.h @@ -51,7 +51,11 @@ typedef struct st_wdt_instance_ctrl // called. void const * p_context; // Placeholder for user data. Passed to the user callback in // wdt_callback_args_t. +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS). +#endif void (* p_callback)(wdt_callback_args_t * p_args); // Callback provided when a WDT NMI ISR occurs. + wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. } wdt_instance_ctrl_t; /********************************************************************************************************************** @@ -79,6 +83,11 @@ fsp_err_t R_WDT_CounterGet(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); fsp_err_t R_WDT_TimeoutGet(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); +fsp_err_t R_WDT_CallbackSet(wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void const * const p_context, + wdt_callback_args_t * const p_callback_memory); + fsp_err_t R_WDT_VersionGet(fsp_version_t * const p_version); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/instances/rm_block_media_sdmmc.h b/ra/fsp/inc/instances/rm_block_media_sdmmc.h index 6de086d03..25afd0954 100644 --- a/ra/fsp/inc/instances/rm_block_media_sdmmc.h +++ b/ra/fsp/inc/instances/rm_block_media_sdmmc.h @@ -63,6 +63,11 @@ typedef struct st_rm_block_media_sdmmc_instance_ctrl uint32_t sector_count; uint32_t sector_size_bytes; bool initialized; + bool write_protected; + + void (* p_callback)(rm_block_media_callback_args_t *); // Pointer to callback + rm_block_media_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } rm_block_media_sdmmc_instance_ctrl_t; /********************************************************************************************************************** @@ -88,10 +93,14 @@ fsp_err_t RM_BLOCK_MEDIA_SDMMC_Write(rm_block_media_ctrl_t * const p_ctrl, uint8_t const * const p_src_address, uint32_t const block_address, uint32_t const num_blocks); -fsp_err_t RM_BLOCK_MEDIA_SDMMC_Flush(rm_block_media_ctrl_t * const p_ctrl); fsp_err_t RM_BLOCK_MEDIA_SDMMC_Erase(rm_block_media_ctrl_t * const p_ctrl, uint32_t const block_address, uint32_t const num_blocks); +fsp_err_t RM_BLOCK_MEDIA_SDMMC_CallbackSet(rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)( + rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory); fsp_err_t RM_BLOCK_MEDIA_SDMMC_StatusGet(rm_block_media_ctrl_t * const p_api_ctrl, rm_block_media_status_t * const p_status); fsp_err_t RM_BLOCK_MEDIA_SDMMC_InfoGet(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_info_t * const p_info); diff --git a/ra/fsp/inc/instances/rm_block_media_usb.h b/ra/fsp/inc/instances/rm_block_media_usb.h index feac1e073..6a81775b3 100644 --- a/ra/fsp/inc/instances/rm_block_media_usb.h +++ b/ra/fsp/inc/instances/rm_block_media_usb.h @@ -98,6 +98,11 @@ fsp_err_t RM_BLOCK_MEDIA_USB_Flush(rm_block_media_ctrl_t * const p_ctrl); fsp_err_t RM_BLOCK_MEDIA_USB_Erase(rm_block_media_ctrl_t * const p_ctrl, uint32_t const block_address, uint32_t const num_blocks); +fsp_err_t RM_BLOCK_MEDIA_USB_CallbackSet(rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)( + rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory); fsp_err_t RM_BLOCK_MEDIA_USB_StatusGet(rm_block_media_ctrl_t * const p_api_ctrl, rm_block_media_status_t * const p_status); fsp_err_t RM_BLOCK_MEDIA_USB_InfoGet(rm_block_media_ctrl_t * const p_ctrl, rm_block_media_info_t * const p_info); diff --git a/ra/fsp/inc/instances/rm_touch.h b/ra/fsp/inc/instances/rm_touch.h index 136ba118c..a2b58aab7 100644 --- a/ra/fsp/inc/instances/rm_touch.h +++ b/ra/fsp/inc/instances/rm_touch.h @@ -48,43 +48,60 @@ FSP_HEADER /** Information of button */ typedef struct { - uint64_t status; ///< Touch result bitmap. - uint16_t *p_threshold; ///< Pointer to Threshold value array. g_touch_button_threshold[] is set by Open API. - uint16_t *p_hysteresis; ///< Pointer to Hysteresis value array. g_touch_button_hysteresis[] is set by Open API. - uint16_t *p_reference; ///< Pointer to Reference value array. g_touch_button_reference[] is set by Open API. - uint16_t *p_on_count; ///< Continuous touch counter. g_touch_button_on_count[] is set by Open API. - uint16_t *p_off_count; ///< Continuous non-touch counter. g_touch_button_off_count[] is set by Open API. - uint32_t *p_drift_buf; ///< Drift reference value. g_touch_button_drift_buf[] is set by Open API. - uint16_t *p_drift_count; ///< Drift counter. g_touch_button_drift_count[] is set by Open API. - uint8_t on_freq; ///< Copy from config by Open API. - uint8_t off_freq; ///< Copy from config by Open API. - uint16_t drift_freq; ///< Copy from config by Open API. - uint16_t cancel_freq; ///< Copy from config by Open API. + uint64_t status; ///< Touch result bitmap. + uint16_t * p_threshold; ///< Pointer to Threshold value array. g_touch_button_threshold[] is set by Open API. + uint16_t * p_hysteresis; ///< Pointer to Hysteresis value array. g_touch_button_hysteresis[] is set by Open API. + uint16_t * p_reference; ///< Pointer to Reference value array. g_touch_button_reference[] is set by Open API. + uint16_t * p_on_count; ///< Continuous touch counter. g_touch_button_on_count[] is set by Open API. + uint16_t * p_off_count; ///< Continuous non-touch counter. g_touch_button_off_count[] is set by Open API. + uint32_t * p_drift_buf; ///< Drift reference value. g_touch_button_drift_buf[] is set by Open API. + uint16_t * p_drift_count; ///< Drift counter. g_touch_button_drift_count[] is set by Open API. + uint8_t on_freq; ///< Copy from config by Open API. + uint8_t off_freq; ///< Copy from config by Open API. + uint16_t drift_freq; ///< Copy from config by Open API. + uint16_t cancel_freq; ///< Copy from config by Open API. } touch_button_info_t; /** Information of slider */ typedef struct { - uint16_t *p_position; ///< Calculated Position data. g_touch_slider_position[] is set by Open API. - uint16_t *p_threshold; ///< Copy from config by Open API. g_touch_slider_threshold[] is set by Open API. + uint16_t * p_position; ///< Calculated Position data. g_touch_slider_position[] is set by Open API. + uint16_t * p_threshold; ///< Copy from config by Open API. g_touch_slider_threshold[] is set by Open API. } touch_slider_info_t; /** Information of wheel */ typedef struct { - uint16_t *p_position; ///< Calculated Position data. g_touch_wheel_position[] is set by Open API. - uint16_t *p_threshold; ///< Copy from config by Open API. g_touch_wheel_threshold[] is set by Open API. + uint16_t * p_position; ///< Calculated Position data. g_touch_wheel_position[] is set by Open API. + uint16_t * p_threshold; ///< Copy from config by Open API. g_touch_wheel_threshold[] is set by Open API. } touch_wheel_info_t; +/** Information of pad */ +typedef struct +{ + uint16_t * p_rx_coordinate; ///< RX coordinate + uint16_t * p_tx_coordinate; ///< TX coordinate + uint16_t * p_num_touch; ///< number of touch + uint16_t * p_threshold; ///< Coordinate calculation threshold value. + uint16_t * p_base_buf; ///< ScanData Base Value Buffer. + uint16_t * p_rx_pixel; ///< X coordinate resolution + uint16_t * p_tx_pixel; ///< Y coordinate resolution + uint8_t * p_max_touch; ///< Maximum number of touch judgments used by the pad. + int32_t * p_drift_buf; ///< Drift reference value. g_touch_button_drift_buf[] is set by Open API. + uint16_t * p_drift_count; ///< Drift counter. g_touch_button_drift_count[] is set by Open API. + uint8_t num_drift; ///< Copy from config by Open API. +} touch_pad_info_t; + /** TOUCH private control block. DO NOT MODIFY. Initialization occurs when RM_TOUCH_Open() is called. */ typedef struct st_touch_instance_ctrl { - uint32_t open; ///< Whether or not driver is open. - touch_button_info_t binfo; ///< Information of button. - touch_slider_info_t sinfo; ///< Information of slider. - touch_wheel_info_t winfo; ///< Information of wheel. - touch_cfg_t const * p_touch_cfg; ///< Pointer to initial configurations. - ctsu_instance_t const * p_ctsu_instance; ///< Pointer to CTSU instance. + uint32_t open; ///< Whether or not driver is open. + touch_button_info_t binfo; ///< Information of button. + touch_slider_info_t sinfo; ///< Information of slider. + touch_wheel_info_t winfo; ///< Information of wheel. + touch_pad_info_t pinfo; ///< Information of pad. + touch_cfg_t const * p_touch_cfg; ///< Pointer to initial configurations. + ctsu_instance_t const * p_ctsu_instance; ///< Pointer to CTSU instance. } touch_instance_ctrl_t; /********************************************************************************************************************** @@ -102,9 +119,20 @@ extern const touch_api_t g_touch_on_ctsu; **********************************************************************************************************************/ fsp_err_t RM_TOUCH_Open(touch_ctrl_t * const p_ctrl, touch_cfg_t const * const p_cfg); fsp_err_t RM_TOUCH_ScanStart(touch_ctrl_t * const p_ctrl); -fsp_err_t RM_TOUCH_DataGet(touch_ctrl_t * const p_ctrl, uint64_t *p_button_status, uint16_t *p_slider_position, uint16_t *p_wheel_position); +fsp_err_t RM_TOUCH_DataGet(touch_ctrl_t * const p_ctrl, + uint64_t * p_button_status, + uint16_t * p_slider_position, + uint16_t * p_wheel_position); +fsp_err_t RM_TOUCH_PadDataGet(touch_ctrl_t * const p_ctrl, + uint16_t * p_pad_rx_coordinate, + uint16_t * p_pad_tx_coordinate, + uint8_t * p_pad_num_touch); +fsp_err_t RM_TOUCH_CallbackSet(touch_ctrl_t * const p_api_ctrl, + void ( * p_callback)(touch_callback_args_t *), + void const * const p_context, + touch_callback_args_t * const p_callback_memory); fsp_err_t RM_TOUCH_Close(touch_ctrl_t * const p_ctrl); -fsp_err_t RM_TOUCH_VersionGet (fsp_version_t * const p_version); +fsp_err_t RM_TOUCH_VersionGet(fsp_version_t * const p_version); /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/rm_vee_flash.h b/ra/fsp/inc/instances/rm_vee_flash.h index 5fe0fe9fc..14fb4c8ad 100644 --- a/ra/fsp/inc/instances/rm_vee_flash.h +++ b/ra/fsp/inc/instances/rm_vee_flash.h @@ -114,6 +114,13 @@ typedef struct st_rm_vee_flash_instance_ctrl uint32_t refresh_xfer_bytes_left; flash_instance_t const * p_flash; uint32_t segment_size; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure; // If the callback is in non-secure memory then a security state transistion is required to call p_callback (BLXNS) +#endif + void (* p_callback)(rm_vee_callback_args_t *); // Pointer to callback + rm_vee_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function } rm_vee_flash_instance_ctrl_t; /********************************************************************************************************************** @@ -143,6 +150,10 @@ fsp_err_t RM_VEE_FLASH_RefDataPtrGet(rm_vee_ctrl_t * const p_api_ctrl, uint8_t * fsp_err_t RM_VEE_FLASH_StatusGet(rm_vee_ctrl_t * const p_api_ctrl, rm_vee_status_t * const p_status); fsp_err_t RM_VEE_FLASH_Refresh(rm_vee_ctrl_t * const p_api_ctrl); fsp_err_t RM_VEE_FLASH_Format(rm_vee_ctrl_t * const p_api_ctrl, uint8_t const * const p_ref_data); +fsp_err_t RM_VEE_FLASH_CallbackSet(rm_vee_ctrl_t * const p_api_ctrl, + void ( * p_callback)(rm_vee_callback_args_t *), + void const * const p_context, + rm_vee_callback_args_t * const p_callback_memory); fsp_err_t RM_VEE_FLASH_Close(rm_vee_ctrl_t * const p_api_ctrl); fsp_err_t RM_VEE_FLASH_VersionGet(fsp_version_t * const p_version); diff --git a/ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a b/ra/fsp/lib/r_ble/cm4_ac6/all/libr_ble.a index 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zyr8(C7c{LHuYefu>Rg*%WmD+@W-_WP8*^_*CVVoQuM2uZ?H-gDkp5Xf7ZM}=M@fhBw|L3B8V}yH1k+7VYK|-8>q4yEaqtH7E=TEEwYTm@^4l+e z!2&+CH9a@tdwV!t>X%vhgVeqT0emATO2bp7DscW_O^fqNF=t|=1f6oJTjtq?V!bs< zwA|?lnybZ>SIrV@;}E6x{EmX34~Z`wn0poP?;)B-SxSx6NrPU1e-iGlTC{9}-e^vZ zD_vYX30)raYrudD<>x4#t;RWGa_1WuGPO@t`Ldk4Uu#)YDy$uY;A~Ci3o<`+~_&x%tbWv@pE+42Dztlbh`}GfKp`w4e z^i^ytZIoA3*=oE`C|}ZVKYj;sty6|tQie6FVc>mvP4Y@EVZ4>gHJ&!PIT#G*sc0Of`;*u!xbS#Qht zZoVrj*5hsc6%q|JtCp|7K+FLTCKNN@4V1u2WIJPE%PZDgCUz`)9&oS?Cy1GZQ;Ver ZD<&UbBdmc&1~*)lo?fHE|3W0|{{bm`LLUGC diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h new file mode 100644 index 000000000..ea3f0fbf1 --- /dev/null +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h @@ -0,0 +1,521 @@ +#ifndef __BASE_ADDRESSES_H +#define __BASE_ADDRESSES_H + +#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers) + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_MPU_BASE 0x40000000 + #define R_TZF_BASE 0x40000E00 + #define R_SRAM_BASE 0x40002000 + #define R_BUS_BASE 0x40003000 + #define R_DMAC0_BASE 0x40005000 + #define R_DMAC1_BASE 0x40005040 + #define R_DMAC2_BASE 0x40005080 + #define R_DMAC3_BASE 0x400050C0 + #define R_DMAC4_BASE 0x40005100 + #define R_DMAC5_BASE 0x40005140 + #define R_DMAC6_BASE 0x40005180 + #define R_DMAC7_BASE 0x400051C0 + #define R_DMA_BASE 0x40005200 + #define R_DTC_BASE 0x40005400 + #define R_ICU_BASE 0x40006000 + #define R_CPSCU_BASE 0x40008000 + #define R_DBG_BASE 0x4001B000 + #define R_FCACHE_BASE 0x4001C000 + #define R_SYSC_BASE 0x4001E000 + #define R_TSN_CAL_BASE 0x407FB17C + #define R_TSN_CTRL_BASE 0x400F3000 + #define R_PFS_BASE 0x40080800 + #define R_ELC_BASE 0x40082000 + #define R_TC_BASE 0x40083000 + #define R_IWDT_BASE 0x40083200 + #define R_WDT_BASE 0x40083400 + #define R_CAC_BASE 0x40083600 + #define R_MSTP_BASE 0x40084004 + +// #define R_MSTP_BASE 0x40084000 + #define R_POEG_BASE 0x4008A000 + #define R_USB_FS0_BASE 0x40090000 + #define R_SDHI0_BASE 0x40092000 + #define R_SSI0_BASE 0x4009D000 + #define R_IIC0_BASE 0x4009F000 + #define R_IIC0WU_BASE 0x4009F014 + #define R_IIC1_BASE 0x4009F100 + #define R_OSPI_BASE 0x400A6000 + #define R_CAN0_BASE 0x400A8000 + #define R_CAN1_BASE 0x400A9000 + #define R_CTSU_BASE 0x400D0000 + #define R_PSCU_BASE 0x400E0000 + #define R_AGT0_BASE 0x400E8000 + #define R_AGT1_BASE 0x400E8100 + #define R_AGT2_BASE 0x400E8200 + #define R_AGT3_BASE 0x400E8300 + #define R_AGT4_BASE 0x400E8400 + #define R_AGT5_BASE 0x400E8500 + #define R_TSN_CTRL_BASE 0x400F3000 + #define R_CRC_BASE 0x40108000 + #define R_DOC_BASE 0x40109000 + #define R_ETHERC_EDMAC_BASE 0x40114000 + #define R_ETHERC0_BASE 0x40114100 + #define R_SCI0_BASE 0x40118000 + #define R_SCI1_BASE 0x40118100 + #define R_SCI2_BASE 0x40118200 + #define R_SCI3_BASE 0x40118300 + #define R_SCI4_BASE 0x40118400 + #define R_SCI5_BASE 0x40118500 + #define R_SCI6_BASE 0x40118600 + #define R_SCI7_BASE 0x40118700 + #define R_SCI8_BASE 0x40118800 + #define R_SCI9_BASE 0x40118900 + #define R_SPI0_BASE 0x4011A000 + #define R_SPI1_BASE 0x4011A100 + #define R_GPT320_BASE 0x40169000 + #define R_GPT321_BASE 0x40169100 + #define R_GPT322_BASE 0x40169200 + #define R_GPT323_BASE 0x40169300 + #define R_GPT164_BASE 0x40169400 + #define R_GPT165_BASE 0x40169500 + #define R_GPT166_BASE 0x40169600 + #define R_GPT167_BASE 0x40169700 + #define R_GPT168_BASE 0x40169800 + #define R_GPT169_BASE 0x40169900 + #define R_GPT_OPS_BASE 0x40169A00 + #define R_ADC120_BASE 0x40170000 + #define R_ADC121_BASE 0x40170200 + #define R_DAC12_BASE 0x40171000 + #define R_FLAD_BASE 0x407FC000 + #define R_FACI_HP_CMD_BASE 0x407E0000 + #define R_FACI_HP_BASE 0x407FE000 + #define R_QSPI_BASE 0x64000000 + +/* Not included in SVD */ + #define R_PORT0_BASE 0x40080000 + #define R_PORT1_BASE 0x40080020 + #define R_PORT2_BASE 0x40080040 + #define R_PORT3_BASE 0x40080060 + #define R_PORT4_BASE 0x40080080 + #define R_PORT5_BASE 0x400800A0 + #define R_PORT6_BASE 0x400800C0 + #define R_PORT7_BASE 0x400800E0 + #define R_PORT8_BASE 0x40080100 + #define R_PORT9_BASE 0x40080120 + #define R_PORT10_BASE 0x40080140 + #define R_PORT11_BASE 0x40080160 + #define R_PFS_BASE 0x40080800 + #define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this + + #define R_GPT_POEG0_BASE 0x4008A000 + #define R_GPT_POEG1_BASE 0x4008A100 + #define R_GPT_POEG2_BASE 0x4008A200 + #define R_GPT_POEG3_BASE 0x4008A300 + + #define R_RTC_BASE 0x40083000 + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +// #define R_MPU ((R_MPU_Type *) R_MPU_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_TC ((R_TC_Type *) R_TC_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_POEG ((R_POEG_Type *) R_POEG_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_ETHERC_EDMAC0 ((R_ETHERC_EDMAC0_Type *) R_ETHERC_EDMAC0_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC12_BASE) + #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + +/* Not in SVD. */ + + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +#else + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000 + #define R_ACMPHS1_BASE 0x40085100 + #define R_ACMPHS2_BASE 0x40085200 + #define R_ACMPHS3_BASE 0x40085300 + #define R_ACMPHS4_BASE 0x40085400 + #define R_ACMPHS5_BASE 0x40085500 + #define R_ACMPLP_BASE 0x40085E00 + #define R_ADC0_BASE 0x4005C000 + #define R_ADC1_BASE 0x4005C200 + #define R_AGT0_BASE 0x40084000 + #define R_AGT1_BASE 0x40084100 + #define R_BUS_BASE 0x40003000 + #define R_CAC_BASE 0x40044600 + #define R_CAN0_BASE 0x40050000 + #define R_CAN1_BASE 0x40051000 + #define R_CRC_BASE 0x40074000 + #define R_CTSU_BASE 0x40081000 + #define R_CTSU2_BASE 0x40082000 + #define R_DAC_BASE 0x4005E000 + #define R_DAC8_BASE 0x4009E000 + #define R_DALI0_BASE 0x4008F000 + #define R_DEBUG_BASE 0x4001B000 + #define R_DMA_BASE 0x40005200 + #define R_DMAC0_BASE 0x40005000 + #define R_DMAC1_BASE 0x40005040 + #define R_DMAC2_BASE 0x40005080 + #define R_DMAC3_BASE 0x400050C0 + #define R_DMAC4_BASE 0x40005100 + #define R_DMAC5_BASE 0x40005140 + #define R_DMAC6_BASE 0x40005180 + #define R_DMAC7_BASE 0x400051C0 + #define R_DOC_BASE 0x40054100 + #define R_DRW_BASE 0x400E4000 + #define R_DTC_BASE 0x40005400 + #define R_ELC_BASE 0x40041000 + #define R_ETHERC0_BASE 0x40064100 + #define R_ETHERC_EDMAC_BASE 0x40064000 + #define R_ETHERC_EPTPC_BASE 0x40065800 + #define R_ETHERC_EPTPC1_BASE 0x40065C00 + #define R_ETHERC_EPTPC_CFG_BASE 0x40064500 + #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000 + #define R_FACI_HP_CMD_BASE 0x407E0000 + #define R_FACI_HP_BASE 0x407FE000 + #define R_FACI_LP_BASE 0x407EC000 + #define R_FCACHE_BASE 0x4001C000 + #define R_GLCDC_BASE 0x400E0000 + #define R_GPT0_BASE 0x40078000 + #define R_GPT1_BASE 0x40078100 + #define R_GPT2_BASE 0x40078200 + #define R_GPT3_BASE 0x40078300 + #define R_GPT4_BASE 0x40078400 + #define R_GPT5_BASE 0x40078500 + #define R_GPT6_BASE 0x40078600 + #define R_GPT7_BASE 0x40078700 + #define R_GPT8_BASE 0x40078800 + #define R_GPT9_BASE 0x40078900 + #define R_GPT10_BASE 0x40078A00 + #define R_GPT11_BASE 0x40078B00 + #define R_GPT12_BASE 0x40078C00 + #define R_GPT13_BASE 0x40078D00 + #define R_GPT_ODC_BASE 0x4007B000 + #define R_GPT_OPS_BASE 0x40078FF0 + #define R_GPT_POEG0_BASE 0x40042000 + #define R_GPT_POEG1_BASE 0x40042100 + #define R_GPT_POEG2_BASE 0x40042200 + #define R_GPT_POEG3_BASE 0x40042300 + #define R_ICU_BASE 0x40006000 + #define R_IIC0_BASE 0x40053000 + #define R_IIC1_BASE 0x40053100 + #define R_IIC2_BASE 0x40053200 + #define R_IRDA_BASE 0x40070F00 + #define R_IWDT_BASE 0x40044400 + #define R_JPEG_BASE 0x400E6000 + #define R_KINT_BASE 0x40080000 + #define R_MMF_BASE 0x40001000 + #define R_MPU_MMPU_BASE 0x40000000 + #define R_MPU_SMPU_BASE 0x40000C00 + #define R_MPU_SPMON_BASE 0x40000D00 + #define R_MSTP_BASE 0x40047000 + #define R_OPAMP_BASE 0x40086000 + #define R_OPAMP2_BASE 0x400867F8 + #define R_PDC_BASE 0x40094000 + #define R_PORT0_BASE 0x40040000 + #define R_PORT1_BASE 0x40040020 + #define R_PORT2_BASE 0x40040040 + #define R_PORT3_BASE 0x40040060 + #define R_PORT4_BASE 0x40040080 + #define R_PORT5_BASE 0x400400A0 + #define R_PORT6_BASE 0x400400C0 + #define R_PORT7_BASE 0x400400E0 + #define R_PORT8_BASE 0x40040100 + #define R_PORT9_BASE 0x40040120 + #define R_PORT10_BASE 0x40040140 + #define R_PORT11_BASE 0x40040160 + #define R_PFS_BASE 0x40040800 + #define R_PMISC_BASE 0x40040D00 + #define R_QSPI_BASE 0x64000000 + #define R_RTC_BASE 0x40044000 + #define R_SCI0_BASE 0x40070000 + #define R_SCI1_BASE 0x40070020 + #define R_SCI2_BASE 0x40070040 + #define R_SCI3_BASE 0x40070060 + #define R_SCI4_BASE 0x40070080 + #define R_SCI5_BASE 0x400700A0 + #define R_SCI6_BASE 0x400700C0 + #define R_SCI7_BASE 0x400700E0 + #define R_SCI8_BASE 0x40070100 + #define R_SCI9_BASE 0x40070120 + #define R_SDADC0_BASE 0x4009C000 + #define R_SDHI0_BASE 0x40062000 + #define R_SDHI1_BASE 0x40062400 + #define R_SLCDC_BASE 0x40082000 + #define R_SPI0_BASE 0x40072000 + #define R_SPI1_BASE 0x40072100 + #define R_SRAM_BASE 0x40002000 + #define R_SRC_BASE 0x40048000 + #define R_SSI0_BASE 0x4004E000 + #define R_SSI1_BASE 0x4004E100 + #define R_SYSTEM_BASE 0x4001E000 + #define R_TSN_BASE 0x407EC000 + #define R_TSN_CAL_BASE 0x407FB17C + #define R_TSN_CTRL_BASE 0x4005D000 + #define R_USB_FS0_BASE 0x40090000 + #define R_USB_HS0_BASE 0x40060000 + #define R_WDT_BASE 0x40044200 + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #if (BSP_FEATURE_CTSU_VERSION == 2) + #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE) + #else + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #endif + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) + #define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE) + #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC0_Type *) R_ETHERC_EPTPC1_BASE) + #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE) + #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) + #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #if (BSP_FEATURE_OPAMP_BASE_ADDRESS == 2U) + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE) + #else + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) + #endif + #define R_PDC ((R_PDC_Type *) R_PDC_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +#endif + +#endif diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h index 52e18073c..68983b5cb 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -89,6 +89,14 @@ extern "C" { #define __FPU_PRESENT 0 /*!< FPU present or not */ #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ #include "core_cm23.h" /*!< Cortex-M23 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M33) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #define __DSP_PRESENT 1 /*!< DSP present or not */ + #include "core_cm33.h" /*!< Cortex-M33 processor and core peripherals */ #endif #include "system.h" /*!< System */ @@ -1870,6 +1878,14 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + /** * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) */ @@ -2281,12 +2297,36 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 2; + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ } ADCSR_b; }; - __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * "1" while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; union { @@ -2362,7 +2402,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure * (ADADC.ADC[2:0] = 010b) */ } ADADC_b; }; - __IM uint8_t RESERVED1; + __IM uint8_t RESERVED; union { @@ -2372,7 +2412,8 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure { uint16_t : 1; __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 2; + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ uint16_t : 2; __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ @@ -2419,7 +2460,9 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure * Group B in group scan mode. */ __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for * Group B in group scan mode. */ - uint16_t : 4; + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ } ADEXICR_b; }; @@ -2519,7 +2562,43 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure * storing the result of A/D conversion. */ } ADDR_b[28]; }; - __IM uint16_t RESERVED2[7]; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; union { @@ -2535,7 +2614,148 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure uint16_t : 5; } ADSHCR_b; }; - __IM uint16_t RESERVED3[9]; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED2; union { @@ -2548,7 +2768,20 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure uint8_t : 3; } ADDISCR_b; }; - __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; union { @@ -2572,28 +2805,41 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure uint8_t : 6; } ADICR_b; }; - __IM uint16_t RESERVED5; + __IM uint16_t RESERVED3; union { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 13; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ } ADGSPCR_b; }; - __IM uint16_t RESERVED6; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; union { @@ -2618,7 +2864,18 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure * triggers during extended operation in double trigger mode. */ } ADDBLDRB_b; }; - __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED4; union { @@ -2634,7 +2891,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ } ADHVREFCNT_b; }; - __IM uint8_t RESERVED8; + __IM uint8_t RESERVED5; union { @@ -2652,8 +2909,8 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure uint8_t : 2; } ADWINMON_b; }; - __IM uint8_t RESERVED9; - __IM uint16_t RESERVED10; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; union { @@ -2829,7 +3086,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure uint8_t : 6; } ADCMPSER_b; }; - __IM uint8_t RESERVED11; + __IM uint8_t RESERVED8; union { @@ -2844,7 +3101,7 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ } ADCMPBNSR_b; }; - __IM uint8_t RESERVED12; + __IM uint8_t RESERVED9; union { @@ -2883,1711 +3140,1516 @@ typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure uint8_t : 7; } ADCMPBSR_b; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14[23]; - __IM uint8_t RESERVED15; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; union { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; union { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; union { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; union { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; union { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; - __IM uint8_t RESERVED16; union { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; - __IM uint8_t RESERVED17; - __IM uint16_t RESERVED18; union { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ struct { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; }; union { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ struct { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[82]; union { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ struct { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - uint16_t : 4; - } ADPGACR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; }; union { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ struct { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - uint16_t : 4; - } ADPGAGS0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; }; - __IM uint16_t RESERVED21[6]; union { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ struct { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 2; - } ADPGADCR0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; }; -} R_ADC0_Type; /*!< Size = 434 (0x1b2) */ - -/* =========================================================================================================================== */ -/* ================ R_AGT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Asynchronous General Purpose Timer (R_AGT0) - */ -typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ -{ union { - __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ struct { - __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written - * to the TSTOP bit in the AGTCRn register, the 16-bit counter - * is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; }; union { - __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ struct { - __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; }; union { - __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ struct { - __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; }; - __IM uint16_t RESERVED; union { - __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; }; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; }; + __IM uint8_t RESERVED12; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; }; - __IM uint8_t RESERVED1; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[4]; + __IM uint8_t RESERVED15; union { - __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating - * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; }; union { - __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; }; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; }; union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ struct { - uint8_t : 4; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; }; -} R_AGT0_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ - -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ - -typedef struct /*!< (@ 0x40044600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ struct { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; }; + __IM uint8_t RESERVED16; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ struct { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; }; + __IM uint8_t RESERVED17; + __IM uint16_t RESERVED18; union { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ struct { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; union { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ struct { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[82]; union { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ struct { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ struct { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; - }; - + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint16_t RESERVED21[6]; + union { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ struct { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; }; + __IM uint16_t RESERVED22; union { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ struct { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED23[21]; + + union + { + __IOM uint8_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint8_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint8_t : 1; + __IOM uint8_t MONSEL : 4; /*!< [7..4] Monitor output selection bit. */ + } ADREFMON_b; + }; + __IM uint8_t RESERVED24; + __IM uint16_t RESERVED25; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ /* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ +/* ================ R_PSCU ================ */ /* =========================================================================================================================== */ /** - * @brief Controller Area Network (CAN) Module (R_CAN0) + * @brief Peripheral Security Control Unit (R_PSCU) */ -typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ { - __IM uint32_t RESERVED[128]; - __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + __IM uint32_t RESERVED; union { - __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 3; - } MKR_b[8]; + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; }; union { - __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } FIDCR_b[2]; + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 12; + __IOM uint32_t PSARC26 : 1; /*!< [26..26] CANFD1 and the MSTPCRC.MSTPC26 bit security attribution */ + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; }; union { - __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ struct { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ - } MKIVLR_b; + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC12 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 9; + } PSARD_b; }; union { - union - { - __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ - } MIER_b; - }; + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - union + struct { - __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox - * Mode */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - } MIER_FIFO_b; - }; + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; }; - __IM uint32_t RESERVED1[252]; union { - union + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct { - __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; - struct - { - __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ - __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox - * setting enabled) */ - __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting - * enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_TX_b[32]; - }; + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ - union + struct { - __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ - - struct - { - __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ - __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting - * enabled) */ - __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_RX_b[32]; - }; + uint32_t : 15; + __IM uint32_t CFS1 : 9; /*!< [23..15] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONA_b; }; union { - __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ struct { - __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ - __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ - __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ - __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ - __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ - __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ - __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ - __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ - __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ - __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ - uint16_t : 2; - } CTLR_b; - }; - - union - { - __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ - - struct - { - __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ - __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ - __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ - __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ - __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ - __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ - __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ - __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ - __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ - __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ - __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ - __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ - __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ - __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ - __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ - uint16_t : 1; - } STR_b; - }; - - union - { - __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ - - struct - { - __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ - uint32_t : 7; - __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ - uint32_t : 1; - __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ - uint32_t : 2; - __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the - * frequency of the CAN communication clock (fCANCLK). */ - uint32_t : 2; - __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ - } BCR_b; + uint32_t : 10; + __IM uint32_t CFS2 : 14; /*!< [23..10] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONB_b; }; union { - __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ struct { - __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ - __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ - __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ - __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ - __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ - __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ - } RFCR_b; + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; }; union { - __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ struct { - __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented - * by writing FFh to RFPCR. */ - } RFPCR_b; + uint32_t : 13; + __IM uint32_t SS1 : 8; /*!< [20..13] SRAM Secure area 1 */ + uint32_t : 11; + } SSAMONA_b; }; union { - __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ struct { - __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ - __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ - uint8_t : 2; - __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ - __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ - } TFCR_b; + uint32_t : 10; + __IM uint32_t SS2 : 11; /*!< [20..10] SRAM secure area 2 */ + uint32_t : 11; + } SSAMONB_b; }; union { - __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ struct { - __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented - * by writing FFh to TFPCR. */ - } TFPCR_b; + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ - union - { - __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ - __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ - __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ - __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ - __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ - __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ - __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ - __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ - } EIER_b; - }; +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ union { - __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ - __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ - __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ - __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ - __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ - __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ - __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ - __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ - } EIFR_b; + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; }; union { - __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ struct { - __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements - * the counter value according to the error status of the - * CAN module during reception. */ - } RECR_b; + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; union { - __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ struct { - __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements - * the counter value according to the error status of the - * CAN module during transmission. */ - } TECR_b; + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ struct { - __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ - __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ - __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ - __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ - __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ - __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ - __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ - __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ - } ECSR_b; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; union { - __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ struct { - __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel - * number is output to MSSR. */ - } CSSR_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ struct { - __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output - * the smallest mailbox number that is searched in each mode - * of MSMR. */ - uint8_t : 2; - __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ - } MSSR_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; + __IM uint8_t RESERVED1; union { - __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ struct { - __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ - uint8_t : 6; - } MSMR_b; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ struct { - __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ - } TSR_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; union { - __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ struct { - __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, - * the value converted for data table search can be read. */ - } AFSR_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ struct { - __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ - __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ - uint8_t : 5; - } TCR_b; + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ +} R_AGT0_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ -/* ================ R_CRC ================ */ +/* ================ R_BUS ================ */ /* =========================================================================================================================== */ /** - * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + * @brief Bus Interface (R_BUS) */ -typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ { - union - { - __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ - - struct - { - __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ - uint8_t : 3; - __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ - __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ - } CRCCR0_b; - }; + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ struct { - uint8_t : 6; - __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ - __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ - } CRCCR1_b; - }; - __IM uint16_t RESERVED; - - union - { - union - { - __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ - - struct - { - __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ - } CRCDIR_b; - }; - - union - { - __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ - - struct - { - __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT - * ) */ - } CRCDIR_BY_b; - }; - }; - - union - { - union - { - __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ - - struct - { - __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ - } CRCDOR_b; - }; - - union - { - __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ - - struct - { - __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT - * ) */ - } CRCDOR_HA_b; - }; - - union - { - __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ - - struct - { - __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ - } CRCDOR_BY_b; - }; - }; - - union - { - __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ - - struct - { - __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ - uint16_t : 2; - } CRCSAR_b; + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; }; - __IM uint16_t RESERVED1; -} R_CRC_Type; /*!< Size = 16 (0x10) */ + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ /* =========================================================================================================================== */ -/* ================ R_CTSU ================ */ +/* ================ R_CAC ================ */ /* =========================================================================================================================== */ /** - * @brief Capacitive Touch Sensing Unit (R_CTSU) + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) */ -typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ { union { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { - __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ - __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - uint8_t : 2; - __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ - } CTSUCR0_b; + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; }; union { - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ struct { - __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ - __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ - __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ - __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ - __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ - __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ - } CTSUCR1_b; + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; }; union { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ struct { - __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended - * setting: 3 (0011b) */ - __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - uint8_t : 1; - } CTSUSDPRS_b; + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; }; union { - __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ struct { - __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value - * of these bits should be fixed to 00010000b. */ - } CTSUSST_b; + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; }; union { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ struct { - __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits - * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] - * bits = 00b).Note2: If the value of CTSUMCH0 was set to - * b'111111 in mode other than self-capacitor single scan - * mode, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH0_b; + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ struct { - __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 - * was set to b'111111, the measurement is stopped. */ - uint8_t : 2; - } CTSUMCH1_b; + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; }; union { - __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ struct { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ - } CTSUCHAC_b[5]; + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; }; union { - __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ struct { - __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ - __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ - } CTSUCHTRC_b[5]; + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ union { - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ struct { - __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should - * be set to 00b. */ - uint8_t : 2; - __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should - * be set to 11b. */ - uint8_t : 2; - } CTSUDCLKC_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; }; union { - __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ struct { - __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ - uint8_t : 1; - __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ - __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ - __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ - __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ - } CTSUST_b; + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; }; union { - __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion - * Control Register */ + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ struct { - uint16_t : 8; - __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ - uint16_t : 4; - } CTSUSSC_b; + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; }; union { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ - struct + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union { - __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is - * CTSUSO ( 0 to 1023 ) */ - __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ - } CTSUSO0_b; + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; }; + __IM uint32_t RESERVED1[252]; union { - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - struct + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union { - __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount - * is CTSUSO ( 0 to 255 ) */ - __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( - * CTSUSDPA + 1 ) x 2 */ - __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ - uint16_t : 1; - } CTSUSO1_b; + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; }; union { - __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ struct { - __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement - * result of the CTSU. These bits indicate FFFFh when an overflow - * occurs. */ - } CTSUSC_b; + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; }; union { - __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ struct { - __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement - * result of the reference ICO.These bits indicate FFFFh when - * an overflow occurs. */ - } CTSURC_b; + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; }; union { - __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ struct { - uint16_t : 15; - __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ - } CTSUERRS_b; + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; }; -} R_CTSU_Type; /*!< Size = 30 (0x1e) */ -/* =========================================================================================================================== */ -/* ================ R_CTSU2 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ -/** - * @brief Capacitive Touch Sensing Unit (R_CTSU2) - */ + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; -typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ -{ union { - union + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct { - __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; - struct - { - __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ - __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ - __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ - __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ - __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ - __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ - __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ - __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power Supply Enable */ - __IOM uint32_t CSW : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control */ - __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ - __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ - __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ - __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ - __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ - __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ - __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ - __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Measurement Load Control */ - __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ - __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ - __IOM uint32_t FCMODE : 1; /*!< [23..23] CTSU SUCLK Control */ - __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ - __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ - __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ - } CTSUCRA_b; - }; + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ struct { - union - { - __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ - - struct - { - __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ - __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ - }; - }; - __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ - __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ - }; + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; }; union { - union - { - __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ - - struct - { - __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment */ - __IOM uint32_t PRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ - __IOM uint32_t SOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ - __IOM uint32_t PROFF : 1; /*!< [7..7] CTSU Random Number Off Control */ - __IOM uint32_t SST : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control */ - uint32_t : 8; - __IOM uint32_t SSMOD : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select */ - uint32_t : 1; - __IOM uint32_t SSCNT : 2; /*!< [29..28] CTSU SUCLK Diffusion Control */ - uint32_t : 2; - } CTSUCRB_b; - }; + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ struct { - union - { - __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ - - struct - { - __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ - __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ - }; - }; - - union - { - __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ - - struct - { - __IM uint8_t RESERVED; - __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ - }; - }; - }; + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; }; union { - union - { - __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - - struct - { - __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ - uint32_t : 2; - __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ - uint32_t : 2; - __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ - __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ - __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ - __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ - uint32_t : 12; - } CTSUMCH_b; - }; + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ struct { - union - { - __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; - struct - { - __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ - }; - }; + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ - union - { - __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ - __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ - }; - }; + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; }; union { - union + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct { - __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; - struct - { - __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ - uint32_t : 1; - __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ - uint32_t : 1; - __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ - uint32_t : 2; - __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ - __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ - } CTSUCHACA_b; - }; + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ struct { - union - { - __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - - struct - { - __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ - }; - }; + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; - union - { - __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ - struct - { - __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ - __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ - }; - }; - }; + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; }; union { - union - { - __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ - struct - { - __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ - __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ - __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ - __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ - uint32_t : 28; - } CTSUCHACB_b; - }; - __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ - __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; }; union { - union + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct { - __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register - * A */ + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; - struct - { - __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; - __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ - uint32_t : 1; - __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ - uint32_t : 2; - __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ - __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ - } CTSUCHTRCA_b; - }; + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ struct { - union - { - __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register - * A */ - - struct - { - __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register - * A */ - __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register - * A */ - }; - }; + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; - union - { - __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register - * A */ + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ - struct - { - __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register - * A */ - __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register - * A */ - }; - }; - }; + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; }; union { - union - { - __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register - * B */ + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ - struct - { - __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ - __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ - __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ - __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ - uint32_t : 28; - } CTSUCHTRCB_b; - }; - __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register - * B */ - __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register - * B */ + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; }; union { - union + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct { - __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ - struct - { - __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ - uint32_t : 3; - __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ - __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ - __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ - __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ - uint32_t : 1; - __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ - __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ - uint32_t : 1; - __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ - __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ - uint32_t : 10; - } CTSUSR_b; - }; +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ struct { - union - { - __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; - struct - { - __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ - __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ - }; - }; + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ - union - { - __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ - __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ - }; - }; + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; }; + __IM uint16_t RESERVED; union { union { - __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ struct { - __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ - __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ - uint32_t : 2; - __IOM uint32_t SSDIV : 4; /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting */ - __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ - } CTSUSO_b; + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; }; - struct + union { - __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ - __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; }; }; @@ -4595,7556 +4657,9807 @@ typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure { union { - __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ struct { - __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ - uint32_t : 16; - } CTSUSCNT_b; + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; }; - __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ - }; - union - { union { - __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ struct { - uint32_t : 2; - __IOM uint32_t TSOD : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select */ - __IOM uint32_t DRV : 1; /*!< [3..3] CTSU Calibration Setting Bit 1 */ - uint32_t : 2; - __IOM uint32_t SUCLKEN : 1; /*!< [6..6] CTSU SUCLK Enable Control */ - __IOM uint32_t TSOC : 1; /*!< [7..7] CTSU Calibration Setting Bit 2 */ - uint32_t : 1; - __IOM uint32_t IOC : 1; /*!< [9..9] CTSU Transfer Pins Control */ - __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select */ - __IOM uint32_t DCOFF : 1; /*!< [11..11] CTSU Down Converter Control */ - uint32_t : 10; - __IOM uint32_t CFCMODE : 1; /*!< [22..22] CTSU CFC Current Source Switching */ - uint32_t : 2; - __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control */ - uint32_t : 1; - __IOM uint32_t SUCARRY : 1; /*!< [27..27] CTSU CCO Carry Control */ - __IOM uint32_t DACCLK : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select */ - __IOM uint32_t CCOCLK : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select */ - __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select */ - uint32_t : 1; - } CTSUCALIB_b; + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; }; - struct + union { - __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ - __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; }; }; union { - __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ struct { - __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ - __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ - }; + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ union { - union - { - __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ - - struct - { - __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ - __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ - __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ - } CTSUSUCLKB_b; - }; + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ struct { - __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ - __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ - }; + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; }; union { - union - { - __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ - struct - { - __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ - uint32_t : 16; - } CTSUCFCCNT_b; - }; - __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; }; -} R_CTSU2_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief D/A Converter (R_DAC) - */ -typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ -{ union { - __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ struct { - __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order - * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL - * = 1, the low-order 4 bits are fixed to 0: left justified - * format. */ - } DADR_b[2]; + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; }; union { - __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ struct { - uint8_t : 5; - __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ - __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ - __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ - } DACR_b; + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; }; union { - __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ struct { - uint8_t : 7; - __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ - } DADPR_b; + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; }; union { - __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ struct { - uint8_t : 7; - __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ - } DAADSCR_b; + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; }; union { - __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ struct { - __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ - uint8_t : 5; - } DAVREFCR_b; + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; }; union { - __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ struct { - uint8_t : 6; - __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ - __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ - } DAAMPCR_b; + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; }; union { - __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ struct { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ - uint8_t : 7; - } DAPC_b; + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; }; - __IM uint16_t RESERVED[9]; union { - __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ struct { - uint8_t : 6; - __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 0. When DAASW0 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 0. When the DAASW0 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 0 is output - * through the output amplifier. */ - __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure - * to wait for stabilization of the output amplifier of D/A - * channel 1. When DAASW1 is set to 1, D/A conversion operates, - * but the conversion result D/A is not output from channel - * 1. When the DAASW1 bit is 0, the stabilization wait time - * stops, and the D/A conversion result of channel 1 is output - * through the output amplifier. */ - } DAASWCR_b; + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2[2129]; union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for - * D/A and A/D synchronous conversions. Set bit [1] to 1 to - * select unit 1 as the target synchronous unit for the MCU. - * When setting the DAADSCR.DAADST bit to 1 for synchronous - * conversions, select the target unit in this register in - * advance. Only set the DAADUSR register while the ADCSR.ADST - * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit - * is set to 0. */ - uint8_t : 1; - } DAADUSR_b; + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ - -/* =========================================================================================================================== */ -/* ================ R_DAC8 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief 8-Bit D/A Converter (R_DAC8) - */ -typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ -{ union { - __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ struct { - __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ - } DACS_b[2]; + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; }; - __IM uint8_t RESERVED; union { - __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ struct { - __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ - __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ - uint8_t : 2; - __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ - __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ - uint8_t : 2; - } DAM_b; + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; }; - __IM uint8_t RESERVED1[2]; union { - __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ struct { - __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ - uint8_t : 7; - } DACADSCR_b; + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; }; union { - __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ struct { - __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ - uint8_t : 7; - } DACPC_b; - }; -} R_DAC8_Type; /*!< Size = 8 (0x8) */ + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 3; + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ -/* ================ R_DALI0 ================ */ +/* ================ R_CTSU2 ================ */ /* =========================================================================================================================== */ /** - * @brief Digital Addressable Lighting Interface (R_DALI0) + * @brief Capacitive Touch Sensing Unit (R_CTSU2) */ -typedef struct /*!< (@ 0x4008F000) R_DALI0 Structure */ +typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ { union { - __IOM uint16_t BTVTHR1; /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register - * 1 */ - - struct + union { - __IOM uint16_t BTV1 : 7; /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing - * violation threshold value 1.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - uint16_t : 1; - __IOM uint16_t BTV2 : 8; /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing - * violation threshold value 2.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - } BTVTHR1_b; - }; + __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ - union - { - __IOM uint16_t BTVTHR2; /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register - * 2 */ + struct + { + __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ + __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ + __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ + __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power Supply Enable */ + __IOM uint32_t CSW : 1; /*!< [9..9] CTSU LPF Capacitance Charging Control */ + __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ + __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ + __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ + __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ + __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ + __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ + __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ + __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Measurement Load Control */ + __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ + __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ + __IOM uint32_t FCMODE : 1; /*!< [23..23] CTSU SUCLK Control */ + __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ + __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ + __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ + } CTSUCRA_b; + }; struct { - __IOM uint16_t BTV3 : 8; /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing - * violation threshold value 3.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - __IOM uint16_t BTV4 : 8; /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing - * violation threshold value 4.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - } BTVTHR2_b; - }; - - union - { - __IOM uint16_t BTVTHR3; /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register - * 3 */ + union + { + __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ - struct - { - __IOM uint16_t BTV5 : 8; /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing - * violation threshold value 5.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - uint16_t : 8; - } BTVTHR3_b; + struct + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ + }; + }; + __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ + __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ + }; }; union { - __IOM uint16_t BTVTHR4; /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register - * 4 */ - - struct + union { - __IOM uint16_t BTV6 : 9; /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing - * violation threshold value 6.Note 1. These bits must be - * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE - * bit is 0. */ - uint16_t : 7; - } BTVTHR4_b; - }; + __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ - union - { - __IOM uint16_t COLTHR1; /*!< (@ 0x00000008) DALI Collision Threshold Register 1 */ + struct + { + __IOM uint32_t PRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count Adjustment */ + __IOM uint32_t PRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint32_t SOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + __IOM uint32_t PROFF : 1; /*!< [7..7] CTSU Random Number Off Control */ + __IOM uint32_t SST : 8; /*!< [15..8] CTSU Sensor Stabilization Wait Control */ + uint32_t : 8; + __IOM uint32_t SSMOD : 3; /*!< [26..24] CTSU SUCLK Diffusion Mode Select */ + uint32_t : 1; + __IOM uint32_t SSCNT : 2; /*!< [29..28] CTSU SUCLK Diffusion Control */ + uint32_t : 2; + } CTSUCRB_b; + }; struct { - __IOM uint16_t COL1 : 6; /*!< [5..0] Collision Threshold 1Specifies the collision threshold - * value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 2; - __IOM uint16_t COL2 : 6; /*!< [13..8] Collision Threshold 2Specifies the collision threshold - * value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 2; - } COLTHR1_b; - }; + union + { + __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ - union - { - __IOM uint16_t COLTHR2; /*!< (@ 0x0000000A) DALI Collision Threshold Register 2 */ + struct + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ + }; + }; - struct - { - __IOM uint16_t COL3 : 7; /*!< [6..0] Collision Threshold 3Specifies the collision threshold - * value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - __IOM uint16_t COL4 : 7; /*!< [14..8] Collision Threshold 4Specifies the collision threshold - * value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - } COLTHR2_b; + union + { + __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ + + struct + { + __IM uint8_t RESERVED; + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ + }; + }; + }; }; union { - __IOM uint16_t COLTHR3; /*!< (@ 0x0000000C) DALI Collision Threshold Register 3 */ - - struct + union { - __IOM uint16_t COL5 : 7; /*!< [6..0] Collision Threshold 5Specifies the collision threshold - * value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - __IOM uint16_t COL6 : 7; /*!< [14..8] Collision Threshold 6Specifies the collision threshold - * value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 1; - } COLTHR3_b; - }; + __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - union - { - __IOM uint16_t COLTHR4; /*!< (@ 0x0000000E) DALI Collision Threshold Register 4 */ + struct + { + __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ + uint32_t : 2; + __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ + uint32_t : 2; + __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ + uint32_t : 12; + } CTSUMCH_b; + }; struct { - __IOM uint16_t COL7 : 8; /*!< [7..0] Collision Threshold 7Specifies the collision threshold - * value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - __IOM uint16_t COL8 : 8; /*!< [15..8] Collision Threshold 8Specifies the collision threshold - * value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - } COLTHR4_b; - }; + union + { + __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ - union - { - __IOM uint16_t COLTHR5; /*!< (@ 0x00000010) DALI Collision Threshold Register 5 */ + struct + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ + }; + }; - struct - { - __IOM uint16_t COL9 : 8; /*!< [7..0] Collision Threshold 9Specifies the collision threshold - * value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE - * bit is 0 and the DALI0.CTR1.TE bit is 0. */ - uint16_t : 8; - } COLTHR5_b; + union + { + __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + }; + }; }; union { - __IOM uint16_t CNFR1; /*!< (@ 0x00000012) DALI Configuration Register 1 */ - - struct + union { - __IOM uint16_t BR : 8; /*!< [7..0] Clock SelectBit rate setting example is shown in Table */ - __IOM uint16_t CKS : 2; /*!< [9..8] Clock Select */ - uint16_t : 2; - __IOM uint16_t CHL : 3; /*!< [14..12] Character Length */ - uint16_t : 1; - } CNFR1_b; - }; + __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - union - { - __IOM uint16_t CNFR2; /*!< (@ 0x00000014) DALI Configuration Register 2 */ + struct + { + __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ + uint32_t : 2; + __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ + } CTSUCHACA_b; + }; struct { - __IOM uint16_t BTVE : 1; /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t BTVM : 1; /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t SGA : 1; /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t TXWE : 1; /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t CDE : 1; /*!< [4..4] Collision Detect EnableNote: The bit must be modified - * only when the DALI0.STR1.BBF bit is 0. */ - __IOM uint16_t CDM0 : 1; /*!< [5..5] Collision Detect ModeNote: The bit must be modified only - * when the DALI0.STR1.BBF bit is 0. */ - uint16_t : 10; - } CNFR2_b; - }; + union + { + __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ - union - { - __IOM uint16_t TXWR1; /*!< (@ 0x00000016) DALI DTX Width Register 1 */ + struct + { + __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ + }; + }; - struct - { - __IOM uint16_t TXLW : 7; /*!< [6..0] DTX Low WidthDTX0 pin low level width */ - uint16_t : 9; - } TXWR1_b; + union + { + __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ + }; + }; + }; }; - __IM uint16_t RESERVED[3]; union { - __IOM uint16_t TDR1H; /*!< (@ 0x0000001E) DALI Transmit Data Register 1H */ - - struct + union { - __IOM uint16_t DTDR : 16; /*!< [15..0] Upper 16-bit DALI transmit data */ - } TDR1H_b; + __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + + struct + { + __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ + uint32_t : 28; + } CTSUCHACB_b; + }; + __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ }; union { - __IOM uint16_t TDR1L; /*!< (@ 0x00000020) DALI Transmit Data Register 1L */ - - struct + union { - __IOM uint16_t DTDR : 16; /*!< [15..0] Lower 16-bit DALI transmit data */ - } TDR1L_b; - }; + __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ - union - { - __OM uint16_t TRSTR1; /*!< (@ 0x00000022) DALI Transmit Control Register 1 */ + struct + { + __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ + uint32_t : 2; + __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ + } CTSUCHTRCA_b; + }; struct { - __OM uint16_t TRST : 1; /*!< [0..0] Transmission Start Trigger */ - uint16_t : 15; - } TRSTR1_b; - }; - __IM uint16_t RESERVED1; + union + { + __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ - union - { - __IOM uint16_t CTR1; /*!< (@ 0x00000026) DALI Control Register 1 */ + struct + { + __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; - struct - { - __IOM uint16_t TE : 1; /*!< [0..0] Transmit Enabling */ - __IOM uint16_t RE : 1; /*!< [1..1] Receive Enabling */ - uint16_t : 6; - __IOM uint16_t SDIE : 1; /*!< [8..8] DALI_SDI Output Enabling */ - __IOM uint16_t DEIE : 1; /*!< [9..9] DALI_DEI Output Enabling */ - __IOM uint16_t CLIE : 1; /*!< [10..10] DALI_CLI Output Enabling */ - __IOM uint16_t BPIE : 1; /*!< [11..11] DALI_BPI Output Enabling */ - __IOM uint16_t FEIE : 1; /*!< [12..12] DALI_FEI Output Enabling */ - uint16_t : 3; - } CTR1_b; + union + { + __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + }; }; union { - __IOM uint16_t TXDCTR1; /*!< (@ 0x00000028) DALI DTX Control Register 1 */ - - struct + union { - __IOM uint16_t TXAS : 1; /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only - * when the DALI0.CTR1.TE bit is 0. */ - __IOM uint16_t TXASE : 1; /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only - * when the DALI0.CTR1.TE bit is 0. */ - uint16_t : 14; - } TXDCTR1_b; + __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + + struct + { + __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ + uint32_t : 28; + } CTSUCHTRCB_b; + }; + __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ }; - __IM uint16_t RESERVED2[2]; union { - __IM uint16_t RDR1H; /*!< (@ 0x0000002E) DALI Reception Data Register 1H */ - - struct + union { - __IM uint16_t DRDR : 16; /*!< [15..0] Upper 16-bit of DALI receive data */ - } RDR1H_b; - }; + __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ - union - { - __IM uint16_t RDR1L; /*!< (@ 0x00000030) DALI Reception Data Register 1L */ + struct + { + __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ + uint32_t : 3; + __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ + __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ + __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ + __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ + uint32_t : 1; + __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ + __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ + uint32_t : 1; + __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ + __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ + uint32_t : 10; + } CTSUSR_b; + }; struct { - __IM uint16_t DRDR : 16; /*!< [15..0] Lower 16-bit of DALI receive data */ - } RDR1L_b; - }; - + union + { + __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ + }; + }; + + union + { + __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ + __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ + }; + }; + }; + union { - __IM uint16_t STR1; /*!< (@ 0x00000032) DALI Status Register 1 */ + union + { + __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ + __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ + uint32_t : 2; + __IOM uint32_t SSDIV : 4; /*!< [23..20] CTSU Spectrum Diffusion Frequency Division Setting */ + __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ + } CTSUSO_b; + }; struct { - __IM uint16_t MFEF : 1; /*!< [0..0] Manchester Flaming Error Flag */ - __IM uint16_t OVF : 1; /*!< [1..1] Overrun Error Flag */ - __IM uint16_t BTVF : 1; /*!< [2..2] Bit Timing Violation Flag */ - __IM uint16_t RDRF : 1; /*!< [3..3] Receive Data Register Full Flag */ - __IM uint16_t TENDF : 1; /*!< [4..4] Transmit End Flag */ - __IM uint16_t BBF : 1; /*!< [5..5] Bus BUSY Flag */ - __IM uint16_t BPDF : 1; /*!< [6..6] Bus Power Down Flag */ - __IM uint16_t O32F : 1; /*!< [7..7] Over 32-Bit Data Reception Flag */ - __IM uint16_t CDF : 1; /*!< [8..8] Collision Detect Flag */ - __IM uint16_t DAF : 1; /*!< [9..9] Destroy Area Flag */ - __IM uint16_t RDBL : 6; /*!< [15..10] Receive Data Bit LengthThese bits store the bit length - * for data received successfully */ - } STR1_b; + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ + }; }; - __IM uint16_t RESERVED3; union { - __IM uint16_t COLR1; /*!< (@ 0x00000036) DALI Collision Register 1 */ - - struct + union { - __IM uint16_t CFTF2 : 4; /*!< [3..0] Collision Detect Timing Flag 2 */ - __IM uint16_t CDTF1 : 1; /*!< [4..4] Collision Detect Timing Flag 1 */ - uint16_t : 5; - __IM uint16_t CLDAF : 1; /*!< [10..10] Collision Last Destroy Area Flag */ - __IM uint16_t RXDMON : 1; /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after - * the DRX0 pin is synchronized */ - __IM uint16_t RXDCEG : 1; /*!< [12..12] DRX Collision Edge */ - __IM uint16_t TXDCV : 1; /*!< [13..13] DTX Collision Value */ - uint16_t : 2; - } COLR1_b; + __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + + struct + { + __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ + uint32_t : 16; + } CTSUSCNT_b; + }; + __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ }; - __IM uint16_t RESERVED4; union { - __OM uint16_t FECR1; /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1 */ + union + { + __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TSOD : 1; /*!< [2..2] CTSU TS Pins Fixed Output Select */ + __IOM uint32_t DRV : 1; /*!< [3..3] CTSU Calibration Setting Bit 1 */ + uint32_t : 2; + __IOM uint32_t SUCLKEN : 1; /*!< [6..6] CTSU SUCLK Enable Control */ + __IOM uint32_t TSOC : 1; /*!< [7..7] CTSU Calibration Setting Bit 2 */ + uint32_t : 1; + __IOM uint32_t IOC : 1; /*!< [9..9] CTSU Transfer Pins Control */ + __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CTSU CFC Counter Read Mode Select */ + __IOM uint32_t DCOFF : 1; /*!< [11..11] CTSU Down Converter Control */ + uint32_t : 10; + __IOM uint32_t CFCMODE : 1; /*!< [22..22] CTSU CFC Current Source Switching */ + uint32_t : 2; + __IOM uint32_t DACCARRY : 1; /*!< [25..25] CTSU DAC Upper Current Source Carry Control */ + uint32_t : 1; + __IOM uint32_t SUCARRY : 1; /*!< [27..27] CTSU CCO Carry Control */ + __IOM uint32_t DACCLK : 1; /*!< [28..28] CTSU DAC Modulation Circuit Clock Select */ + __IOM uint32_t CCOCLK : 1; /*!< [29..29] CTSU CCO Modulation Circuit Clock Select */ + __IOM uint32_t CCOCALIB : 1; /*!< [30..30] CTSU CCO Calibration Mode Select */ + uint32_t : 1; + } CTSUCALIB_b; + }; struct { - __OM uint16_t MFEFC : 1; /*!< [0..0] Manchester Flaming Error Flag Clear */ - __OM uint16_t OVFC : 1; /*!< [1..1] Overrun Error Flag Clear */ - __OM uint16_t BTVFC : 1; /*!< [2..2] Bit Timing Violation Flag Clear */ - __OM uint16_t RDRFC : 1; /*!< [3..3] Receive Data Register Full Flag Clear */ - __OM uint16_t TENDFC : 1; /*!< [4..4] Transmit End Flag Clear */ - __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF - * bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. */ - __OM uint16_t BPDFC : 1; /*!< [6..6] Bus Power Down Flag Clear */ - __OM uint16_t O32FC : 1; /*!< [7..7] Over 32-Bit Data Reception Flag Clear */ - __OM uint16_t CDFC : 1; /*!< [8..8] Collision Detect Flag Clear */ - __OM uint16_t DAFC : 1; /*!< [9..9] Destroy Area Flag Clear */ - uint16_t : 6; - } FECR1_b; + __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ + }; }; union { - __OM uint16_t SWRR1; /*!< (@ 0x0000003C) DALI Software Reset Register 1 */ + __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ struct { - __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software - * reset. */ - uint16_t : 15; - } SWRR1_b; + __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ + }; }; -} R_DALI0_Type; /*!< Size = 62 (0x3e) */ - -/* =========================================================================================================================== */ -/* ================ R_DEBUG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Debug Function (R_DEBUG) - */ -typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ -{ union { - __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + union + { + __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + + struct + { + __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKB_b; + }; struct { - uint32_t : 28; - __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ - __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ - uint32_t : 2; - } DBGSTR_b; + __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ + }; }; - __IM uint32_t RESERVED[3]; union { - __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ - - struct + union { - __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ - __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ - uint32_t : 14; - __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ - __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ - uint32_t : 5; - __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ - __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ - uint32_t : 6; - } DBGSTOPCR_b; + __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + + struct + { + __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ + uint32_t : 16; + } CTSUCFCCNT_b; + }; + __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ }; -} R_DEBUG_Type; /*!< Size = 20 (0x14) */ +} R_CTSU2_Type; /*!< Size = 56 (0x38) */ /* =========================================================================================================================== */ -/* ================ R_DMA ================ */ +/* ================ R_DAC ================ */ /* =========================================================================================================================== */ /** - * @brief DMA Controller Common (R_DMA) + * @brief D/A Converter (R_DAC) */ -typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ { union { - __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ struct { - __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ - uint8_t : 7; - } DMAST_b; + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; }; -} R_DMA_Type; /*!< Size = 1 (0x1) */ -/* =========================================================================================================================== */ -/* ================ R_DMAC0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ -/** - * @brief DMA Controller (R_DMAC0) - */ + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; -typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ -{ union { - __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ struct { - __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ - } DMSAR_b; + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; }; union { - __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ struct { - __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ - } DMDAR_b; + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; }; union { - __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ struct { - __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ - __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ - uint32_t : 6; - } DMCRA_b; + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; }; union { - __IOM uint16_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ struct { - __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or - * repeat transfer operations. */ - } DMCRB_b; + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ struct { - __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ - uint16_t : 6; - __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ - uint16_t : 2; - __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ - __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ - } DMTMD_b; + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; }; - __IM uint8_t RESERVED1; + __IM uint16_t RESERVED[9]; union { - __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ struct { - __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt - * Enable */ - __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ - __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ - __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ - uint8_t : 3; - } DMINT_b; + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; union { - __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the - * extended repeat area on the destination address. For details - * on the settings. */ - uint16_t : 1; - __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ - __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended - * repeat area on the source address. For details on the settings. */ - uint16_t : 1; - __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ - } DMAMD_b; + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; }; - __IM uint16_t RESERVED2; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 8-Bit D/A Converter (R_DAC8) + */ +typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ +{ union { - __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ struct { - __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected - * as the address update mode for transfer source or destination. */ - } DMOFR_b; + __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ + } DACS_b[2]; }; + __IM uint8_t RESERVED; union { - __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ struct { - __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ - uint8_t : 7; - } DMCNT_b; + __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ + __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ + uint8_t : 2; + __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ + __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ + uint8_t : 2; + } DAM_b; }; + __IM uint8_t RESERVED1[2]; union { - __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ struct { - __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ - uint8_t : 3; - __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ - uint8_t : 3; - } DMREQ_b; + __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ + uint8_t : 7; + } DACADSCR_b; }; union { - __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ struct { - __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ - uint8_t : 3; - __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ - uint8_t : 2; - __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ - } DMSTS_b; + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ + uint8_t : 7; + } DACPC_b; }; - __IM uint8_t RESERVED3; -} R_DMAC0_Type; /*!< Size = 32 (0x20) */ +} R_DAC8_Type; /*!< Size = 8 (0x8) */ /* =========================================================================================================================== */ -/* ================ R_DOC ================ */ +/* ================ R_DALI0 ================ */ /* =========================================================================================================================== */ /** - * @brief Data Operation Circuit (R_DOC) + * @brief Digital Addressable Lighting Interface (R_DALI0) */ -typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +typedef struct /*!< (@ 0x4008F000) R_DALI0 Structure */ { union { - __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + __IOM uint16_t BTVTHR1; /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register + * 1 */ struct { - __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ - __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ - uint8_t : 2; - __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ - __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ - uint8_t : 1; - } DOCR_b; + __IOM uint16_t BTV1 : 7; /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing + * violation threshold value 1.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 1; + __IOM uint16_t BTV2 : 8; /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing + * violation threshold value 2.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + } BTVTHR1_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + __IOM uint16_t BTVTHR2; /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register + * 2 */ struct { - __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for - * use in the operations are stored. */ - } DODIR_b; + __IOM uint16_t BTV3 : 8; /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing + * violation threshold value 3.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + __IOM uint16_t BTV4 : 8; /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing + * violation threshold value 4.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + } BTVTHR2_b; }; union { - __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + __IOM uint16_t BTVTHR3; /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register + * 3 */ struct { - __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference - * in data comparison mode. This register also stores the - * results of operations in data addition and data subtraction - * modes. */ - } DODSR_b; + __IOM uint16_t BTV5 : 8; /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing + * violation threshold value 5.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 8; + } BTVTHR3_b; }; -} R_DOC_Type; /*!< Size = 6 (0x6) */ - -/* =========================================================================================================================== */ -/* ================ R_DRW ================ */ -/* =========================================================================================================================== */ - -/** - * @brief 2D Drawing Engine (R_DRW) - */ -typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ -{ union { - union - { - __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ - - struct - { - __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ - __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ - __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ - __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ - __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ - __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ - __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ - __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ - __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ - __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ - __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ - __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ - __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ - __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ - __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ - __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ - __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ - __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ - __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ - __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ - __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ - __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ - __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per - * scanline */ - __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line - * span start */ - uint32_t : 8; - } CONTROL_b; - }; + __IOM uint16_t BTVTHR4; /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register + * 4 */ - union + struct { - __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ - - struct - { - __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ - __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ - __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ - __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ - __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ - __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ - __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ - uint32_t : 1; - __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ - __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ - __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ - uint32_t : 21; - } STATUS_b; - }; + __IOM uint16_t BTV6 : 9; /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing + * violation threshold value 6.Note 1. These bits must be + * modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE + * bit is 0. */ + uint16_t : 7; + } BTVTHR4_b; }; union { - union - { - __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + __IOM uint16_t COLTHR1; /*!< (@ 0x00000008) DALI Collision Threshold Register 1 */ - struct - { - __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and - * COLOR2 depending on PATTERN and pattern index) */ - __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha - * to blend between COLOR1 and COLOR2 */ - __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default - * U limiter.Limiter 5 can be combined with limiter 6 to form - * a quadratic limiter which can be used to make quadratic - * pattern functions to draw radial patterns. */ - __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ - __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT - * above for description */ - __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel - * blending mode (USEACB = 1) */ - __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel - * blending mode (USEACB = 1) */ - __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above - * description. */ - __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per - * default) */ - __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor - * is 1 per default) */ - __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted - * (meaning 1-a or 1-1 depending on BSF) */ - __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will - * be inverted (meaning 1-a or 1-1 depending on BDF) */ - __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ - __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes - * what happens if the U limiter (x direction in texture space) - * calculates a U value outside of the used texture */ - __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes - * what happens if the V limiter (y direction in texture space) - * calculates a V value outside of the used texture */ - __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ - __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ - __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: - * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: - * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) - * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), - * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), - * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), - * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), - * 1 bit indexed color/luminance */ - __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ - __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha - * source' for the framebuffer(USEACB = 0)Blend alpha in color - * 2 instead of framebuffer alpha((USEACB = 1))In not alpha - * channel blending mode (USEACB = 0):Set the 'alpha source' - * for the framebuffer.In alpha channel blending mode (USEACB - * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: - * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: - * BC2A = 0: use alpha in color 2 as destination (DST_A) */ - __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ - __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ - __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ - __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ - __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB - * = 1) */ - __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel - * (USEACB = 1) */ - __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ - } CONTROL2_b; - }; - - union + struct { - __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ - - struct - { - __IM uint32_t REV : 12; /*!< [11..0] Revision number */ - uint32_t : 5; - __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ - __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ - __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ - __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ - __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ - uint32_t : 1; - __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ - __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ - __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ - uint32_t : 1; - __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ - uint32_t : 4; - } HWREVISION_b; - }; + __IOM uint16_t COL1 : 6; /*!< [5..0] Collision Threshold 1Specifies the collision threshold + * value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 2; + __IOM uint16_t COL2 : 6; /*!< [13..8] Collision Threshold 2Specifies the collision threshold + * value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 2; + } COLTHR1_b; }; - __IM uint32_t RESERVED[2]; union { - __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + __IOM uint16_t COLTHR2; /*!< (@ 0x0000000A) DALI Collision Threshold Register 2 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L1START_b; + __IOM uint16_t COL3 : 7; /*!< [6..0] Collision Threshold 3Specifies the collision threshold + * value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + __IOM uint16_t COL4 : 7; /*!< [14..8] Collision Threshold 4Specifies the collision threshold + * value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + } COLTHR2_b; }; union { - __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + __IOM uint16_t COLTHR3; /*!< (@ 0x0000000C) DALI Collision Threshold Register 3 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L2START_b; + __IOM uint16_t COL5 : 7; /*!< [6..0] Collision Threshold 5Specifies the collision threshold + * value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + __IOM uint16_t COL6 : 7; /*!< [14..8] Collision Threshold 6Specifies the collision threshold + * value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 1; + } COLTHR3_b; }; union { - __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + __IOM uint16_t COLTHR4; /*!< (@ 0x0000000E) DALI Collision Threshold Register 4 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L3START_b; + __IOM uint16_t COL7 : 8; /*!< [7..0] Collision Threshold 7Specifies the collision threshold + * value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + __IOM uint16_t COL8 : 8; /*!< [15..8] Collision Threshold 8Specifies the collision threshold + * value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + } COLTHR4_b; }; union { - __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + __IOM uint16_t COLTHR5; /*!< (@ 0x00000010) DALI Collision Threshold Register 5 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L4START_b; + __IOM uint16_t COL9 : 8; /*!< [7..0] Collision Threshold 9Specifies the collision threshold + * value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE + * bit is 0 and the DALI0.CTR1.TE bit is 0. */ + uint16_t : 8; + } COLTHR5_b; }; union { - __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + __IOM uint16_t CNFR1; /*!< (@ 0x00000012) DALI Configuration Register 1 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L5START_b; + __IOM uint16_t BR : 8; /*!< [7..0] Clock SelectBit rate setting example is shown in Table */ + __IOM uint16_t CKS : 2; /*!< [9..8] Clock Select */ + uint16_t : 2; + __IOM uint16_t CHL : 3; /*!< [14..12] Character Length */ + uint16_t : 1; + } CNFR1_b; }; union { - __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + __IOM uint16_t CNFR2; /*!< (@ 0x00000014) DALI Configuration Register 2 */ struct { - __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ - } L6START_b; + __IOM uint16_t BTVE : 1; /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t BTVM : 1; /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t SGA : 1; /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t TXWE : 1; /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t CDE : 1; /*!< [4..4] Collision Detect EnableNote: The bit must be modified + * only when the DALI0.STR1.BBF bit is 0. */ + __IOM uint16_t CDM0 : 1; /*!< [5..5] Collision Detect ModeNote: The bit must be modified only + * when the DALI0.STR1.BBF bit is 0. */ + uint16_t : 10; + } CNFR2_b; }; union { - __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + __IOM uint16_t TXWR1; /*!< (@ 0x00000016) DALI DTX Width Register 1 */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L1XADD_b; + __IOM uint16_t TXLW : 7; /*!< [6..0] DTX Low WidthDTX0 pin low level width */ + uint16_t : 9; + } TXWR1_b; }; + __IM uint16_t RESERVED[3]; union { - __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + __IOM uint16_t TDR1H; /*!< (@ 0x0000001E) DALI Transmit Data Register 1H */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L2XADD_b; + __IOM uint16_t DTDR : 16; /*!< [15..0] Upper 16-bit DALI transmit data */ + } TDR1H_b; }; union { - __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + __IOM uint16_t TDR1L; /*!< (@ 0x00000020) DALI Transmit Data Register 1L */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L3XADD_b; + __IOM uint16_t DTDR : 16; /*!< [15..0] Lower 16-bit DALI transmit data */ + } TDR1L_b; }; union { - __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + __OM uint16_t TRSTR1; /*!< (@ 0x00000022) DALI Transmit Control Register 1 */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L4XADD_b; + __OM uint16_t TRST : 1; /*!< [0..0] Transmission Start Trigger */ + uint16_t : 15; + } TRSTR1_b; }; + __IM uint16_t RESERVED1; union { - __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + __IOM uint16_t CTR1; /*!< (@ 0x00000026) DALI Control Register 1 */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L5XADD_b; + __IOM uint16_t TE : 1; /*!< [0..0] Transmit Enabling */ + __IOM uint16_t RE : 1; /*!< [1..1] Receive Enabling */ + uint16_t : 6; + __IOM uint16_t SDIE : 1; /*!< [8..8] DALI_SDI Output Enabling */ + __IOM uint16_t DEIE : 1; /*!< [9..9] DALI_DEI Output Enabling */ + __IOM uint16_t CLIE : 1; /*!< [10..10] DALI_CLI Output Enabling */ + __IOM uint16_t BPIE : 1; /*!< [11..11] DALI_BPI Output Enabling */ + __IOM uint16_t FEIE : 1; /*!< [12..12] DALI_FEI Output Enabling */ + uint16_t : 3; + } CTR1_b; }; union { - __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + __IOM uint16_t TXDCTR1; /*!< (@ 0x00000028) DALI DTX Control Register 1 */ struct { - __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ - } L6XADD_b; + __IOM uint16_t TXAS : 1; /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only + * when the DALI0.CTR1.TE bit is 0. */ + __IOM uint16_t TXASE : 1; /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only + * when the DALI0.CTR1.TE bit is 0. */ + uint16_t : 14; + } TXDCTR1_b; }; + __IM uint16_t RESERVED2[2]; union { - __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + __IM uint16_t RDR1H; /*!< (@ 0x0000002E) DALI Reception Data Register 1H */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L1YADD_b; + __IM uint16_t DRDR : 16; /*!< [15..0] Upper 16-bit of DALI receive data */ + } RDR1H_b; }; union { - __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + __IM uint16_t RDR1L; /*!< (@ 0x00000030) DALI Reception Data Register 1L */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L2YADD_b; + __IM uint16_t DRDR : 16; /*!< [15..0] Lower 16-bit of DALI receive data */ + } RDR1L_b; }; union { - __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + __IM uint16_t STR1; /*!< (@ 0x00000032) DALI Status Register 1 */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L3YADD_b; + __IM uint16_t MFEF : 1; /*!< [0..0] Manchester Flaming Error Flag */ + __IM uint16_t OVF : 1; /*!< [1..1] Overrun Error Flag */ + __IM uint16_t BTVF : 1; /*!< [2..2] Bit Timing Violation Flag */ + __IM uint16_t RDRF : 1; /*!< [3..3] Receive Data Register Full Flag */ + __IM uint16_t TENDF : 1; /*!< [4..4] Transmit End Flag */ + __IM uint16_t BBF : 1; /*!< [5..5] Bus BUSY Flag */ + __IM uint16_t BPDF : 1; /*!< [6..6] Bus Power Down Flag */ + __IM uint16_t O32F : 1; /*!< [7..7] Over 32-Bit Data Reception Flag */ + __IM uint16_t CDF : 1; /*!< [8..8] Collision Detect Flag */ + __IM uint16_t DAF : 1; /*!< [9..9] Destroy Area Flag */ + __IM uint16_t RDBL : 6; /*!< [15..10] Receive Data Bit LengthThese bits store the bit length + * for data received successfully */ + } STR1_b; }; + __IM uint16_t RESERVED3; union { - __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + __IM uint16_t COLR1; /*!< (@ 0x00000036) DALI Collision Register 1 */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L4YADD_b; - }; - - union - { - __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ - - struct - { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L5YADD_b; + __IM uint16_t CFTF2 : 4; /*!< [3..0] Collision Detect Timing Flag 2 */ + __IM uint16_t CDTF1 : 1; /*!< [4..4] Collision Detect Timing Flag 1 */ + uint16_t : 5; + __IM uint16_t CLDAF : 1; /*!< [10..10] Collision Last Destroy Area Flag */ + __IM uint16_t RXDMON : 1; /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after + * the DRX0 pin is synchronized */ + __IM uint16_t RXDCEG : 1; /*!< [12..12] DRX Collision Edge */ + __IM uint16_t TXDCV : 1; /*!< [13..13] DTX Collision Value */ + uint16_t : 2; + } COLR1_b; }; + __IM uint16_t RESERVED4; union { - __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + __OM uint16_t FECR1; /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1 */ struct { - __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ - } L6YADD_b; + __OM uint16_t MFEFC : 1; /*!< [0..0] Manchester Flaming Error Flag Clear */ + __OM uint16_t OVFC : 1; /*!< [1..1] Overrun Error Flag Clear */ + __OM uint16_t BTVFC : 1; /*!< [2..2] Bit Timing Violation Flag Clear */ + __OM uint16_t RDRFC : 1; /*!< [3..3] Receive Data Register Full Flag Clear */ + __OM uint16_t TENDFC : 1; /*!< [4..4] Transmit End Flag Clear */ + __OM uint16_t BBFC : 1; /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF + * bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. */ + __OM uint16_t BPDFC : 1; /*!< [6..6] Bus Power Down Flag Clear */ + __OM uint16_t O32FC : 1; /*!< [7..7] Over 32-Bit Data Reception Flag Clear */ + __OM uint16_t CDFC : 1; /*!< [8..8] Collision Detect Flag Clear */ + __OM uint16_t DAFC : 1; /*!< [9..9] Destroy Area Flag Clear */ + uint16_t : 6; + } FECR1_b; }; union { - __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + __OM uint16_t SWRR1; /*!< (@ 0x0000003C) DALI Software Reset Register 1 */ struct { - __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ - } L1BAND_b; + __OM uint16_t SWR : 1; /*!< [0..0] Software ResetWriting 1 to this bit causes a software + * reset. */ + uint16_t : 15; + } SWRR1_b; }; +} R_DALI0_Type; /*!< Size = 62 (0x3e) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ union { - __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ struct { - __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ - } L2BAND_b; + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; }; - __IM uint32_t RESERVED1; + __IM uint32_t RESERVED[3]; union { - __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ struct { - __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ - __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ - __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ - __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: - * opaque) */ - } COLOR1_b; + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ union { - __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ struct { - __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ - __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ - __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ - __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: - * opaque) */ - } COLOR2_b; + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; }; - __IM uint32_t RESERVED2[2]; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; union { - __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ struct { - __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ - uint32_t : 24; - } PATTERN_b; + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ union { - __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ struct { - __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to - * 1024 */ - __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 - * to 1024 */ - } SIZE_b; + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; }; union { - __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ struct { - __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used - * to render bottom-up instead of top-down */ - __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ - } PITCH_b; + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; }; union { - __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ struct { - __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ - } ORIGIN_b; + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; }; - __IM uint32_t RESERVED3[3]; union { - __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + __IOM uint16_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ struct { - __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ - } LUSTART_b; + __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; }; + __IM uint16_t RESERVED; union { - __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ struct { - __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ - } LUXADD_b; + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; }; + __IM uint8_t RESERVED1; union { - __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ struct { - __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ - } LUYADD_b; + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; }; union { - __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ struct { - __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ - } LVSTARTI_b; + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; }; + __IM uint16_t RESERVED2; union { - __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ struct { - __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ - uint32_t : 16; - } LVSTARTF_b; + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; }; union { - __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ struct { - __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ - } LVXADDI_b; + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; }; union { - __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ struct { - __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ - } LVYADDI_b; + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; }; union { - __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ struct { - __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ - __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ - } LVYXADDF_b; + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; }; - __IM uint32_t RESERVED4; + __IM uint8_t RESERVED3; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ union { - __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ struct { - __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ - } TEXPITCH_b; + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; }; union { - __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ struct { - __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture - * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width - * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX - * = 1):all widths up to 2048 are allowed. */ - __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = - * 0): texture_height must be a power of 2In texture clamping - * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 - * are allowed. */ - } TEXMASK_b; + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; }; union { - __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ struct { - __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ - } TEXORIGIN_b; + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ - union - { - __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ - struct - { - __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ - __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ - __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ - __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ - __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ - __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ - uint32_t : 26; - } IRQCTL_b; - }; +/** + * @brief Data Operation Circuit (R_DOC) + */ +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ union { - __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ struct { - __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ - __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ - __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ - __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ - uint32_t : 28; - } CACHECTL_b; + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; }; + __IM uint8_t RESERVED; union { - __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ struct { - __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ - } DLISTSTART_b; + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; }; union { - __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ struct { - __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT - * = 0000 0000H. */ - } PERFCOUNT1_b; + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ +{ union { - __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ - struct + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union { - __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT - * = 0000 0000H. */ - } PERFCOUNT2_b; + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; }; union { - __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ - struct + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union { - __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 - * register. */ - __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 - * register */ - } PERFTRIGGER_b; + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; }; - __IM uint32_t RESERVED5; + __IM uint32_t RESERVED[2]; union { - __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ struct { - __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ - uint32_t : 24; - } TEXCLADDR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; }; union { - __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ struct { - __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ - } TEXCLDATA_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; }; union { - __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ struct { - __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] - * is or'ed with the original index */ - uint32_t : 24; - } TEXCLOFFSET_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; }; union { - __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ struct { - __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ - __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ - __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ - uint32_t : 8; - } COLKEY_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; }; -} R_DRW_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_DTC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Data Transfer Controller (R_DTC) - */ -typedef struct /*!< (@ 0x40005400) R_DTC Structure */ -{ union { - __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ struct { - uint8_t : 4; - __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ - uint8_t : 3; - } DTCCR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; union { - __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ struct { - __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set - * in the lower-order 10 bits. These bits are fixed to 0. */ - } DTCVBR_b; + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ struct { - __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ - uint8_t : 7; - } DTCST_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; }; - __IM uint8_t RESERVED3; union { - __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ struct { - __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate - * the vector number for the activating source when DTC transfer - * is in progress.The value is only valid if DTC transfer - * is in progress (the value of the ACT flag is 1) */ - uint16_t : 7; - __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ - } DTCSTS_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; }; -} R_DTC_Type; /*!< Size = 16 (0x10) */ - -/* =========================================================================================================================== */ -/* ================ R_ELC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Event Link Controller (R_ELC) - */ -typedef struct /*!< (@ 0x40041000) R_ELC Structure */ -{ union { - __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ struct { - uint8_t : 7; - __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ - } ELCR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; }; - __IM uint8_t RESERVED; - __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ - __IM uint16_t RESERVED1[5]; - __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ -} R_ELC_Type; /*!< Size = 108 (0x6c) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet MAC Controller (R_ETHERC0) - */ -typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ -{ union { - __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ struct { - __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ - __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ - __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ - __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ - uint32_t : 1; - __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ - __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ - uint32_t : 2; - __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ - uint32_t : 2; - __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ - uint32_t : 3; - __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ - __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ - __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ - __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ - __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ - uint32_t : 11; - } ECMR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ struct { - __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the - * maximum frame length. The minimum value that can be set - * is 1,518 bytes, and the maximum value that can be set is - * 2,048 bytes. Values that are less than 1,518 bytes are - * regarded as 1,518 bytes, and values larger than 2,048 bytes - * are regarded as 2,048 bytes. */ - uint32_t : 20; - } RFLR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; }; - __IM uint32_t RESERVED1; union { - __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ struct { - __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ - __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ - __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ - uint32_t : 1; - __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ - __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ - uint32_t : 26; - } ECSR_b; + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ struct { - __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ - __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ - __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ - __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ - uint32_t : 26; - } ECSIPR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; }; - __IM uint32_t RESERVED3; union { - __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ struct { - __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output - * from the ETn_MDC pin to supply the management data clock - * to the MII or RMII. */ - __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ - __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output - * from the ETn_MDIO pin when the MMD bit is 1 (write). The - * value is not output when the MMD bit is 0 (read). */ - __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level - * of the ETn_MDIO pin. The write value should be 0. */ - uint32_t : 28; - } PIR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; }; - __IM uint32_t RESERVED4; union { - __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ struct { - __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read - * by connecting the link signal output from the PHY-LSI to - * the ETn_LINKSTA pin. For details on the polarity, refer - * to the specifications of the connected PHY-LSI. */ - uint32_t : 31; - } PSR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; }; - __IM uint32_t RESERVED5[5]; union { - __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit - * Setting Register */ + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ struct { - __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ - uint32_t : 12; - } RDMLR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; }; - __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ struct { - __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ - uint32_t : 27; - } IPGR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; }; union { - __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ struct { - __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value - * of the pause_time parameter for a PAUSE frame that is automatically - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. */ - uint32_t : 16; - } APR_b; + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; }; union { - __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ struct { - __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of - * the pause_time parameter for a PAUSE frame that is manually - * transmitted. Transmission is not performed until the set - * value multiplied by 512 bit time has elapsed. The read - * value is undefined. */ - uint32_t : 16; - } MPR_b; + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; }; - __IM uint32_t RESERVED7; union { - __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ struct { - __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ - uint32_t : 24; - } RFCF_b; + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ struct { - __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ - uint32_t : 16; - } TPAUSER_b; + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; }; - __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ union { - __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ struct { - __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ - uint32_t : 16; - } BCFRR_b; + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; }; - __IM uint32_t RESERVED8[20]; + __IM uint32_t RESERVED2[2]; union { - __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ struct { - __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets - * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ - } MAHR_b; + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; }; - __IM uint32_t RESERVED9; union { - __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ struct { - __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets - * the lower 16 bits of the 48-bit MAC address. */ - uint32_t : 16; - } MALR_b; + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; }; - __IM uint32_t RESERVED10; union { - __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ struct { - __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register - * is a counter indicating the number of frames that fail - * to be retransmitted. */ - } TROCR_b; - }; - __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; union { - __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ struct { - __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a - * counter indicating the number of times a loss of carrier - * is detected during frame transmission. */ - } LCCR_b; + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; }; + __IM uint32_t RESERVED3[3]; union { - __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ struct { - __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register - * is a counter indicating the number of times a carrier is - * not detected during preamble transmission. */ - } CNDCR_b; + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; }; - __IM uint32_t RESERVED11; union { - __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ struct { - __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register - * is a counter indicating the number of received frames where - * a CRC error has been detected. */ - } CEFCR_b; + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; }; union { - __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ struct { - __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register - * is a counter indicating the number of times a frame receive - * error has occurred. */ - } FRECR_b; + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; }; union { - __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ struct { - __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register - * is a counter indicating the number of times a short frame - * that is shorter than 64 bytes has been received. */ - } TSFRCR_b; + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; }; union { - __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ struct { - __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register - * is a counter indicating the number of times a long frame - * that is longer than the RFLR register value has been received. */ - } TLFRCR_b; + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; }; union { - __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ struct { - __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR - * register is a counter indicating the number of times a - * frame has been received with the alignment error (frame - * is not an integral number of octets). */ - } RFCR_b; + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; }; union { - __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ struct { - __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe - * MAFCR register is a counter indicating the number of times - * a frame where the multicast address is set has been received. */ - } MAFCR_b; + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; }; -} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EDMAC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) - */ -typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ -{ union { - __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ struct { - __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ - uint32_t : 3; - __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ - __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting - * applies to data for the transmit/receive buffer. It does - * not apply to transmit/receive descriptors and registers. */ - uint32_t : 25; - } EDMR_b; + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; }; - __IM uint32_t RESERVED; + __IM uint32_t RESERVED4; union { - __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ struct { - __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ - uint32_t : 31; - } EDTRR_b; + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; }; - __IM uint32_t RESERVED1; union { - __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ struct { - __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ - uint32_t : 31; - } EDRRR_b; + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ struct { - __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } TDLAR_b; + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; }; - __IM uint32_t RESERVED3; union { - __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ struct { - __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is - * set. Set the start address according to the descriptor - * length selected by the EDMR.DL[1:0] bits.16-byte boundary: - * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte - * boundary: Lower 6 bits = 000000b */ - } RDLAR_b; + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; }; - __IM uint32_t RESERVED4; union { - __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ struct { - __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ - __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ - __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ - __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ - __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ - uint32_t : 2; - __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ - __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ - __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ - __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ - __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ - uint32_t : 4; - __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ - __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ - __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ - __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ - __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ - __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ - __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source - * in the ETHERCn.ECSR register is cleared, the ECI flag is - * also cleared. */ - __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ - __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ - __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ - __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ - uint32_t : 3; - __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ - uint32_t : 1; - } EESR_b; + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; }; - __IM uint32_t RESERVED5; union { - __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ struct { - __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ - __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ - __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ - __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ - __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ - uint32_t : 2; - __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ - __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ - __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ - __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ - __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ - uint32_t : 4; - __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ - __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ - __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ - __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ - __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ - __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ - __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ - __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ - __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ - __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ - uint32_t : 3; - __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ - uint32_t : 1; - } EESIPR_b; + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; }; - __IM uint32_t RESERVED6; union { - __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable - * Register */ + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ struct { - uint32_t : 4; - __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ - uint32_t : 2; - __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ - uint32_t : 24; - } TRSCER_b; + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; }; - __IM uint32_t RESERVED7; union { - __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ struct { - __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of - * frames that are discarded and not transferred to the receive - * buffer during reception. */ - uint32_t : 16; - } RMFCR_b; + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; }; - __IM uint32_t RESERVED8; union { - __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ struct { - __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is - * the set value multiplied by 4. Example: 00Dh: 52 bytes - * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ - uint32_t : 21; - } TFTR_b; - }; - __IM uint32_t RESERVED9; - - union - { - __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ - - struct - { - __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ - uint32_t : 3; - __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ - uint32_t : 19; - } FDR_b; + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; }; - __IM uint32_t RESERVED10; + __IM uint32_t RESERVED5; union { - __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ struct { - __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ - uint32_t : 31; - } RMCR_b; + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; }; - __IM uint32_t RESERVED11[2]; union { - __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ struct { - __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how - * many times the transmit FIFO has underflowed. The counter - * stops when the counter value reaches FFFFh. */ - uint32_t : 16; - } TFUCR_b; + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; }; union { - __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ struct { - __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many - * times the receive FIFO has overflowed. The counter stops - * when the counter value reaches FFFFh. */ - uint32_t : 16; - } RFOCR_b; + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; }; union { - __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ struct { - __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ - uint32_t : 31; - } IOSR_b; + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; }; +} R_DRW_Type; /*!< Size = 236 (0xec) */ - union - { - __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 - * bytes of data is stored in the receive FIFO.) */ - uint32_t : 13; - __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) - * receive frames have been stored in the receive FIFO.) */ - uint32_t : 13; - } FCFTR_b; - }; - __IM uint32_t RESERVED12; +/** + * @brief Data Transfer Controller (R_DTC) + */ +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ union { - __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ struct { - __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ - uint32_t : 10; - __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ - uint32_t : 14; - } RPADIR_b; + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; union { - __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ struct { - __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in - * the mode selected by the TIM bit to notify an interrupt. */ - uint32_t : 3; - __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ - uint32_t : 27; - } TRIMD_b; + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; }; - __IM uint32_t RESERVED13[18]; + __IM uint32_t RESERVED2; union { - __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ struct { - __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register - * indicates the last address that the EDMAC has written data - * to when writing to the receive buffer.Refer to the address - * indicated by the RBWAR register to recognize which address - * in the receive buffer the EDMAC is writing data to. Note - * that the address that the EDMAC is outputting to the receive - * buffer may not match the read value of the RBWAR register - * during data reception. */ - } RBWAR_b; + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; }; + __IM uint8_t RESERVED3; union { - __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ struct { - __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register - * indicates the start address of the last fetched receive - * descriptor when the EDMAC fetches descriptor information - * from the receive descriptor.Refer to the address indicated - * by the RDFAR register to recognize which receive descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the receive descriptor that the - * EDMAC fetches may not match the read value of the RDFAR - * register during data reception. */ - } RDFAR_b; + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; }; - __IM uint32_t RESERVED14; union { - __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ struct { - __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register - * indicates the last address that the EDMAC has read data - * from when reading data from the transmit buffer.Refer to - * the address indicated by the TBRAR register to recognize - * which address in the transmit buffer the EDMAC is reading - * from. Note that the address that the EDMAC is outputting - * to the transmit buffer may not match the read value of - * the TBRAR register. */ - } TBRAR_b; + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; union { - __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ struct { - __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR - * register indicates the start address of the last fetched - * transmit descriptor when the EDMAC fetches descriptor information - * from the transmit descriptor.Refer to the address indicated - * by the TDFAR register to recognize which transmit descriptor - * information the EDMAC is using for the current processing. - * Note that the address of the transmit descriptor that the - * EDMAC fetches may not match the read value of the TDFAR - * register. */ - } TDFAR_b; + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; }; -} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ +} R_DTC_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ -/* ================ R_ETHERC_EPTPC ================ */ +/* ================ R_ELC ================ */ /* =========================================================================================================================== */ /** - * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) + * @brief Event Link Controller (R_ELC) */ -typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ { union { - __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ struct { - __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ - __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ - __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ - uint32_t : 1; - __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ - __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ - __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ - uint32_t : 5; - __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ - uint32_t : 1; - __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ - uint32_t : 1; - __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ - __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ - uint32_t : 14; - } SYSR_b; + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; union { - __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ struct { - __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ - __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ - __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ - uint32_t : 1; - __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ - __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ - __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ - uint32_t : 5; - __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ - uint32_t : 1; - __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ - uint32_t : 1; - __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ - __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ - uint32_t : 14; - } SYIPR_b; + __IOM uint16_t ELSEGR0 : 1; /*!< [0..0] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [1..1] Event Link Software Event Generation Register 1Security + * Attribution */ + __IOM uint16_t ELCR : 1; /*!< [2..2] Event Link Controller RegisterSecurity Attribution */ + uint16_t : 13; + } ELCSARA_b; }; - __IM uint32_t RESERVED[2]; + __IM uint16_t RESERVED3; union { - __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ struct { - __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the local MAC address. */ - uint32_t : 8; - } SYMACRU_b; + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; }; + __IM uint16_t RESERVED4; union { - __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ struct { - __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits - * of the local MAC address. */ - uint32_t : 8; - } SYMACRL_b; + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ - union - { - __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the - * control field in the LLC sublayer when generating IEEE802.3 - * frames. */ - uint32_t : 24; - } SYLLCCTLR_b; - }; +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ +typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ +{ union { - __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ struct { - __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ - } SYIPADDRR_b; - }; - __IM uint32_t RESERVED1[8]; - + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + union { - __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ struct { - __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the - * versionPTP field value of the PTP v2 header.When a message - * is received, this value is compared with the versionPTP - * field of the received frame.In generating messages, the - * value is used for the versionPTP field of the frame for - * transmission.Set these bits to 0010b (PTP v2). */ - __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set - * the transportSpecific field value of the PTP v2 header.When - * a message is received, this value is compared with the - * transportSpecific field of the received frame.In generating - * messages, the value is used for the transportSpecific field - * of the frame for transmission.Set these bits to 0000b (IEEE - * 1588). */ - uint32_t : 24; - } SYSPVRR_b; + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ struct { - __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to - * set the domainNumber field value of the PTP v2 header.When - * a message is received, this value is compared with the - * domainNumber field of the received frame as a condition - * for PTP reception processing.In generating messages, the - * value is used for the domainNumber field of the frame for - * transmission. */ - uint32_t : 24; - } SYDOMR_b; + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; }; - __IM uint32_t RESERVED2[2]; + __IM uint32_t RESERVED2; union { - __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ struct { - __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the - * leap61 member of timePropertiesDS. */ - __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the - * leap59 member of timePropertiesDS. */ - __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical - * value of the currentUtcOffsetValid member of timePropertiesDS. */ - __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value - * of the ptpTimescale member of timePropertiesDS. */ - __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value - * of the timeTraceable member of timePropertiesDS. */ - __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical - * value of the frequencyTraceable member of timePropertiesDS. */ - uint32_t : 2; - __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ - uint32_t : 1; - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } ANFR_b; + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ struct { - uint32_t : 8; - __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ - __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } SYNFR_b; + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; }; + __IM uint32_t RESERVED4; union { - __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ struct { - uint32_t : 10; - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } DYRQFR_b; + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; }; + __IM uint32_t RESERVED5[5]; union { - __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ struct { - uint32_t : 8; - __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ - __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ - __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ - uint32_t : 2; - __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ - __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ - uint32_t : 17; - } DYRPFR_b; + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; }; + __IM uint32_t RESERVED6[3]; union { - __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ struct { - __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the clock-ID of your port. */ - } SYCIDRU_b; + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" */ + uint32_t : 27; + } IPGR_b; }; union { - __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ struct { - __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the clock-ID of your port. */ - } SYCIDRL_b; + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; }; union { - __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ struct { - __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting - * for the port number of the local port. */ + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ uint32_t : 16; - } SYPNUMR_b; + } MPR_b; }; - __IM uint32_t RESERVED3[5]; + __IM uint32_t RESERVED7; union { - __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ struct { - __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ - __OM uint32_t STUP : 1; /*!< [1..1] State Update */ - __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ - uint32_t : 29; - } SYRVLDR_b; + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ struct { - __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ - __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ - uint32_t : 2; - __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ - __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ - __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ - uint32_t : 1; - __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ - __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ - __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ - uint32_t : 1; - __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ - __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ - __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ - uint32_t : 1; - __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ - __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ - __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ - uint32_t : 1; - __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ - __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ - __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ - uint32_t : 1; - __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ - __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ - __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ - uint32_t : 1; - __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ - __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ - __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ - uint32_t : 1; - } SYRFL1R_b; + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ union { - __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ struct { - __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ - __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ - uint32_t : 2; - __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ - __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ - uint32_t : 22; - __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ - __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ - uint32_t : 2; - } SYRFL2R_b; + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; }; + __IM uint32_t RESERVED8[20]; union { - __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ struct { - __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ - uint32_t : 3; - __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ - uint32_t : 3; - __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ - uint32_t : 3; - __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ - uint32_t : 19; - } SYTRENR_b; + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; }; - __IM uint32_t RESERVED5; + __IM uint32_t RESERVED9; union { - __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ struct { - __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the clock-ID of the master clock. */ - } MTCIDU_b; + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ struct { - __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the clock-ID of the master clock. */ - } MTCIDL_b; + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ union { - __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ struct { - __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the - * setting for the port number of the master clock. */ - uint32_t : 16; - } MTPID_b; + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; }; - __IM uint32_t RESERVED6[5]; union { - __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ struct { - __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits - * set the interval for the transmission of Announce messages. */ - __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits - * set the interval for the transmission of Sync messages. - * The setting is also placed in the logMessageInterval field - * of transmitted Sync messages. */ - __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req - * Transmission Interval SettingThe bits set the average interval - * for the transmission of Delay_Req messages and the interval - * for the transmission of Pdelay_Req messages.The setting - * is also placed in the logMessageInterval field of Delay_Resp - * messages. */ - uint32_t : 8; - } SYTLIR_b; + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; }; + __IM uint32_t RESERVED11; union { - __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication - * Register */ + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ struct { - __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese - * bits indicate the logMessageInterval field value of a received - * Announce message. */ - __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese - * bits indicate the logMessageInterval field value of a received - * Sync message. */ - __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese - * bits indicate the logMessageInterval field value of a received - * Delay_Resp message. */ - uint32_t : 8; - } SYRLIR_b; + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; }; union { - __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ struct { - __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the - * calculated offsetFromMaster value. */ - } OFMRU_b; + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; }; union { - __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ struct { - __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated - * offsetFromMaster value. */ - } OFMRL_b; + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; }; union { - __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ struct { - __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the - * calculated meanPathDelay value. */ - } MPDRU_b; + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; }; union { - __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ struct { - __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated - * meanPathDelay value. */ - } MPDRL_b; + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; }; - __IM uint32_t RESERVED7[2]; union { - __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ struct { - __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are - * used to set the value of the grandmasterPriority2 fields - * of Announce messages. */ - uint32_t : 8; - __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits - * are used to set the value of the grandmasterPriority1 fields - * of Announce messages. */ - uint32_t : 8; - } GMPR_b; + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ +typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +{ union { - __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ struct { - __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality - * fields of Announce messages. The correspondence between - * bits and the grandmasterClockQuality fields is as listed - * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 - * to b0: offsetScaledLogVariance */ - } GMCQR_b; + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; }; + __IM uint32_t RESERVED; union { - __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ struct { - __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the value of the grandmasterIdentity fields of - * Announce messages. */ - } GMIDRU_b; + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ struct { - __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the value of the grandmasterIdentity fields of Announce - * messages. */ - } GMIDRL_b; + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; }; + __IM uint32_t RESERVED2; union { - __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ struct { - __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the - * timeSource fields of Announce messages. */ - uint32_t : 8; - __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value - * of the currentUtcOffset fields of Announce messages. */ - } CUOTSR_b; + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; }; + __IM uint32_t RESERVED3; union { - __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ struct { - __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value - * of the stepsRemoved fields of Announce messages. */ - uint32_t : 16; - } SRR_b; + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; }; - __IM uint32_t RESERVED8[2]; + __IM uint32_t RESERVED4; union { - __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting - * Registers */ + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ struct { - __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the destination MAC address for PTP-primary messages. */ - uint32_t : 8; - } PPMACRU_b; + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; }; + __IM uint32_t RESERVED5; union { - __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting - * Registers */ + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ struct { - __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits - * of the destination MAC address for PTP-primary messages. */ - uint32_t : 8; - } PPMACRL_b; + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; }; + __IM uint32_t RESERVED6; union { - __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ struct { - __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 - * bits of the destination MAC address for PTP-pdelay messages. */ - uint32_t : 8; - } PDMACRU_b; + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; }; + __IM uint32_t RESERVED7; union { - __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ struct { - __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits - * of the destination MAC address for PTP-pdelay messages. */ - uint32_t : 8; - } PDMACRL_b; + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; }; + __IM uint32_t RESERVED8; union { - __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ struct { - __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the - * setting for the EtherType field value for frames in the - * Ethernet II format. */ - uint32_t : 16; - } PETYPER_b; + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; }; - __IM uint32_t RESERVED9[3]; + __IM uint32_t RESERVED9; union { - __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting - * Register */ + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ struct { - __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address - * for PTPprimary messages. */ - } PPIPR_b; + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; }; + __IM uint32_t RESERVED10; union { - __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting - * Register */ + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ struct { - __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address - * for PTPpdelay messages. */ - } PDIPR_b; + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; }; + __IM uint32_t RESERVED11[2]; union { - __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ struct { - __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold - * the setting for the value of the TOS field within the IPv4 - * headers of PTP event messages. */ - uint32_t : 24; - } PETOSR_b; + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; }; union { - __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ struct { - __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits - * hold the setting for the value of the TOS field within - * the IPv4 headers of PTP general messages. */ - uint32_t : 24; - } PGTOSR_b; + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; }; union { - __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ struct { - __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits - * hold the setting for the value of the TTL field within - * the IPv4 headers of PTP-primary messages. */ - uint32_t : 24; - } PPTTLR_b; + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; }; union { - __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ struct { - __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the - * setting for the value of the TTL field within the IPv4 - * headers of PTP-pdelay messages. */ - uint32_t : 24; - } PDTTLR_b; + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; }; + __IM uint32_t RESERVED12; union { - __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number - * Setting Register */ + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ struct { - __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese - * bits hold the setting for the value of the destination - * port number field within the UDP headers of PTP event messages. */ - uint32_t : 16; - } PEUDPR_b; + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; }; union { - __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number - * Setting Register */ + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ struct { - __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits - * hold the setting for the value of the destination port - * number field within the UDP headers of PTP general messages. */ - uint32_t : 16; - } PGUDPR_b; + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; }; + __IM uint32_t RESERVED13[18]; union { - __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ struct { - __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these - * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ - __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits - * is only effective when EXTPRM=0 and ENB=1. */ - __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits - * is only effective when EXTPRM=0. */ - uint32_t : 13; - __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ - uint32_t : 15; - } FFLTR_b; + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; }; - __IM uint32_t RESERVED10[31]; union { - __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ struct { - __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 - * bits of the asymmetric delay value. */ - uint32_t : 16; - } DASYMRU_b; + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; }; + __IM uint32_t RESERVED14; union { - __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ struct { - __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the asymmetric delay value. */ - } DASYMRL_b; + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; }; union { - __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ struct { - __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold - * the setting for the time stamp latency (ns) for the input - * ports. */ - __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold - * the setting for the time stamp latency (ns) for the output - * ports. */ - } TSLATR_b; + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) + */ + +typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ +{ union { - __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ + __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ struct { - __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are - * used to set the time from the completion of one transmission - * to the start of the next in cycles of the transmission - * clock. A value n in these bits means that a transmission - * interval of n cycles will be secured.No interval is secured - * if the setting is 00h.We recommend the setting 28h (40 - * cycles). */ - uint32_t : 4; - __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ - uint32_t : 3; - __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ - uint32_t : 3; - __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ - uint32_t : 11; - } SYCONFR_b; + __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ + __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ + uint32_t : 14; + } SYSR_b; }; union { - __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ + __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ struct { - __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ - __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ - uint32_t : 30; - } SYFORMR_b; + __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ + __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ + uint32_t : 14; + } SYIPR_b; }; + __IM uint32_t RESERVED[2]; union { - __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ struct { - __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response - * message not being received within n x 1024 (ns), where - * n is the setting, is judged to represent a timeout. */ - } RSTOUTR_b; + __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address. */ + uint32_t : 8; + } SYMACRU_b; }; -} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ - -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EPTPC_CFG ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) - */ -typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ -{ union { - __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ + __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ struct { - __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ - uint32_t : 31; - } PTRSTR_b; + __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the local MAC address. */ + uint32_t : 8; + } SYMACRL_b; }; union { - __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ + __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ struct { - __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ - uint32_t : 5; - __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ - uint32_t : 21; - } STCSELR_b; + __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the + * control field in the LLC sublayer when generating IEEE802.3 + * frames. */ + uint32_t : 24; + } SYLLCCTLR_b; }; union { - __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ + __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ struct { - __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ - uint32_t : 15; - __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ - uint32_t : 15; - } BYPASS_b; + __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ + } SYIPADDRR_b; }; -} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + __IM uint32_t RESERVED1[8]; -/* =========================================================================================================================== */ -/* ================ R_ETHERC_EPTPC_COMMON ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ -/** - * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) - */ + struct + { + __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the + * versionPTP field value of the PTP v2 header.When a message + * is received, this value is compared with the versionPTP + * field of the received frame.In generating messages, the + * value is used for the versionPTP field of the frame for + * transmission.Set these bits to 0010b (PTP v2). */ + __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set + * the transportSpecific field value of the PTP v2 header.When + * a message is received, this value is compared with the + * transportSpecific field of the received frame.In generating + * messages, the value is used for the transportSpecific field + * of the frame for transmission.Set these bits to 0000b (IEEE + * 1588). */ + uint32_t : 24; + } SYSPVRR_b; + }; -typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ -{ union { - __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ + __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ struct { - __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ - __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ - __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ - __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ - uint32_t : 12; - __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ - __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ - __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ - __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ - __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ - __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ - uint32_t : 10; - } MIESR_b; + __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to + * set the domainNumber field value of the PTP v2 header.When + * a message is received, this value is compared with the + * domainNumber field of the received frame as a condition + * for PTP reception processing.In generating messages, the + * value is used for the domainNumber field of the frame for + * transmission. */ + uint32_t : 24; + } SYDOMR_b; }; + __IM uint32_t RESERVED2[2]; union { - __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ + __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ struct { - __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ - __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ - __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ - __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ - uint32_t : 12; - __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt - * Request Permission */ - __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt - * Request Permission */ - uint32_t : 10; - } MIEIPR_b; + __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the + * leap61 member of timePropertiesDS. */ + __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the + * leap59 member of timePropertiesDS. */ + __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical + * value of the currentUtcOffsetValid member of timePropertiesDS. */ + __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value + * of the ptpTimescale member of timePropertiesDS. */ + __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value + * of the timeTraceable member of timePropertiesDS. */ + __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical + * value of the frequencyTraceable member of timePropertiesDS. */ + uint32_t : 2; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + uint32_t : 1; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } ANFR_b; }; - __IM uint32_t RESERVED[2]; union { - __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission - * Register */ + __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ struct { - __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output - * Enable */ - uint32_t : 2; - __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output - * Enable */ - __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output - * Enable */ - uint32_t : 2; - __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt - * Request Permission */ - uint32_t : 7; - __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt - * Request Permission */ - uint32_t : 7; - } ELIPPR_b; + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } SYNFR_b; }; union { - __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic - * Clearing Register */ + __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ struct { - __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ - __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ - __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ - __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ - __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ - __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ - uint32_t : 2; - __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ - __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ - __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ - __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ - __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ - __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ - uint32_t : 2; - __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ - uint32_t : 7; - __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ - uint32_t : 7; - } ELIPACR_b; + uint32_t : 10; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRQFR_b; }; - __IM uint32_t RESERVED1[10]; union { - __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ + __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ struct { - __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ - __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ - uint32_t : 1; - __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ - __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ - uint32_t : 27; - } STSR_b; + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRPFR_b; }; union { - __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ + __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ struct { - __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ - __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ - uint32_t : 1; - __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ - __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ - uint32_t : 27; - } STIPR_b; + __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of your port. */ + } SYCIDRU_b; }; - __IM uint32_t RESERVED2[2]; union { - __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ + __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ struct { - __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ - uint32_t : 30; - } STCFR_b; + __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of your port. */ + } SYCIDRL_b; }; union { - __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ + __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ struct { - __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ - uint32_t : 5; - __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ - uint32_t : 1; - __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ - __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ - __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ - uint32_t : 4; - __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ - __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ - uint32_t : 2; - } STMR_b; + __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting + * for the port number of the local port. */ + uint32_t : 16; + } SYPNUMR_b; }; + __IM uint32_t RESERVED3[5]; union { - __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ + __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ struct { - __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), - * where n is the setting, leads to a timeout for reception - * of Sync messages, leading to the STSR.SYNTOUT flag being - * set to 1. */ - } SYNTOR_b; + __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ + __OM uint32_t STUP : 1; /*!< [1..1] State Update */ + __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ + uint32_t : 29; + } SYRVLDR_b; }; - __IM uint32_t RESERVED3; + __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ + __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ struct { - __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ - __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ - __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ - __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ - __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ - __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ - uint32_t : 26; - } IPTSELR_b; + __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ + __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ + uint32_t : 2; + __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ + __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ + __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ + uint32_t : 1; + __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ + __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ + __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ + uint32_t : 1; + __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ + __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ + __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ + __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ + __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ + uint32_t : 1; + } SYRFL1R_b; }; union { - __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ + __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ struct { - __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ - __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ - uint32_t : 26; - } MITSELR_b; + __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ + __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ + uint32_t : 2; + __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ + __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ + uint32_t : 22; + __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ + __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ + uint32_t : 2; + } SYRFL2R_b; }; union { - __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ + __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ struct { - __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ - __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ - __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ - __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ - __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ - __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ - uint32_t : 26; - } ELTSELR_b; + __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ + uint32_t : 19; + } SYTRENR_b; }; + __IM uint32_t RESERVED5; union { - __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ + __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ struct { - __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the - * value of this bit while the SYNSTARTR.STR bit is 1. */ - uint32_t : 31; - } STCHSELR_b; + __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of the master clock. */ + } MTCIDU_b; }; - __IM uint32_t RESERVED4[4]; union { - __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ + __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ struct { - __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ - uint32_t : 31; - } SYNSTARTR_b; + __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of the master clock. */ + } MTCIDL_b; }; union { - __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive - * Register */ + __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ struct { - __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ - uint32_t : 31; - } LCIVLDR_b; + __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the + * setting for the port number of the master clock. */ + uint32_t : 16; + } MTPID_b; }; - __IM uint32_t RESERVED5[2]; + __IM uint32_t RESERVED6[5]; union { - __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ + __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ struct { - __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the threshold for detection of loss of synchronization. */ - } SYNTDARU_b; + __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits + * set the interval for the transmission of Announce messages. */ + __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits + * set the interval for the transmission of Sync messages. + * The setting is also placed in the logMessageInterval field + * of transmitted Sync messages. */ + __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req + * Transmission Interval SettingThe bits set the average interval + * for the transmission of Delay_Req messages and the interval + * for the transmission of Pdelay_Req messages.The setting + * is also placed in the logMessageInterval field of Delay_Resp + * messages. */ + uint32_t : 8; + } SYTLIR_b; }; union { - __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ + __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication + * Register */ struct { - __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the threshold for detection of loss of synchronization. */ - } SYNTDARL_b; + __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Announce message. */ + __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Sync message. */ + __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Delay_Resp message. */ + uint32_t : 8; + } SYRLIR_b; }; union { - __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ + __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ struct { - __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 - * bits of the threshold for detection of synchronization. */ - } SYNTDBRU_b; + __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated offsetFromMaster value. */ + } OFMRU_b; }; union { - __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ + __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ struct { - __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the threshold for detection of synchronization. */ - } SYNTDBRL_b; + __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * offsetFromMaster value. */ + } OFMRL_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ + __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ struct { - __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 - * bits of the integer portion of the initial value for the - * local timer counter. */ - uint32_t : 16; - } LCIVRU_b; + __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated meanPathDelay value. */ + } MPDRU_b; }; union { - __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ + __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ struct { - __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the integer portion of the initial value for the local - * timer counter. */ - } LCIVRM_b; + __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * meanPathDelay value. */ + } MPDRL_b; }; + __IM uint32_t RESERVED7[2]; union { - __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ + __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ struct { - __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion - * of the initial value of the local timer counter in nanoseconds. */ - } LCIVRL_b; + __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are + * used to set the value of the grandmasterPriority2 fields + * of Announce messages. */ + uint32_t : 8; + __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits + * are used to set the value of the grandmasterPriority1 fields + * of Announce messages. */ + uint32_t : 8; + } GMPR_b; }; - __IM uint32_t RESERVED7[26]; union { - __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ + __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ struct { - __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ - uint32_t : 31; - } GETW10R_b; + __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality + * fields of Announce messages. The correspondence between + * bits and the grandmasterClockQuality fields is as listed + * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 + * to b0: offsetScaledLogVariance */ + } GMCQR_b; }; union { - __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ + __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ struct { - __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 - * bits of the limit for the positive gradient. */ - uint32_t : 1; - } PLIMITRU_b; + __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the value of the grandmasterIdentity fields of + * Announce messages. */ + } GMIDRU_b; }; union { - __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ + __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ struct { - __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 - * bits of the limit for the positive gradient. */ - } PLIMITRM_b; + __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the value of the grandmasterIdentity fields of Announce + * messages. */ + } GMIDRL_b; }; union { - __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ + __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ struct { - __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the limit for the positive gradient. */ - } PLIMITRL_b; + __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the + * timeSource fields of Announce messages. */ + uint32_t : 8; + __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value + * of the currentUtcOffset fields of Announce messages. */ + } CUOTSR_b; }; union { - __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ + __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ struct { - __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 - * bits of the limit for the negative gradient. */ - uint32_t : 1; - } MLIMITRU_b; + __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value + * of the stepsRemoved fields of Announce messages. */ + uint32_t : 16; + } SRR_b; }; + __IM uint32_t RESERVED8[2]; union { - __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ + __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting + * Registers */ struct { - __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 - * bits of the limit for the negative gradient. */ - } MLIMITRM_b; + __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRU_b; }; union { - __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ + __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting + * Registers */ struct { - __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits - * of the limit for the negative gradient. */ - } MLIMITRL_b; + __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRL_b; }; union { - __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ + __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ struct { - __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching - * is directed, values of various statistical information - * read before completion of information fetching are not - * guaranteed. */ - uint32_t : 31; - } GETINFOR_b; + __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRU_b; }; - __IM uint32_t RESERVED8[11]; union { - __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ + __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ struct { - __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits - * of the integer portion of the local timer counter's value. */ - uint32_t : 16; - } LCCVRU_b; + __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRL_b; }; union { - __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ + __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ struct { - __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of - * the integer portion of the local timer counter's value. */ - } LCCVRM_b; + __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the + * setting for the EtherType field value for frames in the + * Ethernet II format. */ + uint32_t : 16; + } PETYPER_b; }; + __IM uint32_t RESERVED9[3]; union { - __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ + __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting + * Register */ struct { - __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of - * the local timer counter's value (in nanoseconds). */ - } LCCVRL_b; + __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPprimary messages. */ + } PPIPR_b; }; - __IM uint32_t RESERVED9[37]; union { - __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ + __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting + * Register */ struct { - __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits - * of the positive gradient value. */ - } PW10VRU_b; + __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPpdelay messages. */ + } PDIPR_b; }; union { - __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ + __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ struct { - __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits - * of the positive gradient value. */ - } PW10VRM_b; + __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold + * the setting for the value of the TOS field within the IPv4 + * headers of PTP event messages. */ + uint32_t : 24; + } PETOSR_b; }; union { - __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ + __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ struct { - __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of - * the positive gradient value. */ - } PW10VRL_b; + __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits + * hold the setting for the value of the TOS field within + * the IPv4 headers of PTP general messages. */ + uint32_t : 24; + } PGTOSR_b; }; - __IM uint32_t RESERVED10[45]; union { - __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ + __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ struct { - __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits - * of the negative gradient value. */ - } MW10RU_b; + __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits + * hold the setting for the value of the TTL field within + * the IPv4 headers of PTP-primary messages. */ + uint32_t : 24; + } PPTTLR_b; }; union { - __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ + __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ struct { - __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits - * of the negative gradient value. */ - } MW10RM_b; + __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the + * setting for the value of the TTL field within the IPv4 + * headers of PTP-pdelay messages. */ + uint32_t : 24; + } PDTTLR_b; }; union { - __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ + __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number + * Setting Register */ struct { - __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of - * the negative gradient value. */ - } MW10RL_b; + __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese + * bits hold the setting for the value of the destination + * port number field within the UDP headers of PTP event messages. */ + uint32_t : 16; + } PEUDPR_b; }; - __IM uint32_t RESERVED11[9]; - __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ - __IM uint32_t RESERVED12[7]; union { - __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ + __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number + * Setting Register */ struct { - __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ - __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ - __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ - __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ - __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ - __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ - uint32_t : 26; - } TMSTARTR_b; + __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits + * hold the setting for the value of the destination port + * number field within the UDP headers of PTP general messages. */ + uint32_t : 16; + } PGUDPR_b; }; - __IM uint32_t RESERVED13[32]; union { - __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ + __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ struct { - __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ - __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ - __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ - __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ - uint32_t : 4; - __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ - uint32_t : 19; - __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ - __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ - uint32_t : 2; - } PRSR_b; + __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these + * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ + __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0 and ENB=1. */ + __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0. */ + uint32_t : 13; + __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ + uint32_t : 15; + } FFLTR_b; }; + __IM uint32_t RESERVED10[31]; union { - __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ + __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ struct { - __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ - __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ - __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ - __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ - uint32_t : 4; - __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ - uint32_t : 19; - __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ - __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ - uint32_t : 2; - } PRIPR_b; + __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the asymmetric delay value. */ + uint32_t : 16; + } DASYMRU_b; }; - __IM uint32_t RESERVED14[2]; - __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ union { - __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ + __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ struct { - __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ - uint32_t : 30; - } TRNDISR_b; + __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the asymmetric delay value. */ + } DASYMRL_b; }; - __IM uint32_t RESERVED15[3]; union { - __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ + __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ struct { - __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ - uint32_t : 7; - __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ - __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ - uint32_t : 22; - } TRNMR_b; + __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the input + * ports. */ + __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the output + * ports. */ + } TSLATR_b; }; union { - __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ + __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ struct { - __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read - * data from the relay FIFO in cut-through mode (specified - * as the number of bytes)NOTE1: A value cannot be set in - * the lower-order 2 bits. These bits are fixed to 0.NOTE2: - * A value of less than 96 bytes cannot be set. */ - uint32_t : 21; - } TRNCTTDR_b; + __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are + * used to set the time from the completion of one transmission + * to the start of the next in cycles of the transmission + * clock. A value n in these bits means that a transmission + * interval of n cycles will be secured.No interval is secured + * if the setting is 00h.We recommend the setting 28h (40 + * cycles). */ + uint32_t : 4; + __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ + uint32_t : 3; + __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ + uint32_t : 3; + __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ + uint32_t : 11; + } SYCONFR_b; }; -} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ -/* =========================================================================================================================== */ -/* ================ R_FACI_HP_CMD ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ -/** - * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) - */ + struct + { + __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ + __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ + uint32_t : 30; + } SYFORMR_b; + }; -typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ -{ union { - __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ - __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + + struct + { + __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response + * message not being received within n x 1024 (ns), where + * n is the setting, is judged to represent a timeout. */ + } RSTOUTR_b; }; -} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ +} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ /* =========================================================================================================================== */ -/* ================ R_FACI_HP ================ */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ /* =========================================================================================================================== */ /** - * @brief Flash Application Command Interface (R_FACI_HP) + * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) */ -typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ { - __IM uint32_t RESERVED[4]; - union { - __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ struct { - __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ - uint8_t : 2; - __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ - __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ - uint8_t : 2; - __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ - } FASTAT_b; + __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ + uint32_t : 31; + } PTRSTR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; union { - __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ struct { - __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ - __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ - uint8_t : 2; - __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ - } FAEINT_b; + __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ + uint32_t : 5; + __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ + uint32_t : 21; + } STCSELR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; union { - __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ struct { - __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ - uint8_t : 7; - } FRDYIE_b; + __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ + uint32_t : 15; + __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ + uint32_t : 15; + } BYPASS_b; }; - __IM uint8_t RESERVED5; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[5]; +} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) + */ +typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ +{ union { - __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ struct { - __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area - * These bits can be written when FRDY bit of FSTATR register - * is "1". Writing to these bits in FRDY = "0" is ignored. */ - } FSADDR_b; + __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ + __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ + __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ + __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ + uint32_t : 10; + } MIESR_b; }; union { - __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ struct { - __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies - * end address of target area in "Blank Check" command. These - * bits can be written when FRDY bit of FSTATR register is - * "1". Writing to these bits in FRDY = "0" is ignored. */ - } FEADDR_b; + __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ + __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ + __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ + __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt + * Request Permission */ + uint32_t : 10; + } MIEIPR_b; }; - __IM uint32_t RESERVED8[18]; + __IM uint32_t RESERVED[2]; union { - __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission + * Register */ struct { - uint32_t : 2; - __IM uint32_t TBLCRCT : 1; /*!< [2..2] Table Area ECC 1-Bit Error Correction Monitoring Bit */ - __IM uint32_t TBLDTCT : 1; /*!< [3..3] Table Area ECC 2-Bit Error Detection Monitoring Bit */ - __IM uint32_t CFGCRCT : 1; /*!< [4..4] Config Area ECC 1-Bit Error Correction Monitoring Bit */ - __IM uint32_t CFGDTCT : 1; /*!< [5..5] Config Area ECC 2-Bit Error Detection Monitoring Bit */ - __IM uint32_t FHVEERR : 1; /*!< [6..6] "fhve" Error */ - __IM uint32_t FCUERR : 1; /*!< [7..7] FCU Error */ - __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ - __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ - __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ - __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ - __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ - __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ - __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ - __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ - __IM uint32_t OTPCRCT : 1; /*!< [16..16] OTP Bit ECC 1-Bit Error Correction Monitoring Bit */ - __IM uint32_t OTPDTCT : 1; /*!< [17..17] OTP Bit ECC 2-Bit Error Detection Monitoring Bit */ - __IM uint32_t EBFULL : 1; /*!< [18..18] FDMYECC Buffer Full */ - uint32_t : 13; - } FSTATR_b; + __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + } ELIPPR_b; }; union { - __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic + * Clearing Register */ struct { - __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is "1". Writing to this bit - * in FRDY = "0" is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits */ - uint16_t : 6; - __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when - * FRDY bit in FSTATR register is "1". Writing to this bit - * in FRDY = "0" is ignored. Writing to these bits is enabled - * only when this register is accessed in 16-bit size and - * H'AA is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FENTRYR_b; + __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ + uint32_t : 7; + } ELIPACR_b; }; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; + __IM uint32_t RESERVED1[10]; union { - __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ struct { - __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY - * bit of FSTATR register is "1". Writing to this bit in FRDY - * = "0" is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'2D - * is written to KEY bits. */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUINITR_b; + __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ + __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ + uint32_t : 27; + } STSR_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[4]; union { - __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ struct { - __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ - __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ - } FCMDR_b; + __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ + __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ + uint32_t : 27; + } STIPR_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[7]; + __IM uint32_t RESERVED2[2]; union { - __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ struct { - __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ - uint16_t : 8; - } FPESTAT_b; + __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ + uint32_t : 30; + } STCFR_b; }; - __IM uint16_t RESERVED15; - __IM uint32_t RESERVED16[3]; union { - __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ struct { - __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ - uint8_t : 7; - } FBCCNT_b; + __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ + uint32_t : 5; + __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ + uint32_t : 1; + __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ + __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ + __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ + uint32_t : 4; + __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ + __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ + uint32_t : 2; + } STMR_b; }; - __IM uint8_t RESERVED17; - __IM uint16_t RESERVED18; union { - __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ struct { - __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ - uint8_t : 7; - } FBCSTAT_b; + __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), + * where n is the setting, leads to a timeout for reception + * of Sync messages, leading to the STSR.SYNTOUT flag being + * set to 1. */ + } SYNTOR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; + __IM uint32_t RESERVED3; union { - __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ struct { - __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address - * of the first programmed data which is found in "Blank Check" - * command execution. */ - uint32_t : 13; - } FPSADDR_b; + __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ + __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ + __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ + __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ + __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ + __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ + uint32_t : 26; + } IPTSELR_b; }; union { - __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ struct { - __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits - * indicate the start sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot - * Flag and Temporary Boot Swap Control and "Config Clear" - * command execution */ - __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits - * indicate the end sector address for setting the access - * window that is located in the configuration area. */ - uint32_t : 4; - __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ - } FAWMON_b; + __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ + uint32_t : 26; + } MITSELR_b; }; union { - __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ struct { - __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ - uint16_t : 15; - } FCPSR_b; + __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ + __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ + __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ + __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ + __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ + __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ + uint32_t : 26; + } ELTSELR_b; }; - __IM uint16_t RESERVED21; union { - __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ struct { - __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits - * can be written when FRDY bit in FSTATR register is "1". - * Writing to this bit in FRDY = "0" is ignored. Writing to - * these bits is enabled only when this register is accessed - * in 16-bit size and H'1E is written to KEY bits. */ - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FPCKAR_b; + __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the + * value of this bit while the SYNSTARTR.STR bit is 1. */ + uint32_t : 31; + } STCHSELR_b; }; - __IM uint16_t RESERVED22; + __IM uint32_t RESERVED4[4]; union { - __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ struct { - __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY - * bit in FSTATR register is "1". Writing to this bit in FRDY - * = "0" is ignored. Writing to these bits is enabled only - * when this register is accessed in 16-bit size and H'66 - * is written to KEY bits. */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ - } FSUACR_b; + __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ + uint32_t : 31; + } SYNSTARTR_b; }; - __IM uint16_t RESERVED23; -} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - -/* =========================================================================================================================== */ -/* ================ R_FACI_LP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Application Command Interface (R_FACI_LP) - */ - -typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ -{ - __IM uint32_t RESERVED[36]; - __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[27]; union { - __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive + * Register */ struct { - uint8_t : 1; - __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode - * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash - * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ - uint8_t : 1; - __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ - __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to - * the description of the FMS0 bit. */ - uint8_t : 1; - __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ - __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description - * of the FMS0 bit. */ - } FPMCR_b; + __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ + uint32_t : 31; + } LCIVLDR_b; }; - __IM uint8_t RESERVED4; - __IM uint16_t RESERVED5; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ struct { - __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ - uint8_t : 7; - } FASR_b; + __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of loss of synchronization. */ + } SYNTDARU_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; union { - __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ struct { - __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ - } FSARL_b; + __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of loss of synchronization. */ + } SYNTDARL_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9; union { - __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ struct { - __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ - uint16_t : 4; - __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ - } FSARH_b; + __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of synchronization. */ + } SYNTDBRU_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ struct { - __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ - __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ - uint8_t : 1; - __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ - __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ - } FCR_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - - union - { - __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ - - struct - { - __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ - } FEARL_b; + __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of synchronization. */ + } SYNTDBRL_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14; + __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ struct { - __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ - uint32_t : 4; - __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ - uint32_t : 16; - } FEARH_b; + __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the integer portion of the initial value for the + * local timer counter. */ + uint32_t : 16; + } LCIVRU_b; }; union { - __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ struct { - __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ - uint32_t : 31; - } FRESETR_b; + __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the integer portion of the initial value for the local + * timer counter. */ + } LCIVRM_b; }; union { - __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ struct { - __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ - __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ - __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ - __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ - __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ - __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ - uint32_t : 26; - } FSTATR00_b; + __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion + * of the initial value of the local timer counter in nanoseconds. */ + } LCIVRL_b; }; + __IM uint32_t RESERVED7[26]; union { - __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ struct { - uint32_t : 1; - __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ - uint32_t : 4; - __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ - __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ - uint32_t : 24; - } FSTATR1_b; + __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ + uint32_t : 31; + } GETW10R_b; }; union { - __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ struct { - __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBL0_b; + __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the positive gradient. */ + uint32_t : 1; + } PLIMITRU_b; }; - __IM uint32_t RESERVED15; union { - __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ struct { - __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBH0_b; + __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the positive gradient. */ + } PLIMITRM_b; }; union { - __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ struct { - __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ - __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ - uint32_t : 1; - __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ - uint32_t : 28; - } FSTATR01_b; + __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the positive gradient. */ + } PLIMITRL_b; }; union { - __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ struct { - __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBL1_b; + __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the negative gradient. */ + uint32_t : 1; + } MLIMITRU_b; }; union { - __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ struct { - __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ - uint32_t : 16; - } FWBH1_b; + __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the negative gradient. */ + } MLIMITRM_b; }; union { - __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ struct { - __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBL1_b; + __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the negative gradient. */ + } MLIMITRL_b; }; union { - __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ struct { - __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBH1_b; + __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching + * is directed, values of various statistical information + * read before completion of information fetching are not + * guaranteed. */ + uint32_t : 31; + } GETINFOR_b; }; - __IM uint32_t RESERVED16[12]; + __IM uint32_t RESERVED8[11]; union { - __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ struct { - __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ - uint32_t : 24; - } FPR_b; + __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits + * of the integer portion of the local timer counter's value. */ + uint32_t : 16; + } LCCVRU_b; }; union { - __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ struct { - __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ - uint32_t : 31; - } FPSR_b; + __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the integer portion of the local timer counter's value. */ + } LCCVRM_b; }; union { - __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ struct { - __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBL0_b; + __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of + * the local timer counter's value (in nanoseconds). */ + } LCCVRL_b; }; - __IM uint32_t RESERVED17; + __IM uint32_t RESERVED9[37]; union { - __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ struct { - __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ - uint32_t : 16; - } FRBH0_b; + __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the positive gradient value. */ + } PW10VRU_b; }; - __IM uint32_t RESERVED18[11]; union { - __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ struct { - uint32_t : 8; - __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ - uint32_t : 5; - __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ - uint32_t : 17; - } FSCMR_b; + __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the positive gradient value. */ + } PW10VRM_b; }; - __IM uint32_t RESERVED19; union { - __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ struct { - __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ - uint32_t : 20; - } FAWSMR_b; + __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the positive gradient value. */ + } PW10VRL_b; }; - __IM uint32_t RESERVED20; + __IM uint32_t RESERVED10[45]; union { - __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ struct { - __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ - uint32_t : 20; - } FAWEMR_b; + __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the negative gradient value. */ + } MW10RU_b; }; - __IM uint32_t RESERVED21; union { - __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ struct { - __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ - __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ - uint32_t : 24; - } FISR_b; + __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the negative gradient value. */ + } MW10RM_b; }; union { - __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ struct { - __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ - uint32_t : 4; - __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ - uint32_t : 24; - } FEXCR_b; + __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the negative gradient value. */ + } MW10RL_b; }; + __IM uint32_t RESERVED11[9]; + __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ + __IM uint32_t RESERVED12[7]; union { - __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ struct { - __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ - uint32_t : 16; - } FEAML_b; + __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ + __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ + __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ + __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ + __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ + __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ + uint32_t : 26; + } TMSTARTR_b; }; - __IM uint32_t RESERVED22; + __IM uint32_t RESERVED13[32]; union { - __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ struct { - __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ - uint32_t : 16; - } FEAMH_b; + __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ + __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ + uint32_t : 2; + } PRSR_b; }; - __IM uint32_t RESERVED23; union { - __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ struct { - __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ - __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ - __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ - __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ - __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ - __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ - uint32_t : 26; - } FSTATR2_b; + __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ + __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ + uint32_t : 2; + } PRIPR_b; }; - __IM uint32_t RESERVED24[3951]; - __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ - __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; - __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ - -/* =========================================================================================================================== */ -/* ================ R_FCACHE ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Flash Memory Cache (R_FCACHE) - */ - -typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ -{ - __IM uint16_t RESERVED[128]; + __IM uint32_t RESERVED14[2]; + __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ union { - __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ struct { - __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ - uint16_t : 15; - } FCACHEE_b; + __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ + uint32_t : 30; + } TRNDISR_b; }; - __IM uint16_t RESERVED1; + __IM uint32_t RESERVED15[3]; union { - __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ struct { - __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ - uint16_t : 15; - } FCACHEIV_b; + __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ + uint32_t : 7; + __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ + __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ + uint32_t : 22; + } TRNMR_b; }; - __IM uint16_t RESERVED2[11]; union { - __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ struct { - __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ - uint8_t : 5; - } FLWT_b; + __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read + * data from the relay FIFO in cut-through mode (specified + * as the number of bytes)NOTE1: A value cannot be set in + * the lower-order 2 bits. These bits are fixed to 0.NOTE2: + * A value of less than 96 bytes cannot be set. */ + uint32_t : 21; + } TRNCTTDR_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; -} R_FCACHE_Type; /*!< Size = 288 (0x120) */ +} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ /* =========================================================================================================================== */ -/* ================ R_GLCDC ================ */ +/* ================ R_FACI_HP_CMD ================ */ /* =========================================================================================================================== */ /** - * @brief Graphics LCD Controller (R_GLCDC) + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) */ -typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ { union { - __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR1_CLUT0_b[256]; + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; union { - __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR1_CLUT1_b[256]; + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; union { - __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR2_CLUT0_b[256]; + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; union { - __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ struct { - __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ - __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics - * m Plane */ - } GR2_CLUT1_b[256]; + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is "1". Writing to these bits in FRDY = "0" is ignored. */ + } FSADDR_b; }; - __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ - __IM uint32_t RESERVED[57]; - __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ - __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ - __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ - __IM uint32_t RESERVED1[6]; - __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ - __IM uint32_t RESERVED2[5]; - __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ -} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ -/* =========================================================================================================================== */ -/* ================ R_GPT0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ -/** - * @brief General PWM Timer (R_GPT0) - */ + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in "Blank Check" command. These + * bits can be written when FRDY bit of FSTATR register is + * "1". Writing to these bits in FRDY = "0" is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; -typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ -{ union { - __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ struct { - __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ - uint32_t : 7; - __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ - uint32_t : 16; - } GTWP_b; + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but TrustZo */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; union { - __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ struct { - __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter stop. 1 - * means counter running. */ - uint32_t : 18; - } GTSTR_b; + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; }; + __IM uint16_t RESERVED11; union { - __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ struct { - __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's - * counter status (GTCR.CST bit). 0 means counter runnning. - * 1 means counter stop. */ - uint32_t : 18; - } GTSTP_b; + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; }; + __IM uint16_t RESERVED12; union { - __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ struct { - __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ - __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ - __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ - __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ - __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ - __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ - __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ - __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ - __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ - __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ - __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ - __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ - __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ - __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ - uint32_t : 18; - } GTCLR_b; + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; }; union { - __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ struct { - __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ - __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ - __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Start Enable */ - __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Start Enable */ - __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ - __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ - uint32_t : 7; - __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ - } GTSSR_b; + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is "1". Writing to this bit + * in FRDY = "0" is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is "1". Writing to this bit + * in FRDY = "0" is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; union { - __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ struct { - __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ - __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ - __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Stop Enable */ - __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Stop Enable */ - __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ - __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ - uint32_t : 7; - __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ - } GTPSR_b; + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is "1". Writing to this bit in FRDY + * = "0" is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; union { - __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ struct { - __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ - __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ - __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Clear Enable */ - __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Clear Enable */ - __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ - __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ - uint32_t : 7; - __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ - } GTCSR_b; + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; union { - __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ struct { - __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ - __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ - __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Up Enable */ - __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Up Enable */ - __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ - __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ - uint32_t : 8; - } GTUPSR_b; + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; union { - __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ struct { - __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ - __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ - __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * Counter Count Down Enable */ - __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * Counter Count Down Enable */ - __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ - __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ - uint32_t : 8; - } GTDNSR_b; + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; union { - __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select - * Register A */ + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ struct { - __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture - * Enable */ - __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ - __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ - uint32_t : 8; - } GTICASR_b; + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; union { - __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select - * Register B */ + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ struct { - __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture - * Enable */ - __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source - * GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ - __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ - uint32_t : 8; - } GTICBSR_b; + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in "Blank Check" + * command execution. */ + uint32_t : 13; + } FPSADDR_b; }; union { - __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ struct { - __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ - uint32_t : 15; - __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ - uint32_t : 5; - __IOM uint32_t TPCS : 3; /*!< [26..24] Timer Prescaler Select */ - uint32_t : 5; - } GTCR_b; + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and "Config Clear" + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; }; union { - __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting - * Register */ + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ struct { - __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ - __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ - uint32_t : 14; - __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ - __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ - __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 - * percent Duty Setting */ - uint32_t : 4; - } GTUDDTYC_b; + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; }; + __IM uint16_t RESERVED25; union { - __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ struct { - __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ - __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ - uint32_t : 2; - __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ - __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ - __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ - uint32_t : 1; - __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ - __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ - __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ - __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ - uint32_t : 2; - __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ - __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ - } GTIOR_b; + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is "1". + * Writing to this bit in FRDY = "0" is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; }; + __IM uint16_t RESERVED26; union { - __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ struct { - uint32_t : 24; - __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ - uint32_t : 2; - __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ - __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - uint32_t : 1; - } GTINTAD_b; + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is "1". Writing to this bit in FRDY + * = "0" is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ - union - { - __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ - __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ - __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ - __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ - __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ - __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ - __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ - __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ - __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter - * for counting the number of times a timer interrupt has - * been skipped.) */ - uint32_t : 4; - __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ - __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start - * Request Interrupt Enable */ - __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start - * Request Flag */ - __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor - * Start Request Flag */ - uint32_t : 4; - __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ - uint32_t : 3; - __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ - __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ - __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ - uint32_t : 1; - } GTST_b; - }; +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; union { - __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ struct { - __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ - __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ - __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ - __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ - uint32_t : 12; - __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ - __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ - __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ - __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit - * is read as 0. */ - uint32_t : 1; - __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ - uint32_t : 1; - __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle - * wavesNOTE: In the Saw waves, values other than 0 0: Transfer - * at an underflow (in down-counting) or overflow (in up-counting) - * is performed. */ - __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ - uint32_t : 1; - } GTBER_b; + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; union { - __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter - * Start Request Skipping Setting Register */ + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ struct { - __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ - __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ - __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ - __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ - __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ - __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ - __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ - uint32_t : 1; - __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ - uint32_t : 1; - __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ - uint32_t : 17; - } GTITC_b; + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; union { - __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ struct { - __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ - } GTCNT_b; + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; union { - __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ struct { - __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ - } GTCCR_b[6]; + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; }; + __IM uint16_t RESERVED10; union { - __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ struct { - __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ - } GTPR_b; + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; union { - __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ struct { - __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ - } GTPBR_b; + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; union { - __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer - * Register */ + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ struct { - __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ - } GTPDBR_b; + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; }; union { - __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ struct { - __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ - } GTADTRA_b; + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; }; union { - __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register - * A */ + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ struct { - __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ - } GTADTBRA_b; + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; }; union { - __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer - * Register A */ + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ struct { - __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * A */ - } GTADTDBRA_b; + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; }; union { - __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ struct { - __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ - } GTADTRB_b; + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; }; + __IM uint32_t RESERVED15; union { - __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register - * B */ + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ struct { - __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ - } GTADTBRB_b; + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; }; union { - __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer - * Register B */ + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ struct { - __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register - * B */ - } GTADTDBRB_b; + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; }; union { - __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ struct { - __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ - uint32_t : 3; - __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ - __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ - uint32_t : 2; - __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ - uint32_t : 23; - } GTDTCR_b; + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; }; union { - __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ - } GTDVU_b; + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; }; union { - __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ struct { - __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ - } GTDVD_b; + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; }; union { - __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ struct { - __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ - } GTDBU_b; + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; }; + __IM uint32_t RESERVED16[12]; union { - __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ struct { - __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ - } GTDBD_b; + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; }; union { - __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function - * Status Register */ + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ struct { - __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ - uint32_t : 30; - } GTSOS_b; + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; }; union { - __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function - * Temporary Release Register */ + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ struct { - __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ - uint32_t : 31; - } GTSOTR_b; + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; }; -} R_GPT0_Type; /*!< Size = 164 (0xa4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_ODC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief PWM Delay Generation Circuit (R_GPT_ODC) - */ + __IM uint32_t RESERVED17; -typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ -{ union { - __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ struct { - __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ - __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ - uint16_t : 6; - __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select */ - uint16_t : 7; - } GTDLYCR1_b; + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; }; + __IM uint32_t RESERVED18[11]; union { - __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ struct { - __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ - __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ - __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ - __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ - uint16_t : 4; - __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ - uint16_t : 3; - __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ - uint16_t : 3; - } GTDLYCR2_b; + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; }; - __IM uint16_t RESERVED[10]; - __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ - __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ -} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_OPS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Output Phase Switching for GPT (R_GPT_OPS) - */ + __IM uint32_t RESERVED19; -typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ -{ union { - __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ struct { - __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase - * by the software settings.This bit setting is valid when - * the OPSCR.FB bit = 1. */ - uint32_t : 1; - __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the - * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa - * e settings (UF/VF/WF) */ - uint32_t : 1; - __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ - uint32_t : 7; - __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the - * input phase from the software settings and external input. */ - __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ - __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ - __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ - __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ - __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ - uint32_t : 2; - __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ - __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ - uint32_t : 2; - __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter - * sampling clock setting of the external input. */ - } OPSCR_b; + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; }; -} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_GPT_POEG0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Port Output Enable for GPT (R_GPT_POEG0) - */ + __IM uint32_t RESERVED20; -typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ -{ union { - __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ struct { - __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ - __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ - __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ - __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ - __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only - * once after a reset. */ - __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified - * only once after a reset. */ - __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified - * only once after a reset. */ - uint32_t : 1; - __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified - * only once after a reset. */ - uint32_t : 2; - __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ - uint32_t : 11; - __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ - __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ - __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ - } POEGG_b; + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; }; -} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + __IM uint32_t RESERVED21; -/* =========================================================================================================================== */ -/* ================ R_ICU ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ -/** - * @brief Interrupt Controller Unit (R_ICU) - */ + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; -typedef struct /*!< (@ 0x40006000) R_ICU Structure */ -{ union { - __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ struct { - __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ - uint8_t : 2; - __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ - } IRQCR_b[16]; + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; }; - __IM uint32_t RESERVED[60]; union { - __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ struct { - __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ - uint8_t : 3; - __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ - uint8_t : 1; - __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ - } NMICR_b; + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; - __IM uint32_t RESERVED3[7]; + __IM uint32_t RESERVED22; union { - __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ struct { - __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ - __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ - __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ - __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ - __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ - __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ - __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ - __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ - __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ - __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ - uint16_t : 3; - } NMIER_b; + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; }; - __IM uint16_t RESERVED4; - __IM uint32_t RESERVED5[3]; + __IM uint32_t RESERVED23; union { - __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ struct { - __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ - __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ - __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ - __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ - __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ - uint16_t : 1; - __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ - __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ - __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ - __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ - __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ - __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ - __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ - uint16_t : 3; - } NMICLR_b; + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; }; - __IM uint16_t RESERVED6; - __IM uint32_t RESERVED7[3]; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; union { - __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ struct { - __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ - __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ - __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ - __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ - __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ - uint16_t : 1; - __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ - __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ - __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ - __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ - __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ - __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ - __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ - uint16_t : 3; - } NMISR_b; + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; }; - __IM uint16_t RESERVED8; - __IM uint32_t RESERVED9[23]; + __IM uint16_t RESERVED1; union { - __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ struct { - __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ - __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ - __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ - __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ - __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ - __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ - uint32_t : 1; - __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ - __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ - __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ - __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ - __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ - __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ - __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ - __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns - * enable */ - __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns - * enable */ - __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ - } WUPEN_b; - }; - __IM uint32_t RESERVED10[23]; - - union - { - __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ - - struct - { - __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ - uint16_t : 7; - } SELSR0_b; + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; }; - __IM uint16_t RESERVED11; - __IM uint32_t RESERVED12[31]; + __IM uint16_t RESERVED2[11]; union { - __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ struct { - __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the - * IR flag is prohibited. */ - uint32_t : 15; - } DELSR_b[8]; + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; }; - __IM uint32_t RESERVED13[24]; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; union { - __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ struct { - __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event - * signal to be linked . */ - uint32_t : 7; - __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ - uint32_t : 7; - __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ - uint32_t : 7; - } IELSR_b[96]; + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; }; -} R_ICU_Type; /*!< Size = 1152 (0x480) */ +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ /* =========================================================================================================================== */ -/* ================ R_IIC0 ================ */ +/* ================ R_GLCDC ================ */ /* =========================================================================================================================== */ /** - * @brief I2C Bus Interface (R_IIC0) + * @brief Graphics LCD Controller (R_GLCDC) */ -typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ { union { - __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ struct { - __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ - __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ - __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ - __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ - __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ - __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ - __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset - * is initiated using the IICRST bit for a bus hang-up occurred - * during communication with the master device in slave mode, - * the states may become different between the slave device - * and the master device (due to the difference in the bit - * counter information). */ - __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ - } ICCR1_b; + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; }; union { - __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ struct { - uint8_t : 1; - __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start - * condition issuance request) when the BBSY flag is set to - * 0 (bus free state). */ - __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the - * RS bit to 1 while issuing a stop condition. */ - __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP - * bit is not possible while the setting of the BBSY flag - * is 0 (bus free state).Note: Do not set the SP bit to 1 - * while a restart condition is being issued. */ - uint8_t : 1; - __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ - __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ - __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ - } ICCR2_b; + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; }; union { - __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ struct { - __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ - __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ - __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB - * / 2^CKS ) */ - __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ - } ICMR1_b; + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; }; union { - __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ struct { - __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ - __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ - __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ - uint8_t : 1; - __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ - __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ - } ICMR2_b; + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ union { - __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ struct { - __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ - __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ - __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ - __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ - __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ - __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, - * be sure to read the ICDRR beforehand. */ - __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ - } ICMR3_b; + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; }; union { - __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ struct { - __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ - __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ - __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ - __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ - __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ - __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ - __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ - __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ - } ICFER_b; + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; }; union { - __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ struct { - __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ - __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ - __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ - __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ - uint8_t : 1; - __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ - uint8_t : 1; - __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ - } ICSER_b; - }; - - union - { - __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ - - struct - { - __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ - __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ - __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ - __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ - __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ - __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ - __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ - } ICIER_b; + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; }; union { - __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ struct { - __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ - __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ - __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ - __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ - uint8_t : 1; - __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ - } ICSR1_b; + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; }; union { - __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ struct { - __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ - __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ - __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ - __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ - __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ - __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ - __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } ICSR2_b; + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; }; - __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ union { - __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ struct { - __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ - uint8_t : 3; - } ICBRL_b; + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; }; union { - __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ struct { - __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ - uint8_t : 3; - } ICBRH_b; + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + uint32_t : 7; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; }; union { - __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ struct { - __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ - } ICDRT_b; + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + uint32_t : 8; + } GTUPSR_b; }; union { - __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ struct { - __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ - } ICDRR_b; - }; + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + uint32_t : 8; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + uint32_t : 2; + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + uint32_t : 2; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t DLLMOD : 1; /*!< [8..8] DLL Mode Select */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + uint16_t : 3; + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[22]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED13[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; __IM uint8_t RESERVED[2]; union { - __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief JPEG Codec (R_JPEG) + */ + +typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ +{ + union + { + __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ + + struct + { + __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ + __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between + * processing for compression and for decompression, be sure + * to reset this module in advance by setting the JCUSRST + * bit in the software reset control register 2 (SWRSTCR2) + * of the power-downmodes. */ + uint8_t : 4; + } JCMOD_b; + }; + + union + { + __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ + + struct + { + __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, + * set this bit to 1. Do not write this bit to 1 again while + * this module is in operation. */ + __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped + * state caused by requests to read the image size and pixel + * format (enabled by the INT3 bit in JINTE0), set this bit + * to 1. */ + __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only + * for the interrupt sources corresponding to bits INS6, INS5, + * and INS3 in JINTS0. To clear an interrupt request, set + * this bit to 1 */ + uint8_t : 4; + __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the + * bus reset command should not be issued. */ + } JCCMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ + + struct + { + __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component + * NOTE: Read-only in Decompression. */ + uint8_t : 2; + } JCQTN_b; + }; + + union + { + __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ + + struct + { + __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: + * Read-only in Decompression. */ + uint8_t : 2; + } JCHTN_b; + }; + + union + { + __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ + + struct + { + __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRIU_b; + }; + + union + { + __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ + + struct + { + __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRID_b; + }; + + union + { + __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ + + struct + { + __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZU_b; + }; + + union + { + __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ + + struct + { + __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZD_b; + }; + + union + { + __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ + + struct + { + __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZU_b; + }; + + union + { + __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ + + struct + { + __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZD_b; + }; + + union + { + __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ + + struct + { + __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed + * The values of this register are reset before compression + * starts.NOTE: Read-only in Decompression. */ + } JCDTCU_b; + }; + + union + { + __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ + + struct + { + __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts. + * NOTE: Read-only in Decompression. */ + } JCDTCM_b; + }; + + union + { + __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ + + struct + { + __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts.NOTE: + * Read-only in Decompression. */ + } JCDTCD_b; + }; + + union + { + __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it + * has been determined that the image size and the subsampling + * setting of the compressed data can be read through analyzing + * the data. */ + uint8_t : 1; + __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the + * final number of MCU data in the Huffman-coding segment + * is not correct in decompression. When this bit is not set + * to enable interrupt generation, an error code is not returned. */ + __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the + * total number of data in the Huffman-coding segment is not + * correct in decompression. When this bit is not set to enable + * interrupt generation, an error code is not returned. */ + __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the + * number of data in the restart interval of the Huffman-coding + * segment is not correct in decompression.When this bit is + * not set to enable interrupt generation, an error code is + * not returned. */ + } JINTE0_b; + }; + + union + { + __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format + * can be read. When an interrupt occurs, this module stops + * processing and the state is indicated by the JCRST register. + * To make this module resume processing, set the JPEG core + * process stop clear command bit (JRST) in JCCMD. */ + uint8_t : 1; + __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ + __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression + * process normally. */ + uint8_t : 1; + } JINTS0_b; + }; + + union + { + __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ + + struct + { + __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error + * which has occurred in the compressed data analysis for + * decompression. */ + uint8_t : 4; + } JCDERR_b; + }; + + union + { + __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ + + struct + { + __IM uint8_t RST : 1; /*!< [0..0] Operating State */ + uint8_t : 7; + } JCRST_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[11]; + + union + { + __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ + + struct + { + __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ + uint32_t : 1; + __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ + __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the input of image + * data lines is on. Setting this bit to 1 resumes reading + * input image data. This bit is always read as 0. */ + __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data + * Lines This bit is only valid when the count mode for stopping + * the input of image data lines is on. Set this bit before + * writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression + * is swapped. */ + uint32_t : 21; + } JIFECNT_b; + }; + + union + { + __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ + + struct + { + __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFESA_b; + }; + + union + { + __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ + + struct + { + __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower + * three bits should be set to 0. */ + uint32_t : 17; + } JIFESOFST_b; + }; + + union + { + __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address + * Register */ + + struct + { + __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFEDA_b; + }; + + union + { + __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count + * Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line + * units) The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFESLC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ + + struct + { + __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is + * swapped. */ + uint32_t : 1; + __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ + __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the output of image + * data lines is on. Setting this bit to 1 resumes writing + * image data. This bit is always read as 0. */ + __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image + * Data Lines This bit is only valid when the count mode for + * stopping the output of image data lines is on. Set this + * bit before writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression + * is swapped. */ + uint32_t : 1; + __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ + __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only + * when the count mode for stopping the input of coded data + * is on. Setting this bit to 1 resumes reading input coded + * data. This bit is always read as 0. */ + __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed + * This bit is only valid when the count mode for stopping + * the input of coded data is on. Set this bit before writing + * 1 to the data resume command bit. */ + uint32_t : 9; + __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ + __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output + * image data. */ + __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image + * data. */ + uint32_t : 2; + } JIFDCNT_b; + }; + + union + { + __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ + + struct + { + __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source + * Address (in 8-byte units) The lower three bits should be + * set to 0. */ + } JIFDSA_b; + }; + + union + { + __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ + + struct + { + __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + uint32_t : 17; + } JIFDDOFST_b; + }; + + union + { + __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address + * Register */ + + struct + { + __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) + * The lower three bits should be set to 0. */ + } JIFDDA_b; + }; + + union + { + __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count + * Register */ + + struct + { + __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) + * The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFDSDC_b; + }; + + union + { + __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line + * Count Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three + * bits should be set to 0. These bits are read as0.Number + * of input image data lines to be read, in 8-line units. */ + uint32_t : 16; + } JIFDDLC_b; + }; + + union + { + __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ + + struct + { + __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ + uint32_t : 24; + } JIFDADT_b; + }; + __IM uint32_t RESERVED4[6]; + + union + { + __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DOUTLF bit in JINTS1 is set to + * 1 */ + __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt + * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ + __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ + uint32_t : 2; + __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ + __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt + * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ + uint32_t : 25; + } JINTE1_b; + }; + + union + { + __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number + * of lines of output image data indicated by JIFDDLC have + * been written. This bit is only valid when the DOUTLC bit + * in JIFDCNT is set to 1. */ + __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data + * indicated by JIFDSDC is read in decompression. This bit + * is valid only when the JINC bit in JIFDCNT is set to 1. */ + __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data + * is written in decompression. */ + uint32_t : 2; + __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data + * lines indicated by JIFESLC is read in compression. This + * bit is valid only when the DINLC bit in JIFECNT is set + * to 1. */ + __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data + * is written in compression. */ + uint32_t : 25; + } JINTS1_b; + }; + __IM uint32_t RESERVED5[27]; + __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ + __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ + __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ + __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ + __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ + __IM uint32_t RESERVED6; + __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[11]; + __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ + __IM uint32_t RESERVED9; + __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ + __IM uint16_t RESERVED10; +} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_MMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Master MPU (R_MPU_MMPU) + */ + +typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ +{ + __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ +} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SMPU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Slave MPU (R_MPU_SMPU) + */ + +typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ +{ + union + { + __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ + __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting + * of the PROTECT and OAD bit. */ + } SMPUCTL_b; + }; + __IM uint16_t RESERVED[7]; + __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ +} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000000) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] I2C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000004) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 13; + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x00000008) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x0000000C) Module Stop Control Register E */ + + struct + { + uint32_t : 14; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Operational Amplifier (R_OPAMP) + */ + +typedef struct /*!< (@ 0x40086000) R_OPAMP Structure */ +{ + __IM uint8_t RESERVED[8]; + + union + { + __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */ + + struct + { + __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */ + uint8_t : 4; + __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */ + } AMPMC_b; + }; + + union + { + __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */ + + struct + { + __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger + * control */ + } AMPTRM_b; + }; + + union + { + __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select + * Register */ + + struct + { + __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the + * AMPTRS register after setting the AMPTRM register. */ + uint8_t : 6; + } AMPTRS_b; + }; + + union + { + __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */ + + struct + { + __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */ + __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */ + __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */ + __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */ + uint8_t : 3; + __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference + * current circuit */ + } AMPC_b; + }; + + union + { + __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */ + + struct + { + __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */ + __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */ + __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */ + __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */ + uint8_t : 4; + } AMPMON_b; + }; + __IM uint8_t RESERVED1; + __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier + * [0..3] */ + + union + { + __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control + * register */ + + struct + { + __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */ + __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */ + __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */ + uint8_t : 5; + } AMPCPC_b; + }; + __IM uint8_t RESERVED2[4]; + + union + { + __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable + * Register */ + + struct + { + __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */ + __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */ + __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */ + uint8_t : 5; + } AMPUOTE_b; + }; + __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */ +} R_OPAMP_Type; /*!< Size = 38 (0x26) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Data Capture Unit (R_PDC) + */ + +typedef struct /*!< (@ 0x40094000) R_PDC Structure */ +{ + union + { + __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */ + + struct + { + __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */ + __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */ + __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */ + __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */ + __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */ + __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */ + __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */ + __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */ + __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */ + __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */ + __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */ + __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */ + __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */ + uint32_t : 17; + } PCCR0_b; + }; + + union + { + __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */ + + struct + { + __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */ + uint32_t : 31; + } PCCR1_b; + }; + + union + { + __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */ + + struct + { + __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */ + __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */ + __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */ + __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */ + __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */ + __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */ + __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */ + uint32_t : 25; + } PCSR_b; + }; + + union + { + __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */ + + struct + { + __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */ + __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */ + uint32_t : 30; + } PCMONR_b; + }; + + union + { + __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */ + + struct + { + __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the + * storage of captured data. The PCDR register is a 4-byte + * space to which the FIFO is mapped, and four bytes of data + * are read from the PCDR register at a time. */ + } PCDR_b; + }; + + union + { + __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */ + + struct + { + __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line + * where capture is to start. */ + uint32_t : 4; + __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */ + uint32_t : 4; + } VCR_b; + }; + + union + { + __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */ + + struct + { + __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position + * in bytes where capture is to start. */ + uint32_t : 4; + __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture + * horizontally. */ + uint32_t : 4; + } HCR_b; + }; +} R_PDC_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; struct { - __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ - uint8_t : 3; - __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ - __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ - __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ - __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ - } ICWUR_b; + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; }; union { - __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; struct { - __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ - __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ - __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ - uint8_t : 5; - } ICWUR2_b; + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; }; -} R_IIC0_Type; /*!< Size = 24 (0x18) */ -/* =========================================================================================================================== */ -/* ================ R_IRDA ================ */ -/* =========================================================================================================================== */ + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ -/** - * @brief IrDA Interface (R_IRDA) - */ + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; -typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ -{ - union - { - __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ - struct - { - uint8_t : 2; - __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ - __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ - uint8_t : 3; - __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ - } IRCR_b; + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; }; -} R_IRDA_Type; /*!< Size = 1 (0x1) */ +} R_PORT0_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ -/* ================ R_IWDT ================ */ +/* ================ R_PFS ================ */ /* =========================================================================================================================== */ /** - * @brief Independent Watchdog Timer (R_IWDT) + * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - union - { - __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ - - struct - { - __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing - * 0xFF to this register. */ - } IWDTRR_b; - }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; - - union - { - __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ - - struct - { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } IWDTSR_b; - }; -} R_IWDT_Type; /*!< Size = 6 (0x6) */ + __IOM R_PFS_PORT_Type PORT[12]; /*!< (@ 0x00000000) Port [0..11] */ +} R_PFS_Type; /*!< Size = 768 (0x300) */ /* =========================================================================================================================== */ -/* ================ R_JPEG ================ */ +/* ================ R_PMISC ================ */ /* =========================================================================================================================== */ /** - * @brief JPEG Codec (R_JPEG) + * @brief I/O Ports-MISC (R_PMISC) */ -typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ { union { - __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ - - struct - { - __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ - __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between - * processing for compression and for decompression, be sure - * to reset this module in advance by setting the JCUSRST - * bit in the software reset control register 2 (SWRSTCR2) - * of the power-downmodes. */ - uint8_t : 4; - } JCMOD_b; - }; - - union - { - __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ - - struct - { - __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, - * set this bit to 1. Do not write this bit to 1 again while - * this module is in operation. */ - __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped - * state caused by requests to read the image size and pixel - * format (enabled by the INT3 bit in JINTE0), set this bit - * to 1. */ - __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only - * for the interrupt sources corresponding to bits INS6, INS5, - * and INS3 in JINTS0. To clear an interrupt request, set - * this bit to 1 */ - uint8_t : 4; - __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the - * bus reset command should not be issued. */ - } JCCMD_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ struct { - __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: - * Read-only in Decompression. */ - __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component - * NOTE: Read-only in Decompression. */ - uint8_t : 2; - } JCQTN_b; + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; }; + __IM uint8_t RESERVED[2]; union { - __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ struct { - __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: - * Read-only in Decompression. */ - __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: - * Read-only in Decompression. */ - __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component - * NOTE: Read-only in Decompression. */ - __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: - * Read-only in Decompression. */ - uint8_t : 2; - } JCHTN_b; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; }; + __IM uint8_t RESERVED1; union { - __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ struct { - __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper - * and lower bytes are set to 00h, neither a DRI nor an RST - * marker is placed.NOTE: Read-only in Decompression. */ - } JCDRIU_b; + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[9]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 34 (0x22) */ - union - { - __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper - * and lower bytes are set to 00h, neither a DRI nor an RST - * marker is placed.NOTE: Read-only in Decompression. */ - } JCDRID_b; - }; +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ union { - __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ struct { - __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, - * a downloaded value from the JPEG coded data is set. NOTE: - * Read-only in Decompression. */ - } JCVSZU_b; + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; }; union { - __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ struct { - __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, - * a downloaded value from the JPEG coded data is set. NOTE: - * Read-only in Decompression. */ - } JCVSZD_b; + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; }; union { - __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ struct { - __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression - * process, a downloaded value from the JPEG coded data is - * set. NOTE: Read-only in Decompression. */ - } JCHSZU_b; + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; }; union { - __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ struct { - __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression - * process, a downloaded value from the JPEG coded data is - * set. NOTE: Read-only in Decompression. */ - } JCHSZD_b; + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; }; union { - __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ struct { - __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed - * The values of this register are reset before compression - * starts.NOTE: Read-only in Decompression. */ - } JCDTCU_b; + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; }; union { - __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ struct { - __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe - * values of this register are reset before compression starts. - * NOTE: Read-only in Decompression. */ - } JCDTCM_b; + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; }; union { - __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ struct { - __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe - * values of this register are reset before compression starts.NOTE: - * Read-only in Decompression. */ - } JCDTCD_b; + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; }; + __IM uint32_t RESERVED; union { - __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ struct { - uint8_t : 3; - __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it - * has been determined that the image size and the subsampling - * setting of the compressed data can be read through analyzing - * the data. */ - uint8_t : 1; - __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the - * final number of MCU data in the Huffman-coding segment - * is not correct in decompression. When this bit is not set - * to enable interrupt generation, an error code is not returned. */ - __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the - * total number of data in the Huffman-coding segment is not - * correct in decompression. When this bit is not set to enable - * interrupt generation, an error code is not returned. */ - __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the - * number of data in the restart interval of the Huffman-coding - * segment is not correct in decompression.When this bit is - * not set to enable interrupt generation, an error code is - * not returned. */ - } JINTE0_b; + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; }; union { - __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ struct { - uint8_t : 3; - __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format - * can be read. When an interrupt occurs, this module stops - * processing and the state is indicated by the JCRST register. - * To make this module resume processing, set the JPEG core - * process stop clear command bit (JRST) in JCCMD. */ - uint8_t : 1; - __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ - __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression - * process normally. */ - uint8_t : 1; - } JINTS0_b; + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; }; union { - __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ struct { - __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error - * which has occurred in the compressed data analysis for - * decompression. */ - uint8_t : 4; - } JCDERR_b; + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; }; + __IM uint32_t RESERVED1; union { - __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ struct { - __IM uint8_t RST : 1; /*!< [0..0] Operating State */ - uint8_t : 7; - } JCRST_b; + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[11]; union { - __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ struct { - __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ - uint32_t : 1; - __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ - __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid - * only when the count mode for stopping the input of image - * data lines is on. Setting this bit to 1 resumes reading - * input image data. This bit is always read as 0. */ - __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data - * Lines This bit is only valid when the count mode for stopping - * the input of image data lines is on. Set this bit before - * writing 1 to the data-line resume command bit. */ - uint32_t : 1; - __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression - * is swapped. */ - uint32_t : 21; - } JIFECNT_b; + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; }; + __IM uint32_t RESERVED2[499]; union { - __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ struct { - __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The - * lower three bits should be set to 0. */ - } JIFESA_b; + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ union { - __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ struct { - __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower - * three bits should be set to 0. */ - uint32_t : 17; - } JIFESOFST_b; + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; }; + __IM uint8_t RESERVED; union { - __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address - * Register */ + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - struct + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union { - __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The - * lower three bits should be set to 0. */ - } JIFEDA_b; + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; }; + __IM uint8_t RESERVED1; union { - __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count - * Register */ + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - struct + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union { - __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line - * units) The lower three bits should be set to 0. */ - uint32_t : 16; - } JIFESLC_b; + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; }; - __IM uint32_t RESERVED3; + __IM uint8_t RESERVED2; union { - __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ - - struct + union { - __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is - * swapped. */ - uint32_t : 1; - __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ - __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid - * only when the count mode for stopping the output of image - * data lines is on. Setting this bit to 1 resumes writing - * image data. This bit is always read as 0. */ - __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image - * Data Lines This bit is only valid when the count mode for - * stopping the output of image data lines is on. Set this - * bit before writing 1 to the data-line resume command bit. */ - uint32_t : 1; - __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression - * is swapped. */ - uint32_t : 1; - __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ - __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only - * when the count mode for stopping the input of coded data - * is on. Setting this bit to 1 resumes reading input coded - * data. This bit is always read as 0. */ - __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed - * This bit is only valid when the count mode for stopping - * the input of coded data is on. Set this bit before writing - * 1 to the data resume command bit. */ - uint32_t : 9; - __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ - __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output - * image data. */ - __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image - * data. */ - uint32_t : 2; - } JIFDCNT_b; + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; }; + __IM uint8_t RESERVED3; union { - __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - struct + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union { - __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source - * Address (in 8-byte units) The lower three bits should be - * set to 0. */ - } JIFDSA_b; + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; }; + __IM uint8_t RESERVED4; union { - __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ struct { - __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The - * lower three bits should be set to 0. */ - uint32_t : 17; - } JIFDDOFST_b; + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; }; + __IM uint8_t RESERVED5; union { - __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address - * Register */ + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ struct { - __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) - * The lower three bits should be set to 0. */ - } JIFDDA_b; + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count - * Register */ + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ struct { - __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) - * The lower three bits should be set to 0. */ - uint32_t : 16; - } JIFDSDC_b; + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; }; union { - __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line - * Count Register */ + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - struct + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union { - __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three - * bits should be set to 0. These bits are read as0.Number - * of input image data lines to be read, in 8-line units. */ - uint32_t : 16; - } JIFDDLC_b; + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; }; + __IM uint8_t RESERVED7; union { - __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - struct + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union { - __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ - uint32_t : 24; - } JIFDADT_b; + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; }; - __IM uint32_t RESERVED4[6]; + __IM uint8_t RESERVED8; union { - __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - struct + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union { - __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt - * request (JDTI) when the DOUTLF bit in JINTS1 is set to - * 1 */ - __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt - * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ - __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt - * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ - uint32_t : 2; - __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt - * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ - __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt - * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ - uint32_t : 25; - } JINTE1_b; + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; }; + __IM uint8_t RESERVED9; union { - __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - struct + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union { - __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number - * of lines of output image data indicated by JIFDDLC have - * been written. This bit is only valid when the DOUTLC bit - * in JIFDCNT is set to 1. */ - __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data - * indicated by JIFDSDC is read in decompression. This bit - * is valid only when the JINC bit in JIFDCNT is set to 1. */ - __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data - * is written in decompression. */ - uint32_t : 2; - __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data - * lines indicated by JIFESLC is read in compression. This - * bit is valid only when the DINLC bit in JIFECNT is set - * to 1. */ - __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data - * is written in compression. */ - uint32_t : 25; - } JINTS1_b; + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; }; - __IM uint32_t RESERVED5[27]; - __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ - __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ - __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ - __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ - __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ - __IM uint32_t RESERVED6; - __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ - __IM uint16_t RESERVED7; - __IM uint32_t RESERVED8[11]; - __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ - __IM uint32_t RESERVED9; - __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ - __IM uint16_t RESERVED10; -} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ + __IM uint8_t RESERVED10; -/* =========================================================================================================================== */ -/* ================ R_KINT ================ */ -/* =========================================================================================================================== */ + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ -/** - * @brief Key Interrupt Function (R_KINT) - */ + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; -typedef struct /*!< (@ 0x40080000) R_KINT Structure */ -{ union { - __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ - struct + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union { - __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ - uint8_t : 6; - __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ - } KRCTL_b; + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; }; - __IM uint8_t RESERVED[3]; + __IM uint8_t RESERVED12; union { - __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ - struct + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union { - __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ - __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ - __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ - __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ - __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ - __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ - __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ - __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ - } KRF_b; + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; }; - __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ - - struct + union { - __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ - __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ - __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ - __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ - __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ - __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ - __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ - __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ - } KRM_b; - }; -} R_KINT_Type; /*!< Size = 9 (0x9) */ + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ -/* =========================================================================================================================== */ -/* ================ R_MMF ================ */ -/* =========================================================================================================================== */ + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; -/** - * @brief Memory Mirror Function (R_MMF) - */ + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; -typedef struct /*!< (@ 0x40001000) R_MMF Structure */ -{ union { - __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ struct { - uint32_t : 7; - __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot - * be set in the low-order 7 bits. These bits are fixed to - * 0. */ - uint32_t : 1; - __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ - } MMSFR_b; + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; }; + __IM uint8_t RESERVED15; union { - __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ struct { - __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ - uint32_t : 23; - __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ - } MMEN_b; + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; }; -} R_MMF_Type; /*!< Size = 8 (0x8) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_MMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Master MPU (R_MPU_MMPU) - */ - -typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */ -{ - __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers */ -} R_MPU_MMPU_Type; /*!< Size = 3072 (0xc00) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SMPU ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Slave MPU (R_MPU_SMPU) - */ + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; -typedef struct /*!< (@ 0x40000C00) R_MPU_SMPU Structure */ -{ union { - __IOM uint16_t SMPUCTL; /*!< (@ 0x00000000) Slave MPU Control Register */ + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ struct { - __IOM uint16_t OAD : 1; /*!< [0..0] Master Group enable */ - __IOM uint16_t PROTECT : 1; /*!< [1..1] Protection of register */ - uint16_t : 6; - __OM uint16_t KEY : 8; /*!< [15..8] Key Code This bit is used to enable or disable rewriting - * of the PROTECT and OAD bit. */ - } SMPUCTL_b; + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; }; - __IM uint16_t RESERVED[7]; - __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU */ -} R_MPU_SMPU_Type; /*!< Size = 56 (0x38) */ - -/* =========================================================================================================================== */ -/* ================ R_MPU_SPMON ================ */ -/* =========================================================================================================================== */ - -/** - * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) - */ - -typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ -{ - __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ -} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ - -/* =========================================================================================================================== */ -/* ================ R_MSTP ================ */ -/* =========================================================================================================================== */ - -/** - * @brief System-Module Stop (R_MSTP) - */ + __IM uint8_t RESERVED18; -typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ -{ union { - __IOM uint32_t MSTPCRB; /*!< (@ 0x00000000) Module Stop Control Register B */ + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ struct { - uint32_t : 1; - __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ - __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ - uint32_t : 2; - __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ - __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ - __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ - __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ - __IOM uint32_t MSTPB9 : 1; /*!< [9..9] I2C Bus Interface 0 Module Stop */ - uint32_t : 1; - __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ - __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ - __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ - __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ - __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ - uint32_t : 2; - __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ - __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ - uint32_t : 2; - __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ - __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ - __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ - __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ - __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ - __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ - __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ - __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ - __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ - __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ - } MSTPCRB_b; + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; }; union { - __IOM uint32_t MSTPCRC; /*!< (@ 0x00000004) Module Stop Control Register C */ + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ struct { - __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ - __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ - __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ - __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ - __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ - uint32_t : 8; - __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ - __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 13; - __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ - uint32_t : 2; - __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ - } MSTPCRC_b; + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; }; union { - __IOM uint32_t MSTPCRD; /*!< (@ 0x00000008) Module Stop Control Register D */ + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ struct { - uint32_t : 2; - __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state - * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. - * In case the count source is sub-clock or LOCO, this bit - * should be set to 1 except when accessing the registers - * of AGT1. */ - __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state - * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. - * In case the count source is sub-clock or LOCO, this bit - * should be set to 1 except when accessing the registers - * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT ch0 Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT ch6 - ch1 Module Stop */ - uint32_t : 7; - __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ - uint32_t : 1; - __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ - __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; - __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ - __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ - uint32_t : 7; - __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ - __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ - uint32_t : 1; - __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ - } MSTPCRD_b; + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; }; -} R_MSTP_Type; /*!< Size = 12 (0xc) */ + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ /* =========================================================================================================================== */ -/* ================ R_OPAMP ================ */ +/* ================ R_SCI0 ================ */ /* =========================================================================================================================== */ /** - * @brief Operational Amplifier (R_OPAMP) + * @brief Serial Communications Interface (R_SCI0) */ -typedef struct /*!< (@ 0x40086000) R_OPAMP Structure */ +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ { - __IM uint8_t RESERVED[8]; - union { - __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */ - - struct + union { - __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */ - __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */ - __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */ - uint8_t : 4; - __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */ - } AMPMC_b; - }; + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - union - { - __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */ + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; - struct + union { - __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger - * control */ - __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger - * control */ - __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger - * control */ - __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger - * control */ - } AMPTRM_b; + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; }; union { - __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select - * Register */ + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ struct { - __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the - * AMPTRS register after setting the AMPTRM register. */ - uint8_t : 6; - } AMPTRS_b; + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; }; union { - __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */ - - struct + union { - __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */ - __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */ - __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */ - __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */ - uint8_t : 3; - __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference - * current circuit */ - } AMPC_b; - }; + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - union - { - __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */ + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; - struct + union { - __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */ - __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */ - __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */ - __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */ - uint8_t : 4; - } AMPMON_b; + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; }; - __IM uint8_t RESERVED1; - __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier - * [0..3] */ union { - __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control - * register */ + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ struct { - __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */ - __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */ - __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */ - uint8_t : 5; - } AMPCPC_b; + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; }; - __IM uint8_t RESERVED2[4]; union { - __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable - * Register */ + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - struct + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union { - __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */ - __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */ - __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */ - uint8_t : 5; - } AMPUOTE_b; - }; - __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */ -} R_OPAMP_Type; /*!< Size = 38 (0x26) */ + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ -/* =========================================================================================================================== */ -/* ================ R_PDC ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; -/** - * @brief Parallel Data Capture Unit (R_PDC) - */ + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; -typedef struct /*!< (@ 0x40094000) R_PDC Structure */ -{ union { - __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */ + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ struct { - __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */ - __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */ - __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */ - __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */ - __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */ - __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */ - __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */ - __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */ - __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */ - __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */ - __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */ - __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */ - __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */ - uint32_t : 17; - } PCCR0_b; + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; }; union { - __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */ + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ struct { - __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */ - uint32_t : 31; - } PCCR1_b; + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; }; union { - __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */ + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ struct { - __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */ - __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */ - __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */ - __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */ - __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */ - __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */ - __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */ - uint32_t : 25; - } PCSR_b; + uint8_t : 2; + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; }; union { - __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */ + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ struct { - __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */ - __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */ - uint32_t : 30; - } PCMONR_b; + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; }; union { - __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */ + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ struct { - __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the - * storage of captured data. The PCDR register is a 4-byte - * space to which the FIFO is mapped, and four bytes of data - * are read from the PCDR register at a time. */ - } PCDR_b; + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; }; union { - __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */ + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ struct { - __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line - * where capture is to start. */ - uint32_t : 4; - __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */ - uint32_t : 4; - } VCR_b; + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; }; union { - __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */ + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ struct { - __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position - * in bytes where capture is to start. */ - uint32_t : 4; - __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture - * horizontally. */ - uint32_t : 4; - } HCR_b; + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; }; -} R_PDC_Type; /*!< Size = 28 (0x1c) */ - -/* =========================================================================================================================== */ -/* ================ R_PORT0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief I/O Ports (R_PORT0) - */ -typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ -{ union { - union - { - __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ - - struct - { - __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ - __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ - } PCNTR1_b; - }; + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ struct { - union - { - __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ - - struct - { - __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ - __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ - __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ - __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ - __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ - __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ - __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ - __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ - __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ - __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ - __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ - __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ - __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ - __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ - __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ - __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ - } PODR_b; - }; - - union - { - __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ - - struct - { - __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ - __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ - __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ - __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ - __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ - __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ - __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ - __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ - __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ - __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ - __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ - __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ - __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ - __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ - __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ - __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ - } PDR_b; - }; - }; + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; }; union - { - union - { - __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ - - struct - { - __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ - __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ - } PCNTR2_b; - }; - - struct - { - union - { - __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ - - struct - { - __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ - __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ - __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ - __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ - __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ - __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ - __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ - __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ - __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ - __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ - __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ - __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ - __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ - __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ - __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ - __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ - } EIDR_b; - }; - - union - { - __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ - - struct - { - __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ - __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ - __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ - __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ - __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ - __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ - __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ - __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ - __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ - __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ - __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ - __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ - __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ - __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ - __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ - __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ - } PIDR_b; - }; - }; + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + uint8_t : 1; + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; }; union { union { - __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ struct { - __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ - __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ - } PCNTR3_b; + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; }; struct { union { - __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ struct { - __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ - __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ - __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ - __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ - __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ - __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ - __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ - __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ - __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ - __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ - __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ - __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ - __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ - __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ - __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ - __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ - } PORR_b; + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; }; union { - __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ struct { - __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ - __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ - __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ - __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ - __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ - __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ - __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ - __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ - __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ - __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ - __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ - __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ - __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ - __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ - __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ - __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ - } POSR_b; + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; }; }; }; @@ -12153,6487 +14466,6258 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure { union { - __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ struct { - __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ - __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ - } PCNTR4_b; + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; }; struct { union { - __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ struct { - __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ - __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ - __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ - __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ - __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ - __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ - __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ - __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ - __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ - __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ - __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ - __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ - __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ - __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ - __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ - __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ - } EORR_b; + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; }; union { - __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ struct { - __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ - __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ - __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ - __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ - __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ - __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ - __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ - __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ - __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ - __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ - __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ - __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ - __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ - __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ - __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ - __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ - } EOSR_b; + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; }; }; }; -} R_PORT0_Type; /*!< Size = 16 (0x10) */ -/* =========================================================================================================================== */ -/* ================ R_PFS ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ -/** - * @brief I/O Ports-PFS (R_PFS) - */ + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ -{ - __IOM R_PFS_PORT_Type PORT[12]; /*!< (@ 0x00000000) Port [0..11] */ -} R_PFS_Type; /*!< Size = 768 (0x300) */ + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ -/* =========================================================================================================================== */ -/* ================ R_PMISC ================ */ -/* =========================================================================================================================== */ + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; -/** - * @brief I/O Ports-MISC (R_PMISC) - */ + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; -typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ -{ union { - __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ struct { - uint8_t : 4; - __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ - __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ - uint8_t : 2; - } PFENET_b; + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; }; - __IM uint8_t RESERVED[2]; union { - __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ struct { - uint8_t : 6; - __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ - __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ - } PWPR_b; + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; }; -} R_PMISC_Type; /*!< Size = 4 (0x4) */ -/* =========================================================================================================================== */ -/* ================ R_QSPI ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ -/** - * @brief Quad Serial Peripheral Interface (R_QSPI) - */ + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; -typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ -{ union { - __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ struct { - __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ - uint32_t : 1; - __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ - __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ - __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations - * other than on byte boundaries */ - __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by - * input to CFGMD3. */ - __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for - * the serial interface */ - __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ - __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ - uint32_t : 3; - __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ - uint32_t : 16; - } SFMSMD_b; + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; }; union { - __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ struct { - __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ - __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ - __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ - uint32_t : 26; - } SFMSSC_b; + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; }; union { - __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ struct { - __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention - * to the irregularity.)NOTE: When PCLKA multiplied by an - * odd number is selected, the high-level width of the SCK - * signal is longer than the low-level width by 1 x PCLKA - * before duty ratio correction. */ - __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the - * SCK signal */ - uint32_t : 26; - } SFMSKC_b; + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; }; union { - __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ struct { - __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 - * (No combination other than the above is available.) */ - uint32_t : 1; - __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ - __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ - uint32_t : 24; - } SFMSST_b; + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; }; union { - __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ struct { - __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output - * to and from this port is converted to a SPIbus cycle. This - * port is accessible in the direct communication mode (DCOM=1) - * only.Access to this port is ignored in the ROM access mode. */ - uint32_t : 24; - } SFMCOM_b; + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; }; union { - __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ struct { - __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ - uint32_t : 31; - } SFMCMD_b; + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; }; union { - __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ struct { - __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ - uint32_t : 6; - __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication - * modeNOTE: Writing of 0 only is possible. Writing of 1 is - * ignored. */ - uint32_t : 24; - } SFMCST_b; + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; }; - __IM uint32_t RESERVED; union { - __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ struct { - __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ - uint32_t : 24; - } SFMSIC_b; + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; }; union { - __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ struct { - __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ - uint32_t : 2; - __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial - * Interface address width is selected 4 bytes. */ - uint32_t : 27; - } SFMSAC_b; + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ union { - __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ struct { - __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read - * instructions */ - uint32_t : 2; - __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ - __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ - __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ - uint32_t : 16; - } SFMSDC_b; + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; }; - __IM uint32_t RESERVED1; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ union { - __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ struct { - __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol - * is required to be set by software separately. */ - uint32_t : 2; - __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, - * when Dual SPI protocol or Quad SPI protocol is selected. */ - uint32_t : 27; - } SFMSPC_b; + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ union { - __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ struct { - uint32_t : 2; - __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ - uint32_t : 29; - } SFMPMD_b; + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; }; - __IM uint32_t RESERVED2[499]; union { - __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ struct { - uint32_t : 26; - __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 - * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order - * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ - } SFMCNT1_b; + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; }; -} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ /* =========================================================================================================================== */ -/* ================ R_RTC ================ */ +/* ================ R_SDADC0 ================ */ /* =========================================================================================================================== */ /** - * @brief Realtime Clock (R_RTC) + * @brief R_SDADC0 (R_SDADC0) */ -typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +typedef struct /*!< (@ 0x4009C000) R_SDADC0 Structure */ { union { - __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + __IOM uint16_t STC1; /*!< (@ 0x00000000) Startup Control Register 1 */ + + struct + { + __IOM uint16_t CLKDIV : 4; /*!< [3..0] SDADC24 Reference Clock Division */ + uint16_t : 3; + __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select */ + __IOM uint16_t VSBIAS : 4; /*!< [11..8] Reference voltage select */ + uint16_t : 3; + __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select */ + } STC1_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t STC2; /*!< (@ 0x00000004) Startup Control Register 2 */ + + struct + { + __IOM uint8_t BGRPON : 1; /*!< [0..0] BGR part power control */ + __IOM uint8_t ADCPON : 1; /*!< [1..1] ADREG forced power-down */ + __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part */ + uint8_t : 5; + } STC2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint32_t PGAC[5]; /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register */ + + struct + { + __IOM uint32_t PGAGC : 5; /*!< [4..0] Gain selection of a programmable gain instrumentation + * amplifier ( Gset1, Gset2, Gtotal ) */ + __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select */ + __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select */ + uint32_t : 1; + __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select */ + __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select */ + __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count + * (N) in AUTOSCAN */ + __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count + * (N) in AUTOSCAN */ + __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged */ + __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing */ + __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select */ + uint32_t : 1; + __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable */ + __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of + * A/D conversions in ADSCAN */ + } PGAC_b[5]; + }; + + union + { + __IOM uint32_t ADC1; /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1 */ + + struct + { + __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode */ + uint32_t : 3; + __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal */ + uint32_t : 3; + __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer */ + uint32_t : 3; + __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection */ + __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting */ + uint32_t : 2; + __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable */ + uint32_t : 11; + } ADC1_b; + }; + + union + { + __IOM uint8_t ADC2; /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2 */ struct { - __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ - __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ - __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ - __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ - __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ - __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ - __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ - uint8_t : 1; - } R64CNT_b; + __IOM uint8_t SDADST : 1; /*!< [0..0] Control of A/D conversion */ + uint8_t : 7; + } ADC2_b; }; - __IM uint8_t RESERVED; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; union { - union - { - __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ - - struct - { - __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ - uint8_t : 1; - } RSECCNT_b; - }; + __IOM uint32_t ADCR; /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register */ - union + struct { - __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ - - struct - { - __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary - * counter b7 to b0. */ - } BCNT0_b; - }; + __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result */ + __IM uint32_t SDADCRS : 1; /*!< [24..24] Status of an A/D conversion result */ + __IM uint32_t SDADCRC : 3; /*!< [27..25] Channel number for an A/D conversion result */ + uint32_t : 4; + } ADCR_b; }; - __IM uint8_t RESERVED1; union { - union - { - __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ - uint8_t : 1; - } RMINCNT_b; - }; + __IM uint32_t ADAR; /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register */ - union + struct { - __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ - - struct - { - __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary - * counter b15 to b8. */ - } BCNT1_b; - }; + __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value */ + __IM uint32_t SDADMVS : 1; /*!< [24..24] Status of an A/D conversion result */ + __IM uint32_t SDADMVC : 3; /*!< [27..25] Channel number for an A/D conversion result */ + uint32_t : 4; + } ADAR_b; }; - __IM uint8_t RESERVED2; + __IM uint32_t RESERVED5; union { - union - { - __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from - * the ones place. */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - uint8_t : 1; - } RHRCNT_b; - }; + __IOM uint8_t CLBC; /*!< (@ 0x00000030) Calibration Control Register */ - union + struct { - __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ - - struct - { - __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2_b; - }; + __IOM uint8_t CLBMD : 2; /*!< [1..0] These bits are read as 0. The write value should be 0. */ + uint8_t : 6; + } CLBC_b; }; - __IM uint8_t RESERVED3; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; union { - union - { - __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 5; - } RWKCNT_b; - }; + __IOM uint8_t CLBSTR; /*!< (@ 0x00000034) Calibration Start Control Register */ - union + struct { - __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ - - struct - { - __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3_b; - }; + __IOM uint8_t CLBST : 1; /*!< [0..0] Calibration start control */ + uint8_t : 7; + } CLBSTR_b; }; - __IM uint8_t RESERVED4; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; union { - __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + __IM uint8_t CLBSSR; /*!< (@ 0x0000003C) Calibration Status Register */ struct { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry - * is generated, 1 is added to the tens place. */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the - * ones place. */ - uint8_t : 2; - } RDAYCNT_b; + __IM uint8_t CLBSS : 1; /*!< [0..0] Calibration status */ + uint8_t : 7; + } CLBSSR_b; }; - __IM uint8_t RESERVED5; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; +} R_SDADC0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ +typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ +{ union { - __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ struct { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When - * a carry is generated, 1 is added to the tens place. */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from - * the ones place. */ - uint8_t : 3; - } RMONCNT_b; + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; }; - __IM uint8_t RESERVED6; + __IM uint32_t RESERVED; union { - __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ struct { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a - * carry is generated, 1 is added to the tens place. */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from - * ones place. When a carry is generated in the tens place, - * 1 is added to the hundreds place. */ - uint16_t : 8; - } RYRCNT_b; + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; }; union { - union - { - __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ - - struct - { - __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ - __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RSECAR_b; - }; + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ - union + struct { - __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ - - struct - { - __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b7 to b0. */ - } BCNT0AR_b; - }; + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; }; - __IM uint8_t RESERVED7; union { - union - { - __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ - - struct - { - __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ - __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMINAR_b; - }; + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ - union + struct { - __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ - - struct - { - __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register - * corresponding to 32-bit binary counter b15 to b8. */ - } BCNT1AR_b; - }; + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes emp */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically i */ + uint32_t : 23; + } SD_STOP_b; }; - __IM uint8_t RESERVED8; union { - union - { - __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ - - struct - { - __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ - __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ - __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RHRAR_b; - }; + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ - union + struct { - __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ - - struct - { - __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary - * counter b23 to b16. */ - } BCNT2AR_b; - }; + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; }; - __IM uint8_t RESERVED9; union { - union - { - __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ - - struct - { - __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ - uint8_t : 4; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RWKAR_b; - }; + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ - union + struct { - __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ - - struct - { - __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary - * counter b31 to b24. */ - } BCNT3AR_b; - }; + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; }; - __IM uint8_t RESERVED10; union { - union - { - __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ - - struct - { - __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ - __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ - uint8_t : 1; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RDAYAR_b; - }; + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ - union + struct { - __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b7 to b0. */ - } BCNT0AER_b; - }; + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; }; - __IM uint8_t RESERVED11; union { - union + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct { - __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; - struct - { - __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ - __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ - uint8_t : 2; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RMONAR_b; - }; + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ - union + struct { - __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b15 to b8. */ - } BCNT1AER_b; - }; + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; }; - __IM uint8_t RESERVED12; union { - union + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct { - __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; - struct - { - __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ - __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ - uint16_t : 8; - } RYRAR_b; - }; + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ - union + struct { - __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ - - struct - { - __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b23 to b16. */ - uint16_t : 8; - } BCNT2AER_b; - }; + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; }; union { - union + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct { - __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; - struct - { - uint8_t : 7; - __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ - } RYRAREN_b; - }; + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ - union + struct { - __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ - - struct - { - __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register - * for setting the alarm enable corresponding to 32-bit binary - * counter b31 to b24. */ - } BCNT3AER_b; - }; + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; }; - __IM uint8_t RESERVED13; - __IM uint16_t RESERVED14; union { - __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ struct { - __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ - __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ - __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ - __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ - __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ - } RCR1_b; + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; }; - __IM uint8_t RESERVED15; union { - __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ struct { - __IOM uint8_t START : 1; /*!< [0..0] Start */ - __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ - __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ - __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ - __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, - * the setting of this bit is disabled.) */ - __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock - * is selected, the setting of this bit is disabled.) */ - __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ - __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ - } RCR2_b; + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; }; - __IM uint8_t RESERVED16; - __IM uint16_t RESERVED17; union { - __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ struct { - __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ - uint8_t : 6; - __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ - } RCR4_b; + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ struct { - __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating - * clock from the LOCOclock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - uint16_t : 15; - } RFRH_b; + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; }; union { - __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ struct { - __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating - * clock from the main clock, this bit sets the comparison - * value of the 128-Hz clock cycle. */ - } RFRL_b; + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; }; union { - __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ struct { - __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value - * from the prescaler. */ - __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ - } RADJ_b; + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mult */ + uint32_t : 22; + } SD_SIZE_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20[8]; - __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ - __IM uint16_t RESERVED21[5]; - __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ -} R_RTC_Type; /*!< Size = 128 (0x80) */ - -/* =========================================================================================================================== */ -/* ================ R_SCI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Communications Interface (R_SCI0) - */ -typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ -{ union { - union - { - __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ - __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ - __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ - } SMR_b; - }; + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ - union + struct { - __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ - - struct - { - __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ - __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ - __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ - __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ - __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ - __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ - } SMR_SMCI_b; - }; + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; }; + __IM uint32_t RESERVED1; union { - __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ struct { - __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ - } BRR_b; + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; }; union { - union - { - __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous - * mode when SMR.MP = 1) */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_b; - }; + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ - union + struct { - __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ - - struct - { - __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ - __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ - __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ - __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ - __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ - __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ - __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ - } SCR_SMCI_b; - }; + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; }; union { - __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ struct { - __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ - } TDR_b; + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; }; + __IM uint32_t RESERVED2; union { - union - { - __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ - - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_b; - }; - - union - { - __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ - - struct - { - __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including - * multi-processor) and FIFO selected) */ - uint8_t : 1; - __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ - __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ - } SSR_FIFO_b; - }; - - union - { - __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ - struct - { - __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart - * card interface mode. */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface - * mode. */ - __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ - __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ - __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ - __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ - __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ - } SSR_SMCI_b; - }; + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; }; union { - __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ struct { - __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ - } RDR_b; + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; }; union { - __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ struct { - __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ - uint8_t : 1; - __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if - * operation is to be in simple I2C mode. */ - __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The - * setting is invalid and a fixed data length of 8 bits is - * used in modes other than asynchronous mode.Set this bit - * to 1 if operation is to be in simple I2C mode. */ - __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ - uint8_t : 2; - __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles - * in combination with the SMR.BCP[1:0] bits */ - } SCMR_b; + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; }; + __IM uint32_t RESERVED3[79]; union { - __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ struct { - uint8_t : 2; - __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ - __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid - * only in asynchronous mode and SCR.CKE[1]=0) */ - __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous - * mode) */ - __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should - * be 0 without simple I2C mode and asynchronous mode.)In - * asynchronous mode, for RXDn input only. In simple I2C mode, - * for RXDn/TxDn input. */ - __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid - * the CKE[1] bit in SCR is 0 in asynchronous mode). */ - __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only - * in asynchronous mode) */ - } SEMR_b; + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; }; + __IM uint32_t RESERVED4[3]; union { - __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ struct { - __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ - uint8_t : 5; - } SNFR_b; + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; }; + __IM uint32_t RESERVED5[2]; union { - __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ struct { - __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ - uint8_t : 2; - __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock - * signal from the on-chip baud rate generator. */ - } SIMR1_b; + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; }; + __IM uint32_t RESERVED6[4]; union { - __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ struct { - __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ - __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ - uint8_t : 3; - __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ - uint8_t : 2; - } SIMR2_b; + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Segment LCD Controller/Driver (R_SLCDC) + */ +typedef struct /*!< (@ 0x40082000) R_SLCDC Structure */ +{ union { - __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + __IOM uint8_t LCDM0; /*!< (@ 0x00000000) LCD Mode Register 0 */ struct { - __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ - __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ - __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ - __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed - * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ - __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ - __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ - } SIMR3_b; + __IOM uint8_t LBAS : 2; /*!< [1..0] LCD Display Bias Method Select */ + __IOM uint8_t LDTY : 3; /*!< [4..2] Time Slice of LCD Display Select */ + __IOM uint8_t LWAVE : 1; /*!< [5..5] LCD display waveform selection */ + __IOM uint8_t MDSET : 2; /*!< [7..6] LCD drive voltage generator selection */ + } LCDM0_b; }; union { - __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + __IOM uint8_t LCDM1; /*!< (@ 0x00000001) LCD Mode Register 1 */ struct { - __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ - uint8_t : 7; - } SISR_b; + __IOM uint8_t LCDVLM : 1; /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control */ + uint8_t : 2; + __IOM uint8_t LCDSEL : 1; /*!< [3..3] Display data area control */ + __IOM uint8_t BLON : 1; /*!< [4..4] Display data area control */ + __IOM uint8_t VLCON : 1; /*!< [5..5] Voltage boost circuit or capacitor split circuit operation + * enable/disable */ + __IOM uint8_t SCOC : 1; /*!< [6..6] LCD Display Enable/Disable */ + __IOM uint8_t LCDON : 1; /*!< [7..7] LCD Display Enable/Disable */ + } LCDM1_b; }; union { - __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + __IOM uint8_t LCDC0; /*!< (@ 0x00000002) LCD Clock Control Register 0 */ struct { - __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ - __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ - __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ - uint8_t : 1; - __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ - uint8_t : 1; - __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ - __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ - } SPMR_b; + __IOM uint8_t LCDC : 6; /*!< [5..0] LCD clock (LCDCL) */ + uint8_t : 2; + } LCDC0_b; }; union { - union + __IOM uint8_t VLCD; /*!< (@ 0x00000003) LCD Boost Level Control Register */ + + struct { - __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ + uint8_t : 3; + } VLCD_b; + }; + __IM uint8_t RESERVED[252]; - struct - { - __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ - } TDRHL_b; - }; + union + { + __IOM uint8_t SEG[64]; /*!< (@ 0x00000100) LCD Display Data Array */ - union + struct { - __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + __IOM uint8_t A : 4; /*!< [3..0] A-Pattern Area */ + __IOM uint8_t B : 4; /*!< [7..4] B-Pattern Area */ + } SEG_b[64]; + }; +} R_SLCDC_Type; /*!< Size = 320 (0x140) */ - struct - { - __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint16_t : 6; - } FTDRHL_b; - }; +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ struct { - union - { - __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; - struct - { - __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous - * mode and SMR.MP=1 and FIFO selected) */ - uint8_t : 6; - } FTDRH_b; - }; + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ - union - { - __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; - struct - { - __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * and FIFO selected) */ - } FTDRL_b; - }; - }; + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; }; union { - union - { - __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ - - struct - { - __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ - } RDRHL_b; - }; + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ - union + struct { - __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; - struct - { - __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ - __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ - __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ - __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ - __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint16_t : 1; - } FRDRHL_b; - }; + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ struct { - union - { - __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ - - struct - { - __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode - * with SMR.MP=1 and FIFO selected) It can read multi-processor - * bit corresponded to serial receive data(RDATA[8:0]) */ - __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ - __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ - __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ - __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ - __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ - uint8_t : 1; - } FRDRH_b; - }; + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; - union - { - __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ - struct - { - __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: - * When reading both of FRDRH register and FRDRL register, - * please read by an order of the FRDRH register and the FRDRL - * register. */ - } FRDRL_b; - }; - }; + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; }; union { - __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ struct { - __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ - } MDDR_b; + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; }; union { - __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ struct { - __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ - uint8_t : 2; - __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ - __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ - uint8_t : 1; - __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including - * multi-processor) */ - __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous - * mode(including multi-processor) */ - } DCCR_b; + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; }; union { - __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ struct { - __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode) */ - __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ - __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a - * reception data ready, the interrupt request is selected.) */ - __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode) */ - __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only - * in asynchronous mode(including multi-processor) or clock - * synchronous mode) */ - } FCR_b; + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; }; union { - __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ struct { - __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive - * data stored in FRDRH and FRDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit - * data stored in FTDRH and FTDRL(Valid only in asynchronous - * mode(including multi-processor) or clock synchronous mode, - * while FCR.FM=1) */ - uint16_t : 3; - } FDR_b; + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; }; union { - __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ struct { - __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including - * multi-processor) or clock synchronous mode, and FIFO selected) */ - uint16_t : 1; - __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with - * a framing error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 1; - __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with - * a parity error among the receive data stored in the receive - * FIFO data register (FRDRH and FRDRL). */ - uint16_t : 3; - } LSR_b; + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; }; union { - __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ struct { - __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match - * wake-up function */ - uint16_t : 7; - } CDR_b; + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; }; union { - __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ struct { - __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal - * is shown.) */ - __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of - * TxD terminal is selected when SCR.TE = 0.) */ - __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value - * of SPB2DT is output to TxD terminal.) */ - uint8_t : 5; - } SPTR_b; + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; }; - __IM uint8_t RESERVED; - __IM uint16_t RESERVED1; -} R_SCI0_Type; /*!< Size = 32 (0x20) */ -/* =========================================================================================================================== */ -/* ================ R_SDADC0 ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ -/** - * @brief R_SDADC0 (R_SDADC0) - */ + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; -typedef struct /*!< (@ 0x4009C000) R_SDADC0 Structure */ -{ union { - __IOM uint16_t STC1; /*!< (@ 0x00000000) Startup Control Register 1 */ + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ struct { - __IOM uint16_t CLKDIV : 4; /*!< [3..0] SDADC24 Reference Clock Division */ - uint16_t : 3; - __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select */ - __IOM uint16_t VSBIAS : 4; /*!< [11..8] Reference voltage select */ - uint16_t : 3; - __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select */ - } STC1_b; + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; }; __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; union { - __IOM uint8_t STC2; /*!< (@ 0x00000004) Startup Control Register 2 */ + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ struct { - __IOM uint8_t BGRPON : 1; /*!< [0..0] BGR part power control */ - __IOM uint8_t ADCPON : 1; /*!< [1..1] ADREG forced power-down */ - __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part */ - uint8_t : 5; - } STC2_b; + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ union { - __IOM uint32_t PGAC[5]; /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register */ + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ struct { - __IOM uint32_t PGAGC : 5; /*!< [4..0] Gain selection of a programmable gain instrumentation - * amplifier ( Gset1, Gset2, Gtotal ) */ - __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select */ - __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select */ - uint32_t : 1; - __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select */ - __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select */ - __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count - * (N) in AUTOSCAN */ - __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count - * (N) in AUTOSCAN */ - __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged */ - __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing */ - __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select */ - uint32_t : 1; - __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable */ - __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of - * A/D conversions in ADSCAN */ - } PGAC_b[5]; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; }; + __IM uint8_t RESERVED[3]; union { - __IOM uint32_t ADC1; /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1 */ + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ struct { - __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode */ - uint32_t : 3; - __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal */ - uint32_t : 3; - __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer */ - uint32_t : 3; - __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection */ - __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting */ - uint32_t : 2; - __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable */ - uint32_t : 11; - } ADC1_b; + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; }; + __IM uint8_t RESERVED1[3]; union { - __IOM uint8_t ADC2; /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2 */ + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ struct { - __IOM uint8_t SDADST : 1; /*!< [0..0] Control of A/D conversion */ - uint8_t : 7; - } ADC2_b; + __IOM uint8_t ECCRAMWRWTEN : 1; /*!< [0..0] ECCRAM Write Wait Enable */ + __IOM uint8_t ECCRAMRDWTEN : 1; /*!< [1..1] ECCRAM Read wait enable */ + __IOM uint8_t SRAM0WTEN : 1; /*!< [2..2] SRAM0 Wait Enable */ + __IOM uint8_t SRAM1WTEN : 1; /*!< [3..3] SRAM1 Wait Enable */ + __IOM uint8_t SRAMHSWTEN : 1; /*!< [4..4] SRAMHS Wait Enable */ + uint8_t : 3; + } SRAMWTSC_b; }; - __IM uint8_t RESERVED3; - __IM uint16_t RESERVED4; + __IM uint8_t RESERVED2[3]; union { - __IOM uint32_t ADCR; /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register */ + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ struct { - __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result */ - __IM uint32_t SDADCRS : 1; /*!< [24..24] Status of an A/D conversion result */ - __IM uint32_t SDADCRC : 3; /*!< [27..25] Channel number for an A/D conversion result */ - uint32_t : 4; - } ADCR_b; + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; }; + __IM uint8_t RESERVED3[179]; union { - __IM uint32_t ADAR; /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register */ + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ struct { - __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value */ - __IM uint32_t SDADMVS : 1; /*!< [24..24] Status of an A/D conversion result */ - __IM uint32_t SDADMVC : 3; /*!< [27..25] Channel number for an A/D conversion result */ - uint32_t : 4; - } ADAR_b; + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; }; - __IM uint32_t RESERVED5; union { - __IOM uint8_t CLBC; /*!< (@ 0x00000030) Calibration Control Register */ + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ struct { - __IOM uint8_t CLBMD : 2; /*!< [1..0] These bits are read as 0. The write value should be 0. */ - uint8_t : 6; - } CLBC_b; + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; union { - __IOM uint8_t CLBSTR; /*!< (@ 0x00000034) Calibration Start Control Register */ + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ struct { - __IOM uint8_t CLBST : 1; /*!< [0..0] Calibration start control */ - uint8_t : 7; - } CLBSTR_b; + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; }; - __IM uint8_t RESERVED8; - __IM uint16_t RESERVED9; - __IM uint32_t RESERVED10; union { - __IM uint8_t CLBSSR; /*!< (@ 0x0000003C) Calibration Status Register */ + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ struct { - __IM uint8_t CLBSS : 1; /*!< [0..0] Calibration status */ - uint8_t : 7; - } CLBSSR_b; + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; -} R_SDADC0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SDHI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SD/MMC Host Interface (R_SDHI0) - */ -typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ -{ union { - __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ struct { - __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] - * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: - * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ - __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ - __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used - * in normal mode, see section 1.4.10, Example of SD_CMD Register - * Setting to select mode/response type. */ - __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ - __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data - * is handled) */ - __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command - * with data is handled) */ - __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block - * transfer) */ - uint32_t : 16; - } SD_CMD_b; + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; }; - __IM uint32_t RESERVED; + __IM uint8_t RESERVED4[11]; union { - __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ struct { - __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ - } SD_ARG_b; + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; }; + __IM uint8_t RESERVED5[3]; union { - __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ struct { - __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ - uint32_t : 16; - } SD_ARG1_b; + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; }; + __IM uint8_t RESERVED6[3]; union { - __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ struct { - __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, - * CMD12 is issued to halt the transfer through the SD host - * interface.However, if a command sequence is halted because - * of a communications error or timeout, CMD12 is not issued. - * Although continued buffer access is possible even after - * STP has been set to 1, the buffer access error bit (ERR5 - * or ERR4) in SD_INFO2 will be set accordingly.- When STP - * has been set to 1 during transfer for single block write, - * the access end flag is set when SD_BUF becomes emp */ - uint32_t : 7; - __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When - * SD_CMD is set as follows to start the command sequence - * while SEC is set to 1, CMD12 is automatically issued to - * stop multi-block transfer with the number of blocks which - * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] - * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is - * automatically issued, multiple block transfer)When the - * command sequence is halted because of a communications - * error or timeout, CMD12 is not automatically i */ - uint32_t : 23; - } SD_STOP_b; + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ union { - __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ struct { - __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value - * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ - } SD_SECCNT_b; + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; }; + __IM uint32_t RESERVED[588]; union { - __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ struct { - __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP10_b; + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; }; union { - __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ struct { - __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP1_b; + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; }; union { - __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ struct { - __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP32_b; + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; }; union { - __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ struct { - __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP3_b; + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; }; union { - __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ struct { - __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ - } SD_RSP54_b; + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; }; union { - __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ struct { - __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ - uint32_t : 16; - } SD_RSP5_b; + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ - union - { - __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ - uint32_t : 8; - } SD_RSP76_b; - }; +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ union { - __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ struct { - __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ - uint32_t : 24; - } SD_RSP7_b; + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; }; union { - __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ struct { - __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ - uint32_t : 1; - __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ - __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ - __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ - __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ - uint32_t : 1; - __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ - __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ - __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ - __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ - uint32_t : 21; - } SD_INFO1_b; + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; }; + __IM uint32_t RESERVED[2]; union { - __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ struct { - __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ - __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ - __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ - __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ - __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ - __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ - __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ - __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified - * by SD_PORTSEL. */ - __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ - __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ - uint32_t : 3; - __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, - * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN - * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 - * cycles of SDCLK have elapsed after setting of the CBSY - * bit to 0 due to completion of the command sequence. */ - __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ - __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ - uint32_t : 16; - } SD_INFO2_b; + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; }; union { - __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ struct { - __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ - __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ - __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ - uint32_t : 3; - __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ - __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ - uint32_t : 22; - } SD_INFO1_MASK_b; + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; }; union { - __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ - - struct + union { - __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ - __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ - __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ - __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ - __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ - __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ - __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ - uint32_t : 1; - __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ - __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ - uint32_t : 5; - __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ - uint32_t : 16; - } SD_INFO2_MASK_b; + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ }; union { - __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ - - struct + union { - __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ - __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ - __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ - uint32_t : 22; - } SD_CLK_CTRL_b; + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ }; union { - __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ struct { - __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 - * and 512 bytes for the transfer of single blocks.In cases - * of multiple block transfer with automatic issuing of CMD12 - * (CMD18 and CMD25), the only specifiable transfer data size - * is 512 bytes. Furthermore, in cases of multiple block transfer - * without automatic issuing of CMD12, as well as 512 bytes, - * 32, 64, 128, and 256 bytes are specifiable. However, in - * the reading of 32, 64, 128, and 256 bytes for the transfer - * of multiple blocks, this is restricted to mult */ + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ uint32_t : 22; - } SD_SIZE_b; + } SSIOFR_b; }; union { - __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ struct { - __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ - __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ - __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating - * timeout, software reset should be executed to terminate - * command sequence. */ - uint32_t : 4; - __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ - uint32_t : 1; - __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset - * and when the SOFT_RST.SDRST flag is 0. */ - uint32_t : 16; - } SD_OPTION_b; + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; }; - __IM uint32_t RESERVED1; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; union { - __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ struct { - __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command - * issued within a command sequence */ - __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by - * setting a command index in SD_CMD, this is Indicated in - * CMDE0. */ - __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to - * a command issued within a command sequence */ - __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is - * issued by setting a command index in SD_CMD, this is indicated - * in RSPLENE0. */ - __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ - __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ - uint32_t : 2; - __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a - * command issued within a command sequence */ - __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued - * by setting a command index in SD_CMD, this is indicated - * in RSPCRCE0. */ - __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ - __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ - __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal - * value is 010b) */ - uint32_t : 17; - } SD_ERR_STS1_b; + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; union { - __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ struct { - __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ - __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ - __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ - __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ - __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ - __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ - __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ - uint32_t : 25; - } SD_ERR_STS2_b; + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; }; union { - __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ struct { - __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write - * data is written to this register. When reading from the - * SD card, the read data is read from this register. This - * register is internally connected to two 512-byte buffers.If - * both buffers are not empty when executing multiple block - * read, SD/MMC clock is stopped to suspend receiving data. - * When one of buffers is empty, SD/MMC clock is supplied - * to resume receiving data. */ - } SD_BUF0_b; + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; }; - __IM uint32_t RESERVED2; union { - __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ struct { - __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ - uint32_t : 1; - __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ - uint32_t : 5; - __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ - __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ - uint32_t : 22; - } SDIO_MODE_b; + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; }; + __IM uint8_t RESERVED3; union { - __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ struct { - __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ - uint32_t : 13; - __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ - __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ - uint32_t : 16; - } SDIO_INFO1_b; + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; }; + __IM uint8_t RESERVED4; union { - __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ struct { - __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ - uint32_t : 13; - __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ - __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ - uint32_t : 16; - } SDIO_INFO1_MASK_b; + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; }; - __IM uint32_t RESERVED3[79]; union { - __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ struct { - uint32_t : 1; - __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ - uint32_t : 30; - } SD_DMAEN_b; + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; }; - __IM uint32_t RESERVED4[3]; union { - __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ struct { - __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ - uint32_t : 31; - } SOFT_RST_b; + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; }; - __IM uint32_t RESERVED5[2]; + __IM uint32_t RESERVED5; union { - __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ struct { - uint32_t : 8; - __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ - uint32_t : 23; - } SDIF_MODE_b; + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; }; - __IM uint32_t RESERVED6[4]; union { - __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ struct { - uint32_t : 6; - __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ - __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ - uint32_t : 24; - } EXT_SWAP_b; + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; }; -} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ - -/* =========================================================================================================================== */ -/* ================ R_SLCDC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Segment LCD Controller/Driver (R_SLCDC) - */ -typedef struct /*!< (@ 0x40082000) R_SLCDC Structure */ -{ union { - __IOM uint8_t LCDM0; /*!< (@ 0x00000000) LCD Mode Register 0 */ + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ struct { - __IOM uint8_t LBAS : 2; /*!< [1..0] LCD Display Bias Method Select */ - __IOM uint8_t LDTY : 3; /*!< [4..2] Time Slice of LCD Display Select */ - __IOM uint8_t LWAVE : 1; /*!< [5..5] LCD display waveform selection */ - __IOM uint8_t MDSET : 2; /*!< [7..6] LCD drive voltage generator selection */ - } LCDM0_b; + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; union { - __IOM uint8_t LCDM1; /*!< (@ 0x00000001) LCD Mode Register 1 */ + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ struct { - __IOM uint8_t LCDVLM : 1; /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control */ - uint8_t : 2; - __IOM uint8_t LCDSEL : 1; /*!< [3..3] Display data area control */ - __IOM uint8_t BLON : 1; /*!< [4..4] Display data area control */ - __IOM uint8_t VLCON : 1; /*!< [5..5] Voltage boost circuit or capacitor split circuit operation - * enable/disable */ - __IOM uint8_t SCOC : 1; /*!< [6..6] LCD Display Enable/Disable */ - __IOM uint8_t LCDON : 1; /*!< [7..7] LCD Display Enable/Disable */ - } LCDM1_b; + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; }; + __IM uint8_t RESERVED8; union { - __IOM uint8_t LCDC0; /*!< (@ 0x00000002) LCD Clock Control Register 0 */ + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ struct { - __IOM uint8_t LCDC : 6; /*!< [5..0] LCD clock (LCDCL) */ - uint8_t : 2; - } LCDC0_b; + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; }; union { - __IOM uint8_t VLCD; /*!< (@ 0x00000003) LCD Boost Level Control Register */ + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ struct - { - __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ - uint8_t : 3; - } VLCD_b; + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; }; - __IM uint8_t RESERVED[252]; union { - __IOM uint8_t SEG[64]; /*!< (@ 0x00000100) LCD Display Data Array */ + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ struct { - __IOM uint8_t A : 4; /*!< [3..0] A-Pattern Area */ - __IOM uint8_t B : 4; /*!< [7..4] B-Pattern Area */ - } SEG_b[64]; + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; }; -} R_SLCDC_Type; /*!< Size = 320 (0x140) */ - -/* =========================================================================================================================== */ -/* ================ R_SPI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Peripheral Interface (R_SPI0) - */ -typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ -{ union { - __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ struct { - __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ - __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ - __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ - __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ - __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ - __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ - __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ - __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ - } SPCR_b; + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; }; + __IM uint8_t RESERVED9; union { - __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ struct { - __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ - __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ - __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ - __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ - uint8_t : 4; - } SSLP_b; + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; }; union { - __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ struct { - __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ - __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ - uint8_t : 2; - __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ - __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ - uint8_t : 2; - } SPPCR_b; + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; }; union { - __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ struct { - __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ - __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ - __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ - __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ - __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ - __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ - uint8_t : 1; - __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ - } SPSR_b; + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; }; union { - __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ - __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ - __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; union { - __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ struct { - __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which - * the SPCMD0 to SPCMD07 registers are to be referenced is - * changed in accordance with the sequence length that is - * set in these bits. The relationship among the setting of - * these bits, sequence length, and SPCMD0 to SPCMD7 registers - * referenced by the RSPI is shown above. However, the RSPI - * in slave mode always references SPCMD0. */ - uint8_t : 5; - } SPSCR_b; + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ struct { - __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ - } SPBR_b; + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; }; + __IM uint8_t RESERVED12; + __IM uint32_t RESERVED13; union { - __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ struct { - __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ - uint8_t : 2; - __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ - __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ - __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ - uint8_t : 1; - } SPDCR_b; + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; }; + __IM uint8_t RESERVED14; union { - __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ struct { - __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ - uint8_t : 5; - } SPCKD_b; + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; }; union { - __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ struct { - __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ - uint8_t : 5; - } SSLND_b; + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; }; + __IM uint32_t RESERVED15[3]; + __IM uint8_t RESERVED16; union { - __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ struct { - __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ - uint8_t : 5; - } SPND_b; + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; }; union { - __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ struct { - __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ - __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ - __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ - __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ - __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ - uint8_t : 3; - } SPCR2_b; + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; }; + __IM uint8_t RESERVED17; + __IM uint32_t RESERVED18[2]; union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; }; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - uint8_t : 7; - } SPDCR2_b; + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; }; - __IM uint8_t RESERVED1; - __IM uint16_t RESERVED2; -} R_SPI0_Type; /*!< Size = 36 (0x24) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; }; - __IM uint8_t RESERVED[3]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; }; - __IM uint8_t RESERVED1[3]; + __IM uint16_t RESERVED21; + __IM uint32_t RESERVED22[4]; union { - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ struct { - __IOM uint8_t ECCRAMWRWTEN : 1; /*!< [0..0] ECCRAM Write Wait Enable */ - __IOM uint8_t ECCRAMRDWTEN : 1; /*!< [1..1] ECCRAM Read wait enable */ - __IOM uint8_t SRAM0WTEN : 1; /*!< [2..2] SRAM0 Wait Enable */ - __IOM uint8_t SRAM1WTEN : 1; /*!< [3..3] SRAM1 Wait Enable */ - __IOM uint8_t SRAMHSWTEN : 1; /*!< [4..4] SRAMHS Wait Enable */ - uint8_t : 3; - } SRAMWTSC_b; + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; }; - __IM uint8_t RESERVED2[183]; + __IM uint32_t RESERVED23; + __IM uint16_t RESERVED24; union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; }; + __IM uint8_t RESERVED25; union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; }; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; }; + __IM uint16_t RESERVED26; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; }; + __IM uint16_t RESERVED27; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; }; - __IM uint8_t RESERVED3[11]; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; }; - __IM uint8_t RESERVED4[3]; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; }; - __IM uint8_t RESERVED5[3]; + __IM uint8_t RESERVED28; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ - -/* =========================================================================================================================== */ -/* ================ R_SRC ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Sampling Rate Converter (R_SRC) - */ + __IM uint8_t RESERVED29[2]; -typedef struct /*!< (@ 0x40048000) R_SRC Structure */ -{ union { - __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ struct { - __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ - uint32_t : 10; - } SRCFCTR_b[5552]; + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; }; - __IM uint32_t RESERVED[588]; + __IM uint16_t RESERVED30[2]; union { - __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ struct { - __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to - * input the data before sampling rate conversion. All the - * bits are read as 0. */ - } SRCID_b; + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; }; + __IM uint8_t RESERVED31; + __IM uint32_t RESERVED32[5]; union { - __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ struct { - __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output - * the data after sampling rate conversion. The data in the - * 16-stage output data FIFO is read through SRCOD. When the - * number of data in the output data FIFO is zero after the - * start of conversion, the value previously read is read - * again. */ - } SRCOD_b; + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; }; + __IM uint16_t RESERVED33; + __IM uint32_t RESERVED34[3]; union { - __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ struct { - __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ - uint16_t : 6; - __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ - __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ - uint16_t : 6; - } SRCIDCTRL_b; + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; }; union { - __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ struct { - __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ - uint16_t : 6; - __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ - __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ - __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ - uint16_t : 5; - } SRCODCTRL_b; + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; union { - __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ struct { - __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ - uint16_t : 1; - __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ - __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ - __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ - __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ - __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ - __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ - __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ - } SRCCTRL_b; + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; }; union { - __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ struct { - __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ - __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ - __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ - __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ - __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ - __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ - uint16_t : 1; - __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units - * in the input FIFO. */ - __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data - * units in the output FIFO. */ - } SRCSTAT_b; + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; }; -} R_SRC_Type; /*!< Size = 24576 (0x6000) */ -/* =========================================================================================================================== */ -/* ================ R_SSI0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) - */ - -typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ -{ union { - __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ struct { - __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ - __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ - uint32_t : 1; - __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value - * of outputting serial data is rewritten to 0 but data transmission - * is not stopped. Write dummy data to the SSIFTDR not to - * generate a transmit underflow because the number of data - * in the transmit FIFO is decreasing. */ - __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ - __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ - __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ - __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ - __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ - __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ - __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ - __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings - * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings - * are prohibited. */ - uint32_t : 1; - __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the - * bit clock frequency/2 fs. */ - __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ - __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ - uint32_t : 1; - __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ - __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ - __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ - __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ - __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ - __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ - uint32_t : 1; - } SSICR_b; + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; }; union { - __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ struct { - __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ - __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ - __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ - __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ - __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ - uint32_t : 18; - __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ - __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: - * Writable only to clear the flag. Confirm the value is 1 - * and then write 0. */ - uint32_t : 2; - } SSISR_b; + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; }; - __IM uint32_t RESERVED[2]; + __IM uint32_t RESERVED37[183]; union { - __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ struct { - __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ - __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ - __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by - * clearing either the RDF flag (see the description of the - * RDF bit for details) or RIE bit. */ - __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by - * clearing either the TDE flag (see the description of the - * TDE bit for details) or TIE bit. */ - __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ - __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis - * are the number of empty stages in SSIFTDR at which the - * TDE flag is set. */ - uint32_t : 8; - __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ - uint32_t : 14; - __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ - } SSIFCR_b; + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; }; + __IM uint32_t RESERVED38; union { - __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ struct { - __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register - * is a 32-byte FIFO register, the maximum number of data - * bytes that can be read from it while the RDF flag is 1 - * is indicated in the RDC[3:0] flags. If reading data from - * the SSIFRDR register is continued after all the data is - * read, undefined values will be read. */ - uint32_t : 7; - __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data - * units stored in SSIFRDR) */ - uint32_t : 2; - __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register - * is a 32-byte FIFO register, the maximum number of bytes - * that can be written to it while the TDE flag is 1 is 8 - * - TDC[3:0]. If writing data to the SSIFTDR register is - * continued after all the data is written, writing will be - * invalid and an overflow occurs. */ - uint32_t : 7; - __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of - * data units stored in SSIFTDR) */ - uint32_t : 2; - } SSIFSR_b; + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; }; union { union { - __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ struct { - __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of - * eight stages of 32-bit registers for storing data to be - * serially transmitted. NOTE: that when the SSIFTDR register - * is full of data (32 bytes), the next data cannot be written - * to it. If writing is attempted, it will be ignored and - * an overflow occurs. */ - } SSIFTDR_b; + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; }; - __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ - }; - union - { union { - __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ struct { - __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight - * stages of 32-bit registers for storing serially received - * data. */ - } SSIFRDR_b; + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; }; - __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ - __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ }; union { - __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ struct { - __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ - uint32_t : 6; - __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ - __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in - * Idle Status */ - uint32_t : 22; - } SSIOFR_b; + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; }; + __IM uint32_t RESERVED39[3]; union { - __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ struct { - __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ - uint32_t : 3; - __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ - uint32_t : 19; - } SSISCR_b; + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; }; -} R_SSI0_Type; /*!< Size = 40 (0x28) */ + __IM uint32_t RESERVED40[6]; + __IM uint16_t RESERVED41; -/* =========================================================================================================================== */ -/* ================ R_SYSTEM ================ */ -/* =========================================================================================================================== */ + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ -/** - * @brief System Pins (R_SYSTEM) - */ + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; -typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ -{ - __IM uint32_t RESERVED[3]; + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; union { - __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ struct { - uint16_t : 14; - __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ - __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ - } SBYCR_b; + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ struct { - __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ - __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ - uint32_t : 3; - __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ - __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ - __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ - uint32_t : 14; - __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ - uint32_t : 9; - } MSTPCRA_b; + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; }; union { - __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ struct { - __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ - uint32_t : 1; - __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ - uint32_t : 1; - __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ - uint32_t : 1; - __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ - uint32_t : 1; - __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ - uint32_t : 5; - __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ - uint32_t : 1; - __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ - uint32_t : 1; - } SCKDIVCR_b; + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; }; union { - __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ struct { - uint8_t : 4; - __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ - uint8_t : 1; - } SCKDIVCR2_b; + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; }; - __IM uint8_t RESERVED3; union { - __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ struct { - __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ - uint8_t : 5; - } SCKSCR_b; + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; }; - __IM uint8_t RESERVED4; union { - __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ struct { - __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ - uint16_t : 2; - __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ - uint16_t : 3; - __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency - * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - - * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 - * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 - * 111011: x30.0 */ - uint16_t : 2; - } PLLCCR_b; + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; }; union { - __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ struct { - __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ - uint8_t : 7; - } PLLCR_b; + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; }; + __IM uint8_t RESERVED42; union { - __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ struct { - __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ - uint8_t : 1; - __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ - } PLLCCR2_b; + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; }; - __IM uint32_t RESERVED5; union { - __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ struct { - __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ - uint8_t : 7; - } BCKCR_b; + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; }; union { - __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ struct { - __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT - * is prohibited when SCKDIVCR.ICK selects division by 1 and - * SCKSCR.CKSEL[2:0] bits select thesystem clock source that - * is faster than 32 MHz (ICLK > 32 MHz). */ - uint8_t : 7; - } MEMWAIT_b; + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; }; union { - __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ struct { - __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ - uint8_t : 7; - } MOSCCR_b; + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; }; - __IM uint8_t RESERVED6; - __IM uint16_t RESERVED7; + __IM uint8_t RESERVED43; union { - __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ struct { - __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ - uint8_t : 7; - } HOCOCR_b; + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; }; - __IM uint8_t RESERVED8; + __IM uint16_t RESERVED44; union { - __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ struct { - __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ - uint8_t : 7; - } MOCOCR_b; + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; }; union { - __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ - struct + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union { - __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ - uint8_t : 7; - } FLLCR1_b; + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; }; union { - __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ - struct + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union { - __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the - * FLL reference clock select */ - uint16_t : 5; - } FLLCR2_b; + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; }; + __IM uint8_t RESERVED45; union { - __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ struct { - __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF - * bit value after a reset is 1 when the OFS1.HOCOEN bit is - * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ - uint8_t : 2; - __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ uint8_t : 1; - __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ - uint8_t : 2; - } OSCSF_b; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; }; - __IM uint8_t RESERVED9; union { - __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ struct { - __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ - uint8_t : 1; - __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ - __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ - } CKOCR_b; + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; }; + __IM uint8_t RESERVED46; union { - __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ struct { - __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ - uint8_t : 3; - __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ - } TRCKCR_b; + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; }; union { - __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ struct { - __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ - uint8_t : 6; - __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ - } OSTDCR_b; + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; }; union { - __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ struct { - __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ - uint8_t : 7; - } OSTDSR_b; + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; }; - __IM uint16_t RESERVED10; - __IM uint32_t RESERVED11[3]; + __IM uint32_t RESERVED47[24]; union { - __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ struct { - __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ - uint8_t : 4; - __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ - } SLCDSCKCR_b; + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; }; - __IM uint8_t RESERVED12; union { - __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ struct { - __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ - uint8_t : 7; - } EBCKOCR_b; + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; }; + __IM uint16_t RESERVED48; + __IM uint32_t RESERVED49[3]; union { - __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ struct { - __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ - uint8_t : 7; - } SDCKOCR_b; + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; }; - __IM uint32_t RESERVED13[3]; - __IM uint8_t RESERVED14; + __IM uint8_t RESERVED50; union { - __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ struct { - __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original MOCO + +126 0111_1111 : +127These bits are added to original LOCO * trimming bits */ - } MOCOUTCR_b; + } LOCOUTCR_b; }; + __IM uint8_t RESERVED51; + __IM uint32_t RESERVED52[7]; union { - __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ struct { - __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original HOCO - * trimming bits */ - } HOCOUTCR_b; + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; }; - __IM uint8_t RESERVED15; - __IM uint32_t RESERVED16[11]; - __IM uint16_t RESERVED17; union { - __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ struct { - __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other - * than in asynchronous mode. */ - __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ - uint8_t : 5; - __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ - } SNZCR_b; + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; }; - __IM uint8_t RESERVED18; union { - __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ struct { - __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ - __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ - __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ - __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ - __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ - __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ - __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set - * to 1 other than in asynchronous mode. */ - } SNZEDCR_b; + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; }; - __IM uint8_t RESERVED19; - __IM uint16_t RESERVED20; + __IM uint8_t RESERVED53; union { - __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ struct { - __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ - __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ - __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ - __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ - __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ - __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ - __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ - __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ - __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ - __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ - __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ - __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ - __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ - __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ - __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ - __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ - uint32_t : 1; - __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ - uint32_t : 4; - __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze - * request */ - __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze - * request */ - __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ - __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ - uint32_t : 2; - __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze - * request */ - __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A - * snooze request */ - __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B - * snooze request */ - uint32_t : 1; - } SNZREQCR_b; + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; }; - __IM uint16_t RESERVED21; + __IM uint8_t RESERVED54; union { - __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ struct { - __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ - uint8_t : 3; - __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ - uint8_t : 3; - } FLSTOP_b; + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; }; + __IM uint8_t RESERVED55; union { - __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ struct { - __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ - uint8_t : 6; - } PSMCR_b; + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; }; union { - __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ struct { - __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ - uint8_t : 2; - __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } OPCCR_b; + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; }; - __IM uint8_t RESERVED22; union { - __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ struct { - __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ - uint8_t : 4; - } MOSCWTCR_b; + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; }; - __IM uint8_t RESERVED23[2]; union { - __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ struct { - __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of - * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ - uint8_t : 5; - } HOCOWTCR_b; + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; }; - __IM uint16_t RESERVED24[2]; union { - __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ struct { - __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ - uint8_t : 3; - __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ - uint8_t : 3; - } SOPCCR_b; + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; }; - __IM uint8_t RESERVED25; - __IM uint32_t RESERVED26[5]; union { - __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ struct { - __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable - * only to clear the flag. Confirm the value is 1 and then - * write 0. */ - __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 5; - __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - uint16_t : 3; - } RSTSR1_b; + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; }; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28[3]; union { - __IOM uint8_t USBCKCR; /*!< (@ 0x000000D0) USB Clock Control Register */ + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ struct { - __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock - * (UCLK). */ - uint8_t : 7; - } USBCKCR_b; + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; }; union { - __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control - * Register */ + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ struct { - __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ - uint8_t : 6; - __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ - } SDADCCKCR_b; + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; }; - __IM uint16_t RESERVED29; - __IM uint32_t RESERVED30[3]; union { - __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ struct { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD1CR1_b; + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; }; + __IM uint8_t RESERVED56; + __IM uint16_t RESERVED57; + __IM uint32_t RESERVED58[15]; union { - __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ struct { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD1SR_b; + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; union { - __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ struct { - __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ - __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ - uint8_t : 5; - } LVD2CR1_b; + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; }; union { - __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ struct { - __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only - * 0 can be written to this bit. After writing 0 to this bit, - * it takes 2 system clock cycles for the bit to be read as - * 0. */ - __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ - uint8_t : 6; - } LVD2SR_b; + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; }; - __IM uint32_t RESERVED31[198]; - __IM uint16_t RESERVED32; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ union { - __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ struct { - __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock - * generation circuit. */ - __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating - * modes, the low power consumption modes and the battery - * backup function. */ - uint16_t : 1; - __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ - uint16_t : 4; - __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ - } PRCR_b; + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ union { - __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ struct { - __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ - uint8_t : 4; - __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ - __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ - } DPSBYCR_b; + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; }; - __IM uint8_t RESERVED33; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ union { - __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ struct { - __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER0_b; + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; }; union { - __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ struct { - __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ - __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ - } DPSIER1_b; + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; }; union { - __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ struct { - __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ - __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ - __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ - uint8_t : 3; - } DPSIER2_b; + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; }; union { - __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ struct { - __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ - __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ - uint8_t : 5; - } DPSIER3_b; + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; }; union { - __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ struct { - __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR0_b; + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; }; + __IM uint16_t RESERVED; union { - __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ struct { - __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ - __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ - } DPSIFR1_b; + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ struct { - __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ - __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ - __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ - __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ - uint8_t : 3; - } DPSIFR2_b; + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; }; union { - __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ struct { - __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ - __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ - uint8_t : 5; - } DPSIFR3_b; - }; + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; - union - { - __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - struct - { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR0_b; + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; }; union { - __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ struct { - __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ - __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ - } DPSIEGR1_b; + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; }; union { - __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ struct { - __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ - __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ - uint8_t : 2; - __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ - uint8_t : 3; - } DPSIEGR2_b; + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; }; - __IM uint8_t RESERVED34; union { - __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ struct { - __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ - uint8_t : 6; - __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ - } SYOCDCR_b; + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; }; + __IM uint32_t RESERVED6; union { - __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ struct { - __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ - uint8_t : 6; - } STCONR_b; + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; }; union { - __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ struct { - __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear - * the flag. Confirm the value is 1 and then write 0. */ - __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only - * to clear the flag. Confirm the value is 1 and then write - * 0. */ - uint8_t : 3; - __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to - * clear the flag. Confirm the value is 1 and then write 0. */ - } RSTSR0_b; + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; }; union { - __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ struct { - __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ - uint8_t : 7; - } RSTSR2_b; + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; }; - __IM uint8_t RESERVED35; union { - __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control - * Register */ + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ struct { - uint8_t : 3; - __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ - __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ - __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ - __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching - * Enable */ - } MOMCR_b; + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; }; - __IM uint16_t RESERVED36; union { - __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ struct { - __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ - uint8_t : 6; - } FWEPROR_b; + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; }; union { - __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ struct { - uint8_t : 5; - __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ - __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ - uint8_t : 1; - } LVCMPCR_b; + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; }; + __IM uint16_t RESERVED7; union { - __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ struct { - __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during - * fall in voltage) */ - __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during - * fall in voltage) */ - } LVDLVLR_b; + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; }; - __IM uint8_t RESERVED37; union { - __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ struct { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD1CR0_b; + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; }; union { - __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ - struct - { - __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ - __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ - __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ - uint8_t : 1; - __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ - __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ - __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ - } LVD2CR0_b; + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; }; - __IM uint16_t RESERVED38; - __IM uint8_t RESERVED39; union { - __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ struct { - __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ - uint8_t : 7; - } VBTCR1_b; + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; }; - __IM uint32_t RESERVED40[24]; union { - __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ struct { - __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ - uint8_t : 7; - } SOSCCR_b; + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; }; union { - __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ struct { - __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ - uint8_t : 6; - } SOMCR_b; + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; }; - __IM uint16_t RESERVED41; - __IM uint32_t RESERVED42[3]; union { - __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ struct { - __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ - uint8_t : 7; - } LOCOCR_b; + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; }; - __IM uint8_t RESERVED43; + __IM uint16_t RESERVED8; union { - __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ struct { - __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 - * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center - * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : - +126 0111_1111 : +127These bits are added to original LOCO - * trimming bits */ - } LOCOUTCR_b; + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; }; - __IM uint8_t RESERVED44; - __IM uint32_t RESERVED45[7]; union { - __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ struct { - uint8_t : 4; - __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ - uint8_t : 1; - __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ - } VBTCR2_b; + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; }; union { - __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ struct { - __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ - __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ - uint8_t : 2; - __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ - uint8_t : 3; - } VBTSR_b; + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; }; union { - __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ struct { - __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ - uint8_t : 7; - } VBTCMPCR_b; + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; }; - __IM uint8_t RESERVED46; union { - __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control - * Register */ + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ struct { - __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ - __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ - uint8_t : 6; - } VBTLVDICR_b; + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; }; - __IM uint8_t RESERVED47; union { - __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ struct { - __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ - uint8_t : 7; - } VBTWCTLR_b; + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; }; - __IM uint8_t RESERVED48; + __IM uint16_t RESERVED9; union { - __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ struct { - uint8_t : 1; - __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ - __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH0OTSR_b; + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; }; union { - __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ struct { - __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ - __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH1OTSR_b; + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; }; union { - __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ struct { - __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ - __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ - uint8_t : 1; - __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ - __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ - __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ - uint8_t : 2; - } VBTWCH2OTSR_b; + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; }; union { - __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ struct { - __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ - __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ - __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ - uint8_t : 5; - } VBTICTLR_b; + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; }; union { - __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ struct { - __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ - __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ - __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ - __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ - __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ - __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ - uint8_t : 2; - } VBTOCTLR_b; + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; }; union { - __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ struct { - __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ - __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ - __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ - __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ - __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ - __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ - uint8_t : 2; - } VBTWTER_b; + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; }; union { - __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ struct { - __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ - __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ - uint8_t : 5; - } VBTWEGR_b; + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; }; + __IM uint16_t RESERVED10; union { - __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ struct { - __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ - __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ - __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ - __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ - __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ - __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ - uint8_t : 2; - } VBTWFR_b; + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; }; - __IM uint32_t RESERVED49[16]; + __IM uint16_t RESERVED11; union { - __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ struct { - __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store - * data powered by VBATT.The value of this register is retained - * even when VCC is not powered but VBATT is powered.VBTBKR - * is initialized by VBATT selected voltage power-on-reset. */ - } VBTBKR_b[512]; + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; }; -} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN) - */ - -typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ -{ - __IM uint8_t RESERVED[552]; + __IM uint16_t RESERVED12; union { - __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register - * L */ + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ struct { - __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the converted - * value. */ - } TSCDRL_b; + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; }; union { - __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register - * H */ + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ struct { - __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the - * convertedvalue. */ - } TSCDRH_b; + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; }; -} R_TSN_Type; /*!< Size = 554 (0x22a) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CAL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CAL) - */ -typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ -{ union { - __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ struct { - __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor - * calibration converted value. */ - } TSCDR_b; + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; }; -} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ - -/* =========================================================================================================================== */ -/* ================ R_TSN_CTRL ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Temperature Sensor (R_TSN_CTRL) - */ + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; -typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ -{ union { - __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ struct { - uint8_t : 4; - __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ - uint8_t : 2; - __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ - } TSCR_b; + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; }; -} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_FS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_FS0) - */ + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; -typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ -{ union { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ struct { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 2; - __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - uint16_t : 1; - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - uint16_t : 5; - } SYSCFG_b; + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; union { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ struct { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - uint16_t : 12; - } BUSWAIT_b; + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; }; + __IM uint16_t RESERVED20; union { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ struct { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ - uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; }; + __IM uint32_t RESERVED21[3]; union { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ struct { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - uint16_t : 15; - } PLLSTA_b; + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; }; + __IM uint32_t RESERVED22[3]; union { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ struct { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - uint16_t : 4; - } DVSTCTR0_b; + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; }; - __IM uint16_t RESERVED; union { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ struct { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - uint16_t : 12; - } TESTMODE_b; + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; + __IM uint32_t RESERVED23[15]; union { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ struct { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; }; + __IM uint16_t RESERVED24; union { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ struct { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; }; union { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ struct { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; }; union { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ struct { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; }; union { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ struct { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; }; - __IM uint32_t RESERVED6; + __IM uint32_t RESERVED25[5]; union { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ struct { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; }; union { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ struct { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; }; union { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ struct { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; }; union { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ struct { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; }; + __IM uint32_t RESERVED26[165]; union { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ struct { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; }; union { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ struct { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 4; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; }; - __IM uint16_t RESERVED7; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - union - { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } BRDYENB_b; - }; +/** + * @brief USB 2.0 Module (R_USB_HS0) + */ +typedef struct /*!< (@ 0x40090000) R_USB_HS0 Structure */ +{ union { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ struct { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - uint16_t : 6; - } NRDYENB_b; + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + } SYSCFG_b; }; union { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ struct { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - uint16_t : 6; - } BEMPENB_b; + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + } BUSWAIT_b; }; union { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ struct { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - uint16_t : 7; - } SOFCFG_b; + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; }; union { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ struct { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + } PLLSTA_b; }; union { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ struct { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + } DVSTCTR0_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ struct { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + } TESTMODE_b; }; - __IM uint16_t RESERVED8; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; union { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ struct { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - uint16_t : 6; - } BRDYSTS_b; + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; }; union { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ struct { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - uint16_t : 6; - } NRDYSTS_b; + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; }; union { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ struct { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - uint16_t : 6; - } BEMPSTS_b; + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; }; union { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ struct { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; }; union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; }; + __IM uint32_t RESERVED6; union { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ struct { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - uint16_t : 5; - } USBADDR_b; + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; }; - __IM uint16_t RESERVED9; union { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ struct { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; }; union { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ struct { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; }; union { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ struct { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; }; union { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ struct { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; }; union { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ struct { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - uint16_t : 7; - } DCPCFG_b; + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; }; + __IM uint16_t RESERVED7; union { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ struct { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + } BRDYENB_b; }; union { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ struct { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 2; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + } NRDYENB_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ struct { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - uint16_t : 12; - } PIPESEL_b; + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + } BEMPENB_b; }; - __IM uint16_t RESERVED11; union { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ struct { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - uint16_t : 1; - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + } SOFCFG_b; }; - __IM uint16_t RESERVED12; union { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ struct - { - __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and - * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [8:7] are not provided.) */ - uint16_t : 3; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; }; union { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ struct { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - uint16_t : 3; - } PIPEPERI_b; + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; }; union { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ struct { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[3]; + __IM uint16_t RESERVED8; union { - __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ struct { - __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ - __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ - __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ - __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ - __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ - uint16_t : 1; - __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ - __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ - __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ - uint16_t : 6; - } USBBCCTRL0_b; + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + } BRDYSTS_b; }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[4]; union { - __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ struct { - __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ - uint16_t : 15; - } UCKSEL_b; + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + } NRDYSTS_b; }; - __IM uint16_t RESERVED18; - __IM uint32_t RESERVED19; union { - __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ struct { - __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ - uint16_t : 6; - __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ - uint16_t : 8; - } USBMC_b; + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + } BEMPSTS_b; }; - __IM uint16_t RESERVED20; union { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ struct { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - uint16_t : 1; - } DEVADD_b[10]; + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; }; - __IM uint32_t RESERVED21[3]; union { - __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ struct { - __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ - __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ - __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ - uint32_t : 28; - } PHYSLEW_b; + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; }; - __IM uint32_t RESERVED22[3]; union { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ struct { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - uint16_t : 8; - } LPCTRL_b; + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + } USBADDR_b; }; + __IM uint16_t RESERVED9; union { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ struct { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - uint16_t : 1; - } LPSTS_b; + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; }; - __IM uint32_t RESERVED23[15]; union { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ struct { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - uint16_t : 6; - } BCCTRL_b; + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; }; - __IM uint16_t RESERVED24; union { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ struct { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - uint16_t : 1; - } PL1CTRL1_b; + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; }; union { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ struct { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - uint16_t : 3; - } PL1CTRL2_b; + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; }; union { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ struct { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - uint16_t : 13; - } HL1CTRL1_b; + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + } DCPCFG_b; }; union { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ - - struct - { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; }; - __IM uint32_t RESERVED25[5]; union { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ struct { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - uint32_t : 8; - } DPUSR0R_b; + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; }; + __IM uint16_t RESERVED10; union { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ struct { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - uint32_t : 8; - } DPUSR1R_b; + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + } PIPESEL_b; }; + __IM uint16_t RESERVED11; union { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ struct { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - uint16_t : 6; - } DPUSR2R_b; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; }; union { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A)Pipe Buffer Register */ struct { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - uint16_t : 14; - } DPUSRCR_b; + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number of the + * selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + } PIPEBUF_b; /*!< BitSize */ }; - __IM uint32_t RESERVED26[165]; union { - __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin - * Monitor Register */ + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ struct { - __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ - __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ - uint32_t : 1; - __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ - __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ - uint32_t : 11; - __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ - __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ - uint32_t : 2; - __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal - * of the USB. */ - __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal - * of the USB. */ - uint32_t : 1; - __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the - * USB. */ - uint32_t : 8; - } DPUSR0R_FS_b; + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 1024 bytes (400h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h),512bytes(200h) ([2:0] are not + * provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [10:7] are not provided.) */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; }; union { - __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt - * Register */ + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ struct { - __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ - __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ - uint32_t : 2; - __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ - __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ - uint32_t : 1; - __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ - uint32_t : 8; - __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ - __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ - uint32_t : 2; - __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ - __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ - uint32_t : 1; - __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ - uint32_t : 8; - } DPUSR1R_FS_b; + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + } PIPEPERI_b; }; -} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_USB_HS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief USB 2.0 Module (R_USB_HS0) - */ -typedef struct /*!< (@ 0x40090000) R_USB_HS0 Structure */ -{ union { - __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ struct { - __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ - uint16_t : 3; - __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ - __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ - __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ - __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ - __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ - uint16_t : 1; - __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ - } SYSCFG_b; + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[11]; union { - __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ struct { - __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 - * access cycles) */ - } BUSWAIT_b; + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + } DEVADD_b[10]; }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[6]; union { - __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ struct { - __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ - __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ - uint16_t : 2; - __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is - * Selected. */ - __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ uint16_t : 7; - __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe - * OCVMON[1] bit indicates the status of the USBHS_OVRCURA - * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB - * pin. */ - } SYSSTS0_b; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + } LPCTRL_b; }; union { - __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ struct { - __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ - } PLLSTA_b; + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + } LPSTS_b; }; + __IM uint32_t RESERVED18[15]; union { - __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ struct { - __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ - uint16_t : 1; - __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ - __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ - __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ - __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ - __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ - __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ - __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ - __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is - * used when switching from device B to device A while in - * OTG mode. If the HNPBTOA bit is 1, the internal function - * control keeps the suspended state until the HNP processing - * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is - * set. */ - } DVSTCTR0_b; + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + } BCCTRL_b; }; - __IM uint16_t RESERVED; + __IM uint16_t RESERVED19; union { - __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ struct { - __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ - } TESTMODE_b; + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + } PL1CTRL1_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2; union { - __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ struct { - union - { - __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ - __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ - }; - - union - { - __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED3; - __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ - }; - }; - }; + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + } PL1CTRL2_b; }; union { - __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ struct { - union - { - __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ - __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED4; - __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ - }; - }; - }; + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + } HL1CTRL1_b; }; union { - __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ struct { - union - { - __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ - __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ - }; - - union - { - __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ - - struct - { - __IM uint8_t RESERVED5; - __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ - }; - }; - }; + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; }; + __IM uint32_t RESERVED20; union { - __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150)PHY Timing Register 1 */ struct { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ - uint16_t : 1; - __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ - uint16_t : 2; - __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ - uint16_t : 2; - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } CFIFOSEL_b; + __IOM uint16_t DRISE : 2; /*!< [1..0]FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2]FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7]PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8]HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12]terminating resistance offset value setting.Offset value for + * adjusting the terminating resistance. */ + } PHYTRIM1_b; /*!< BitSize */ }; union { - __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152)PHY Timing Register 2 */ struct { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } CFIFOCTR_b; + __IOM uint16_t SQU : 4; /*!< [3..0]Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7]HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8]HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12]Disconnect Detection Level */ + } PHYTRIM2_b; /*!< BitSize */ }; - __IM uint32_t RESERVED6; + __IM uint32_t RESERVED21[3]; union { - __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ struct { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D0FIFOSEL_b; + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + } DPUSR0R_b; }; union { - __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ struct { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D0FIFOCTR_b; + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + } DPUSR1R_b; }; union { - __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ struct { - __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ - uint16_t : 4; - __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ - uint16_t : 1; - __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ - __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ - __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified - * Pipe Data is Read */ - __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ - __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ - } D1FIFOSEL_b; + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + } DPUSR2R_b; }; union { - __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ struct { - __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive - * data. */ - uint16_t : 1; - __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ - __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ - __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ - } D1FIFOCTR_b; + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + } DPUSRCR_b; }; +} R_USB_HS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ union { - __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ struct { - uint16_t : 8; - __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ - __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ - __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ - __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ - __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ - __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ - __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ - __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ - } INTENB0_b; + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; }; + __IM uint8_t RESERVED; union { - __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ struct { - __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ - uint16_t : 3; - __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ - __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ - __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ - __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ - __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ - uint16_t : 1; - __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ - __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ - } INTENB1_b; + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; }; - __IM uint16_t RESERVED7; union { - __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ struct { - __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ - } BRDYENB_b; + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; }; union { - __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ struct { - __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ - } NRDYENB_b; + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; }; + __IM uint8_t RESERVED1; union { - __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ struct { - __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ - __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ - } BEMPENB_b; + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ union { - __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ struct { - uint16_t : 4; - __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ - __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ - __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ - uint16_t : 1; - __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ - } SOFCFG_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ struct { - __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ - __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ - uint16_t : 1; - __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ - __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ - uint16_t : 2; - __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ - uint16_t : 1; - __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ - uint16_t : 3; - __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ - } PHYSET_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; union { - __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ struct { - __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ - __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ - __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ - __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ - __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ - __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ - __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ - __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ - __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ - __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ - __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ - __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ - } INTSTS0_b; + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + __IM uint32_t RESERVED[4]; union { - __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ struct { - __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ - uint16_t : 3; - __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ - __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ - __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ - __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ - uint16_t : 1; - __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ - __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ - uint16_t : 1; - __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ - __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ - } INTSTS1_b; + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; }; - __IM uint16_t RESERVED8; union { - __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ struct { - __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ - } BRDYSTS_b; + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; }; + __IM uint32_t RESERVED1[6]; union { - __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ struct { - __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ - __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ - } NRDYSTS_b; + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; }; union { - __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ struct { - __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ - __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ - } BEMPSTS_b; + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; }; + __IM uint32_t RESERVED2[2]; union { - __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ struct { - __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ - uint16_t : 3; - __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ - __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ - } FRMNUM_b; + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; }; union { - __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ struct { - __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ - uint16_t : 12; - __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ - } UFRMNUM_b; + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; }; union { - __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ struct { - __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate - * the USB address assigned by the host when the USBHS processed - * the SET_ADDRESS request successfully. */ - uint16_t : 1; - __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ - } USBADDR_b; + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; }; - __IM uint16_t RESERVED9; union { - __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ struct { - __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType - * value. */ - __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ - } USBREQ_b; + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; }; union { - __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ struct { - __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ - } USBVAL_b; + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; }; union { - __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ struct { - __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ - } USBINDX_b; + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; }; + __IM uint32_t RESERVED3[6]; union { - __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ struct { - __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ - } USBLENG_b; + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; }; union { - __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ struct { - uint16_t : 4; - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - } DCPCFG_b; + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; }; union { - __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ struct { - __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount - * of data (maximum packet size) in payloads for the DCP. */ - uint16_t : 5; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } DCPMAXP_b; + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; }; + __IM uint32_t RESERVED4[33]; union { - __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ struct { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ - uint16_t : 1; - __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - uint16_t : 2; - __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ - __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ - __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } DCPCTR_b; + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; }; - __IM uint16_t RESERVED10; union { - __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ struct { - __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ - } PIPESEL_b; + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; }; - __IM uint16_t RESERVED11; + __IM uint32_t RESERVED5[10]; union { - __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ struct { - __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number - * for the selected pipe.Setting 0000b means unused pipe. */ - __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ - uint16_t : 2; - __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ - __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ - __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ - __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ - uint16_t : 3; - __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ - } PIPECFG_b; + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; }; union { - __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A)Pipe Buffer Register */ + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ struct { - __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number of the - * selected pipe (04h to 87h). */ - uint16_t : 2; - __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ - } PIPEBUF_b; /*!< BitSize */ + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; }; + __IM uint32_t RESERVED6[30]; union { - __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ struct { - __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to - * 1024 bytes (400h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes - * (010h), 32 bytes (020h), 64 bytes (040h),512bytes(200h) ([2:0] are not - * provided.)PIPE6 to PIPE9: 1 byte (001h) to - * 64 bytes (040h) (Bits [10:7] are not provided.) */ - uint16_t : 1; - __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ - } PIPEMAXP_b; + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ +/* =========================================================================================================================== */ +/* ================ R_OSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Octa Serial Peripheral Interface (R_OSPI) + */ + +typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ +{ union { - __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ struct { - __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval - * error detection timing for the selected pipe in terms of - * frames, which is expressed as nth power of 2. */ - uint16_t : 9; - __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ - } PIPEPERI_b; + __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ + __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ + uint32_t : 16; + } DCR_b; }; union { - __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ struct { - __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ - uint16_t : 3; - __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ - __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ - __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ - __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ - __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ - __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ - uint16_t : 1; - __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of - * Split Transaction of the relevant pipe */ - __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing - * the CSSTS bit of the relevant pipe */ - __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ - __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ - } PIPE_CTR_b[9]; + __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ + __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ + __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ + __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ + } DAR_b; }; - __IM uint16_t RESERVED13; - __IM uint32_t RESERVED14[3]; - __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ - __IM uint32_t RESERVED15[11]; union { - __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ struct { - uint16_t : 6; - __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ - __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ - __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ - } DEVADD_b[10]; + __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ + __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ + uint32_t : 3; + __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ + __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ + __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ + __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ + __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ + __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ + __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ + uint32_t : 2; + } DCSR_b; }; - __IM uint16_t RESERVED16; - __IM uint32_t RESERVED17[6]; union { - __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ struct { - uint16_t : 7; - __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ - } LPCTRL_b; + __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ + __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ + } DSR_b[2]; }; union { - __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ struct { - uint16_t : 14; - __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ - } LPSTS_b; + __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ + __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ + __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ + __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ + __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ + uint32_t : 4; + } MDTR_b; }; - __IM uint32_t RESERVED18[15]; union { - __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ struct { - __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ - __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ - __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ - __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ - __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ - __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ - uint16_t : 2; - __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ - __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ - } BCCTRL_b; + __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ + } ACTR_b; }; - __IM uint16_t RESERVED19; union { - __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ struct { - __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ - __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ - __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid - * only when the L1RESPMD[1:0] value is 2'b11. */ - __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates - * the L1 state together with the device state bits DVSQ[2:0]. */ - __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold - * value used for L1NEGOMD.The format is the same as the HIRD - * field in HL1CTRL. */ - uint16_t : 2; - __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ - } PL1CTRL1_b; + __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ + } ACAR_b[2]; }; + __IM uint32_t RESERVED[4]; union { - __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting + * Register */ struct { - uint16_t : 8; - __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ - __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ - } PL1CTRL2_b; + __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ + __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ + __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ + __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ + __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ + __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ + __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ + __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ + } DRCSTR_b; }; union { - __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting + * Register */ struct { - __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ - __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ - } HL1CTRL1_b; + __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ + __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ + __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ + __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ + __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ + __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ + __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ + __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ + } DWCSTR_b; }; union { - __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ struct { - __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to - * be set in the ADDR field of LPM token. */ - uint16_t : 4; - __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ - __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the - * value to be set in the RWE field of LPM token. */ - uint16_t : 2; - __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive - * period at the time of L1 Resume. */ - } HL1CTRL2_b; + uint32_t : 8; + __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ + __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ + __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ + uint32_t : 16; + } DCSTR_b; }; - __IM uint32_t RESERVED20; union { - __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150)PHY Timing Register 1 */ + __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ struct { - __IOM uint16_t DRISE : 2; /*!< [1..0]FS/LS Rising-Edge Output Waveform Adjustment Function */ - __IOM uint16_t DFALL : 2; /*!< [3..2]FS/LS Falling-Edge Output Waveform Adjustment Function */ - uint16_t : 3; - __IOM uint16_t PCOMPENB : 1; /*!< [7..7]PVDD Start-up Detection */ - __IOM uint16_t HSIUP : 4; /*!< [11..8]HS Output Level Setting */ - __IOM uint16_t IMPOFFSET : 3; /*!< [14..12]terminating resistance offset value setting.Offset value for - * adjusting the terminating resistance. */ - } PHYTRIM1_b; /*!< BitSize */ + __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ + __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ + __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ + __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ + uint32_t : 4; + __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device + * 0 */ + __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device + * 1 */ + __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ + uint32_t : 17; + __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ + } CDSR_b; }; union { - __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152)PHY Timing Register 2 */ + __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ struct { - __IOM uint16_t SQU : 4; /*!< [3..0]Squelch Detection Level */ - uint16_t : 3; - __IOM uint16_t HSRXENMO : 1; /*!< [7..7]HS Receive Enable Control Mode */ - __IOM uint16_t PDR : 2; /*!< [9..8]HS Output Adjustment Function */ - uint16_t : 2; - __IOM uint16_t DIS : 3; /*!< [14..12]Disconnect Detection Level */ - } PHYTRIM2_b; /*!< BitSize */ + __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ + __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ + __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ + __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ + } MDLR_b; }; - __IM uint32_t RESERVED21[3]; union { - __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor - * Register */ + __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ struct { - uint32_t : 20; - __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the - * HS side of USB port. */ - __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the - * HS side of USB port. */ - uint32_t : 1; - __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side - * of USB port. */ - } DPUSR0R_b; + __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ + __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ + __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ + __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ + } MRWCR_b[2]; }; union { - __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ struct { - uint32_t : 4; - __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ - __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ - uint32_t : 1; - __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ - uint32_t : 12; - __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ - __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ - uint32_t : 1; - __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ - } DPUSR1R_b; + __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ + __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ + __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ + __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ + __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ + __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ + __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ + uint32_t : 1; + __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ + __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ + __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ + __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ + __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ + __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ + __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ + uint32_t : 1; + } MRWCSR_b; }; union { - __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ struct { - __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ - __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ - uint16_t : 2; - __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB - * port. */ - __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB - * port. */ - uint16_t : 2; - __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ - __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ - } DPUSR2R_b; + __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ + __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ + uint32_t : 16; + } ESR_b; }; union { - __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ struct { - __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ - __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ - } DPUSRCR_b; + __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ + } CWNDR_b; }; -} R_USB_HS0_Type; /*!< Size = 1032 (0x408) */ - -/* =========================================================================================================================== */ -/* ================ R_WDT ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Watchdog Timer (R_WDT) - */ -typedef struct /*!< (@ 0x40044200) R_WDT Structure */ -{ union { - __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ struct { - __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter - * of the WDT. */ - } WDTRR_b; + __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ + __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ + __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ + __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ + } CWDR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ struct { - __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ - uint16_t : 2; - __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ - __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ - uint16_t : 2; - __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ - uint16_t : 2; - } WDTCR_b; + __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ + __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ + __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ + __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ + } CRR_b; }; union { - __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ struct { - __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ - __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ - __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ - } WDTSR_b; + __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ + __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ + uint32_t : 26; + } ACSR_b; }; + __IM uint32_t RESERVED1[5]; union { - __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ struct { - uint8_t : 7; - __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ - } WDTRCR_b; + __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are + * Low in single continuous write of OctaRAM. */ + uint32_t : 7; + __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 + * are Low in single continuous read of OctaRAM. */ + uint32_t : 7; + } DCSMXR_b; }; - __IM uint8_t RESERVED1; union { - __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating + * size Register */ struct { - uint8_t : 7; - __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ - } WDTCSTPR_b; + __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single + * continuous write of device 0. */ + uint32_t : 5; + __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single + * continuous write of device 1. */ + uint32_t : 5; + } DWSCTSR_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_WDT_Type; /*!< Size = 12 (0xc) */ +} R_OSPI_Type; /*!< Size = 132 (0x84) */ /** @} */ /* End of group Device_Peripheral_peripherals */ -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - - #define R_ACMPHS0_BASE 0x40085000UL - #define R_ACMPHS1_BASE 0x40085100UL - #define R_ACMPHS2_BASE 0x40085200UL - #define R_ACMPHS3_BASE 0x40085300UL - #define R_ACMPHS4_BASE 0x40085400UL - #define R_ACMPHS5_BASE 0x40085500UL - #define R_ACMPLP_BASE 0x40085E00UL - #define R_ADC0_BASE 0x4005C000UL - #define R_ADC1_BASE 0x4005C200UL - #define R_AGT0_BASE 0x40084000UL - #define R_AGT1_BASE 0x40084100UL - #define R_BUS_BASE 0x40003000UL - #define R_CAC_BASE 0x40044600UL - #define R_CAN0_BASE 0x40050000UL - #define R_CAN1_BASE 0x40051000UL - #define R_CRC_BASE 0x40074000UL - #define R_CTSU_BASE 0x40081000UL - #define R_CTSU2_BASE 0x40082000UL - #define R_DAC_BASE 0x4005E000UL - #define R_DAC8_BASE 0x4009E000UL - #define R_DALI0_BASE 0x4008F000UL - #define R_DEBUG_BASE 0x4001B000UL - #define R_DMA_BASE 0x40005200UL - #define R_DMAC0_BASE 0x40005000UL - #define R_DMAC1_BASE 0x40005040UL - #define R_DMAC2_BASE 0x40005080UL - #define R_DMAC3_BASE 0x400050C0UL - #define R_DMAC4_BASE 0x40005100UL - #define R_DMAC5_BASE 0x40005140UL - #define R_DMAC6_BASE 0x40005180UL - #define R_DMAC7_BASE 0x400051C0UL - #define R_DOC_BASE 0x40054100UL - #define R_DRW_BASE 0x400E4000UL - #define R_DTC_BASE 0x40005400UL - #define R_ELC_BASE 0x40041000UL - #define R_ETHERC0_BASE 0x40064100UL - #define R_ETHERC_EDMAC_BASE 0x40064000UL - #define R_ETHERC_EPTPC_BASE 0x40065800UL - #define R_ETHERC_EPTPC1_BASE 0x40065C00UL - #define R_ETHERC_EPTPC_CFG_BASE 0x40064500UL - #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000UL - #define R_FACI_HP_CMD_BASE 0x407E0000UL - #define R_FACI_HP_BASE 0x407FE000UL - #define R_FACI_LP_BASE 0x407EC000UL - #define R_FCACHE_BASE 0x4001C000UL - #define R_GLCDC_BASE 0x400E0000UL - #define R_GPT0_BASE 0x40078000UL - #define R_GPT1_BASE 0x40078100UL - #define R_GPT2_BASE 0x40078200UL - #define R_GPT3_BASE 0x40078300UL - #define R_GPT4_BASE 0x40078400UL - #define R_GPT5_BASE 0x40078500UL - #define R_GPT6_BASE 0x40078600UL - #define R_GPT7_BASE 0x40078700UL - #define R_GPT8_BASE 0x40078800UL - #define R_GPT9_BASE 0x40078900UL - #define R_GPT10_BASE 0x40078A00UL - #define R_GPT11_BASE 0x40078B00UL - #define R_GPT12_BASE 0x40078C00UL - #define R_GPT13_BASE 0x40078D00UL - #define R_GPT_ODC_BASE 0x4007B000UL - #define R_GPT_OPS_BASE 0x40078FF0UL - #define R_GPT_POEG0_BASE 0x40042000UL - #define R_GPT_POEG1_BASE 0x40042100UL - #define R_GPT_POEG2_BASE 0x40042200UL - #define R_GPT_POEG3_BASE 0x40042300UL - #define R_ICU_BASE 0x40006000UL - #define R_IIC0_BASE 0x40053000UL - #define R_IIC1_BASE 0x40053100UL - #define R_IIC2_BASE 0x40053200UL - #define R_IRDA_BASE 0x40070F00UL - #define R_IWDT_BASE 0x40044400UL - #define R_JPEG_BASE 0x400E6000UL - #define R_KINT_BASE 0x40080000UL - #define R_MMF_BASE 0x40001000UL - #define R_MPU_MMPU_BASE 0x40000000UL - #define R_MPU_SMPU_BASE 0x40000C00UL - #define R_MPU_SPMON_BASE 0x40000D00UL - #define R_MSTP_BASE 0x40047000UL - #define R_OPAMP_BASE 0x40086000UL - #define R_OPAMP2_BASE 0x400867F8UL - #define R_PDC_BASE 0x40094000UL - #define R_PORT0_BASE 0x40040000UL - #define R_PORT1_BASE 0x40040020UL - #define R_PORT2_BASE 0x40040040UL - #define R_PORT3_BASE 0x40040060UL - #define R_PORT4_BASE 0x40040080UL - #define R_PORT5_BASE 0x400400A0UL - #define R_PORT6_BASE 0x400400C0UL - #define R_PORT7_BASE 0x400400E0UL - #define R_PORT8_BASE 0x40040100UL - #define R_PORT9_BASE 0x40040120UL - #define R_PORT10_BASE 0x40040140UL - #define R_PORT11_BASE 0x40040160UL - #define R_PFS_BASE 0x40040800UL - #define R_PMISC_BASE 0x40040D00UL - #define R_QSPI_BASE 0x64000000UL - #define R_RTC_BASE 0x40044000UL - #define R_SCI0_BASE 0x40070000UL - #define R_SCI1_BASE 0x40070020UL - #define R_SCI2_BASE 0x40070040UL - #define R_SCI3_BASE 0x40070060UL - #define R_SCI4_BASE 0x40070080UL - #define R_SCI5_BASE 0x400700A0UL - #define R_SCI6_BASE 0x400700C0UL - #define R_SCI7_BASE 0x400700E0UL - #define R_SCI8_BASE 0x40070100UL - #define R_SCI9_BASE 0x40070120UL - #define R_SDADC0_BASE 0x4009C000UL - #define R_SDHI0_BASE 0x40062000UL - #define R_SDHI1_BASE 0x40062400UL - #define R_SLCDC_BASE 0x40082000UL - #define R_SPI0_BASE 0x40072000UL - #define R_SPI1_BASE 0x40072100UL - #define R_SRAM_BASE 0x40002000UL - #define R_SRC_BASE 0x40048000UL - #define R_SSI0_BASE 0x4004E000UL - #define R_SSI1_BASE 0x4004E100UL - #define R_SYSTEM_BASE 0x4001E000UL - #define R_TSN_BASE 0x407EC000UL - #define R_TSN_CAL_BASE 0x407FB17CUL - #define R_TSN_CTRL_BASE 0x4005D000UL - #define R_USB_FS0_BASE 0x40090000UL - #define R_USB_HS0_BASE 0x40060000UL - #define R_WDT_BASE 0x40044200UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - - #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) - #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) - #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) - #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) - #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) - #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) - #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) - #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) - #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) - #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) - #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) - #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) - #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) - #define R_CRC ((R_CRC_Type *) R_CRC_BASE) - #if (BSP_FEATURE_CTSU_VERSION == 2) - #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE) - #else - #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) - #endif - #define R_CTSU2 ((R_CTSU2_Type *) R_CTSU2_BASE) - #define R_DAC ((R_DAC_Type *) R_DAC_BASE) - #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) - #define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE) - #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) - #define R_DMA ((R_DMA_Type *) R_DMA_BASE) - #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) - #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) - #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) - #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) - #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) - #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) - #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) - #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) - #define R_DOC ((R_DOC_Type *) R_DOC_BASE) - #define R_DRW ((R_DRW_Type *) R_DRW_BASE) - #define R_DTC ((R_DTC_Type *) R_DTC_BASE) - #define R_ELC ((R_ELC_Type *) R_ELC_BASE) - #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) - #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) - #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE) - #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC1_BASE) - #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE) - #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE) - #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) - #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) - #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) - #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) - #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) - #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) - #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) - #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) - #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) - #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) - #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) - #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) - #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) - #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) - #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) - #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) - #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) - #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) - #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) - #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) - #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) - #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) - #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) - #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) - #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) - #define R_ICU ((R_ICU_Type *) R_ICU_BASE) - #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) - #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) - #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) - #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) - #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) - #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE) - #define R_KINT ((R_KINT_Type *) R_KINT_BASE) - #define R_MMF ((R_MMF_Type *) R_MMF_BASE) - #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE) - #define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE) - #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) - #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) - #if (BSP_FEATURE_OPAMP_BASE_ADDRESS == 2U) - #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE) - #else - #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) - #endif - #define R_PDC ((R_PDC_Type *) R_PDC_BASE) - #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) - #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) - #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) - #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) - #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) - #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) - #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) - #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) - #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) - #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) - #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) - #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) - #define R_PFS ((R_PFS_Type *) R_PFS_BASE) - #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) - #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) - #define R_RTC ((R_RTC_Type *) R_RTC_BASE) - #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) - #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) - #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) - #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) - #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) - #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) - #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) - #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) - #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) - #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) - #define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE) - #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) - #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) - #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE) - #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) - #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) - #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) - #define R_SRC ((R_SRC_Type *) R_SRC_BASE) - #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) - #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) - #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) - #define R_TSN ((R_TSN_Type *) R_TSN_BASE) - #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) - #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) - #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) - #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) - #define R_WDT ((R_WDT_Type *) R_WDT_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ + #include "base_addresses.h" /* ========================================= End of section using anonymous unions ========================================= */ #if defined(__CC_ARM) @@ -19414,6 +21498,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + /* =========================================================================================================================== */ /* ================ RTCCR ================ */ /* =========================================================================================================================== */ @@ -19604,6 +21694,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ /* ======================================================== ADANSA ========================================================= */ #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ @@ -19630,6 +21722,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ /* ======================================================== ADSTRGR ======================================================== */ #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ @@ -19648,6 +21742,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ /* ======================================================== ADANSB ========================================================= */ #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ @@ -19697,6 +21795,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ /* ========================================================= ADICR ========================================================= */ #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ @@ -19814,6 +21914,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ /* ========================================================= ADRD ========================================================== */ #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ @@ -19846,6 +21954,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ /* ======================================================= ADPGADCR0 ======================================================= */ #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ @@ -19861,6 +21971,349 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (4UL) /*!< MONSEL (Bit 4) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC26_Pos (26UL) /*!< PSARC26 (Bit 26) */ + #define R_PSCU_PSARC_PSARC26_Msk (0x4000000UL) /*!< PSARC26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS1_Pos (15UL) /*!< CFS1 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS1_Msk (0xff8000UL) /*!< CFS1 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS2_Pos (10UL) /*!< CFS2 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS2_Msk (0xfffc00UL) /*!< CFS2 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS1_Pos (13UL) /*!< SS1 (Bit 13) */ + #define R_PSCU_SSAMONA_SS1_Msk (0x1fe000UL) /*!< SS1 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS2_Pos (10UL) /*!< SS2 (Bit 10) */ + #define R_PSCU_SSAMONB_SS2_Msk (0x1ffc00UL) /*!< SS2 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ /* =========================================================================================================================== */ /* ================ R_AGT0 ================ */ @@ -19930,6 +22383,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ======================================================= AGTIOSEL ======================================================== */ #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ R_BUS ================ */ @@ -20525,6 +22980,15 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ======================================================= CTSUERRS ======================================================== */ #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ /* =========================================================================================================================== */ /* ================ R_CTSU2 ================ */ @@ -21096,14 +23560,23 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMA ================ */ /* =========================================================================================================================== */ /* ========================================================= DMAST ========================================================= */ - #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ - #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DMAC0 ================ */ @@ -21132,6 +23605,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ /* ========================================================= DMINT ========================================================= */ #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ @@ -21152,6 +23627,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ /* ========================================================= DMOFR ========================================================= */ #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ @@ -21170,6 +23649,21 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DOC ================ */ @@ -21530,27 +24024,85 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* =========================================================================================================================== */ /* ========================================================= DTCCR ========================================================= */ - #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ - #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ /* ======================================================== DTCVBR ========================================================= */ - #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ - #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ /* ========================================================= DTCST ========================================================= */ - #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ - #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ /* ======================================================== DTCSTS ========================================================= */ - #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ - #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ - #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ - #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ELC ================ */ /* =========================================================================================================================== */ /* ========================================================= ELCR ========================================================== */ - #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ - #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (0UL) /*!< ELSEGR0 (Bit 0) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x1UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (1UL) /*!< ELSEGR1 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x2UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELCR_Pos (2UL) /*!< ELCR (Bit 2) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x4UL) /*!< ELCR (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_ETHERC0 ================ */ @@ -22531,118 +25083,125 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* =========================================================================================================================== */ /* ======================================================== FASTAT ========================================================= */ - #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ - #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ - #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ - #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ - #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ /* ======================================================== FAEINT ========================================================= */ - #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ - #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ - #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ - #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ - #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ /* ======================================================== FRDYIE ========================================================= */ - #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ - #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ /* ======================================================== FSADDR ========================================================= */ - #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ - #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ /* ======================================================== FEADDR ========================================================= */ - #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ - #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ /* ======================================================== FSTATR ========================================================= */ - #define R_FACI_HP_FSTATR_EBFULL_Pos (18UL) /*!< EBFULL (Bit 18) */ - #define R_FACI_HP_FSTATR_EBFULL_Msk (0x40000UL) /*!< EBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTPDTCT_Pos (17UL) /*!< OTPDTCT (Bit 17) */ - #define R_FACI_HP_FSTATR_OTPDTCT_Msk (0x20000UL) /*!< OTPDTCT (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_OTPCRCT_Pos (16UL) /*!< OTPCRCT (Bit 16) */ - #define R_FACI_HP_FSTATR_OTPCRCT_Msk (0x10000UL) /*!< OTPCRCT (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ - #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ - #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ - #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ - #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ - #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ - #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ - #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ - #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FCUERR_Pos (7UL) /*!< FCUERR (Bit 7) */ - #define R_FACI_HP_FSTATR_FCUERR_Msk (0x80UL) /*!< FCUERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_FHVEERR_Pos (6UL) /*!< FHVEERR (Bit 6) */ - #define R_FACI_HP_FSTATR_FHVEERR_Msk (0x40UL) /*!< FHVEERR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_CFGDTCT_Pos (5UL) /*!< CFGDTCT (Bit 5) */ - #define R_FACI_HP_FSTATR_CFGDTCT_Msk (0x20UL) /*!< CFGDTCT (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_CFGCRCT_Pos (4UL) /*!< CFGCRCT (Bit 4) */ - #define R_FACI_HP_FSTATR_CFGCRCT_Msk (0x10UL) /*!< CFGCRCT (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_TBLDTCT_Pos (3UL) /*!< TBLDTCT (Bit 3) */ - #define R_FACI_HP_FSTATR_TBLDTCT_Msk (0x8UL) /*!< TBLDTCT (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FSTATR_TBLCRCT_Pos (2UL) /*!< TBLCRCT (Bit 2) */ - #define R_FACI_HP_FSTATR_TBLCRCT_Msk (0x4UL) /*!< TBLCRCT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ /* ======================================================== FENTRYR ======================================================== */ - #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ - #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ - #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ /* ======================================================= FSUINITR ======================================================== */ - #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ - #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ /* ========================================================= FCMDR ========================================================= */ - #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ - #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ - #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ /* ======================================================== FPESTAT ======================================================== */ - #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ - #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ /* ======================================================== FBCCNT ========================================================= */ - #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ - #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ /* ======================================================== FBCSTAT ======================================================== */ - #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ - #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ /* ======================================================== FPSADDR ======================================================== */ - #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ - #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ /* ======================================================== FAWMON ========================================================= */ - #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ - #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ - #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ - #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ - #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ - #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ - #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ /* ========================================================= FCPSR ========================================================= */ - #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ - #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ /* ======================================================== FPCKAR ========================================================= */ - #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ - #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ /* ======================================================== FSUACR ========================================================= */ - #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ - #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ - #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ /* =========================================================================================================================== */ /* ================ R_FACI_LP ================ */ @@ -22798,14 +25357,19 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* =========================================================================================================================== */ /* ======================================================== FCACHEE ======================================================== */ - #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ - #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ /* ======================================================= FCACHEIV ======================================================== */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ - #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ /* ========================================================= FLWT ========================================================== */ - #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ - #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GLCDC ================ */ @@ -22857,6 +25421,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ /* ========================================================= GTSTR ========================================================= */ #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ @@ -23034,8 +25606,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ /* ========================================================= GTCR ========================================================== */ - #define R_GPT0_GTCR_TPCS_Pos (24UL) /*!< TPCS (Bit 24) */ - #define R_GPT0_GTCR_TPCS_Msk (0x7000000UL) /*!< TPCS (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ @@ -23095,6 +25667,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ /* ========================================================= GTST ========================================================== */ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ @@ -23132,6 +25706,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ /* ========================================================= GTBER ========================================================= */ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ @@ -23238,6 +25814,56 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ======================================================== GTSOTR ========================================================= */ #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_GPT_ODC ================ */ @@ -23364,6 +25990,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ /* ========================================================= NMIER ========================================================= */ #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ @@ -23389,6 +26019,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ /* ======================================================== NMICLR ========================================================= */ #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ @@ -23414,6 +26048,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ /* ========================================================= NMICR ========================================================= */ #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ @@ -23469,6 +26107,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_IIC0 ================ */ @@ -23997,6 +26642,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ @@ -24014,6 +26673,18 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ @@ -24022,8 +26693,16 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -24032,6 +26711,35 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_OPAMP ================ */ @@ -24198,6 +26906,11 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_QSPI ================ */ @@ -24757,6 +27470,151 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ /* =========================================================================================================================== */ /* ================ R_SDADC0 ================ */ @@ -25148,6 +28006,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ /* ========================================================= SPPCR ========================================================= */ #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ @@ -25172,6 +28038,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ /* ========================================================= SPDR ========================================================== */ /* ======================================================== SPDR_HA ======================================================== */ /* ======================================================== SPDR_BY ======================================================== */ @@ -25190,6 +28058,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ /* ========================================================= SPCKD ========================================================= */ #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ @@ -25210,6 +28080,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ /* ========================================================= SPCMD ========================================================= */ #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ @@ -25234,6 +28106,27 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ======================================================== SPDCR2 ========================================================= */ #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ /* =========================================================================================================================== */ /* ================ R_SRAM ================ */ @@ -25286,6 +28179,11 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ======================================================== ECCOAD ========================================================= */ #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ /* =========================================================================================================================== */ /* ================ R_SRC ================ */ @@ -25436,6 +28334,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ /* ======================================================== SSIFSR ========================================================= */ #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ @@ -25554,6 +28454,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ /* ========================================================= CKOCR ========================================================= */ #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ @@ -25675,6 +28577,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ /* ======================================================== STCONR ========================================================= */ #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ @@ -25688,9 +28594,9 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ -/* ======================================================== USBCKCR ======================================================== */ - #define R_SYSTEM_USBCKCR_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ - #define R_SYSTEM_USBCKCR_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ /* ======================================================= SDADCCKCR ======================================================= */ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ @@ -25715,6 +28621,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIER0 ======================================================== */ #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ @@ -25739,6 +28647,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ /* ======================================================== DPSIFR0 ======================================================== */ #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ @@ -25763,6 +28673,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ /* ======================================================= DPSIEGR0 ======================================================== */ #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ @@ -25816,11 +28728,21 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ /* ======================================================== LVDLVLR ======================================================== */ #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ /* ======================================================== LVD1CR0 ======================================================== */ #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ @@ -25977,6 +28899,180 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ======================================================== FWEPROR ======================================================== */ #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_TSN ================ */ @@ -26590,6 +29686,323 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DCR ========================================================== */ + #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ + #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ + #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ +/* ========================================================== DAR ========================================================== */ + #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ + #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ + #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ + #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ + #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ +/* ========================================================= DCSR ========================================================== */ + #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ + #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ + #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ + #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ + #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ + #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ + #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ + #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ + #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ + #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DSR ========================================================== */ + #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ + #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ + #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ + #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ +/* ========================================================= MDTR ========================================================== */ + #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ + #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ + #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ + #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ + #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ + #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ + #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ + #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ +/* ========================================================= ACTR ========================================================== */ + #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ + #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ACAR ========================================================== */ + #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ + #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DRCSTR ========================================================= */ + #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ + #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ + #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ + #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ + #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ + #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ + #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ + #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ + #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ + #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ + #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ + #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ +/* ======================================================== DWCSTR ========================================================= */ + #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ + #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ + #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ + #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ + #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ + #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ + #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ + #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ + #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ + #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ + #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ + #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ +/* ========================================================= DCSTR ========================================================= */ + #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ + #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ + #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ + #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ +/* ========================================================= CDSR ========================================================== */ + #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ + #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ + #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ + #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ + #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ + #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ + #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ + #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ + #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ +/* ========================================================= MDLR ========================================================== */ + #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ + #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ + #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ + #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ + #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ +/* ========================================================= MRWCR ========================================================= */ + #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ + #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ + #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ + #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ + #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ +/* ======================================================== MRWCSR ========================================================= */ + #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ + #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ + #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ + #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ + #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ + #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ + #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ + #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ + #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ + #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ + #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ + #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ + #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ + #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ + #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ESR ========================================================== */ + #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ + #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ + #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ + #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ +/* ========================================================= CWNDR ========================================================= */ + #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ + #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CWDR ========================================================== */ + #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ + #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ + #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ + #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ + #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ +/* ========================================================== CRR ========================================================== */ + #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ + #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ + #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ + #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ + #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ +/* ========================================================= ACSR ========================================================== */ + #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ + #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ + #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ +/* ======================================================== DCSMXR ========================================================= */ + #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ + #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ + #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ + #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DWSCTSR ======================================================== */ + #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ + #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ + #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ + #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ + /** @} */ /* End of group PosMask_peripherals */ #ifdef __cplusplus diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd b/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd index c9bc9fc08..1d2bd186d 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd @@ -1,5 +1,5 @@ - - + + Renesas Renesas RA @@ -1202,6 +1202,25 @@ 4 read-write + + ADIE + Scan End Interrupt Enable + 12 + 12 + read-write + + + 0 + Disables S12ADI0 interrupt generation upon scan completion. + #0 + + + 1 + Enables S12ADI0 interrupt generation upon scan completion. + #1 + + + @@ -1503,6 +1522,25 @@ + + DCE + Discharge Enable + 4 + 4 + read-write + + + 0 + Discharge after the A/D conversion is disabled. + #0 + + + 1 + Discharge after the A/D conversion is enabled. + #1 + + + @@ -1653,6 +1691,49 @@ + + EXSEL + Extended Analog Input Select + 14 + 14 + read-write + + + 00 + Analog input channel (ANnXX) + #00 + + + 01 + ANEX1 + #01 + + + others + Setting prohibited. + true + + + + + EXOEN + Extended Analog Output Control + 15 + 15 + read-write + + + 0 + Output is disabled. + #0 + + + 1 + Output is enabled. + #1 + + + @@ -2089,6 +2170,25 @@ + + GBEXTRG + External trigger selection bit for group B. + 8 + 8 + read-write + + + 0 + An external trigger is not selected the trigger of group B. + #0 + + + 1 + An external trigger is selected the trigger of group B. + #1 + + + @@ -3227,6 +3327,82 @@ 0 0 + + P003SEL0 + A through amplifier is enable for PGA P003 + 12 + 12 + read-write + + + 0 + Not through the PGA in amplifier + #0 + + + 1 + I will through in the PGA amplifier. + #1 + + + + + P003SEL1 + The amplifier passing is enable for PGA P003 + 13 + 13 + read-write + + + 0 + By way of the amplifier in PGA. + #0 + + + 1 + Note 1 that by way of amplifier in PGA + #1 + + + + + P003ENAMP + Amplifier enable bit for PGA P003 + 14 + 14 + read-write + + + 0 + The amplifier in PGA is not used. + #0 + + + 1 + The amplifier in PGA is used. + #1 + + + + + P003GEN + PGA P003 gain setting and enable bit + 15 + 15 + read-write + + + 0 + The gain setting is invalidated (AIN is not input in PGA). + #0 + + + 1 + The gain setting is effectively done (AIN is input in PGA). + #1 + + + @@ -3583,70 +3759,159 @@ 0 3 - - - - ADPGADCR0 - A/D Programmable Gain Amplifier Differential Input Control Register - 0x1B0 - 16 - read-write - 0x0000 - 0xFFFF - - P003DG - P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b. + P003GAIN + PGA P003 gain setting bit.The gain magnification of (ADPGSDCR0.P003GEN=0b) when the shingle end is input and each PGA P003 is set. When the differential motion is input, (ADPGSDCR0.P003GEN=1b) sets the gain magnification when the differential motion is input by the combination with ADPGSDCR0.P003DG 1:0. 12 - 13 + 15 read-write - 00 - x 1.5 - #00 + 0000 + x 2.000 (ADPGADDCR0.P003DEN=0) + #0000 - 01 - x 2.333 - #01 + 0001 + x 2.500 (ADPGADDCR0.P003DEN=0) / x 1.500 (ADPGADDCR0.P003DEN=1) + #0001 - 10 - x 4.0 - #10 + 0010 + x 2.667 (ADPGADDCR0.P003DEN=0) + #0010 - 11 - x 5.667 - #11 + 0011 + x 2.857 (ADPGADDCR0.P003DEN=0) + #0011 - - - - P002DEN - P002 Differential Input Enable - 11 - 11 - read-write - - 0 - Differential input is disabled. - #0 + 0100 + x 3.077 (ADPGADDCR0.P003DEN=0) + #0100 - 1 - Differential input is enabled. - #1 + 0101 + x 3.333 (ADPGADDCR0.P003DEN=0) / x 2.333 (ADPGADDCR0.P003DEN=1) + #0101 + + + 0110 + x 3.636 (ADPGADDCR0.P003DEN=0) + #0110 + + + 0111 + x 4.000 (ADPGADDCR0.P003DEN=0) + #0111 + + + 1000 + x 4.444 (ADPGADDCR0.P003DEN=0) + #1000 + + + 1001 + x 5.000 (ADPGADDCR0.P003DEN=0) / x 4.00 (ADPGADDCR0.P003DEN=1) + #1001 + + + 1010 + x 5.714 (ADPGADDCR0.P003DEN=0) + #1010 + + + 1011 + x 6.667 (ADPGADDCR0.P003DEN=0) / x 5.667 (ADPGADDCR0.P003DEN=1) + #1011 + + + 1100 + x 8.000 (ADPGADDCR0.P003DEN=0) + #1100 + + + 1101 + x 10.000 (ADPGADDCR0.P003DEN=0) + #1101 + + + 1110 + x 13.333 (ADPGADDCR0.P003DEN=0) + #1110 + + + 1111 + x 1.000 (for offset measurement) (ADPGADDCR0.P003DEN=0) + #1111 + + + + ADPGADCR0 + A/D Programmable Gain Amplifier Differential Input Control Register + 0x1B0 + 16 + read-write + 0x0000 + 0xFFFF + - P002DG - P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. - 8 - 9 + P003DG + P003 Differential Input Gain SettingNOTE: When these bits are used, set {P003DEN, P003GEN} to 11b. + 12 + 13 + read-write + + + 00 + x 1.5 + #00 + + + 01 + x 2.333 + #01 + + + 10 + x 4.0 + #10 + + + 11 + x 5.667 + #11 + + + + + P002DEN + P002 Differential Input Enable + 11 + 11 + read-write + + + 0 + Differential input is disabled. + #0 + + + 1 + Differential input is enabled. + #1 + + + + + P002DG + P002 Differential Input Gain SettingNOTE: When these bits are used, set {P002DEN, P002GEN} to 11b. + 8 + 9 read-write @@ -3767,31936 +4032,9490 @@ - - - - - - R_ADC1 - 0x4005C200 - - - R_AGT0 - Asynchronous General Purpose Timer - 0x40084000 - - 0x00000000 - 0x006 - registers - - - 0x00000008 - 0x003 - registers - - - 0x0000000C - 0x004 - registers - - - - AGT - AGT Counter Register - 0x00 - 16 - read-write - 0xFFFF - 0xFFFF - - - AGT - 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. - 0 - 15 - read-write - - - - - AGTCMA - AGT Compare Match A Register - 0x02 - 16 - read-write - 0xFFFF - 0xFFFF - - - AGTCMA - AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH - 0 - 15 - read-write - - - - - AGTCMB - AGT Compare Match B Register - 0x04 - 16 - read-write - 0xFFFF - 0xFFFF - - AGTCMB - AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH - 0 + P003DEN + P003 Differential Input Enable + 15 15 read-write + + + 0 + Differential input is disabled. + #0 + + + 1 + Differential input is enabled. + #1 + + - AGTCR - AGT Control Register - 0x08 + ADREF + A/D status register + 0x002 8 read-write 0x00 0xFF - TCMBF - Compare match B flag - 7 - 7 + ADF + Scanning end flag bitThis bit is a status bit that becomes "1" while scanning. + 0 + 0 read-write zeroToClear modify 0 - No match + State of the idol or scanning. #0 1 - Match. + End of scanning #1 - TCMAF - Compare match A flag - 6 + Reserved + These bits are read as 000000. The write value should be 000000. + 1 6 read-write - zeroToClear - modify + + + ADSCACT + Scanning status bit + 7 + 7 + read-only 0 - No match + State of idol #0 1 - Match. + It is Scanning #1 + + + + ADEXREF + A/D enhancing status register + 0x003 + 8 + read-write + 0x00 + 0xFF + - TUNDF - Underflow flag - 5 - 5 + GBADF + Group B scanning end flag bit. + 0 + 0 read-write zeroToClear modify 0 - No match + State of the idol or scanning. #0 1 - Match. + End of scanning #1 - TEDGF - Active edge judgment flag - 4 - 4 + Reserved + These bits are read as 0000000. The write value should be 0000000. + 1 + 7 + read-write + + + + + ADAMPOFF + A/D RRAMP off state register + 0x062 + 8 + read-write + 0x0C + 0xFF + + + OPOFF + 0 + 7 + read-write + + + + + ADTSTPR + A/D Test Protecting Release Register + 0x063 + 8 + read-write + 0x00 + 0xFF + + + PRO + Test register protecting bit. + 0 + 0 read-write - zeroToClear - modify 0 - No active edge received + R/W is improper of ADEXTSTR, ADTSTRA/B/C/D, and ADSWTSTR0/1/2. #0 1 - Active edge received. + R/W is available of ADEXTSTR, ADTSTRA/B/C/D, and ADSWTSTR0/1/2. #1 - TSTOP - AGT count forced stop + B0WI + Bit 0 writing permission bit. + 1 + 1 + read-write + + + Reserved + These bits are read as 000000. The write value should be 000000. 2 + 7 + read-write + + + + + ADDDACER + A/D RRAMP Discharge Period Register + 0x064 + 16 + read-write + 0x1E03 + 0xFFFF + + + WRION + 0 + 4 + read-write + + + Reserved + These bits are read as 000. The write value should be 000. + 5 + 7 + read-write + + + WRIOFF + 8 + 12 + read-write + + + Reserved + These bits are read as 00. The write value should be 00. + 13 + 14 + read-write + + + ADHS + 15 + 15 + read-write + + + + + ADEXTSTR + A/D Enhancing Test Register + 0x068 + 16 + read-write + 0x0000 + 0xFFFF + + + SHTEST + Test mode bit for S&H circuit.Test mode bit of S&H circuit only for channel. + 0 2 - write-only + read-write + + + Reserved + This bit is read as 0. The write value should be 0. + 3 + 3 + read-write + + + SWTST + Test selection bit for pressure switch. + 4 + 5 + read-write - 0 - Writing is invalid - #0 + 00 + Test non-selection + #00 - 1 - The count is forcibly stopped. - #1 + 01 + Pressure test mode + #01 - - - - TCSTF - AGT count status flag - 1 - 1 - read-only - - 0 - Count stops - #0 + 10 + PMOS test mode + #10 - 1 - Count in progress. - #1 + 11 + Setting prohibited (PMOS test mode) + #11 - TSTART - AGT count start + Reserved + These bits are read as 00. The write value should be 00. + 6 + 7 + read-write + + + SHTRM + Current adjustment trim bit for S&H circuit.Trim bit for adjustment to hardening of process. + 8 + 9 + read-write + + + Reserved + This bit is read as 0. The write value should be 0. + 10 + 10 + read-write + + + ADTRM3 + Trim bit 3 for A/D hard macro.3bit Flash comparator power save bit for A/D hard macro to hardening of process. + 11 + 11 + read-write + + + ADTRM2 + Trim bit 2 for A/D hard macro.Bias adjustment trim bit for A/D hard macro to hardening of process. + 12 + 13 + read-write + + + ADTRM1 + Trim bit 1 for A/D hard macro.Timing adjustment trim bit for A/D hard macro to hardening of process. + 14 + 15 + read-write + + + + + ADTSTRA + A/D Test Register A + 0x06A + 16 + read-write + 0x0000 + 0xFFFF + + + ATBUSSEL + Analog test bus selection bit. 0 0 read-write 0 - Count stops + ATBUS use test non-selection #0 1 - Count starts. + ATBUS use test selection #1 - - - - AGTMR1 - AGT Mode Register 1 - 0x09 - 8 - read-write - 0x00 - 0xFF - - TCK - Count source + TSTSWREF + Pressure switch refreshing setting bit for S&H circuit amplifier test.Refreshing the pressure switch that opens for the DAC output voltage charge period when the amplifier of the S&H circuit is tested only for the channel is set. + 1 + 3 + read-write + + + Reserved + This bit is read as 0. The write value should be 0. 4 - 6 + 4 + read-write + + + OCSW + Internal reference voltage analog switch test control bit. + 5 + 5 read-write - 000 - PCLKB - #000 - - - 001 - PCLKB/8 - #001 - - - 011 - PCLKB/2 - #011 - - - 100 - Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register - #100 - - - 101 - Underflow event signal from AGT0*6 - #101 - - - 110 - Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. - #110 + 0 + Internal reference voltage analog switch H/W control + #0 - others - settings are prohibited. - true + 1 + Internal reference voltage analog switch ON + #1 - TEDGPL - Edge polarity - 3 - 3 + TSSW + Temperature sensor output analogue switch test control bit + 6 + 6 read-write 0 - Single-edge + Temperature sensor output analogue switch H/W control #0 1 - Both-edge. + Temperature sensor output analogue switch ON #1 - TMOD - Operating mode - 0 - 2 + Reserved + This bit is read as 0. The write value should be 0. + 7 + 7 + read-write + + + ADTEST_AD + Test bit for A/D analog module Bit for test of A/D analog module Details are described to the bit explanation. + 8 + 11 read-write - 000 - Timer mode - #000 + 0000 + Conversion mode usually + #0000 - 001 - Pulse output mode - #001 + 0001 + Self Test(VRB) + #0001 - 010 - Event counter mode - #010 + 0010 + Self Test(1/4) + #0010 - 011 - Pulse width measurement mode - #011 + 0011 + Self Test(2/4) + #0011 - 100 - Pulse period measurement mode. - #100 + 0100 + Self Test(3/4) + #0100 + + + 0101 + Self Test(VRT) + #0101 + + + 1001 + ADCOM input test + #1001 + + + 1100 + Resistance DAC output test + #1100 + + + 1101 + ADVAL input test + #1101 others - settings are prohibited + Setting prohibited true + + ADTEST_IO + Test bit for analog I/ODetails are described to the bit explanation. + 12 + 15 + read-write + - AGTMR2 - AGT Mode Register 2 - 0x0A - 8 + ADTSTRB + A/D Test Register B + 0x06C + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - LPM - Low Power Mode - 7 - 7 + ADVAL + Signal input bit bit14-0 for A/D analog module test.It corresponds to ADVAL 14:0 input of A/D analog module. + 0 + 14 read-write - - - 0 - Normal mode + + + Reserved + This bit is read as 0. The write value should be 0. + 15 + 15 + read-write + + + + + ADTSTRC + A/D Test Register C + 0x06E + 16 + read-write + 0x0000 + 0xFFFF + + + ADMD + Bit for A/D analog module test.ADMODE 6:0 input of A/D analog module. + 0 + 7 + read-write + + + Reserved + These bits are read as 0000. The write value should be 0000. + 8 + 11 + read-write + + + SYNCERR + Synchronous analog to digital conversion error bit. + 12 + 12 + read-write + + + 0 + A/D analog module and the A/D control part (soft macro part) are lights as for synchronization or 0. #0 1 - Low Power mode + Neither A/D analog module nor the A/D control part (soft macro part) have synchronized nor it is a light as for one. #1 - CKS - AGTLCLK/AGTSCLK count source clock frequency division ratio + Reserved + These bits are read as 000. The write value should be 000. + 13 + 15 + read-write + + + + + ADTSTRD + A/D Test Register D + 0x070 + 16 + read-write + 0x0000 + 0xFFFF + + + ADVAL16 + Signal input bit bit16 for A/D analog module test.It corresponds to ADVAL 16 input of A/D analog module. + 0 + 0 + read-write + + + Reserved + These bits are read as 000000000000000. The write value should be 000000000000000. + 1 + 15 + read-write + + + + + ADSWTSTR0 + A/D Channel Switch Test Control Register 0 + 0x072 + 16 + read-write + 0x0000 + 0xFFFF + + + CHSW00 + Channel switch test control bit. 0 + 0 + read-write + + + 0 + ch00 switch OFF + #0 + + + 1 + ch00 switch ON + #1 + + + + + CHSW01 + Channel switch test control bit. + 1 + 1 + read-write + + + 0 + ch01 switch OFF + #0 + + + 1 + ch01 switch ON + #1 + + + + + CHSW02 + Channel switch test control bit. + 2 2 read-write - 000 - 1/1 - #000 + 0 + ch02 switch OFF + #0 - 001 - 1/2 - #001 + 1 + ch02 switch ON + #1 + + + + CHSW03 + Channel switch test control bit. + 3 + 3 + read-write + - 010 - 1/4 - #010 + 0 + ch03 switch OFF + #0 - 011 - 1/8 - #011 + 1 + ch03 switch ON + #1 + + + + CHSW04 + Channel switch test control bit. + 4 + 4 + read-write + - 100 - 1/16 - #100 + 0 + ch04 switch OFF + #0 - 101 - 1/32 - #101 + 1 + ch04 switch ON + #1 + + + + CHSW05 + Channel switch test control bit. + 5 + 5 + read-write + - 110 - 1/64 - #110 + 0 + ch05 switch OFF + #0 - 111 - 1/128. - #111 + 1 + ch05 switch ON + #1 + + Reserved + These bits are read as 0000000000. The write value should be 0000000000. + 6 + 15 + read-write + - AGTIOC - AGT I/O Control Register - 0x0C - 8 + ADSWTSTR1 + A/D Channel Switch Test Control Register 1 + 0x074 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - TIOGT - Count control - 6 - 7 + CHSW16 + Channel switch test control bit. + 0 + 0 read-write - 00 - Event is always counted - #00 + 0 + ch16 switch OFF + #0 - 01 - Event is counted during polarity period specified for AGTEEn. - #01 + 1 + ch16 switch ON + #1 + + + + + CHSW17 + Channel switch test control bit. + 1 + 1 + read-write + + + 0 + ch17 switch OFF + #0 - others - settings are prohibited. - true + 1 + ch17 switch ON + #1 - TIPF - Input filter - 4 - 5 + CHSW18 + Channel switch test control bit. + 2 + 2 read-write - 00 - No filter - #00 + 0 + ch18 switch OFF + #0 - 01 - Filter sampled at PCLKB - #01 + 1 + ch18 switch ON + #1 + + + + CHSW19 + Channel switch test control bit. + 3 + 3 + read-write + - 10 - Filter sampled at PCLKB/8 - #10 + 0 + ch19 switch OFF + #0 - 11 - Filter sampled at PCLKB/32 - #11 + 1 + ch19 switch ON + #1 - TOE - AGTOn output enable - 2 - 2 + CHSW20 + Channel switch test control bit. + 4 + 4 read-write 0 - AGTOn output disabled + ch20 switch OFF #0 1 - AGTOn output enabled. + ch20 switch ON #1 - TEDGSEL - I/O polarity switchFunction varies depending on the operating mode. - 0 - 0 + CHSW21 + Channel switch test control bit. + 5 + 5 + read-write + + + 0 + ch21 switch OFF + #0 + + + 1 + ch21 switch ON + #1 + + + + + Reserved + These bits are read as 0000000000. The write value should be 0000000000. + 6 + 15 read-write - AGTISR - AGT Event Pin Select Register - 0x0D - 8 + ADSWTSTR2 + A/D Channel Switch Test Control Register 2 + 0x076 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - EEPS - AGTEE polarty selection + EX0SW + Test control of 0 enhancing input channel switches bit (ANEX0 switch) + 0 + 0 + read-write + + + 0 + Channel switch OFF + #0 + + + 1 + Channel switch ON + #1 + + + + + EX1SW + Test control of one enhancing input channel switch bit (ANEX1 switch). + 1 + 1 + read-write + + + 0 + Channel switch OFF + #0 + + + 1 + Channel switch ON + #1 + + + + + Reserved + These bits are read as 00. The write value should be 00. 2 - 2 + 3 + read-write + + + SHBYPS0 + S&H circuit by-pass switch control bit 0. + 4 + 4 read-write 0 - An event is counted during the low-level period + S&H by-pass switch OFF #0 1 - An event is counted during the high-level period + S&H by-pass switch ON #1 - - - - AGTCMSR - AGT Compare Match Function Select Register - 0x0E - 8 - read-write - 0x00 - 0xFF - - TOPOLB - AGTOB polarity select + SHBYPS1 + S&H circuit by-pass switch control bit 1. + 5 + 5 + read-write + + + 0 + S&H by-pass switch OFF + #0 + + + 1 + S&H by-pass switch ON + #1 + + + + + SHBYPS2 + S&H circuit by-pass switch control bit 2. 6 6 read-write 0 - AGTOB Output is started at low + S&H by-pass switch OFF #0 1 - AGTOB Output is started at high + S&H by-pass switch ON #1 - TOEB - AGTOB output enable - 5 - 5 + Reserved + This bit is read as 0. The write value should be 0. + 7 + 7 + read-write + + + GRP0SW + Test control of 0 group switches bit. + 8 + 8 read-write 0 - AGTOB output disabled (port) + Channel switch OFF #0 1 - AGTOB output enabled + Channel switch ON #1 - TCMEB - Compare match B register enable - 4 - 4 + GRP1SW + Test control of one group switch bit. + 9 + 9 read-write 0 - Disable compare match B register + Channel switch OFF #0 1 - Enable compare match B register + Channel switch ON #1 - TOPOLA - AGTOA polarity select - 2 - 2 + GRP2SW + Test control of two group switches bit + 10 + 10 read-write 0 - AGTOA Output is started at low + Channel switch OFF #0 1 - AGTOA Output is started at high + Channel switch ON #1 - TOEA - AGTOA output enable - 1 - 1 + GRP3SW + Test control of two group switches bit + 11 + 11 read-write 0 - AGTOA output disabled (port) + Channel switch OFF #0 1 - AGTOA output enabled + Channel switch ON #1 - TCMEA - Compare match A register enable - 0 - 0 + GRPEX1SW + Switch test control bit of enhancing analog ANEX1 + 12 + 12 read-write 0 - Disable compare match A register + Enhancing analog ANEX1 switch OFF #0 1 - Enable compare match A register + Enhancing analog ANEX1 switch ON #1 + + Reserved + These bits are read as 000. The write value should be 000. + 13 + 15 + read-write + - AGTIOSEL - AGT Pin Select Register - 0x0F + ADSWCR + A/D Pressure Switch Control Register + 0x07B 8 read-write 0x00 0xFF - TIES - AGTIO input enable + ADSWREF + These bits are read as 0. The write value should be 0.Refreshing the pressure switch in A/D analog module is set. + 0 + 2 + read-write + + + Reserved + This bit is read as 0. The write value should be 0. + 3 + 3 + read-write + + + SHSWREF + S&H Boost Switch Refresh Interval Setting 4 - 4 + 6 read-write - 0 - External event input is disabled during Software Standby mode - #0 + 000 + Non-Refresh + #000 - 1 - External event input is enabled during Software Standby mode. - #1 + 001 + 64 * ADCLK (Refresh Interval) / 1 * ADCLK (Refresh Period) + #001 + + + 010 + 32 * ADCLK (Refresh Interval) / 1 * ADCLK (Refresh Period) + #010 + + + 011 + 16 * ADCLK (Refresh Interval) / 1 * ADCLK (Refresh Period) + #011 + + + 100 + 128 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) + #100 + + + 101 + 64 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) + #101 + + + 110 + 32 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) + #110 + + + 111 + 16 * ADCLK (Refresh Interval) / 8 * ADCLK (Refresh Period) + #111 + + Reserved + This bit is read as 0. The write value should be 0. + 7 + 7 + read-write + - - - - R_AGT1 - 0x40084100 - - - R_BUS - Bus Interface - 0x40003000 - - 0x00000002 - 0x00A - registers - - - 0x00000012 - 0x00A - registers - - - 0x00000022 - 0x00A - registers - - - 0x00000032 - 0x00A - registers - - - 0x00000042 - 0x00A - registers - - - 0x00000052 - 0x00A - registers - - - 0x00000062 - 0x00A - registers - - - 0x00000072 - 0x00A - registers - - - 0x00000802 - 0x02 - registers - - - 0x0000080A - 0x02 - registers - - - 0x00000812 - 0x02 - registers - - - 0x0000081A - 0x02 - registers - - - 0x00000822 - 0x02 - registers - - - 0x0000082A - 0x02 - registers - - - 0x00000832 - 0x02 - registers - - - 0x0000083A - 0x02 - registers - - - 0x00000842 - 0x02 - registers - - - 0x0000084A - 0x02 - registers - - - 0x00000852 - 0x02 - registers - - - 0x0000085A - 0x02 - registers - - - 0x00000862 - 0x02 - registers - - - 0x0000086A - 0x02 - registers - - - 0x00000872 - 0x02 - registers - - - 0x0000087A - 0x02 - registers - - - 0x00000880 - 0x02 - registers - - - 0x00000C00 - 0x003 - registers - - - 0x00000C10 - 0x01 - registers - - - 0x00000C14 - 0x003 - registers - - - 0x00000C20 - 0x01 - registers - - - 0x00000C24 - 0x02 - registers - - - 0x00000C40 - 0x01 - registers - - - 0x00000C44 - 0x006 - registers - - - 0x00000C50 - 0x01 - registers - - - 0x00001000 - 0x02 - registers - - - 0x00001004 - 0x02 - registers - - - 0x00001008 - 0x02 - registers - - - 0x0000100C - 0x02 - registers - - - 0x00001010 - 0x02 - registers - - - 0x00001014 - 0x02 - registers - - - 0x00001100 - 0x02 - registers - - - 0x00001104 - 0x02 - registers - - - 0x00001108 - 0x02 - registers - - - 0x0000110C - 0x02 - registers - - - 0x00001110 - 0x02 - registers - - - 0x00001114 - 0x02 - registers - - - 0x00001118 - 0x02 - registers - - - 0x0000111C - 0x02 - registers - - - 0x00001120 - 0x02 - registers - - - 0x00001124 - 0x02 - registers - - - 0x00001128 - 0x02 - registers - - - 0x0000112C - 0x02 - registers - - - 0x00001130 - 0x02 - registers - - - 0x00001134 - 0x02 - registers - - - 0x00001138 - 0x02 - registers - - - 0x0000113C - 0x02 - registers - - - 0x00001800 - 0x005 - registers - - - 0x00001810 - 0x005 - registers - - - 0x00001820 - 0x005 - registers - - - 0x00001830 - 0x005 - registers - - - 0x00001840 - 0x005 - registers - - - 0x00001850 - 0x005 - registers - - - 0x00001860 - 0x005 - registers - - - 0x00001870 - 0x005 - registers - - - 0x00001880 - 0x005 - registers - - - 0x00001890 - 0x005 - registers - - - 0x000018A0 - 0x005 - registers - - - - 8 - 0x10 - CSa[%s] - CS Registers - 0x0000 - - MOD - Mode Register - 0x0002 - 16 - read-write - 0x0000 - 0xFFFF - - - PRMOD - Page Read Access Mode Select - 15 - 15 - read-write - - - 0 - Normal access compatible mode - #0 - - - 1 - External data read continuous assertion mode - #1 - - - - - PWENB - Page Write Access Enable - 9 - 9 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - PRENB - Page Read Access Enable - 8 - 8 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - EWENB - External Wait Enable - 3 - 3 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - WRMOD - Write Access Mode Select - 0 - 0 - read-write - - - 0 - Byte strobe mode - #0 - - - 1 - Single write strobe mode - #1 - - - - - - - WCR1 - Wait Control Register 1 - 0x0004 - 32 - read-write - 0x07070707 - 0xFFFFFFFF - - - CSRWAIT - Normal Read Cycle Wait Select - 24 - 28 - read-write - - - 0x00 - No wait is inserted. - 0x00 - - - others - Wait with a length of CSRWAIT clock cycle is inserted. - true - - - - - CSWWAIT - Normal Write Cycle Wait Select - 16 - 20 - read-write - - - 0x00 - No wait is inserted. - 0x00 - - - others - Wait with a length of CSWWAIT clock cycle is inserted. - true - - - - - CSPRWAIT - Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. - 8 - 10 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of CSPRWAIT clock cycle is inserted. - true - - - - - CSPWWAIT - Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. - 0 - 2 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of CSPWWAIT clock cycle is inserted. - true - - - - - - - WCR2 - Wait Control Register 2 - 0x0008 - 32 - read-write - 0x00000007 - 0xFFFFFFFF - - - CSON - CS Assert Wait Select - 28 - 30 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of CSON clock cycle is inserted. - true - - - - - WDON - Write Data Output Wait Select - 24 - 26 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of WDON clock cycle is inserted. - true - - - - - WRON - WR Assert Wait Select - 20 - 22 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of WRON clock cycle is inserted. - true - - - - - RDON - RD Assert Wait Select - 16 - 18 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of RDON clock cycle is inserted. - true - - - - - AWAIT - CS Assert Wait Select - 12 - 13 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of AWAIT clock cycle is inserted. - true - - - - - WDOFF - Write Data Output Extension Cycle Select - 8 - 10 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of WDOFF clock cycle is inserted. - true - - - - - CSWOFF - Write-Access CS Extension Cycle Select - 4 - 6 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of CSWOFF clock cycle is inserted. - true - - - - - CSROFF - Read-Access CS Extension Cycle Select - 0 - 2 - read-write - - - 0x0 - No wait is inserted. - 0x0 - - - others - Wait with a length of CSROFF clock cycle is inserted. - true - - - - - - - - 8 - 0x10 - CSb[%s] - CS Registers - 0x0800 - - CR - Control Register - 0x002 - 16 - read-write - 0x0000 - 0xFFFF - - - MPXEN - Address/Data Multiplexed I/O Interface Select - 12 - 12 - read-write - - - 0 - Separate bus interface is selected for area n - #0 - - - 1 - Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) - #1 - - - - - EMODE - Endian Mode - 8 - 8 - read-write - - - 0 - Little Endian - #0 - - - 1 - Big Endian - #1 - - - - - BSIZE - External Bus Width Select - 4 - 5 - read-write - - - 00 - A 16-bit bus space - #00 - - - 01 - Setting prohibited - #01 - - - 10 - An 8-bit bus space - #10 - - - 11 - Setting prohibited - #11 - - - - - EXENB - Operation Enable - 0 - 0 - read-write - - - 0 - Disable operation - #0 - - - 1 - Enable operation - #1 - - - - - - - REC - Recovery Cycle Register - 0x00A - 16 - read-write - 0x0000 - 0xFFFF - - - WRCV - Write Recovery - 8 - 11 - read-write - - - 0x0 - No recovery cycle is inserted. - 0x0 - - - others - WRCV recovery cycle is inserted. - true - - - - - RRCV - Read Recovery - 0 - 3 - read-write - - - 0x0 - No recovery cycle is inserted. - 0x0 - - - others - RRCV recovery cycle is inserted. - true - - - - - - - - SDRAM - SDRAM Registers - 0x0C00 - - SDCCR - SDC Control Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - - BSIZE - SDRAM Bus Width Select - 4 - 5 - read-write - - - 00 - A 16-bit bus space - #00 - - - 01 - Setting prohibited - #01 - - - 10 - An 8-bit bus space - #10 - - - 11 - Setting prohibited - #11 - - - - - EXENB - Operation Enable - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - - - SDCMOD - SDC Mode Register - 0x01 - 8 - read-write - 0x00 - 0xFF - - - EMODE - Endian Mode - 0 - 0 - read-write - - - 0 - Endian order of SDRAM address space is the same as the endian order of the operating mode - #0 - - - 1 - Endian order of SDRAM address space is not the endian order of the operating mode. - #1 - - - - - - - SDAMOD - SDRAM Access Mode Register - 0x02 - 8 - read-write - 0x00 - 0xFF - - - BE - Continuous Access Enable - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable. - #1 - - - - - - - SDSELF - SDRAM Self-Refresh Control Register - 0x10 - 8 - read-write - 0x00 - 0xFF - - - SFEN - SDRAM Self-Refresh Enable - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - - - SDRFCR - SDRAM Refresh Control Register - 0x14 - 16 - read-write - 0x0001 - 0xFFFF - - - REFW - Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles ) - 12 - 15 - read-write - - - RFC - Auto-Refresh Request Interval Setting - 0 - 11 - read-write - - - 0x0 - Setting prohibited - 0x0 - - - others - RFC+1 cycles inserted - true - - - - - - - SDRFEN - SDRAM Auto-Refresh Control Register - 0x16 - 8 - read-write - 0x00 - 0xFF - - - RFEN - Auto-Refresh Operation Enable - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - - - SDICR - SDRAM Initialization Sequence Control Register - 0x20 - 8 - read-write - 0x00 - 0xFF - - - INIRQ - Initialization Sequence Start - 0 - 0 - read-write - - - 0 - Invalid - #0 - - - 1 - Initialization sequence starts - #1 - - - - - - - SDIR - SDRAM Initialization Register - 0x24 - 16 - read-write - 0x0010 - 0xFFFF - - - PRC - Initialization Precharge Cycle Count ( PRF+3 cycles ) - 8 - 10 - read-write - - - ARFC - Initialization Auto-Refresh Count - 4 - 7 - read-write - - - 0x0 - Setting prohibited - 0x0 - - - others - ARFC+1 times - true - - - - - ARFI - Initialization Auto-Refresh Interval ( PRF+3 cycles ) - 0 - 3 - read-write - - - - - SDADR - SDRAM Address Register - 0x40 - 8 - read-write - 0x00 - 0xFF - - - MXC - Address Multiplex Select - 0 - 1 - read-write - - - 00 - 8-bit shift - #00 - - - 01 - 9-bit shift - #01 - - - 10 - 10-bit shift - #10 - - - 11 - 11-bit shift - #11 - - - - - - - SDTR - SDRAM Timing Register - 0x44 - 32 - read-write - 0x00000002 - 0xFFFFFFFF - - - RAS - Row Active Interval - 16 - 18 - read-write - - - 000 - 1 cycle - #000 - - - 001 - 2 cycles - #001 - - - 010 - 3 cycles - #010 - - - 011 - 4 cycles - #011 - - - 100 - 5 cycles - #100 - - - 101 - 6 cycles - #101 - - - 110 - 7 cycles - #110 - - - 111 - Setting prohibited - #111 - - - - - RCD - Row Column Latency ( RCD+1 cycles ) - 12 - 13 - read-write - - - RP - Row Precharge Interval ( RP+1 cycles ) - 9 - 11 - read-write - - - WR - Write Recovery Interval - 8 - 8 - read-write - - - 0 - 1 cycle - #0 - - - 1 - 2 cycles - #1 - - - - - CL - SDRAMC Column Latency - 0 - 2 - read-write - - - 001 - 1 cycle - #001 - - - 010 - 2 cycles - #010 - - - 011 - 3 cycles - #011 - - - others - Setting prohibited - true - - - - - - - SDMOD - SDRAM Mode Register - 0x48 - 16 - read-write - 0x0000 - 0xFFFF - - - MR - Mode Register SettingWriting to these bits: Mode register set command is issued. - 0 - 14 - read-write - - - - - SDSR - SDRAM Status Register - 0x50 - 8 - read-only - 0x00 - 0xFF - - - SRFST - Self-Refresh Transition/Recovery Status - 4 - 4 - read-only - - - 0 - Transition/recovery not in progress - #0 - - - 1 - Transition/recovery in progress - #1 - - - - - INIST - Initialization Status - 3 - 3 - read-only - - - 0 - Initialization sequence not in progress - #0 - - - 1 - Initialization sequence in progress - #1 - - - - - MRSST - Mode Register Setting Status - 0 - 0 - read-only - - - 0 - Mode register setting not in progress - #0 - - - 1 - Mode register setting in progress - #1 - - - - - - - - 11 - 0x10 - - - BUS1 - BUS1 - 0 - - - BUS2 - BUS2 - 1 - - - BUS3 - BUS3 - 2 - - - BUS4 - BUS4 - 3 - - - BUS5 - BUS5 - 4 - - - BUS6 - BUS6 - 5 - - - BUS7 - BUS7 - 6 - - - BUS8 - BUS8 - 7 - - - BUS9 - BUS9 - 8 - - - BUS10 - BUS10 - 9 - - - BUS11 - BUS11 - 10 - - - BUSERR[%s] - Bus Error Registers - 0x1800 - - ADD - Bus Error Address Register - 0x00 - 32 - read-only - 0x00000000 - 0x00000000 - - - BERAD - Bus Error AddressWhen a bus error occurs, It stores an error address. - 0 - 31 - read-only - - - - - STAT - Bus Error Status Register - 0x04 - 8 - read-only - 0x00 - 0xFE - - - ERRSTAT - Bus Error StatusWhen bus error assert, error flag occurs. - 7 - 7 - read-only - - - 0 - No bus error occurred - #0 - - - 1 - Bus error occurred - #1 - - - - - ACCSTAT - Error access statusThe status at the time of the error - 0 - 0 - read-only - - - 0 - Read access - #0 - - - 1 - Write Access - #1 - - - - - - - - 6 - 0x4 - - - M4I - M4I - 0 - - - M4D - M4D - 1 - - - SYS - SYS - 2 - - - DMA - DMA - 3 - - - EDM - EDM - 4 - - - GPX - GPX - 5 - - - BUSM[%s] - Master Bus Control Register Array - 0x1000 - - CNT - Master Bus Control Register - 0x0 - 16 - read-write - 0x0000 - 0xFFFF - - - IERES - Ignore Error Responses - 15 - 15 - read-write - - - 0 - Bus error will be reported. - #0 - - - 1 - Bus error will not be reported. - #1 - - - - - - - - 16 - 0x4 - - - FLI - FLI - 0 - - - RAMH - RAMH - 1 - - - MBIU - MBIU - 2 - - - RAM0 - RAM0 - 3 - - - RAM1 - RAM1 - 4 - - - P0B - P0B - 5 - - - P2B - P2B - 6 - - - P3B - P3B - 7 - - - P4B - P4B - 8 - - - PxB - PxB - 9 - - - P6B - P6B - 10 - - - P7B - P7B - 11 - - - FBU - FBU - 12 - - - EXT - EXT - 13 - - - EXT2 - EXT2 - 14 - - - GPX - GPX - 15 - - - BUSS[%s] - Slave Bus Control Register Array - 0x1100 - - CNT - Slave Bus Control Register - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - - ARBMET - Arbitration MethodSpecify the priority between groups - 4 - 5 - read-write - - - 00 - fixed priority - #00 - - - 01 - round-robin - #01 - - - others - Setting prohibited - true - - - - - - - - CSRECEN - CS Recovery Cycle Insertion Enable Register - 0x0880 - 16 - read-write - 0x3E3E - 0xFFFF - - - 8 - 1 - RCVENM%s - Multiplexed Bus Recovery Cycle Insertion Enable - 8 - 8 - read-write - - - 0 - Recovery cycle insertion is disabled. - #0 - - - 1 - Recovery cycle insertion is enabled. - #1 - - - - - 8 - 1 - RCVEN%s - Separate Bus Recovery Cycle Insertion Enable - 0 - 0 - read-write - - - 0 - Recovery cycle insertion is disabled. - #0 - - - 1 - Recovery cycle insertion is enabled. - #1 - - - - - - - - - R_CAC - Clock Frequency Accuracy Measurement Circuit - 0x40044600 - - 0x00000000 - 0x005 - registers - - - 0x00000006 - 0x006 - registers - - - - CACR0 - CAC Control Register 0 - 0x00 - 8 - read-write - 0x00 - 0xFF - - - CFME - Clock Frequency Measurement Enable. - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - - - CACR1 - CAC Control Register 1 - 0x01 - 8 - read-write - 0x00 - 0xFF - - - EDGES - Valid Edge Select - 6 - 7 - read-write - - - 00 - Rising edge - #00 - - - 01 - Falling edge - #01 - - - 10 - Both rising and falling edges - #10 - - - 11 - Setting prohibited - #11 - - - - - TCSS - Measurement Target Clock Frequency Division Ratio Select - 4 - 5 - read-write - - - 00 - No division - #00 - - - 01 - x 1/4 clock - #01 - - - 10 - x 1/8 clock - #10 - - - 11 - x 1/32 clock - #11 - - - - - FMCS - Measurement Target Clock Select - 1 - 3 - read-write - - - 000 - Main clock - #000 - - - 001 - Sub-clock - #001 - - - 010 - HOCO clock - #010 - - - 011 - MOCO clock - #011 - - - 100 - LOCO clock - #100 - - - 101 - Peripheral module clock(PCLKB) - #101 - - - 110 - IWDTCLK clock - #110 - - - 111 - Setting prohibited - #111 - - - - - CACREFE - CACREF Pin Input Enable - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - - - CACR2 - CAC Control Register 2 - 0x02 - 8 - read-write - 0x00 - 0xFF - - - DFS - Digital Filter Selection - 6 - 7 - read-write - - - 00 - Digital filtering is disabled. - #00 - - - 01 - The sampling clock for the digital filter is the frequency measuring clock. - #01 - - - 10 - The sampling clock for the digital filter is the frequency measuring clock divided by 4. - #10 - - - 11 - The sampling clock for the digital filter is the frequency measuring clock divided by 16. - #11 - - - - - RCDS - Measurement Reference Clock Frequency Division Ratio Select - 4 - 5 - read-write - - - 00 - 1/32 clock - #00 - - - 01 - 1/128 clock - #01 - - - 10 - 1/1024 clock - #10 - - - 11 - 1/8192 clock - #11 - - - - - RSCS - Measurement Reference Clock Select - 1 - 3 - read-write - - - 000 - Main clock - #000 - - - 001 - Sub-clock - #001 - - - 010 - HOCO clock - #010 - - - 011 - MOCO clock - #011 - - - 100 - LOCO clock - #100 - - - 101 - Peripheral module clock(PCLKB) - #101 - - - 110 - IWDTCLK clock - #110 - - - 111 - Setting prohibited - #111 - - - - - RPS - Reference Signal Select - 0 - 0 - read-write - - - 0 - CACREF pin input - #0 - - - 1 - Internal clock (internally generated signal) - #1 - - - - - - - CAICR - CAC Interrupt Control Register - 0x03 - 8 - read-write - 0x00 - 0xFF - - - OVFFCL - OVFF Clear - 6 - 6 - write-only - - - 0 - No effect on operations - #0 - - - 1 - Clears the OVFF flag - #1 - - - - - MENDFCL - MENDF Clear - 5 - 5 - write-only - - - 0 - No effect on operations - #0 - - - 1 - Clears the MENDF flag - #1 - - - - - FERRFCL - FERRF Clear - 4 - 4 - write-only - - - 0 - No effect on operations - #0 - - - 1 - Clears the FERRF flag - #1 - - - - - OVFIE - Overflow Interrupt Request Enable - 2 - 2 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - MENDIE - Measurement End Interrupt Request Enable - 1 - 1 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - FERRIE - Frequency Error Interrupt Request Enable - 0 - 0 - read-write - - - 0 - Disable - #0 - - - 1 - Enable - #1 - - - - - - - CASTR - CAC Status Register - 0x04 - 8 - read-only - 0x00 - 0xFF - - - OVFF - Counter Overflow Flag - 2 - 2 - read-only - - - 0 - The counter has not overflowed. - #0 - - - 1 - The counter has overflowed. - #1 - - - - - MENDF - Measurement End Flag - 1 - 1 - read-only - - - 0 - Measurement is in progress. - #0 - - - 1 - Measurement has ended. - #1 - - - - - FERRF - Frequency Error Flag - 0 - 0 - read-only - - - 0 - The clock frequency is within the range corresponding to the settings. - #0 - - - 1 - The clock frequency has deviated beyond the range corresponding to the settings (frequency error). - #1 - - - - - - - CAULVR - CAC Upper-Limit Value Setting Register - 0x06 - 16 - read-write - 0x0000 - 0xFFFF - - - CAULVR - CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency. - 0 - 15 - read-write - - - - - CALLVR - CAC Lower-Limit Value Setting Register - 0x08 - 16 - read-write - 0x0000 - 0xFFFF - - - CALLVR - CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency. - 0 - 15 - read-write - - - - - CACNTBR - CAC Counter Buffer Register - 0x0A - 16 - read-only - 0x0000 - 0xFFFF - - - CACNTBR - CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input - 0 - 15 - read-only - - - - - - - R_CAN0 - Controller Area Network (CAN) Module - 0x40050000 - - 0x00000200 - 0x230 - registers - - - 0x00000820 - 0x039 - registers - - - - 32 - 0x10 - MB[%s] - Mailbox - 0x200 - - ID - Mailbox ID Register - 0x0 - 32 - read-write - 0x00000000 - 0x00000000 - - - IDE - ID Extension - 31 - 31 - read-write - - - 0 - Standard ID - #0 - - - 1 - Extended ID - #1 - - - - - RTR - Remote Transmission Request - 30 - 30 - read-write - - - 0 - Data frame - #0 - - - 1 - Remote frame - #1 - - - - - SID - Standard ID - 18 - 28 - read-write - - - EID - Extended ID - 0 - 17 - read-write - - - - - DL - Mailbox DLC Register - 0x4 - 16 - read-write - 0x0000 - 0x0000 - - - DLC - Data Length Code - 0 - 3 - read-write - - - 0000 - Data length = 0 byte - #0000 - - - 0001 - Data length = 1 byte - #0001 - - - 0010 - Data length = 2 bytes - #0010 - - - 0011 - Data length = 3 bytes - #0011 - - - 0100 - Data length = 4 bytes - #0100 - - - 0101 - Data length = 5 bytes - #0101 - - - 0110 - Data length = 6 bytes - #0110 - - - 0111 - Data length = 7 bytes - #0111 - - - others - Data length = 8 bytes - true - - - - - - - 8 - 0x01 - D[%s] - Mailbox Data Register - 0x6 - 8 - read-write - 0x00 - 0x00 - - - DATA - DATA0 to DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB-first, and transmission or reception starts from bit 7 - 0 - 7 - read-write - - - - - TS - Mailbox Timestamp Register - 0xE - 16 - read-write - 0x0000 - 0x0000 - - - TSH - Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. - 8 - 15 - read-write - - - TSL - Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. - 0 - 7 - read-write - - - - - - 8 - 0x4 - MKR[%s] - Mask Register - 0x400 - 32 - read-write - 0x00000000 - 0x00000000 - - - SID - Standard ID - 18 - 28 - read-write - - - EID - Extended ID - 0 - 17 - read-write - - - - - 2 - 0x4 - FIDCR[%s] - FIFO Received ID Compare Registers - 0x420 - 32 - read-write - 0x00000000 - 0x00000000 - - - IDE - ID Extension - 31 - 31 - read-write - - - 0 - Standard ID - #0 - - - 1 - Extended ID - #1 - - - - - RTR - Remote Transmission Request - 30 - 30 - read-write - - - 0 - Data frame - #0 - - - 1 - Remote frame - #1 - - - - - SID - Standard ID - 18 - 28 - read-write - - - EID - Extended ID - 0 - 17 - read-write - - - - - MKIVLR - Mask Invalid Register - 0x428 - 32 - read-write - 0x00000000 - 0x00000000 - - - MB31 - mailbox 31 Mask Invalid - 31 - 31 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB30 - mailbox 30 Mask Invalid - 30 - 30 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB29 - mailbox 29 Mask Invalid - 29 - 29 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB28 - mailbox 28 Mask Invalid - 28 - 28 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB27 - mailbox 27 Mask Invalid - 27 - 27 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB26 - mailbox 26 Mask Invalid - 26 - 26 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB25 - mailbox 25 Mask Invalid - 25 - 25 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB24 - mailbox 24 Mask Invalid - 24 - 24 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB23 - mailbox 23 Mask Invalid - 23 - 23 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB22 - mailbox 22 Mask Invalid - 22 - 22 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB21 - mailbox 21 Mask Invalid - 21 - 21 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB20 - mailbox 20 Mask Invalid - 20 - 20 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB19 - mailbox 19 Mask Invalid - 19 - 19 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB18 - mailbox 18 Mask Invalid - 18 - 18 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB17 - mailbox 17 Mask Invalid - 17 - 17 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB16 - mailbox 16 Mask Invalid - 16 - 16 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB15 - mailbox 15 Mask Invalid - 15 - 15 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB14 - mailbox 14 Mask Invalid - 14 - 14 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB13 - mailbox 13 Mask Invalid - 13 - 13 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB12 - mailbox 12 Mask Invalid - 12 - 12 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB11 - mailbox 11 Mask Invalid - 11 - 11 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB10 - mailbox 10 Mask Invalid - 10 - 10 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB9 - mailbox 9 Mask Invalid - 9 - 9 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB8 - mailbox 8 Mask Invalid - 8 - 8 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB7 - mailbox 7 Mask Invalid - 7 - 7 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB6 - mailbox 6 Mask Invalid - 6 - 6 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB5 - mailbox 5 Mask Invalid - 5 - 5 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB4 - mailbox 4 Mask Invalid - 4 - 4 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB3 - mailbox 3 Mask Invalid - 3 - 3 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB2 - mailbox 2 Mask Invalid - 2 - 2 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB1 - mailbox 1 Mask Invalid - 1 - 1 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - MB0 - mailbox 0 Mask Invalid - 0 - 0 - read-write - - - 0 - Mask valid - #0 - - - 1 - Mask invalid - #1 - - - - - - - MIER - Mailbox Interrupt Enable Register - 0x42C - 32 - read-write - 0x00000000 - 0x00000000 - - - MB31 - mailbox 31 Interrupt Enable - 31 - 31 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB30 - mailbox 30 Interrupt Enable - 30 - 30 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB29 - mailbox 29 Interrupt Enable - 29 - 29 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB28 - mailbox 28 Interrupt Enable - 28 - 28 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB27 - mailbox 27 Interrupt Enable - 27 - 27 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB26 - mailbox 26 Interrupt Enable - 26 - 26 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB25 - mailbox 25 Interrupt Enable - 25 - 25 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB24 - mailbox 24 Interrupt Enable - 24 - 24 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB23 - mailbox 23 Interrupt Enable - 23 - 23 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB22 - mailbox 22 Interrupt Enable - 22 - 22 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB21 - mailbox 21 Interrupt Enable - 21 - 21 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB20 - mailbox 20 Interrupt Enable - 20 - 20 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB19 - mailbox 19 Interrupt Enable - 19 - 19 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB18 - mailbox 18 Interrupt Enable - 18 - 18 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB17 - mailbox 17 Interrupt Enable - 17 - 17 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB16 - mailbox 16 Interrupt Enable - 16 - 16 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB15 - mailbox 15 Interrupt Enable - 15 - 15 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB14 - mailbox 14 Interrupt Enable - 14 - 14 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB13 - mailbox 13 Interrupt Enable - 13 - 13 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB12 - mailbox 12 Interrupt Enable - 12 - 12 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB11 - mailbox 11 Interrupt Enable - 11 - 11 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB10 - mailbox 10 Interrupt Enable - 10 - 10 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB9 - mailbox 9 Interrupt Enable - 9 - 9 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB8 - mailbox 8 Interrupt Enable - 8 - 8 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB7 - mailbox 7 Interrupt Enable - 7 - 7 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB6 - mailbox 6 Interrupt Enable - 6 - 6 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB5 - mailbox 5 Interrupt Enable - 5 - 5 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB4 - mailbox 4 Interrupt Enable - 4 - 4 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB3 - mailbox 3 Interrupt Enable - 3 - 3 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB2 - mailbox 2 Interrupt Enable - 2 - 2 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB1 - mailbox 1 Interrupt Enable - 1 - 1 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB0 - mailbox 0 Interrupt Enable - 0 - 0 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - - - MIER_FIFO - Mailbox Interrupt Enable Register for FIFO Mailbox Mode - MIER - 0x42C - 32 - read-write - 0x00000000 - 0x00000000 - - - MB29 - Receive FIFO Interrupt Generation Timing Control - 29 - 29 - read-write - - - 0 - Every time reception is completed - #0 - - - 1 - When the receive FIFO becomes buffer warning by completion of reception - #1 - - - - - MB28 - Receive FIFO Interrupt Enable - 28 - 28 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB25 - Transmit FIFO Interrupt Generation Timing Control - 25 - 25 - read-write - - - 0 - Every time transmission is completed - #0 - - - 1 - When the transmit FIFO becomes empty due to completion of transmission - #1 - - - - - MB24 - Transmit FIFO Interrupt Enable - 24 - 24 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB23 - mailbox 23 Interrupt Enable - 23 - 23 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB22 - mailbox 22 Interrupt Enable - 22 - 22 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB21 - mailbox 21 Interrupt Enable - 21 - 21 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB20 - mailbox 20 Interrupt Enable - 20 - 20 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB19 - mailbox 19 Interrupt Enable - 19 - 19 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB18 - mailbox 18 Interrupt Enable - 18 - 18 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB17 - mailbox 17 Interrupt Enable - 17 - 17 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB16 - mailbox 16 Interrupt Enable - 16 - 16 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB15 - mailbox 15 Interrupt Enable - 15 - 15 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB14 - mailbox 14 Interrupt Enable - 14 - 14 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB13 - mailbox 13 Interrupt Enable - 13 - 13 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB12 - mailbox 12 Interrupt Enable - 12 - 12 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB11 - mailbox 11 Interrupt Enable - 11 - 11 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB10 - mailbox 10 Interrupt Enable - 10 - 10 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB9 - mailbox 9 Interrupt Enable - 9 - 9 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB8 - mailbox 8 Interrupt Enable - 8 - 8 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB7 - mailbox 7 Interrupt Enable - 7 - 7 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB6 - mailbox 6 Interrupt Enable - 6 - 6 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB5 - mailbox 5 Interrupt Enable - 5 - 5 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB4 - mailbox 4 Interrupt Enable - 4 - 4 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB3 - mailbox 3 Interrupt Enable - 3 - 3 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB2 - mailbox 2 Interrupt Enable - 2 - 2 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB1 - mailbox 1 Interrupt Enable - 1 - 1 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - MB0 - mailbox 0 Interrupt Enable - 0 - 0 - read-write - - - 0 - Interrupt disabled - #0 - - - 1 - Interrupt enabled - #1 - - - - - - - 32 - 0x1 - MCTL_TX[%s] - Message Control Register for Transmit - 0x820 - 8 - read-write - 0x00 - 0xFF - - - TRMREQ - Transmit Mailbox Request - 7 - 7 - read-write - - - 0 - Not configured for transmission - #0 - - - 1 - Configured for transmission - #1 - - - - - RECREQ - Receive Mailbox Request - 6 - 6 - read-write - - - 0 - Not configured for reception - #0 - - - 1 - Configured for reception - #1 - - - - - ONESHOT - One-Shot Enable - 4 - 4 - read-write - - - 0 - One-shot reception or one-shot transmission disabled - #0 - - - 1 - One-shot reception or one-shot transmission enabled - #1 - - - - - TRMABT - Transmission Abort Complete Flag (Transmit mailbox setting enabled) - 2 - 2 - read-write - - - 0 - Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested - #0 - - - 1 - Transmission abort is completed - #1 - - - - - TRMACTIVE - Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) - 1 - 1 - read-only - - - 0 - Transmission is pending or transmission is not requested - #0 - - - 1 - From acceptance of transmission request to completion of transmission, or error/arbitration-lost - #1 - - - - - SENTDATA - Transmission Complete Flag - 0 - 0 - read-write - - - 0 - Transmission is not completed - #0 - - - 1 - Transmission is completed - #1 - - - - - - - 32 - 0x1 - MCTL_RX[%s] - Message Control Register for Receive - MCTL_TX[%s] - 0x820 - 8 - read-write - 0x00 - 0xFF - - - TRMREQ - Transmit Mailbox Request - 7 - 7 - read-write - - - 0 - Not configured for transmission - #0 - - - 1 - Configured for transmission - #1 - - - - - RECREQ - Receive Mailbox Request - 6 - 6 - read-write - - - 0 - Not configured for reception - #0 - - - 1 - Configured for reception - #1 - - - - - ONESHOT - One-Shot Enable - 4 - 4 - read-write - - - 0 - One-shot reception or one-shot transmission disabled - #0 - - - 1 - One-shot reception or one-shot transmission enabled - #1 - - - - - MSGLOST - Message Lost Flag(Receive mailbox setting enabled) - 2 - 2 - read-write - - - 0 - Message is not overwritten or overrun - #0 - - - 1 - Message is overwritten or overrun - #1 - - - - - INVALDATA - Reception-in-Progress Status Flag (Receive mailbox setting enabled) - 1 - 1 - read-only - - - 0 - Message valid - #0 - - - 1 - Message being updated - #1 - - - - - NEWDATA - Reception Complete Flag - 0 - 0 - read-write - - - 0 - No data has been received or 0 is written to the NEWDATA bit - #0 - - - 1 - A new message is being stored or has been stored to the mailbox - #1 - - - - - - - CTLR - Control Register - 0x840 - 16 - read-write - 0x0500 - 0xFFFF - - - RBOC - Forcible Return From Bus-Off - 13 - 13 - read-write - - - 0 - Nothing occurred - #0 - - - 1 - Forcible return from bus-off - #1 - - - - - BOM - Bus-Off Recovery Mode by a program request - 11 - 12 - read-write - - - 00 - Normal mode (ISO11898-1 compliant) - #00 - - - 01 - Entry to CAN halt mode automatically at bus-off entry - #01 - - - 10 - Entry to CAN halt mode automatically at bus-off end - #10 - - - 11 - Entry to CAN halt mode (during bus-off recovery period) - #11 - - - - - SLPM - CAN Sleep Mode - 10 - 10 - read-write - - - 0 - Other than CAN sleep mode - #0 - - - 1 - CAN sleep mode - #1 - - - - - CANM - CAN Operating Mode Select - 8 - 9 - read-write - - - 00 - CAN operation mode - #00 - - - 01 - CAN reset mode - #01 - - - 10 - CAN halt mode - #10 - - - 11 - CAN reset mode (forcible transition) - #11 - - - - - TSPS - Time Stamp Prescaler Select - 6 - 7 - read-write - - - 00 - Every bit time - #00 - - - 01 - Every 2-bit time - #01 - - - 10 - Every 4-bit time - #10 - - - 11 - Every 8-bit time - #11 - - - - - TSRC - Time Stamp Counter Reset Command - 5 - 5 - read-write - - - 0 - Nothing occurred - #0 - - - 1 - Reset - #1 - - - - - TPM - Transmission Priority Mode Select - 4 - 4 - read-write - - - 0 - ID priority transmit mode - #0 - - - 1 - Mailbox number priority transmit mode - #1 - - - - - MLM - Message Lost Mode Select - 3 - 3 - read-write - - - 0 - Overwrite mode - #0 - - - 1 - Overrun mode - #1 - - - - - IDFM - ID Format Mode Select - 1 - 2 - read-write - - - 00 - Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids. - #00 - - - 01 - Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. - #01 - - - 10 - Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO. - #10 - - - 11 - Do not use this combination - #11 - - - - - MBM - CAN Mailbox Mode Select - 0 - 0 - read-write - - - 0 - Normal mailbox mode - #0 - - - 1 - FIFO mailbox mode - #1 - - - - - - - STR - Status Register - 0x842 - 16 - read-only - 0x0500 - 0xFFFF - - - RECST - Receive Status Flag (receiver) - 14 - 14 - read-only - - - 0 - Bus idle or transmission in progress - #0 - - - 1 - Reception in progress - #1 - - - - - TRMST - Transmit Status Flag (transmitter) - 13 - 13 - read-only - - - 0 - Bus idle or reception in progress - #0 - - - 1 - Transmission in progress or in bus-off state - #1 - - - - - BOST - Bus-Off Status Flag - 12 - 12 - read-only - - - 0 - Not in bus-off state - #0 - - - 1 - In bus-off state - #1 - - - - - EPST - Error-Passive Status Flag - 11 - 11 - read-only - - - 0 - Not in error-passive state - #0 - - - 1 - In error-passive state - #1 - - - - - SLPST - CAN Sleep Status Flag - 10 - 10 - read-only - - - 0 - Not in CAN sleep mode - #0 - - - 1 - In CAN sleep mode - #1 - - - - - HLTST - CAN Halt Status Flag - 9 - 9 - read-only - - - 0 - Not in CAN halt mode - #0 - - - 1 - In CAN halt mode - #1 - - - - - RSTST - CAN Reset Status Flag - 8 - 8 - read-only - - - 0 - Not in CAN reset mode - #0 - - - 1 - In CAN reset mode - #1 - - - - - EST - Error Status Flag - 7 - 7 - read-only - - - 0 - No error occurred - #0 - - - 1 - Error occurred - #1 - - - - - TABST - Transmission Abort Status Flag - 6 - 6 - read-only - - - 0 - No mailbox with TRMABT bit = 1 - #0 - - - 1 - Mailbox(es) with TRMABT bit = 1 - #1 - - - - - FMLST - FIFO Mailbox Message Lost Status Flag - 5 - 5 - read-only - - - 0 - RFMLF bit = 0 - #0 - - - 1 - RFMLF bit = 1 - #1 - - - - - NMLST - Normal Mailbox Message Lost Status Flag - 4 - 4 - read-only - - - 0 - No mailbox with MSGLOST bit = 1 - #0 - - - 1 - Mailbox(es) with MSGLOST bit = 1 - #1 - - - - - TFST - Transmit FIFO Status Flag - 3 - 3 - read-only - - - 0 - Transmit FIFO is full - #0 - - - 1 - Transmit FIFO is not full - #1 - - - - - RFST - Receive FIFO Status Flag - 2 - 2 - read-only - - - 0 - No message in receive FIFO (empty) - #0 - - - 1 - Message in receive FIFO - #1 - - - - - SDST - SENTDATA Status Flag - 1 - 1 - read-only - - - 0 - No mailbox with SENTDATA bit = 1 - #0 - - - 1 - Mailbox(es) with SENTDATA bit = 1 - #1 - - - - - NDST - NEWDATA Status Flag - 0 - 0 - read-only - - - 0 - No mailbox with NEWDATA bit = 1 - #0 - - - 1 - Mailbox(es) with NEWDATA bit = 1 - #1 - - - - - - - BCR - Bit Configuration Register - 0x844 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TSEG1 - Time Segment 1 Control - 28 - 31 - read-write - - - 0000 - Setting prohibited - #0000 - - - 0001 - Setting prohibited - #0001 - - - 0010 - Setting prohibited - #0010 - - - 0011 - 4 Tq - #0011 - - - 0100 - 5 Tq - #0100 - - - 0101 - 6 Tq - #0101 - - - 0110 - 7 Tq - #0110 - - - 0111 - 8 Tq - #0111 - - - 1000 - 9 Tq - #1000 - - - 1001 - 10 Tq - #1001 - - - 1010 - 11 Tq - #1010 - - - 1011 - 12 Tq - #1011 - - - 1100 - 13 Tq - #1100 - - - 1101 - 14 Tq - #1101 - - - 1110 - 15 Tq - #1110 - - - 1111 - 16 Tq - #1111 - - - - - BRP - Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). - 16 - 25 - read-write - - - SJW - Resynchronization Jump Width Control - 12 - 13 - read-write - - - 00 - 1 Tq - #00 - - - 01 - 2 Tq - #01 - - - 10 - 3 Tq - #10 - - - 11 - 4 Tq - #11 - - - - - TSEG2 - Time Segment 2 Control - 8 - 10 - read-write - - - 000 - Setting prohibited - #000 - - - 001 - 2 Tq - #001 - - - 010 - 3 Tq - #010 - - - 011 - 4 Tq - #011 - - - 100 - 5 Tq - #100 - - - 101 - 6 Tq - #101 - - - 110 - 7 Tq - #110 - - - 111 - 8 Tq - #111 - - - - - CCLKS - CAN Clock Source Selection - 0 - 0 - read-write - - - 0 - PCLK (generated by the PLL clock) - #0 - - - 1 - CANMCLK (generated by the main clock) - #1 - - - - - - - RFCR - Receive FIFO Control Register - 0x848 - 8 - read-write - 0x80 - 0xFF - - - RFEST - Receive FIFO Empty Status Flag - 7 - 7 - read-only - - - 0 - Unread message in receive FIFO - #0 - - - 1 - No unread message in receive FIFO - #1 - - - - - RFWST - Receive FIFO Buffer Warning Status Flag - 6 - 6 - read-only - - - 0 - Receive FIFO is not buffer warning - #0 - - - 1 - Receive FIFO is buffer warning (3 unread messages) - #1 - - - - - RFFST - Receive FIFO Full Status Flag - 5 - 5 - read-only - - - 0 - Receive FIFO is not full - #0 - - - 1 - Receive FIFO is full (4 unread messages) - #1 - - - - - RFMLF - Receive FIFO Message Lost Flag - 4 - 4 - read-write - - - 0 - No receive FIFO message lost has occurred - #0 - - - 1 - Receive FIFO message lost has occurred - #1 - - - - - RFUST - Receive FIFO Unread Message Number Status - 1 - 3 - read-only - - - 000 - No unread message - #000 - - - 001 - 1 unread message - #001 - - - 010 - 2 unread messages - #010 - - - 011 - 3 unread messages - #011 - - - 100 - 4 unread messages - #100 - - - others - Setting prohibited - true - - - - - RFE - Receive FIFO Enable - 0 - 0 - read-write - - - 0 - Receive FIFO disabled - #0 - - - 1 - Receive FIFO enabled - #1 - - - - - - - RFPCR - Receive FIFO Pointer Control Register - 0x849 - 8 - write-only - 0x00 - 0x00 - - - RFPCR - The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR. - 0 - 7 - write-only - - - - - TFCR - Transmit FIFO Control Register - 0x84A - 8 - read-write - 0x80 - 0xFF - - - TFEST - Transmit FIFO Empty Status - 7 - 7 - read-only - - - 0 - Unsent message in transmit FIFO - #0 - - - 1 - No unsent message in transmit FIFO - #1 - - - - - TFFST - Transmit FIFO Full Status - 6 - 6 - read-only - - - 0 - Transmit FIFO is not full - #0 - - - 1 - Transmit FIFO is full (4 unsent messages) - #1 - - - - - TFUST - Transmit FIFO Unsent Message Number Status - 1 - 3 - read-only - - - 000 - No unsent message - #000 - - - 001 - 1 unsent message - #001 - - - 010 - 2 unsent messages - #010 - - - 011 - 3 unsent messages - #011 - - - 100 - 4 unsent messages - #100 - - - others - Setting prohibited - true - - - - - TFE - Transmit FIFO Enable - 0 - 0 - read-write - - - 0 - Transmit FIFO disabled - #0 - - - 1 - Transmit FIFO enabled - #1 - - - - - - - TFPCR - Transmit FIFO Pointer Control Register - 0x84B - 8 - write-only - 0x00 - 0x00 - - - TFPCR - The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR. - 0 - 7 - write-only - - - - - EIER - Error Interrupt Enable Register - 0x84C - 8 - read-write - 0x00 - 0xFF - - - BLIE - Bus Lock Interrupt Enable - 7 - 7 - read-write - - - 0 - Bus lock interrupt disabled - #0 - - - 1 - Bus lock interrupt enabled - #1 - - - - - OLIE - Overload Frame Transmit Interrupt Enable - 6 - 6 - read-write - - - 0 - Overload frame transmit interrupt disabled - #0 - - - 1 - Overload frame transmit interrupt enabled - #1 - - - - - ORIE - Overrun Interrupt Enable - 5 - 5 - read-write - - - 0 - Receive overrun interrupt disabled - #0 - - - 1 - Receive overrun interrupt enabled - #1 - - - - - BORIE - Bus-Off Recovery Interrupt Enable - 4 - 4 - read-write - - - 0 - Bus-off recovery interrupt disabled - #0 - - - 1 - Bus-off recovery interrupt enabled - #1 - - - - - BOEIE - Bus-Off Entry Interrupt Enable - 3 - 3 - read-write - - - 0 - Bus-off entry interrupt disabled - #0 - - - 1 - Bus-off entry interrupt enabled - #1 - - - - - EPIE - Error-Passive Interrupt Enable - 2 - 2 - read-write - - - 0 - Error-passive interrupt disabled - #0 - - - 1 - Error-passive interrupt enabled - #1 - - - - - EWIE - Error-Warning Interrupt Enable - 1 - 1 - read-write - - - 0 - Error-warning interrupt disabled - #0 - - - 1 - Error-warning interrupt enabled - #1 - - - - - BEIE - Bus Error Interrupt Enable - 0 - 0 - read-write - - - 0 - Bus error interrupt disabled - #0 - - - 1 - Bus error interrupt enabled - #1 - - - - - - - EIFR - Error Interrupt Factor Judge Register - 0x84D - 8 - read-write - 0x00 - 0xFF - - - BLIF - Bus Lock Detect Flag - 7 - 7 - read-write - - - 0 - No bus lock detected - #0 - - - 1 - Bus lock detected - #1 - - - - - OLIF - Overload Frame Transmission Detect Flag - 6 - 6 - read-write - - - 0 - No overload frame transmission detected - #0 - - - 1 - Overload frame transmission detected - #1 - - - - - ORIF - Receive Overrun Detect Flag - 5 - 5 - read-write - - - 0 - No receive overrun detected - #0 - - - 1 - Receive overrun detected - #1 - - - - - BORIF - Bus-Off Recovery Detect Flag - 4 - 4 - read-write - - - 0 - No bus-off recovery detected - #0 - - - 1 - Bus-off recovery detected - #1 - - - - - BOEIF - Bus-Off Entry Detect Flag - 3 - 3 - read-write - - - 0 - No bus-off entry detected - #0 - - - 1 - Bus-off entry detected - #1 - - - - - EPIF - Error-Passive Detect Flag - 2 - 2 - read-write - - - 0 - No error-passive detected - #0 - - - 1 - Error-passive detected - #1 - - - - - EWIF - Error-Warning Detect Flag - 1 - 1 - read-write - - - 0 - No error-warning detected - #0 - - - 1 - Error-warning detected - #1 - - - - - BEIF - Bus Error Detect Flag - 0 - 0 - read-write - - - 0 - No bus error detected - #0 - - - 1 - Bus error detected - #1 - - - - - - - RECR - Receive Error Count Register - 0x84E - 8 - read-only - 0x00 - 0xFF - - - RECR - Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception. - 0 - 7 - read-only - - - - - TECR - Transmit Error Count Register - 0x84F - 8 - read-only - 0x00 - 0xFF - - - TECR - Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission. - 0 - 7 - read-only - - - - - ECSR - Error Code Store Register - 0x850 - 8 - read-write - 0x00 - 0xFF - - - EDPM - Error Display Mode Select - 7 - 7 - read-write - - - 0 - Output of first detected error code - #0 - - - 1 - Output of accumulated error code - #1 - - - - - ADEF - ACK Delimiter Error Flag - 6 - 6 - read-write - - - 0 - No ACK delimiter error detected - #0 - - - 1 - ACK delimiter error detected - #1 - - - - - BE0F - Bit Error (dominant) Flag - 5 - 5 - read-write - - - 0 - No bit error (dominant) detected - #0 - - - 1 - Bit error (dominant) detected - #1 - - - - - BE1F - Bit Error (recessive) Flag - 4 - 4 - read-write - - - 0 - No bit error (recessive) detected - #0 - - - 1 - Bit error (recessive) detected - #1 - - - - - CEF - CRC Error Flag - 3 - 3 - read-write - - - 0 - No CRC error detected - #0 - - - 1 - CRC error detected - #1 - - - - - AEF - ACK Error Flag - 2 - 2 - read-write - - - 0 - No ACK error detected - #0 - - - 1 - ACK error detected - #1 - - - - - FEF - Form Error Flag - 1 - 1 - read-write - - - 0 - No form error detected - #0 - - - 1 - Form error detected - #1 - - - - - SEF - Stuff Error Flag - 0 - 0 - read-write - - - 0 - No stuff error detected - #0 - - - 1 - Stuff error detected - #1 - - - - - - - CSSR - Channel Search Support Register - 0x851 - 8 - read-write - 0x00 - 0x00 - - - CSSR - When the value for the channel search is input, the channel number is output to MSSR. - 0 - 7 - read-write - - - - - MSSR - Mailbox Search Status Register - 0x852 - 8 - read-only - 0x80 - 0xFF - - - SEST - Search Result Status - 7 - 7 - read-only - - - 0 - Search result found - #0 - - - 1 - No search result - #1 - - - - - MBNST - Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR. - 0 - 4 - read-only - - - - - MSMR - Mailbox Search Mode Register - 0x853 - 8 - read-write - 0x00 - 0xFF - - - MBSM - Mailbox Search Mode Select - 0 - 1 - read-write - - - 00 - Receive mailbox search mode - #00 - - - 01 - Transmit mailbox search mode - #01 - - - 10 - Message lost search mode - #10 - - - 11 - Channel search mode - #11 - - - - - - - TSR - Time Stamp Register - 0x854 - 16 - read-only - 0x0000 - 0xFFFF - - - TSR - Free-running counter value for the time stamp function - 0 - 15 - read-only - - - - - AFSR - Acceptance Filter Support Register - 0x856 - 16 - read-write - 0x0000 - 0x0000 - - - AFSR - After the standard ID of a received message is written, the value converted for data table search can be read. - 0 - 15 - read-write - - - - - TCR - Test Control Register - 0x858 - 8 - read-write - 0x00 - 0xFF - - - TSTM - CAN Test Mode Select - 1 - 2 - read-write - - - 00 - Other than CAN test mode - #00 - - - 01 - Listen-only mode - #01 - - - 10 - Self-test mode 0 (external loopback) - #10 - - - 11 - Self-test mode 1 (internal loopback) - #11 - - - - - TSTE - CAN Test Mode Enable - 0 - 0 - read-write - - - 0 - CAN test mode disabled - #0 - - - 1 - CAN test mode enabled - #1 - - - - - - - - - R_CAN1 - 0x40051000 - - - R_CRC - Cyclic Redundancy Check (CRC) Calculator - 0x40074000 - - 0x00000000 - 0x002 - registers - - - 0x00000004 - 0x00A - registers - - - - CRCCR0 - CRC Control Register0 - 0x00 - 8 - read-write - 0x00 - 0xFF - - - DORCLR - CRCDOR Register Clear - 7 - 7 - write-only - - - 0 - No effect. - #0 - - - 1 - Clears the CRCDOR register. - #1 - - - - - LMS - CRC Calculation Switching - 6 - 6 - read-write - - - 0 - Generates CRC for LSB first communication. - #0 - - - 1 - Generates CRC for MSB first communication. - #1 - - - - - GPS - CRC Generating Polynomial Switching - 0 - 2 - read-write - - - 000 - No calculation is executed. - #000 - - - 001 - 8-bit CRC-8 (X8 + X2 + X + 1) - #001 - - - 010 - 16-bit CRC-16 (X16 + X15 + X2 + 1) - #010 - - - 011 - 16-bit CRC-CCITT (X16 + X12 + X5 + 1) - #011 - - - 100 - 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) - #100 - - - 101 - 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) - #101 - - - others - No calculation is executed. - true - - - - - - - CRCCR1 - CRC Control Register1 - 0x01 - 8 - read-write - 0x00 - 0xFF - - - CRCSEN - Snoop enable bit - 7 - 7 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - CRCSWR - Snoop-on-write/read switch bit - 6 - 6 - read-write - - - 0 - Snoop-on-read - #0 - - - 1 - Snoop-on-write - #1 - - - - - - - CRCDIR - CRC Data Input Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRCDIR - Calculation input Data (Case of CRC-32, CRC-32C ) - 0 - 31 - read-write - - - - - CRCDIR_BY - CRC Data Input Register (byte access) - CRCDIR - 0x04 - 8 - read-write - 0x00 - 0xFF - - - CRCDIR_BY - Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) - 0 - 7 - read-write - - - - - CRCDOR - CRC Data Output Register - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CRCDOR - Calculation output Data (Case of CRC-32, CRC-32C ) - 0 - 31 - read-write - - - - - CRCDOR_HA - CRC Data Output Register (halfword access) - CRCDOR - 0x08 - 16 - read-write - 0x0000 - 0xFFFF - - - CRCDOR_HA - Calculation output Data (Case of CRC-16 or CRC-CCITT ) - 0 - 15 - read-write - - - - - CRCDOR_BY - CRC Data Output Register(byte access) - CRCDOR - 0x08 - 8 - read-write - 0x00 - 0xFF - - - CRCDOR_BY - Calculation output Data (Case of CRC-8 ) - 0 - 7 - read-write - - - - - CRCSAR - Snoop Address Register - 0x0C - 16 - read-write - 0x0000 - 0xFFFF - - - CRCSA - snoop address bitSet the I/O register address to snoop - 0 - 13 - read-write - - - 0x0003 - SCI0.TDR - 0x0003 - - - 0x0005 - SCI0.RDR - 0x0005 - - - 0x0023 - SCI1.TDR - 0x0023 - - - 0x0025 - SCI1.RDR - 0x0025 - - - 0x0043 - SCI2.TDR - 0x0043 - - - 0x0045 - SCI2.RDR - 0x0045 - - - 0x0063 - SCI3.TDR - 0x0063 - - - 0x0065 - SCI3.RDR - 0x0065 - - - 0x0083 - SCI4.TDR - 0x0083 - - - 0x0085 - SCI4.RDR - 0x0085 - - - 0x00A3 - SCI5.TDR - 0x00A3 - - - 0x00A5 - SCI5.RDR - 0x00A5 - - - 0x00C3 - SCI6.TDR - 0x00C3 - - - 0x00C5 - SCI6.RDR - 0x00C5 - - - 0x00E3 - SCI7.TDR - 0x00E3 - - - 0x00E5 - SCI7.RDR - 0x00E5 - - - 0x0103 - SCI8.TDR - 0x0103 - - - 0x0105 - SCI8.RDR - 0x0105 - - - 0x0123 - SCI9.TDR - 0x0123 - - - 0x0125 - SCI9.RDR - 0x0125 - - - others - Settings other than above are prohibited. - true - - - - - - - - - R_CTSU - Capacitive Touch Sensing Unit - 0x40081000 - - 0x00000000 - 0x01E - registers - - - - CTSUCR0 - CTSU Control Register 0 - 0x00 - 8 - read-write - 0x00 - 0xFF - - - CTSUTXVSEL - CTSU Transmission power supply selection - 7 - 7 - read-write - - - 0 - Select Vcc - #0 - - - 1 - Select internal logic power supply - #1 - - - - - CTSUINIT - CTSU Control Block Initialization - 4 - 4 - read-write - - - 0 - Writing a 0 has no effect, this bit is read as 0. - #0 - - - 1 - initializes the CTSU control block and registers. - #1 - - - - - CTSUIOC - CTSU Transmit Pin Control - 3 - 3 - read-write - - - 0 - Low-level output from transmit channel non-measurement pin. - #0 - - - 1 - High-level output from transmit channel non-measurement pin. - #1 - - - - - CTSUSNZ - CTSU Wait State Power-Saving Enable - 2 - 2 - read-write - - - 0 - Power-saving function during wait state is disabled. - #0 - - - 1 - Power-saving function during wait state is enabled. - #1 - - - - - CTSUCAP - CTSU Measurement Operation Start Trigger Select - 1 - 1 - read-write - - - 0 - Software trigger. - #0 - - - 1 - External trigger. - #1 - - - - - CTSUSTRT - CTSU Measurement Operation Start - 0 - 0 - read-write - - - 0 - Measurement operation stops. - #0 - - - 1 - Measurement operation starts. - #1 - - - - - - - CTSUCR1 - CTSU Control Register 1 - 0x01 - 8 - read-write - 0x00 - 0xFF - - - CTSUMD - CTSU Measurement Mode Select - 6 - 7 - read-write - - - 00 - Self-capacitance single scan mode - #00 - - - 01 - Self-capacitance multi-scan mode - #01 - - - 10 - Mutual capacitance simple scan mode - #10 - - - 11 - Mutual capacitance full scan mode - #11 - - - - - CTSUCLK - CTSU Operating Clock Select - 4 - 5 - read-write - - - 00 - PCLK - #00 - - - 01 - PCLK/2 (PCLK divided by 2) - #01 - - - 10 - PCLK/2 (PCLK divided by 4) - #10 - - - 11 - Setting prohibited - #11 - - - - - CTSUATUNE1 - CTSU Power Supply Capacity Adjustment - 3 - 3 - read-write - - - 0 - Normal output - #0 - - - 1 - High-current output - #1 - - - - - CTSUATUNE0 - CTSU Power Supply Operating Mode Setting - 2 - 2 - read-write - - - 0 - Normal operating mode - #0 - - - 1 - Low-voltage operating mode - #1 - - - - - CTSUCSW - CTSU LPF Capacitance Charging Control - 1 - 1 - read-write - - - 0 - Turned off capacitance switch - #0 - - - 1 - Turned on capacitance switch - #1 - - - - - CTSUPON - CTSU Power Supply Enable - 0 - 0 - read-write - - - 0 - Powered off the CTSU - #0 - - - 1 - Powered on the CTSU - #1 - - - - - - - CTSUSDPRS - CTSU Synchronous Noise Reduction Setting Register - 0x02 - 8 - read-write - 0x00 - 0xFF - - - CTSUSOFF - CTSU High-Pass Noise Reduction Function Off Setting - 6 - 6 - read-write - - - 0 - High-pass noise reduction function turned on - #0 - - - 1 - High-pass noise reduction function turned off - #1 - - - - - CTSUPRMODE - CTSU Base Period and Pulse Count Setting - 4 - 5 - read-write - - - 00 - 510 pulses - #00 - - - 01 - 126 pulses - #01 - - - 10 - 62 pulses (recommended setting value) - #10 - - - 11 - Setting prohibited - #11 - - - - - CTSUPRRATIO - CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b) - 0 - 3 - read-write - - - - - CTSUSST - CTSU Sensor Stabilization Wait Control Register - 0x03 - 8 - read-write - 0x00 - 0xFF - - - CTSUSST - CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b. - 0 - 7 - read-write - - - - - CTSUMCH0 - CTSU Measurement Channel Register 0 - 0x04 - 8 - read-write - 0x3F - 0xFF - - - CTSUMCH0 - CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan mode, the measurement is stopped. - 0 - 5 - read-write - - - TS0 - measured TS0 - 0 - - - TS1 - measured TS1 - 1 - - - TS2 - measured TS2 - 2 - - - TS3 - measured TS3 - 3 - - - TS4 - measured TS4 - 4 - - - TS5 - measured TS5 - 5 - - - TS6 - measured TS6 - 6 - - - TS7 - measured TS7 - 7 - - - TS8 - measured TS8 - 8 - - - TS9 - measured TS9 - 9 - - - TS10 - measured TS10 - 10 - - - TS11 - measured TS11 - 11 - - - TS12 - measured TS12 - 12 - - - TS13 - measured TS13 - 13 - - - TS14 - measured TS14 - 14 - - - TS15 - measured TS15 - 15 - - - TS16 - measured TS16 - 16 - - - TS17 - measured TS17 - 17 - - - TS18 - measured TS18 - 18 - - - TS19 - measured TS19 - 19 - - - TS20 - measured TS20 - 20 - - - TS21 - measured TS21 - 21 - - - TS22 - measured TS22 - 22 - - - TS23 - measured TS23 - 23 - - - TS24 - measured TS24 - 24 - - - TS25 - measured TS25 - 25 - - - TS26 - measured TS26 - 26 - - - TS27 - measured TS27 - 27 - - - TS28 - measured TS28 - 28 - - - TS29 - measured TS29 - 29 - - - TS30 - measured TS30 - 30 - - - TS31 - measured TS31 - 31 - - - TS32 - measured TS32 - 32 - - - TS33 - measured TS33 - 33 - - - TS34 - measured TS34 - 34 - - - TS35 - measured TS35 - 35 - - - STOP - Conversion Stopped - #111111 - - - - - - - CTSUMCH1 - CTSU Measurement Channel Register 1 - 0x05 - 8 - read-write - 0x3F - 0xFF - - - CTSUMCH1 - CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 was set to b'111111, the measurement is stopped. - 0 - 5 - read-only - - - TS0 - measured TS0 - 0 - - - TS1 - measured TS1 - 1 - - - TS2 - measured TS2 - 2 - - - TS3 - measured TS3 - 3 - - - TS4 - measured TS4 - 4 - - - TS5 - measured TS5 - 5 - - - TS6 - measured TS6 - 6 - - - TS7 - measured TS7 - 7 - - - TS8 - measured TS8 - 8 - - - TS9 - measured TS9 - 9 - - - TS10 - measured TS10 - 10 - - - TS11 - measured TS11 - 11 - - - TS12 - measured TS12 - 12 - - - TS13 - measured TS13 - 13 - - - TS14 - measured TS14 - 14 - - - TS15 - measured TS15 - 15 - - - TS16 - measured TS16 - 16 - - - TS17 - measured TS17 - 17 - - - TS18 - measured TS18 - 18 - - - TS19 - measured TS19 - 19 - - - TS20 - measured TS20 - 20 - - - TS21 - measured TS21 - 21 - - - TS22 - measured TS22 - 22 - - - TS23 - measured TS23 - 23 - - - TS24 - measured TS24 - 24 - - - TS25 - measured TS25 - 25 - - - TS26 - measured TS26 - 26 - - - TS27 - measured TS27 - 27 - - - TS28 - measured TS28 - 28 - - - TS29 - measured TS29 - 29 - - - TS30 - measured TS30 - 30 - - - TS31 - measured TS31 - 31 - - - TS32 - measured TS32 - 32 - - - TS33 - measured TS33 - 33 - - - TS34 - measured TS34 - 34 - - - TS35 - measured TS35 - 35 - - - STOP - Conversion Stopped - #111111 - - - - - - - 5 - 1 - CTSUCHAC[%s] - CTSU Channel Enable Control Register - 0x06 - 8 - read-write - 0x00 - 0xFF - - - 8 - 1 - TS%s - CTSU Channel Enable Control - 0 - 0 - read-write - - - 0 - Do not measure - 0 - - - 1 - Measure - 1 - - - - - - - 5 - 1 - CTSUCHTRC[%s] - CTSU Channel Transmit/Receive Control Register - 0x0B - 8 - read-write - 0x00 - 0xFF - - - 8 - 1 - TS%s - CTSU Channel Transmit/Receive Control - 0 - 0 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - - - CTSUDCLKC - CTSU High-Pass Noise Reduction Control Register - 0x10 - 8 - read-write - 0x00 - 0xFF - - - CTSUSSCNT - CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b. - 4 - 5 - read-write - - - CTSUSSMOD - CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b. - 0 - 1 - read-write - - - - - CTSUST - CTSU Status Register - 0x11 - 8 - read-write - 0x00 - 0xFF - - - CTSUPS - CTSU Mutual Capacitance Status Flag - 7 - 7 - read-only - - - 0 - First measurement - #0 - - - 1 - Second measurement - #1 - - - - - CTSUROVF - CTSU Reference Counter Overflow Flag - 6 - 6 - read-write - - - 0 - No overflow - #0 - - - 1 - An overflow - #1 - - - - - CTSUSOVF - CTSU Sensor Counter Overflow Flag - 5 - 5 - read-write - - - 0 - No overflow - #0 - - - 1 - An overflow - #1 - - - - - CTSUDTSR - CTSU Data Transfer Status Flag - 4 - 4 - read-only - - - 0 - Measurement result has been read - #0 - - - 1 - Measurement result has not been read - #1 - - - - - CTSUSTC - CTSU Measurement Status Counter - 0 - 2 - read-only - - - 000 - Status 0 - #000 - - - 001 - Status 1 - #001 - - - 010 - Status 2 - #010 - - - 011 - Status 3 - #011 - - - 100 - Status 4 - #100 - - - 101 - Status 5 - #101 - - - - - - - CTSUSSC - CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register - 0x12 - 16 - read-write - 0x0000 - 0xFFFF - - - CTSUSSDIV - CTSU Spectrum Diffusion Frequency Division Setting - 8 - 11 - read-write - - - 0000 - 4.00 <= fb - #0000 - - - 0001 - 2.00 <= fb < 4.00 - #0001 - - - 0010 - 1.33 <= fb < 2.00 - #0010 - - - 0011 - 1.00 <= fb < 1.33 - #0011 - - - 0100 - 0.80 <= fb < 1.00 - #0100 - - - 0101 - 0.67 <= fb < 0.80 - #0101 - - - 0110 - 0.57 <= fb < 0.67 - #0110 - - - 0111 - 0.50 <= fb < 0.57 - #0111 - - - 1000 - 0.44 <= fb < 0.50 - #1000 - - - 1001 - 0.40 <= fb < 0.44 - #1001 - - - 1010 - 0.36 <= fb < 0.40 - #1010 - - - 1011 - 0.33 <= fb < 0.36 - #1011 - - - 1100 - 0.31 <= fb < 0.33 - #1100 - - - 1101 - 0.29 <= fb < 0.31 - #1101 - - - 1110 - 0.27 <= fb < 0.29 - #1110 - - - 1111 - fb < 0.27 - #1111 - - - - - - - CTSUSO0 - CTSU Sensor Offset Register 0 - 0x14 - 16 - read-write - 0x0000 - 0xFFFF - - - CTSUSNUM - CTSU Measurement Count Setting - 10 - 15 - read-write - - - CTSUSO - CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 ) - 0 - 9 - read-write - - - - - CTSUSO1 - CTSU Sensor Offset Register 1 - 0x16 - 16 - read-write - 0x0000 - 0xFFFF - - - CTSUICOG - CTSU ICO Gain Adjustment - 13 - 14 - read-write - - - 00 - 100 percent gain - #00 - - - 01 - 66 percent gain - #01 - - - 10 - 50 percent gain - #10 - - - 11 - 40 percent gain - #11 - - - - - CTSUSDPA - CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2 - 8 - 12 - read-write - - - CTSURICOA - CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 ) - 0 - 7 - read-write - - - - - CTSUSC - CTSU Sensor Counter - 0x18 - 16 - read-only - 0x0000 - 0xFFFF - - - CTSUSC - CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs. - 0 - 15 - read-only - - - - - CTSURC - CTSU Reference Counter - 0x1A - 16 - read-only - 0x0000 - 0xFFFF - - - CTSURC - CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs. - 0 - 15 - read-only - - - - - CTSUERRS - CTSU Error Status Register - 0x1C - 16 - read-only - 0x0000 - 0xFFFF - - - CTSUICOMP - TSCAP Voltage Error Monitor - 15 - 15 - read-only - - - 0 - Normal TSCAP voltage - #0 - - - 1 - Abnormal TSCAP voltage - #1 - - - - - - - - - R_CTSU2 - Capacitive Touch Sensing Unit - 0x40082000 - - 0x00 - 12 - registers - - - 0x0C - 8 - registers - - - 0x14 - 8 - registers - - - 0x1C - 4 - registers - - - 0x20 - 8 - registers - - - 0x28 - 16 - registers - - - - CTSUCRA - CTSU Control Register A - 0x00 - 32 - read-write - 0x00000000 - 0xffffffff - - - STRT - CTSU Measurement Operation Start - 0 - 0 - read-write - - - 0 - Stop measurement operation - #0 - - - 1 - Start measurement operation - #1 - - - - - CAP - CTSU Measurement Operation Start Trigger Select - 1 - 1 - read-write - - - 0 - Software trigger - #0 - - - 1 - External trigger - #1 - - - - - SNZ - CTSU Wait State Power-Saving Enable - 2 - 2 - read-write - - - 0 - Disable power-saving function during wait state - #0 - - - 1 - Enable power-saving function during wait state - #1 - - - - - CFCON - CTSU CFC Power on Control - 3 - 3 - read-write - - - 0 - CFC power off - #0 - - - 1 - CFC power on - #1 - - - - - INIT - CTSU Control Block Initialization - 4 - 4 - write-only - - - PUMPON - CTSU Boost Circuit Control - 5 - 5 - read-write - - - 0 - Boost circuit off - #0 - - - 1 - Boost circuit on - #1 - - - - - TXVSEL - CTSU Transmission Power Supply Selection - 6 - 7 - read-write - - - 00 - VCC is selected as the power supply for the transmit pins in measurement methods other than self-capacitance method. - #00 - - - 01 - VCC is selected as the power supply for the transmit pins in self-capacitance method. - #01 - - - 10 - VCL is selected as the power-supply voltage for the transmit pins. - #10 - - - 11 - Setting prohibited - #11 - - - - - PON - CTSU Power Supply Enable - 8 - 8 - read-write - - - 0 - Power off the CTSU - #0 - - - 1 - Power on the CTSU - #1 - - - - - CSW - CTSU LPF Capacitance Charging Control - 9 - 9 - read-write - - - 0 - Turn off capacitance switch - #0 - - - 1 - Turn on capacitance switch - #1 - - - - - ATUNE0 - CTSU Power Supply Operating Mode Setting - 10 - 10 - read-write - - - 0 - VCC ≥ 2.4 V: Normal operating mode - VCC < 2.4 V: Setting prohibited - - #0 - - - 1 - Low-voltage operating mode - #1 - - - - - ATUNE1 - CTSU Current Range Adjustment - 11 - 11 - read-write - - - 0 - 40 µA when CTSUATUNE2 = 0 - 20 µA when CTSUATUNE2 = 1 - - #0 - - - 1 - 80 µA when CTSUATUNE2 = 0 - 160 µA when CTSUATUNE2 = 1 - - #1 - - - - - CLK - CTSU Operating Clock Select - 12 - 13 - read-write - - - 00 - PCLKB - #00 - - - 01 - PCLKB/2 (PCLKB divided by 2) - #01 - - - 10 - PCLKB/4 (PCLKB divided by 4) - #10 - - - 11 - PCLKB/8 (PCLKB divided by 8) - #11 - - - - - MD0 - CTSU Measurement Mode Select 0 - 14 - 14 - read-write - - - 0 - Single scan mode - #0 - - - 1 - Multi-scan mode - #1 - - - - - MD1 - CTSU Measurement Mode Select 1 - 15 - 15 - read-write - - - 0 - Single scan mode - #0 - - - 1 - Multi-scan mode - #1 - - - - - MD2 - CTSU Measurement Mode Select 2 - 16 - 16 - read-write - - - 0 - Measure the current that flows through the switched capacitor. - #0 - - - 1 - Measure the transfer charge in CFC circuit (high speed measurement) - #1 - - - - - ATUNE2 - CTSU Current Range Adjustment - 17 - 17 - read-write - - - 0 - 40 µA when CTSUATUNE1 = 0 - 80 µA when CTSUATUNE2 = 1 - - #0 - - - 1 - 20 µA when CTSUATUNE1 = 0 - 160 µA when CTSUATUNE2 = 1 - - #1 - - - - - LOAD - CTSU Measurement Load Control - 18 - 19 - read-write - - - 00 - Normal measurement mode - #00 - - - 01 - Load off mode - #01 - - - 10 - Current load mode - #10 - - - 11 - Resistance load mode - #11 - - - - - POSEL - CTSU Non-measured Channel Output Select - 20 - 21 - read-write - - - 00 - Output low through GPIO - #00 - - - 01 - Hi-Z - #01 - - - 10 - Output low through the power setting in the TXVSEL[1:0] bits - #10 - - - 11 - Same phase pulse output as transmission channel through the power setting in the TXVSEL[1:0] bits - #11 - - - - - SDPSEL - CTSU Sensor Drive Pulse Select - 22 - 22 - read-write - - - 0 - Random pulse mode - #0 - - - 1 - High resolution pulse mode - #1 - - - - - FCMODE - CTSU SUCLK Control - 23 - 23 - read-write - - - 0 - SUCLK is used as frequency diffusion clock - #0 - - - 1 - SUCLK is used as recovery clock for multi-clock measurement - #1 - - - - - STCLK - CTSU STCLK Select - 24 - 29 - read-write - - - DCMODE - CTSU Current Measurement Mode Select - 30 - 30 - read-write - - - 0 - Normal mode - #0 - - - 1 - Current measurement mode - #1 - - - - - DCBACK - CTSU Current Measurement Feedback Select - 31 - 31 - read-write - - - 0 - TSCAP pin is selected - #0 - - - 1 - Measurement pin is selected - #1 - - - - - - - CTSUCRAL - CTSU Control Register A - CTSUCRA - 0x00 - 16 - read-write - 0x0000 - 0xffff - - - CTSUCR0 - CTSU Control Register A - CTSUCRA - 0x00 - 8 - read-write - 0x00 - 0xff - - - CTSUCR1 - CTSU Control Register A - CTSUCRA - 0x01 - 8 - read-write - 0x00 - 0xff - - - CTSUCR2 - CTSU Control Register A - CTSUCRAH - 0x02 - 8 - read-write - 0x00 - 0xff - - - CTSUCR3 - CTSU Control Register A - CTSUCRA - 0x03 - 8 - read-write - 0x00 - 0xff - - - CTSUCRB - CTSU Control Register B - 0x04 - 32 - read-write - 0x00000000 - 0xffffffff - - - PRRATIO - CTSU Measurement Time and Pulse Count Adjustment - 0 - 3 - read-write - - - PRMODE - CTSU Base Period and Pulse Count Setting - 4 - 5 - read-write - - - 00 - 510 pulses (512 pulses when PROFF bit is 1) - #00 - - - 01 - 126 pulses (128 pulses when PROFF bit is 1) - #01 - - - 10 - 62 pulses (recommended setting) (64 pulses when PROFF bit is 1) - #10 - - - 11 - Setting prohibited - #11 - - - - - SOFF - CTSU High-Pass Noise Reduction Function Off Setting - 6 - 6 - read-write - - - 0 - Turn spectrum diffusion on. - #0 - - - 1 - Turn spectrum diffusion off. - #1 - - - - - PROFF - CTSU Random Number Off Control - 7 - 7 - read-write - - - 0 - There is random number control. - #0 - - - 1 - There is no random number control. - #1 - - - - - SST - CTSU Sensor Stabilization Wait Control - 8 - 15 - read-write - - - SSMOD - CTSU SUCLK Diffusion Mode Select - 24 - 26 - read-write - - - SSCNT - CTSU SUCLK Diffusion Control - 28 - 29 - read-write - - - - - CTSUCRBL - CTSU Control Register B - CTSUCRB - 0x04 - 16 - read-write - 0x0000 - 0xffff - - - CTSUSDPRS - CTSU Control Register B - CTSUCRB - 0x04 - 8 - read-write - 0x00 - 0xff - - - CTSUSST - CTSU Control Register B - CTSUCRB - 0x05 - 8 - read-write - 0x00 - 0xff - - - CTSUCRBH - CTSU Control Register B - CTSUCRB - 0x06 - 16 - read-write - 0x0000 - 0xffff - - - CTSUDCLKC - CTSU Control Register B - CTSUCRB - 0x07 - 8 - read-write - 0x00 - 0xff - - - CTSUMCH - CTSU Measurement Channel Register - 0x08 - 32 - read-write - 0x00003f3f - 0xffffffff - - - MCH0 - CTSU Measurement Channel 0 - 0 - 5 - read-write - - - 0x00 - TS00 - 0x00 - - - 0x02 - TS02 - 0x02 - - - 0x04 - TS04 - 0x04 - - - 0x05 - TS05 - 0x05 - - - 0x06 - TS06 - 0x06 - - - 0x07 - TS07 - 0x07 - - - 0x08 - TS08 - 0x08 - - - 0x09 - TS09 - 0x09 - - - 0x0A - TS10 - 0x0a - - - 0x0B - TS11 - 0x0b - - - 0x0C - TS12 - 0x0c - - - 0x0D - TS13 - 0x0d - - - 0x0E - TS14 - 0x0e - - - 0x0F - TS15 - 0x0f - - - 0x10 - TS16 - 0x10 - - - 0x11 - TS17 - 0x11 - - - 0x12 - TS18 - 0x12 - - - 0x15 - TS21 - 0x15 - - - 0x16 - TS22 - 0x16 - - - 0x17 - TS23 - 0x17 - - - 0x18 - TS24 - 0x18 - - - 0x19 - TS25 - 0x19 - - - 0x1A - TS26 - 0x1a - - - 0x1B - TS27 - 0x1b - - - 0x1C - TS28 - 0x1c - - - 0x1D - TS29 - 0x1d - - - 0x1E - TS30 - 0x1e - - - 0x1F - TS31 - 0x1f - - - 0x20 - TS32 - 0x20 - - - 0x21 - TS33 - 0x21 - - - 0x22 - TS34 - 0x22 - - - 0x23 - TS35 - 0x23 - - - 0x3F - Measurement is being stopped. - 0x3f - - - - - MCH1 - CTSU Measurement Channel 1 - 8 - 13 - read-write - - - 0x00 - TS00 - 0x00 - - - 0x02 - TS02 - 0x02 - - - 0x04 - TS04 - 0x04 - - - 0x05 - TS05 - 0x05 - - - 0x06 - TS06 - 0x06 - - - 0x07 - TS07 - 0x07 - - - 0x08 - TS08 - 0x08 - - - 0x09 - TS09 - 0x09 - - - 0x0A - TS10 - 0x0a - - - 0x0B - TS11 - 0x0b - - - 0x0C - TS12 - 0x0c - - - 0x0D - TS13 - 0x0d - - - 0x0E - TS14 - 0x0e - - - 0x0F - TS15 - 0x0f - - - 0x10 - TS16 - 0x10 - - - 0x11 - TS17 - 0x11 - - - 0x12 - TS18 - 0x12 - - - 0x15 - TS21 - 0x15 - - - 0x16 - TS22 - 0x16 - - - 0x17 - TS23 - 0x17 - - - 0x18 - TS24 - 0x18 - - - 0x19 - TS25 - 0x19 - - - 0x1A - TS26 - 0x1a - - - 0x1B - TS27 - 0x1b - - - 0x1C - TS28 - 0x1c - - - 0x1D - TS29 - 0x1d - - - 0x1E - TS30 - 0x1e - - - 0x1F - TS31 - 0x1f - - - 0x20 - TS32 - 0x20 - - - 0x21 - TS33 - 0x21 - - - 0x22 - TS34 - 0x22 - - - 0x23 - TS35 - 0x23 - - - 0x3F - Measurement is being stopped. - 0x3f - - - - - MCA0 - CTSU Multiple Valid Clock Control - 16 - 16 - read-write - - - 0 - Valid - #0 - - - 1 - Invalid - #1 - - - - - MCA1 - CTSU Multiple Valid Clock Control - 17 - 17 - read-write - - - 0 - Valid - #0 - - - 1 - Invalid - #1 - - - - - MCA2 - CTSU Multiple Valid Clock Control - 18 - 18 - read-write - - - 0 - Valid - #0 - - - 1 - Invalid - #1 - - - - - MCA3 - CTSU Multiple Valid Clock Control - 19 - 19 - read-write - - - 0 - Valid - #0 - - - 1 - Invalid - #1 - - - - - - - CTSUMCHL - CTSU Measurement Channel Register - CTSUMCH - 0x08 - 16 - read-write - 0x0000 - 0xffff - - - CTSUMCH0 - CTSU Measurement Channel Register - CTSUMCH - 0x08 - 8 - read-write - 0x00 - 0xff - - - CTSUMCH1 - CTSU Measurement Channel Register - CTSUMCH - 0x09 - 8 - read-write - 0x00 - 0xff - - - CTSUMCHH - CTSU Measurement Channel Register - CTSUMCH - 0x0A - 16 - read-write - 0x3f3f - 0xffff - - - CTSUMFAF - CTSU Measurement Channel Register - CTSUMCHH - 0x0A - 8 - read-write - 0x3f - 0xff - - - CTSUCHACA - CTSU Channel Enable Control Register A - 0x0C - 32 - read-write - 0x00000000 - 0xffffffff - - - CHAC00 - CTSU Channel Enable Control A - 0 - 0 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC02 - CTSU Channel Enable Control A - 2 - 2 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC04 - CTSU Channel Enable Control A - 4 - 4 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC05 - CTSU Channel Enable Control A - 5 - 5 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC06 - CTSU Channel Enable Control A - 6 - 6 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC07 - CTSU Channel Enable Control A - 7 - 7 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC08 - CTSU Channel Enable Control A - 8 - 8 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC09 - CTSU Channel Enable Control A - 9 - 9 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC10 - CTSU Channel Enable Control A - 10 - 10 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC11 - CTSU Channel Enable Control A - 11 - 11 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC12 - CTSU Channel Enable Control A - 12 - 12 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC13 - CTSU Channel Enable Control A - 13 - 13 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC14 - CTSU Channel Enable Control A - 14 - 14 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC15 - CTSU Channel Enable Control A - 15 - 15 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC16 - CTSU Channel Enable Control A - 16 - 16 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC17 - CTSU Channel Enable Control A - 17 - 17 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC18 - CTSU Channel Enable Control A - 18 - 18 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC21 - CTSU Channel Enable Control A - 21 - 21 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC22 - CTSU Channel Enable Control A - 22 - 22 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC23 - CTSU Channel Enable Control A - 23 - 23 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC24 - CTSU Channel Enable Control A - 24 - 24 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC25 - CTSU Channel Enable Control A - 25 - 25 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC26 - CTSU Channel Enable Control A - 26 - 26 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC27 - CTSU Channel Enable Control A - 27 - 27 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC28 - CTSU Channel Enable Control A - 28 - 28 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC29 - CTSU Channel Enable Control A - 29 - 29 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC30 - CTSU Channel Enable Control A - 30 - 30 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC31 - CTSU Channel Enable Control A - 31 - 31 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - - - CTSUCHACAL - CTSU Channel Enable Control Register A - CTSUCHACA - 0x0C - 16 - read-write - 0x0000 - 0xffff - - - CTSUCHAC0 - CTSU Channel Enable Control Register A - CTSUCHACA - 0x0C - 8 - read-write - 0x00 - 0xff - - - CTSUCHAC1 - CTSU Channel Enable Control Register A - CTSUCHACA - 0x0D - 8 - read-write - 0x00 - 0xff - - - CTSUCHACAH - CTSU Channel Enable Control Register A - CTSUCHACA - 0x0E - 16 - read-write - 0x0000 - 0xffff - - - CTSUCHAC2 - CTSU Channel Enable Control Register A - CTSUCHACAH - 0x0E - 8 - read-write - 0x00 - 0xff - - - CTSUCHAC3 - CTSU Channel Enable Control Register A - CTSUCHACA - 0x0F - 8 - read-write - 0x00 - 0xff - - - CTSUCHACB - CTSU Channel Enable Control Register B - 0x10 - 32 - read-write - 0x00000000 - 0xffffffff - - - CHAC32 - CTSU Channel Enable Control B - 0 - 0 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC33 - CTSU Channel Enable Control B - 1 - 1 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC34 - CTSU Channel Enable Control B - 2 - 2 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - CHAC35 - CTSU Channel Enable Control B - 3 - 3 - read-write - - - 0 - Do not measure. - #0 - - - 1 - Measure. - #1 - - - - - - - CTSUCHACBL - CTSU Channel Enable Control Register B - CTSUCHACB - 0x10 - 16 - read-write - 0x0000 - 0xffff - - - CTSUCHAC4 - CTSU Channel Enable Control Register B - CTSUCHACB - 0x10 - 8 - read-write - 0x00 - 0xff - - - CTSUCHTRCA - CTSU Channel Transmit/Receive Control Register A - 0x14 - 32 - read-write - 0x00000000 - 0xffffffff - - - CHTRC - CTSU Channel Transmit/Receive Control A - 0 - 0 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC02 - CTSU Channel Transmit/Receive Control A - 2 - 2 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC04 - CTSU Channel Transmit/Receive Control A - 4 - 4 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC05 - CTSU Channel Transmit/Receive Control A - 5 - 5 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC06 - CTSU Channel Transmit/Receive Control A - 6 - 6 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC07 - CTSU Channel Transmit/Receive Control A - 7 - 7 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC08 - CTSU Channel Transmit/Receive Control A - 8 - 8 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC09 - CTSU Channel Transmit/Receive Control A - 9 - 9 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC10 - CTSU Channel Transmit/Receive Control A - 10 - 10 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC11 - CTSU Channel Transmit/Receive Control A - 11 - 11 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC12 - CTSU Channel Transmit/Receive Control A - 12 - 12 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC13 - CTSU Channel Transmit/Receive Control A - 13 - 13 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC14 - CTSU Channel Transmit/Receive Control A - 14 - 14 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC15 - CTSU Channel Transmit/Receive Control A - 15 - 15 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC16 - CTSU Channel Transmit/Receive Control A - 16 - 16 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC17 - CTSU Channel Transmit/Receive Control A - 17 - 17 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC18 - CTSU Channel Transmit/Receive Control A - 18 - 18 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC21 - CTSU Channel Transmit/Receive Control A - 21 - 21 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC22 - CTSU Channel Transmit/Receive Control A - 22 - 22 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC23 - CTSU Channel Transmit/Receive Control A - 23 - 23 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC24 - CTSU Channel Transmit/Receive Control A - 24 - 24 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC25 - CTSU Channel Transmit/Receive Control A - 25 - 25 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC26 - CTSU Channel Transmit/Receive Control A - 26 - 26 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC27 - CTSU Channel Transmit/Receive Control A - 27 - 27 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC28 - CTSU Channel Transmit/Receive Control A - 28 - 28 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC29 - CTSU Channel Transmit/Receive Control A - 29 - 29 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC30 - CTSU Channel Transmit/Receive Control A - 30 - 30 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC31 - CTSU Channel Transmit/Receive Control A - 31 - 31 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - - - CTSUCHTRCAL - CTSU Channel Transmit/Receive Control Register A - CTSUCHTRCA - 0x14 - 16 - read-write - 0x0000 - 0xffff - - - CTSUCHTRC0 - CTSU Channel Transmit/Receive Control Register A - CTSUCHTRCA - 0x14 - 8 - read-write - 0x00 - 0xff - - - CTSUCHTRC1 - CTSU Channel Transmit/Receive Control Register A - CTSUCHTRCA - 0x15 - 8 - read-write - 0x00 - 0xff - - - CTSUCHTRCAH - CTSU Channel Transmit/Receive Control Register A - CTSUCHTRCA - 0x16 - 16 - read-write - 0x0000 - 0xffff - - - CTSUCHTRC2 - CTSU Channel Transmit/Receive Control Register A - CTSUCHTRCAH - 0x16 - 8 - read-write - 0x00 - 0xff - - - CTSUCHTRC3 - CTSU Channel Transmit/Receive Control Register A - CTSUCHTRCA - 0x17 - 8 - read-write - 0x00 - 0xff - - - CTSUCHTRCB - CTSU Channel Transmit/Receive Control Register B - 0x18 - 32 - read-write - 0x00000000 - 0xffffffff - - - CHTRC32 - CTSU Channel Transmit/Receive Control B - 0 - 0 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC33 - CTSU Channel Transmit/Receive Control B - 1 - 1 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC34 - CTSU Channel Transmit/Receive Control B - 2 - 2 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - CHTRC35 - CTSU Channel Transmit/Receive Control B - 3 - 3 - read-write - - - 0 - Reception - #0 - - - 1 - Transmission - #1 - - - - - - - CTSUCHTRCBL - CTSU Channel Transmit/Receive Control Register B - CTSUCHTRCB - 0x18 - 16 - read-write - 0x0000 - 0xffff - - - CTSUCHTRC4 - CTSU Channel Transmit/Receive Control Register B - CTSUCHTRCB - 0x18 - 8 - read-write - 0x00 - 0xff - - - CTSUSR - CTSU Status Register - 0x1C - 32 - read-write - 0x00000000 - 0xffffffff - - - MFC - CTSU Multi-clock Counter - 0 - 1 - read-write - - - 00 - Multi-clock 0 - #00 - - - 01 - Multi-clock 1 - #01 - - - 10 - Multi-clock 2 - #10 - - - 11 - Multi-clock 3 - #11 - - - - - ICOMPRST - CTSU CTSUICOMP1 Flag Reset - 5 - 5 - write-only - - - ICOMP1 - CTSU Sense Current Error Monitor - 6 - 6 - read-only - - - 0 - Normal sensor current - #0 - - - 1 - Abnormal sensor current - #1 - - - - - ICOMP0 - TSCAP Voltage Error Monitor - 7 - 7 - read-only - - - 0 - Normal TSCAP voltage - #0 - - - 1 - Abnormal TSCAP voltage - #1 - - - - - STC - CTSU Measurement Status Counter - 8 - 10 - read-only - - - 000 - Status 0 - #000 - - - 001 - Status 1 - #001 - - - 010 - Status 2 - #010 - - - 011 - Status 3 - #011 - - - 100 - Status 4 - #100 - - - 101 - Status 5 - #101 - - - - - DTSR - CTSU Data Transfer Status Flag - 12 - 12 - read-only - - - 0 - Read - #0 - - - 1 - Not read - #1 - - - - - SENSOVF - CTSU Sensor Counter Overflow Flag - 13 - 13 - read-write - - - 0 - No overflow occurred - #0 - - - 1 - Overflow occurred - #1 - - - - - PS - CTSU Mutual Capacitance Status Flag - 15 - 15 - read-only - - - 0 - First measurement - #0 - - - 1 - Second measurement - #1 - - - - - CFCRDCH - CTSU CFC Read Channel Select - 16 - 21 - read-write - - - 0x00 - TS00 - 0x00 - - - 0x02 - TS02 (CFC) - 0x02 - - - 0x04 - TS04 - 0x04 - - - 0x05 - TS05 - 0x05 - - - 0x06 - TS06 - 0x06 - - - 0x07 - TS07 - 0x07 - - - 0x08 - TS08 (CFC) - 0x08 - - - 0x09 - TS09 (CFC) - 0x09 - - - 0x0A - TS10 (CFC) - 0x0a - - - 0x0B - TS11 (CFC) - 0x0b - - - 0x0C - TS12 (CFC) - 0x0c - - - 0x0D - TS13 (CFC) - 0x0d - - - 0x0E - TS14 (CFC) - 0x0e - - - 0x0F - TS15 (CFC) - 0x0f - - - 0x10 - TS16 (CFC) - 0x10 - - - 0x11 - TS17 - 0x11 - - - 0x12 - TS18 - 0x12 - - - 0x15 - TS21 - 0x15 - - - 0x16 - TS22 - 0x16 - - - 0x17 - TS23 - 0x17 - - - 0x18 - TS24 - 0x18 - - - 0x19 - TS25 - 0x19 - - - 0x1A - TS26 (CFC) - 0x1a - - - 0x1B - TS27 (CFC) - 0x1b - - - 0x1C - TS28 (CFC) - 0x1c - - - 0x1D - TS29 (CFC) - 0x1d - - - 0x1E - TS30 (CFC) - 0x1e - - - 0x1F - TS31 (CFC) - 0x1f - - - 0x20 - TS32 (CFC) - 0x20 - - - 0x21 - TS33 (CFC) - 0x21 - - - 0x22 - TS34 (CFC) - 0x22 - - - 0x23 - TS35 (CFC) - 0x23 - - - - - - - CTSUSRL - CTSU Status Register - CTSUSR - 0x1C - 16 - read-write - 0x0000 - 0xffff - - - CTSUSR0 - CTSU Status Register - CTSUSR - 0x1C - 8 - read-write - 0x00 - 0xff - - - CTSUST - CTSU Status Register - CTSUSR - 0x1D - 8 - read-write - 0x00 - 0xff - - - CTSUSRH - CTSU Status Register - CTSUSR - 0x1E - 16 - read-write - 0x0000 - 0xffff - - - CTSUSR2 - CTSU Status Register - CTSUSRH - 0x1E - 8 - read-write - 0x00 - 0xff - - - CTSUSO - CTSU Sensor Offset Register - 0x20 - 32 - read-write - 0x00000000 - 0xffffffff - - - SO - CTSU Sensor Offset Adjustment - 0 - 9 - read-write - - - SNUM - CTSU Measurement Count Setting - 10 - 17 - read-write - - - SSDIV - CTSU Spectrum Diffusion Frequency Division Setting - 20 - 23 - read-write - - - SDPA - CTSU Base Clock Setting - 24 - 31 - read-write - - - - - CTSUSO0 - CTSU Sensor Offset Register - CTSUSO - 0x20 - 16 - read-write - 0x0000 - 0xffff - - - CTSUSO1 - CTSU Sensor Offset Register - CTSUSO - 0x22 - 16 - read-write - 0x0000 - 0xffff - - - CTSUSCNT - CTSU Sensor Counter Register - 0x24 - 32 - read-only - 0x00000000 - 0xffffffff - - - SENSCNT - CTSU Sensor Counter - 0 - 15 - read-only - - - - - CTSUSC - CTSU Sensor Counter Register - CTSUSCNT - 0x24 - 16 - read-only - 0x0000 - 0xffff - - - CTSUCALIB - CTSU Calibration Register - 0x28 - 32 - read-write - 0x00000000 - 0xffffffff - - - TSOD - CTSU TS Pins Fixed Output Select - 2 - 2 - read-write - - - 0 - Electrostatic capacitance measurement mode - #0 - - - 1 - TS pins fix output (High output/Low output). - #1 - - - - - DRV - CTSU Calibration Setting Bit 1 - 3 - 3 - read-write - - - 0 - Electrostatic capacitance measurement mode - #0 - - - 1 - Calibration setting 1 - #1 - - - - - SUCLKEN - CTSU SUCLK Enable Control - 6 - 6 - read-write - - - 0 - SUCLK operation is disabled. - #0 - - - 1 - SUCLK operation is enabled. - #1 - - - - - TSOC - CTSU Calibration Setting Bit 2 - 7 - 7 - read-write - - - 0 - Electrostatic capacitance measurement mode - #0 - - - 1 - Calibration setting 2 - #1 - - - - - IOC - CTSU Transfer Pins Control - 9 - 9 - read-write - - - 0 - Low level - #0 - - - 1 - High level - #1 - - - - - CFCRDMD - CTSU CFC Counter Read Mode Select - 10 - 10 - read-write - - - 0 - Read by DTC - #0 - - - 1 - Read by CPU - #1 - - - - - DCOFF - CTSU Down Converter Control - 11 - 11 - read-write - - - 0 - Normal operation mode - #0 - - - 1 - The down converter is off. - #1 - - - - - CFCMODE - CTSU CFC Current Source Switching - 22 - 22 - read-write - - - 0 - CFC current measurement (normal mode) - #0 - - - 1 - External current measurement for calibration - #1 - - - - - DACCARRY - CTSU DAC Upper Current Source Carry Control - 25 - 25 - read-write - - - 0 - Do not carry - #0 - - - 1 - Carry - #1 - - - - - SUCARRY - CTSU CCO Carry Control - 27 - 27 - read-write - - - 0 - Do not carry - #0 - - - 1 - Carry - #1 - - - - - DACCLK - CTSU DAC Modulation Circuit Clock Select - 28 - 28 - read-write - - - 0 - Divided PCLK specified by CTSUCRA.CLK[1:0] bits - #0 - - - 1 - SUCLK - #1 - - - - - CCOCLK - CTSU CCO Modulation Circuit Clock Select - 29 - 29 - read-write - - - 0 - Divided PCLK specified by CTSUCRA.CLK[1:0] bits - #0 - - - 1 - SUCLK - #1 - - - - - CCOCALIB - CTSU CCO Calibration Mode Select - 30 - 30 - read-write - - - 0 - Normal mode - #0 - - - 1 - Oscillator calibration mode - #1 - - - - - - - CTSUDBGR0 - CTSU Calibration Register - CTSUCALIB - 0x28 - 16 - read-write - 0x0000 - 0xffff - - - CTSUDBGR1 - CTSU Calibration Register - CTSUCALIB - 0x2A - 16 - read-write - 0x0000 - 0xffff - - - CTSUSUCLKA - CTSU Sensor Unit Clock Control Register A - 0x2C - 32 - read-write - 0x00000000 - 0xffffffff - - - CTSUSUCLK0 - CTSU Sensor Unit Clock Control Register A - CTSUSUCLKA - 0x2C - 16 - read-write - 0x0000 - 0xffff - - - CTSUSUCLK1 - CTSU Sensor Unit Clock Control Register A - CTSUSUCLKA - 0x2E - 16 - read-write - 0x0000 - 0xffff - - - CTSUSUCLKB - CTSU Sensor Unit Clock Control Register B - 0x30 - 32 - read-write - 0x00000000 - 0xffffffff - - - SUADJ2 - CTSU SUCLK Frequency Adjustment - 0 - 7 - read-write - - - SUMULTI2 - CTSU SUCLK Multiplier Rate Setting - 8 - 15 - read-write - - - SUADJ3 - CTSU SUCLK Frequency Adjustment - 16 - 23 - read-write - - - SUMULTI3 - CTSU SUCLK Multiplier Rate Setting - 24 - 31 - read-write - - - - - CTSUSUCLK2 - CTSU Sensor Unit Clock Control Register B - CTSUSUCLKB - 0x30 - 16 - read-write - 0x0000 - 0xffff - - - CTSUSUCLK3 - CTSU Sensor Unit Clock Control Register B - CTSUSUCLKB - 0x32 - 16 - read-write - 0x0000 - 0xffff - - - CTSUCFCCNT - CTSU CFC Counter Register - 0x34 - 32 - read-only - 0x00000000 - 0xffffffff - - - CFCCNT - CTSU CFC Counter - 0 - 15 - read-only - - - - - CTSUCFCCNTL - CTSU CFC Counter Register - CTSUCFCCNT - 0x34 - 16 - read-only - 0x0000 - 0xffff - - - - - R_DAC - D/A Converter - 0x4005E000 - - 0x00000000 - 0x00A - registers - - - - DACR - D/A Control Register - 0x04 - 8 - read-write - 0x1F - 0xFF - - - DAE - D/A Enable - 5 - 5 - read-write - - - 0 - Control D/A conversion of channels 0 and 1 individually - #0 - - - - - 2 - 1 - DAOE%s - D/A Output Enable 0 - 6 - 6 - read-write - - - 0 - Analog output of channel 0 (DA0) is disabled. - #0 - - - 1 - D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. - #1 - - - - - - - 2 - 2 - DADR[%s] - D/A Data Register - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - - DADR - D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format. - 0 - 15 - read-write - - - - - DADPR - DADR0 Format Select Register - 0x05 - 8 - read-write - 0x00 - 0xFF - - - DPSEL - DADRm Format Select - 7 - 7 - read-write - - - 0 - Right justified format. - #0 - - - 1 - Left justified format. - #1 - - - - - - - DAADSCR - D/A-A/D Synchronous Start Control Register - 0x06 - 8 - read-write - 0x00 - 0xFF - - - DAADST - D/A-A/D Synchronous Conversion - 7 - 7 - read-write - - - 0 - D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled). - #0 - - - 1 - D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled). - #1 - - - - - - - DAVREFCR - D/A VREF Control Register - 0x07 - 8 - read-write - 0x00 - 0xFF - - - REF - D/A Reference Voltage Select - 0 - 2 - read-write - - - 000 - Not selected - #000 - - - 001 - AVCC0/AVSS0 - #001 - - - 011 - Internal reference voltage/AVSS0 - #011 - - - 110 - VREFH/VREFL - #110 - - - others - Setting prohibited - true - - - - - - - DAPC - D/A Switch Charge Pump Control Register - 0x09 - 8 - read-write - 0x00 - 0xFF - - - PUMPEN - Charge Pump Enable - 0 - 0 - read-write - - - 0 - Charge pump disabled - #0 - - - 1 - Charge pump enabled - #1 - - - - - - - DAAMPCR - D/A Output Amplifier Control Register - 0x08 - 8 - read-write - 0x1F - 0xFF - - - 2 - 1 - DAAMP%s - Amplifier Control - 6 - 6 - read-write - - - 0 - Do not use channel output amplifier - #0 - - - - - - - DAASWCR - D/A Amplifier Stabilization Wait Control Register - 0x1C - 8 - read-write - 0x00 - 0xFF - - - DAASW1 - Set the DAASW1 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 1. When DAASW1 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 1. When the DAASW1 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 1 is output through the output amplifier. - 7 - 7 - read-write - - - 0 - Amplifier stabilization wait off (output) for channel 1 - #0 - - - 1 - Amplifier stabilization wait on (high-Z) for channel 1 - #1 - - - - - DAASW0 - Set the DAASW0 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 0. When DAASW0 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 0. When the DAASW0 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 0 is output through the output amplifier. - 6 - 6 - read-write - - - 0 - Amplifier stabilization wait off (output) for channel 0 - #0 - - - 1 - Amplifier stabilization wait on (high-Z) for channel 0 - #1 - - - - - - - DAADUSR - D/A A/D Synchronous Unit Select Register - 0x10C0 - 8 - read-write - 0x00 - 0xFF - - - AMADSEL1 - The DAADUSR register selects the target ADC12 unit for D/A and A/D synchronous conversions. Set bit [1] to 1 to select unit 1 as the target synchronous unit for the MCU. When setting the DAADSCR.DAADST bit to 1 for synchronous conversions, select the target unit in this register in advance. Only set the DAADUSR register while the ADCSR.ADST bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit is set to 0. - 6 - 6 - read-write - - - 0 - Do not select unit 1 - #0 - - - 1 - Select unit 1 - #1 - - - - - - - - - R_DAC8 - 8-Bit D/A Converter - 0x4009E000 - - 0x00000000 - 0x002 - registers - - - 0x00000003 - 0x01 - registers - - - 0x00000006 - 0x002 - registers - - - - DAM - D/A Converter Mode Register - 0x03 - 8 - read-write - 0x00 - 0xFF - - - DACE1 - D/A operation enable 1 - 5 - 5 - read-write - - - 0 - D/A conversion disabled for channel 1 - #0 - - - 1 - D/A conversion enabled for channel 1 - #1 - - - - - DACE0 - D/A operation enable 0 - 4 - 4 - read-write - - - 0 - D/A conversion disabled for channel 0 - #0 - - - 1 - D/A conversion enabled for channel 0 - #1 - - - - - DAMD1 - D/A operation mode select 1 - 1 - 1 - read-write - - - 0 - Channel 1 for normal operation mode - #0 - - - 1 - Channel 1 for real-time output mode(event link) - #1 - - - - - DAMD0 - D/A operation mode select 0 - 0 - 0 - read-write - - - 0 - Channel 0 for normal operation mode - #0 - - - 1 - Channel 0 for real-time output mode(event link) - #1 - - - - - - - 2 - 0x01 - DACS[%s] - D/A Conversion Value Setting Register %s - 0x00 - 8 - read-write - 0x00 - 0xFF - - - DACS - DACS D/A conversion store data - 0 - 7 - read-write - - - - - DACADSCR - D/A A/D Synchronous Start Control Register - 0x06 - 8 - read-write - 0x00 - 0xFF - - - DACADST - D/A A/D Synchronous Conversion - 0 - 0 - read-write - - - 0 - Do not synchronize DAC8 with ADC16 operation (disable interference reduction between D/A and A/D conversion) - #0 - - - 1 - Synchronize DAC8 with ADC16 operation (enable interference reduction between D/A and A/D conversion). - #1 - - - - - - - DACPC - D/A SW Charge Pump Control Register - 0x07 - 8 - read-write - 0x00 - 0xFF - - - PUMPEN - Charge pump enable - 0 - 0 - read-write - - - 0 - Charge pump disable - #0 - - - 1 - Charge pump enable - #1 - - - - - - - - - R_DALI0 - Digital Addressable Lighting Interface - 0x4008F000 - - 0x00000000 - 0x018 - registers - - - 0x0000001E - 0x006 - registers - - - 0x00000026 - 0x004 - registers - - - 0x0000002E - 0x006 - registers - - - 0x00000036 - 0x02 - registers - - - 0x0000003A - 0x004 - registers - - - - BTVTHR1 - DALI Bit Timing Violation Threshold Register 1 - 0x000 - 16 - read-write - 0x4F00 - 0xFFFF - - - BTV2 - Bit Timing Violation Threshold 2Specifies the bit timing violation threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 8 - 15 - read-write - - - BTV1 - Bit Timing Violation Threshold 1Specifies the bit timing violation threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 6 - read-write - - - - - BTVTHR2 - DALI Bit Timing Violation Threshold Register 2 - 0x002 - 16 - read-write - 0x654F - 0xFFFF - - - BTV4 - Bit Timing Violation Threshold 4Specifies the bit timing violation threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 8 - 15 - read-write - - - BTV3 - Bit Timing Violation Threshold 3Specifies the bit timing violation threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 7 - read-write - - - - - BTVTHR3 - DALI Bit Timing Violation Threshold Register 3 - 0x004 - 16 - read-write - 0x009D - 0xFFFF - - - BTV5 - Bit Timing Violation Threshold 5Specifies the bit timing violation threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 7 - read-write - - - - - BTVTHR4 - DALI Bit Timing Violation Threshold Register 4 - 0x006 - 16 - read-write - 0x00DB - 0xFFFF - - - BTV6 - Bit Timing Violation Threshold 6Specifies the bit timing violation threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 8 - read-write - - - - - COLTHR1 - DALI Collision Threshold Register 1 - 0x008 - 16 - read-write - 0x380F - 0xFFFF - - - COL2 - Collision Threshold 2Specifies the collision threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 8 - 13 - read-write - - - COL1 - Collision Threshold 1Specifies the collision threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 5 - read-write - - - - - COLTHR2 - DALI Collision Threshold Register 2 - 0x00A - 16 - read-write - 0x443C - 0xFFFF - - - COL4 - Collision Threshold 4Specifies the collision threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 8 - 14 - read-write - - - COL3 - Collision Threshold 3Specifies the collision threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 6 - read-write - - - - - COLTHR3 - DALI Collision Threshold Register 3 - 0x00C - 16 - read-write - 0x7148 - 0xFFFF - - - COL6 - Collision Threshold 6Specifies the collision threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 8 - 14 - read-write - - - COL5 - Collision Threshold 5Specifies the collision threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 6 - read-write - - - - - COLTHR4 - DALI Collision Threshold Register 4 - 0x00E - 16 - read-write - 0x8879 - 0xFFFF - - - COL8 - Collision Threshold 8Specifies the collision threshold value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 8 - 15 - read-write - - - COL7 - Collision Threshold 7Specifies the collision threshold value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 7 - read-write - - - - - COLTHR5 - DALI Collision Threshold Register 5 - 0x010 - 16 - read-write - 0x008E - 0xFFFF - - - COL9 - Collision Threshold 9Specifies the collision threshold value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. - 0 - 7 - read-write - - - - - CNFR1 - DALI Configuration Register 1 - 0x012 - 16 - read-write - 0x00FF - 0xFFFF - - - CHL - Character Length - 12 - 14 - read-write - - - 000 - 8 bits - #000 - - - 001 - 16 bits - #001 - - - 010 - 24 bits - #010 - - - 011 - 32 bits - #011 - - - 100 - 20 bits - #100 - - - 101 - 17 bits - #101 - - - others - Setting prohibited - true - - - - - CKS - Clock Select - 8 - 9 - read-write - - - 00 - PCLK clock (x = 0) - #00 - - - 01 - PCLK/4 clock (x = 1) - #01 - - - 10 - PCLK/16 clock (x = 2) - #10 - - - 11 - PCLK/64 clock (x = 3) - #11 - - - - - BR - Clock SelectBit rate setting example is shown in Table - 0 - 7 - read-write - - - - - CNFR2 - DALI Configuration Register 2 - 0x014 - 16 - read-write - 0x0000 - 0xFFFF - - - CDM0 - Collision Detect ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. - 5 - 5 - read-write - - - 0 - Destroy area - #0 - - - 1 - Destroy area and avoidance area (edge) - #1 - - - - - CDE - Collision Detect EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. - 4 - 4 - read-write - - - 0 - Collision detection is disabled. - #0 - - - 1 - Collision detection is enabled. - #1 - - - - - TXWE - DTX Width Modulation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. - 3 - 3 - read-write - - - 0 - The width of DTX0 waveform is not modulated. - #0 - - - 1 - The width of DTX0 waveform is modulated. - #1 - - - - - SGA - Save an Edge of Gray Area ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. - 2 - 2 - read-write - - - 0 - The edge allowable area of the DRX0 input signal is the default. - #0 - - - 1 - The edge allowable area of the DRX0 input signal is extended. - #1 - - - - - BTVM - Bit Timing Violation ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. - 1 - 1 - read-write - - - 0 - Edge in gray area between half bit and 2-half bit is not detected as bit timing violation. - #0 - - - 1 - Edge in gray area between half bit and 2-half bit is detected as bit timing violation. - #1 - - - - - BTVE - Bit Timing Violation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. - 0 - 0 - read-write - - - 0 - Bit timing violation function is disabled. - #0 - - - 1 - Bit timing violation function is enabled. - #1 - - - - - - - TXWR1 - DALI DTX Width Register 1 - 0x016 - 16 - read-write - 0x003F - 0xFFFF - - - TXLW - DTX Low WidthDTX0 pin low level width - 0 - 6 - read-write - - - - - TDR1H - DALI Transmit Data Register 1H - 0x01E - 16 - read-write - 0x0000 - 0xFFFF - - - DTDR - Upper 16-bit DALI transmit data - 0 - 15 - read-write - - - - - TDR1L - DALI Transmit Data Register 1L - 0x020 - 16 - read-write - 0x0000 - 0xFFFF - - - DTDR - Lower 16-bit DALI transmit data - 0 - 15 - read-write - - - - - TRSTR1 - DALI Transmit Control Register 1 - SPDR - 0x022 - 16 - write-only - 0x0000 - 0xFFFF - - - TRST - Transmission Start Trigger - 0 - 0 - write-only - - - 0 - No effect - #0 - - - 1 - Transmission Start - #1 - - - - - - - CTR1 - DALI Control Register 1 - 0x026 - 16 - read-write - 0x0000 - 0xFFFF - - - FEIE - DALI_FEI Output Enabling - 12 - 12 - read-write - - - 0 - DALI_FEI output is disabled. - #0 - - - 1 - DALI_FEI output is enabled. - #1 - - - - - BPIE - DALI_BPI Output Enabling - 11 - 11 - read-write - - - 0 - DALI_BPI output is disabled. - #0 - - - 1 - DALI_BPI output is enabled. - #1 - - - - - CLIE - DALI_CLI Output Enabling - 10 - 10 - read-write - - - 0 - DALI_CLI output is disabled. - #0 - - - 1 - DALI_CLI output is enabled. - #1 - - - - - DEIE - DALI_DEI Output Enabling - 9 - 9 - read-write - - - 0 - DALI_DEI output is disabled. - #0 - - - 1 - DALI_DEI output is enabled. - #1 - - - - - SDIE - DALI_SDI Output Enabling - 8 - 8 - read-write - - - 0 - DALI_SDI output is disabled. - #0 - - - 1 - DALI_SDI output is enabled. - #1 - - - - - RE - Receive Enabling - 1 - 1 - read-write - - - 0 - Storing received data is disabled. - #0 - - - 1 - Storing received data is enabled. - #1 - - - - - TE - Transmit Enabling - 0 - 0 - read-write - - - 0 - Transmit operation is disabled. - #0 - - - 1 - Transmit operation is enabled. - #1 - - - - - - - TXDCTR1 - DALI DTX Control Register 1 - 0x028 - 16 - read-write - 0x0000 - 0xFFFF - - - TXASE - DTX Assert EnablingNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0. - 1 - 1 - read-write - - - 0 - An internal transmit data is output to the DTX0 pin. - #0 - - - 1 - The level specified by TXAS bit is output to the DTX0 pin. - #1 - - - - - TXAS - DTX Assert LevelNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0. - 0 - 0 - read-write - - - 0 - The DTX0 pin is driven low. - #0 - - - 1 - The DTX0 pin is driven high. - #1 - - - - - - - RDR1H - DALI Reception Data Register 1H - 0x02E - 16 - read-only - 0x0000 - 0xFFFF - - - DRDR - Upper 16-bit of DALI receive data - 0 - 15 - read-only - - - - - RDR1L - DALI Reception Data Register 1L - 0x030 - 16 - read-only - 0x0000 - 0xFFFF - - - DRDR - Lower 16-bit of DALI receive data - 0 - 15 - read-only - - - - - STR1 - DALI Status Register 1 - 0x032 - 16 - read-only - 0x0000 - 0xFFFF - - - RDBL - Receive Data Bit LengthThese bits store the bit length for data received successfully - 10 - 15 - read-only - - - DAF - Destroy Area Flag - 9 - 9 - read-only - - - 0 - The collision did not occur in the destroy area or 1 was written to the DALI0.FECR1.DAFC bit. - #0 - - - 1 - The collision occurred in the destroy area. - #1 - - - - - CDF - Collision Detect Flag - 8 - 8 - read-only - - - 0 - No collision occurred or 1 was written to the DALI0.FECR1.CDFC bit. - #0 - - - 1 - A collision occurred. - #1 - - - - - O32F - Over 32-Bit Data Reception Flag - 7 - 7 - read-only - - - 0 - Receive data is 32 bits or less, or 1 was written to the DALI0.FECR1.O32FC bit. - #0 - - - 1 - Receive data is 33 bits or more. - #1 - - - - - BPDF - Bus Power Down Flag - 6 - 6 - read-only - - - 0 - No effected - #0 - - - 1 - Bus power down detected - #1 - - - - - BBF - Bus BUSY Flag - 5 - 5 - read-only - - - 0 - DALI bus is IDLE - #0 - - - 1 - DALI bus is BUSY - #1 - - - - - TENDF - Transmit End Flag - 4 - 4 - read-only - - - 0 - 1 was written to the DALI0.FECR1.TENDFC bit. - #0 - - - 1 - Frame transmission has been completed. - #1 - - - - - RDRF - Receive Data Register Full Flag - 3 - 3 - read-only - - - 0 - The DALI0.RDR1L register was read or 1 was written to the DALI0.FECR1.RDRFC. - #0 - - - 1 - Receive data is stored in the DALI0.RDR1L or DALI0.RDR1H register. - #1 - - - - - BTVF - Bit Timing Violation Flag - 2 - 2 - read-only - - - 0 - No bit timing violation occurred or 1 was written to the DALI0.FECR1.BTVFC bit. - #0 - - - 1 - Bit timing violation occurred - #1 - - - - - OVF - Overrun Error Flag - 1 - 1 - read-only - - - 0 - No overrun error occurred or 1 was written to the DALI0.FECR1.OVFC bit. - #0 - - - 1 - An overrun error occurred. - #1 - - - - - MFEF - Manchester Flaming Error Flag - 0 - 0 - read-only - - - 0 - No MFE occurred or 1 was written to the DALI0.FECR1.MFEFC bit. - #0 - - - 1 - An MFE occurred. - #1 - - - - - - - COLR1 - DALI Collision Register 1 - 0x036 - 16 - read-only - 0x0800 - 0xFFFF - - - TXDCV - DTX Collision Value - 13 - 13 - read-only - - - 0 - Low - #0 - - - 1 - High - #1 - - - - - RXDCEG - DRX Collision Edge - 12 - 12 - read-only - - - 0 - Falling edge - #0 - - - 1 - Rising edge - #1 - - - - - RXDMON - DRX MonitorThis bit monitors the DRX0 pin value after the DRX0 pin is synchronized - 11 - 11 - read-only - - - CLDAF - Collision Last Destroy Area Flag - 10 - 10 - read-only - - - 0 - Collision detected is caused by a DRX0 edge occurrence. - #0 - - - 1 - Collision detected is not caused by a DRX0 edge occurrence. (Last destroy area) - #1 - - - - - CDTF1 - Collision Detect Timing Flag 1 - 4 - 4 - read-only - - - 0 - Collision detection started at the edge on a bit period boundary. - #0 - - - 1 - Collision detection started at the edge in the middle of a bit period. - #1 - - - - - CFTF2 - Collision Detect Timing Flag 2 - 0 - 3 - read-only - - - 0000 - After reset is released - #0000 - - - 0001 - Collision detection timing 1 - #0001 - - - 0010 - Collision detection timing 2 - #0010 - - - 0011 - Collision detection timing 3 - #0011 - - - 0100 - Collision detection timing 4 - #0100 - - - 0101 - Collision detection timing 5 - #0101 - - - 0110 - Collision detection timing 6 - #0110 - - - 0111 - Collision detection timing 7 *1 - #0111 - - - 1000 - Collision detection timing 8 *1 - #1000 - - - 1001 - Collision detection timing 9 *1 - #1001 - - - 1010 - Collision detection timing 10 *1 - #1010 - - - others - Setting prohibited - true - - - - - - - FECR1 - DALI Flag Error Clear Register 1 - 0x03A - 16 - write-only - 0x0000 - 0xFFFF - - - DAFC - Destroy Area Flag Clear - 9 - 9 - write-only - - - 0 - DALI0.STR1.DAF bit is not cleared. - #0 - - - 1 - DALI0.STR1.DAF bit is cleared. - #1 - - - - - CDFC - Collision Detect Flag Clear - 8 - 8 - write-only - - - 0 - DALI0.STR1.CDF bit is not cleared. - #0 - - - 1 - DALI0.STR1.CDF bit is cleared. - #1 - - - - - O32FC - Over 32-Bit Data Reception Flag Clear - 7 - 7 - write-only - - - 0 - DALI0.STR1.O32F bit is not cleared. - #0 - - - 1 - DALI0.STR1.O32F bit is cleared - #1 - - - - - BPDFC - Bus Power Down Flag Clear - 6 - 6 - write-only - - - 0 - DALI0.STR1.BPDF bit is not cleared. - #0 - - - 1 - DALI0.STR1.BPDF bit is cleared. - #1 - - - - - BBFC - Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. - 5 - 5 - write-only - - - 0 - DALI0.STR1.BBF bit is not cleared. - #0 - - - 1 - DALI0.STR1.BBF bit is cleared - #1 - - - - - TENDFC - Transmit End Flag Clear - 4 - 4 - write-only - - - 0 - DALI0.STR1.TENDF bit is not cleared. - #0 - - - 1 - DALI0.STR1.TENDF bit is cleared - #1 - - - - - RDRFC - Receive Data Register Full Flag Clear - 3 - 3 - write-only - - - 0 - DALI0.STR1.RDRF bit is not cleared. - #0 - - - 1 - DALI0.STR1.RDRF bit is cleared. - #1 - - - - - BTVFC - Bit Timing Violation Flag Clear - 2 - 2 - write-only - - - 0 - DALI0.STR1.BTVF bit is not cleared. - #0 - - - 1 - DALI0.STR1.BTVF bit is cleared. - #1 - - - - - OVFC - Overrun Error Flag Clear - 1 - 1 - write-only - - - 0 - DALI0.STR1.OVF bit is not cleared. - #0 - - - 1 - DALI0.STR1.OVF bit is cleared - #1 - - - - - MFEFC - Manchester Flaming Error Flag Clear - 0 - 0 - write-only - - - 0 - DALI0.STR1.MFEF bit is not cleared. - #0 - - - 1 - DALI0.STR1.MFEF bit is cleared - #1 - - - - - - - SWRR1 - DALI Software Reset Register 1 - 0x03C - 16 - write-only - 0x0000 - 0xFFFF - - - SWR - Software ResetWriting 1 to this bit causes a software reset. - 0 - 0 - write-only - - - - - - - R_DEBUG - Debug Function - 0x4001B000 - - 0x00000000 - 0x04 - registers - - - 0x00000010 - 0x04 - registers - - - - DBGSTR - Debug Status Register - 0 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - CDBGPWRUPREQ - Debug power-up request - 28 - 28 - read-only - - - 0 - 0: OCD is not requesting debug power up - #0 - - - 1 - 0: OCD is requesting debug power up - #1 - - - - - CDBGPWRUPACK - Debug power-up acknowledge - 29 - 29 - - - 0 - Debug power-up request is not acknowledged - #0 - - - 1 - Debug power-up request is acknowledged - #1 - - - - - - - DBGSTOPCR - Debug Stop Control Register - 0x10 - 32 - read-write - 0x00000003 - 0xFFFFFFFF - - - DBGSTOP_RPER - Mask bit for SRAM parity error - 24 - 24 - - - 3 - 1 - DBGSTOP_LVD%s - Mask bit for LVD reset/interupt - 16 - 16 - read-write - - - 0 - Enable reset/interupt on corresponding LVD - #0 - - - 1 - Mask reset/interupt on corresponding LVD - #1 - - - - - DBGSTOP_RECCR - Mask bit for SRAM ECC error - 25 - 25 - - - DBGSTOP_IWDT - Mask bit for IWDT reset/interrupt - 0 - 0 - - - DBGSTOP_WDT - Mask bit for WDT reset/interrupt - 1 - 1 - - - - - - - R_DMA - DMA Controller Common - 0x40005200 - - 0x00000000 - 0x01 - registers - - - - DMAST - DMAC Module Activation Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - - DMST - DMAC Operation Enable - 0 - 0 - read-write - - - 0 - Disabled. - #0 - - - 1 - Enabled. - #1 - - - - - - - - - R_DMAC0 - DMA Controller - 0x40005000 - - 0x00000000 - 0x00E - registers - - - 0x00000010 - 0x02 - registers - - - 0x00000013 - 0x003 - registers - - - 0x00000018 - 0x007 - registers - - - - DMSAR - DMA Source Address Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DMSAR - Specifies the transfer source start address. - 0 - 31 - read-write - - - - - DMDAR - DMA Destination Address Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DMDAR - Specifies the transfer destination start address. - 0 - 31 - read-write - - - - - DMCRA - DMA Transfer Count Register - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DMCRAH - Upper bits of transfer count - 16 - 25 - read-write - - - DMCRAL - Lower bits of transfer count - 0 - 15 - read-write - - - - - DMCRB - DMA Block Transfer Count Register - 0x0C - 16 - read-write - 0x0000 - 0xFFFF - - - DMCRB - Specifies the number of block transfer operations or repeat transfer operations. - 0 - 15 - read-write - - - 0000 - 65,536 blocks - #0000 - - - others - DMCRB blocks - true - - - - - - - DMTMD - DMA Transfer Mode Register - 0x10 - 16 - read-write - 0x0000 - 0xFFFF - - - MD - Transfer Mode Select - 14 - 15 - read-write - - - 00 - Normal transfer - #00 - - - 01 - Repeat transfer - #01 - - - 10 - Block transfer - #10 - - - 11 - Setting prohibited - #11 - - - - - DTS - Repeat Area Select - 12 - 13 - read-write - - - 00 - The destination is specified as the repeat area or block area. - #00 - - - 01 - The source is specified as the repeat area or block area. - #01 - - - 10 - The repeat area or block area is not specified. - #10 - - - 11 - Setting prohibited - #11 - - - - - SZ - Transfer Data Size Select - 8 - 9 - read-write - - - 00 - 8 bits - #00 - - - 01 - 16 bits - #01 - - - 10 - 32 bits - #10 - - - 11 - Setting prohibited - #11 - - - - - DCTG - Transfer Request Source Select - 0 - 1 - read-write - - - 00 - Software - #00 - - - 01 - Interrupts*1 from peripheral modules or external interrupt input pins - #01 - - - 10 - Setting prohibited - #10 - - - 11 - Setting prohibited - #11 - - - - - - - DMINT - DMA Interrupt Setting Register - 0x13 - 8 - read-write - 0x00 - 0xFF - - - DTIE - Transfer End Interrupt Enable - 4 - 4 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - ESIE - Transfer Escape End Interrupt Enable - 3 - 3 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - RPTIE - Repeat Size End Interrupt Enable - 2 - 2 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - SARIE - Source Address Extended Repeat Area Overflow Interrupt Enable - 1 - 1 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - DARIE - Destination Address Extended Repeat Area Overflow Interrupt Enable - 0 - 0 - read-write - - - 0 - Disabled - #0 - - - 1 - Enabled - #1 - - - - - - - DMAMD - DMA Address Mode Register - 0x14 - 16 - read-write - 0x0000 - 0xFFFF - - - SM - Source Address Update Mode - 14 - 15 - read-write - - - 00 - Fixed address - #00 - - - 01 - Offset addition - #01 - - - 10 - Incremented address - #10 - - - 11 - Decremented address. - #11 - - - - - SARA - Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. - 8 - 12 - read-write - - - DM - Destination Address Update Mode - 6 - 7 - read-write - - - 00 - Fixed address - #00 - - - 01 - Offset addition - #01 - - - 10 - Incremented address - #10 - - - 11 - Decremented address. - #11 - - - - - DARA - Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. - 0 - 4 - read-write - - - - - DMOFR - DMA Offset Register - 0x18 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DMOFR - Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. - 0 - 31 - read-write - - - - - DMCNT - DMA Transfer Enable Register - 0x1C - 8 - read-write - 0x00 - 0xFF - - - DTE - DMA Transfer Enable - 0 - 0 - read-write - modify - - - 0 - Disabled - #0 - - - 1 - Enabled. - #1 - - - - - - - DMREQ - DMA Software Start Register - 0x1D - 8 - read-write - 0x00 - 0xFF - - - CLRS - DMA Software Start Bit Auto Clear Select - 4 - 4 - read-write - - - 0 - SWREQ bit is cleared after DMA transfer is started by software. - #0 - - - 1 - SWREQ bit is not cleared after DMA transfer is started by software. - #1 - - - - - SWREQ - DMA Software Start - 0 - 0 - read-write - modify - - - 0 - DMA transfer is not requested. - #0 - - - 1 - DMA transfer is requested. - #1 - - - - - - - DMSTS - DMA Status Register - 0x1E - 8 - read-write - 0x00 - 0xFF - - - ACT - DMA Active Flag - 7 - 7 - read-only - - - 0 - DMAC operation suspended - #0 - - - 1 - DMAC operating. - #1 - - - - - DTIF - Transfer End Interrupt Flag - 4 - 4 - read-write - zeroToClear - modify - - - 0 - No interrupt - #0 - - - 1 - Interrupt occurred. - #1 - - - - - ESIF - Transfer Escape End Interrupt Flag - 0 - 0 - read-write - zeroToClear - modify - - - 0 - No interrupt - #0 - - - 1 - Interrupt occurred. - #1 - - - - - - - - - R_DMAC1 - 0x40005040 - - - R_DMAC2 - 0x40005080 - - - R_DMAC3 - 0x400050C0 - - - R_DMAC4 - 0x40005100 - - - R_DMAC5 - 0x40005140 - - - R_DMAC6 - 0x40005180 - - - R_DMAC7 - 0x400051C0 - - - R_DOC - Data Operation Circuit - 0x40054100 - - 0x00000000 - 0x01 - registers - - - 0x00000002 - 0x004 - registers - - - - DOCR - DOC Control Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - - DOPCFCL - DOPCF Clear - 6 - 6 - read-write - - - 0 - Maintains the DOPCF flag state. - #0 - - - 1 - Clears the DOPCF flag. - #1 - - - - - DOPCF - Data Operation Circuit Flag - 5 - 5 - read-only - - - DCSEL - Detection Condition Select - 2 - 2 - read-write - - - 0 - DOPCF is set when data mismatch is detected. - #0 - - - 1 - DOPCF is set when data match is detected. - #1 - - - - - OMS - Operating Mode Select - 0 - 1 - read-write - - - 00 - Data comparison mode - #00 - - - 01 - Data addition mode - #01 - - - 10 - Data subtraction mode - #10 - - - 11 - Setting prohibited - #11 - - - - - - - DODIR - DOC Data Input Register - 0x02 - 16 - read-write - 0x0000 - 0xFFFF - - - DODIR - 16-bit read-write register in which 16-bit data for use in the operations are stored. - 0 - 15 - read-write - - - - - DODSR - DOC Data Setting Register - 0x04 - 16 - read-write - 0x0000 - 0xFFFF - - - DODSR - This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes. - 0 - 15 - read-write - - - - - - - R_DRW - 2D Drawing Engine - 0x400E4000 - - 0x00000000 - 0x008 - registers - - - 0x00000010 - 0x050 - registers - - - 0x00000064 - 0x008 - registers - - - 0x00000074 - 0x010 - registers - - - 0x00000090 - 0x020 - registers - - - 0x000000B4 - 0x024 - registers - - - 0x000000DC - 0x010 - registers - - - - CONTROL - Geometry Control Register - 0x00 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - SPANSTORE - Nextline span start is always equal or left to current-line span start - 23 - 23 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - SPANABORT - Shape is horizontally convex, only a single span per scanline - 22 - 22 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - UNIONCD - Combine outputs C & D as union (output is final) - 21 - 21 - write-only - - - 0 - minimum/intersect - #0 - - - 1 - maximum/union - #1 - - - - - UNIONAB - Combine outputs A & B as union (output is called C) - 20 - 20 - write-only - - - 0 - minimum/intersect - #0 - - - 1 - maximum/union - #1 - - - - - UNION56 - Combine limter 5 & 6 as union (output is called D) - 19 - 19 - write-only - - - 0 - minimum/intersect - #0 - - - 1 - maximum/union - #1 - - - - - UNION34 - Combine limter 3 & 4 as union (output is called B) - 18 - 18 - write-only - - - 0 - minimum/intersect - #0 - - - 1 - maximum/union - #1 - - - - - UNION12 - Combine limter 1 & 2 as union (output is called A) - 17 - 17 - write-only - - - 0 - minimum/intersect - #0 - - - 1 - maximum/union - #1 - - - - - BAND2ENABLE - Enable band postprocess for limiter 1 (see L1BAND) - 16 - 16 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - BAND1ENABLE - Enable band postprocess for limiter 1 (see L1BAND) - 15 - 15 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM6THRESHOLD - Enable limiter 6 threshold mode - 14 - 14 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM5THRESHOLD - Enable limiter 5 threshold mode - 13 - 13 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM4THRESHOLD - Enable limiter 4 threshold mode - 12 - 12 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM3THRESHOLD - Enable limiter 3 threshold mode - 11 - 11 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM2THRESHOLD - Enable limiter 2 threshold mode - 10 - 10 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM1THRESHOLD - Enable limiter 1 threshold mode - 9 - 9 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - QUAD3ENABLE - Enable quadratic coupling of limiters 5 and 6 - 8 - 8 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - QUAD2ENABLE - Enable quadratic coupling of limiters 3 and 4 - 7 - 7 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - QUAD1ENABLE - Enable quadratic coupling of limiters 1 and 2 - 6 - 6 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM6ENABLE - Enable limiter 6 - 5 - 5 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM5ENABLE - Enable limiter 5 - 4 - 4 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM4ENABLE - Enable limiter 4 - 3 - 3 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM3ENABLE - Enable limiter 3 - 2 - 2 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM2ENABLE - Enable limiter 2 - 1 - 1 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - LIM1ENABLE - Enable limiter 1 - 0 - 0 - write-only - - - 0 - disabled - #0 - - - 1 - enabled - #1 - - - - - - - CONTROL2 - Surface Control Register - 0x04 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - RLEPIXELWIDTH - Texel width for RLE unit - 30 - 31 - write-only - - - 00 - 1 byte per texel - #00 - - - 01 - 2 byte per texel - #01 - - - 10 - 3 byte per texel - #10 - - - 11 - 4 byte per texel - #11 - - - - - BDIA - Blend destination factor inverted in alpha channel (USEACB = 1) - 29 - 29 - write-only - - - 0 - use blend factor as specified through BDFA - #0 - - - 1 - invert blend destination factor (1-x) - #1 - - - - - BSIA - Blend source factor inverted in alpha channel (USEACB = 1) - 28 - 28 - write-only - - - 0 - use blend factor as specified through BSFA - #0 - - - 1 - invert blend source factor (1-x) - #1 - - - - - CLUTFORMAT - Format of the CLUT - 27 - 27 - write-only - - - 0 - aRGB(8888) - #0 - - - 1 - RGB(565) - #1 - - - - - COLKEYENABLE - color keying enable - 26 - 26 - write-only - - - 0 - color keying disabled - #0 - - - 1 - color keying enabled - #1 - - - - - CLUTENABLE - CLUT enable - 25 - 25 - write-only - - - 0 - CLUT disabled - #0 - - - 1 - CLUT enabled - #1 - - - - - RLEENABLE - RLE enable - 24 - 24 - write-only - - - 0 - RLE disabled - #0 - - - 1 - RLE enabled - #1 - - - - - WRITEALPHA - Writeback alpha source for framebufferSet the 'alpha source' for the framebuffer(USEACB = 0)Blend alpha in color 2 instead of framebuffer alpha((USEACB = 1))In not alpha channel blending mode (USEACB = 0):Set the 'alpha source' for the framebuffer.In alpha channel blending mode (USEACB = 1):Blend alpha in color 2 instead of framebuffer alpha00B: BC2A = 1: use alpha from framebuffer as destination (DST_A)else: BC2A = 0: use alpha in color 2 as destination (DST_A) - 22 - 23 - write-only - - - 00 - use alpha from color 2 - #00 - - - 01 - use source alpha (pixel coverage) - #01 - - - 10 - use 0.0 as alpha - #10 - - - 11 - use alpha from framebuffer - #11 - - - - - WRITEFORMAT10 - Pixel format of the framebuffer - 20 - 21 - write-only - - - 00 - 8bpp a(8)0 - #00 - - - 01 - 16bpp RGB(565) - #01 - - - 10 - 32bpp aRGB(8888) - #10 - - - 11 - 16bpp aRGB(4444) - #11 - - - - - READFORMAT10 - Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance - 18 - 19 - write-only - - - 00 - 8 bpp a(8) (READFORMAT32=00) / 16 bpp aRGB(1555) (READFORMAT32=01) / 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance (READFORMAT32=11) - #00 - - - 01 - 16 bpp RGB(565) (READFORMAT32=00) / 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color (READFORMAT32=01) / 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance (READFORMAT32=10) - #01 - - - 10 - 32 bpp aRGB(8888) (READFORMAT32=00) / 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance (READFORMAT32=10) - #10 - - - 11 - 16 bpp aRGB(4444) (READFORMAT32=00) / 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance (READFORMAT32=10) - #11 - - - - - TEXTUREFILTERY - Linear filtering on texture V axis - 17 - 17 - write-only - - - 0 - no filtering on texture V axis - #0 - - - 1 - linear filtering on texture V axis - #1 - - - - - TEXTUREFILTERX - Linear filtering on texture U axis - 16 - 16 - write-only - - - 0 - no filtering on texture U axis - #0 - - - 1 - linear filtering on texture U axis - #1 - - - - - TEXTURECLAMPY - Calculating V limiter outside use textureThe bit describes what happens if the V limiter (y direction in texture space) calculates a V value outside of the used texture - 15 - 15 - write-only - - - 0 - Texture wrap mode: The integer part of the calculated value from the v limiter is anded with TEXVMASK. This results in a repetition of the texture in y/v direction. - #0 - - - 1 - Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in y/v direction. - #1 - - - - - TEXTURECLAMPX - Calculating U limiter outside use textureThe bit describes what happens if the U limiter (x direction in texture space) calculates a U value outside of the used texture - 14 - 14 - write-only - - - 0 - Texture wrap mode: The integer part of the calculated value from the u limiter is anded with TEXUMASK. This results in a repetition of the texture in x/u direction. - #0 - - - 1 - Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in x/u direction. - #1 - - - - - BC2 - Blend color 2 instead of framebuffer pixel - 13 - 13 - write-only - - - 0 - use pixel from framebuffer as destination (DST) - #0 - - - 1 - use color 2 as destination (DST) - #1 - - - - - BDI - Blend destination factor is inverteddst factor will be inverted (meaning 1-a or 1-1 depending on BDF) - 12 - 12 - write-only - - - 0 - use blend factor as specified through BDF - #0 - - - 1 - invert blend destinationfactor (1-x) - #1 - - - - - BSI - Blend source factor is invertedsrc factor will be inverted (meaning 1-a or 1-1 depending on BSF) - 11 - 11 - write-only - - - 0 - use blend factor as specified through BSF - #0 - - - 1 - invert blend source factor (1-x) - #1 - - - - - BDF - Blend destination factordst factor is alpha (factor is 1 per default) - 10 - 10 - write-only - - - 0 - use 1.0 as blend destination factor - #0 - - - 1 - use alpha as blend destination factor - #1 - - - - - BSF - Blend source factorsrc factor is alpha (factor is 1 per default) - 9 - 9 - write-only - - - 0 - use 1.0 as blend source factor - #0 - - - 1 - use alpha as blend source factor - #1 - - - - - WRITEFORMAT2 - Bit 3 of framebuffer pixel formatSee WRITEFORMAT above description. - 8 - 8 - write-only - - - BDFA - Blend destinetion factor for alpha channel in alpha channel blending mode (USEACB = 1) - 7 - 7 - write-only - - - 0 - use 1.0 as blend destination factor for alpha channel - #0 - - - 1 - use alpha as blend destination factor for alpha channel - #1 - - - - - BSFA - Blend source factor for alpha channel in alpha channel blending mode (USEACB = 1) - 6 - 6 - write-only - - - 0 - use 1.0 as blend source factor for alpha channel - #0 - - - 1 - use alpha as blend source factor for alpha channel - #1 - - - - - READFORMAT32 - Bit 4 and 3 of the texture buffer format.See READFORMAT above for description - 4 - 5 - write-only - - - USEACB - Alpha blend mode - 3 - 3 - write-only - - - 0 - use WRITEALPHA[1:0] mode - #0 - - - 1 - use full alpha channel blending mode - #1 - - - - - PATTERNSOURCEL5 - Limiter 5 is used as pattern index instead of the default U limiter.Limiter 5 can be combined with limiter 6 to form a quadratic limiter which can be used to make quadratic pattern functions to draw radial patterns. - 2 - 2 - write-only - - - TEXTUREENABLE - Pixel source is read from texture and used as an alpha to blend between COLOR1 and COLOR2 - 1 - 1 - write-only - - - 0 - disabled texture - #0 - - - 1 - enabled texture - #1 - - - - - PATTERNENABLE - Pixel source is a pattern color (blend of COLOR1 and COLOR2 depending on PATTERN and pattern index) - 0 - 0 - write-only - - - 0 - disabled pattern - #0 - - - 1 - enabled pattern - #1 - - - - - - - IRQCTL - Interrupt Control Register - 0xC0 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - BUSIRQCLR - Clear bus error interrupt BUSIRQ - 5 - 5 - write-only - - - 0 - no BUSIRQCLR clear - #0 - - - 1 - clear BUSIRQCLR - #1 - - - - - BUSIRQEN - BUSIRQ interrupt mask enable - 4 - 4 - write-only - - - 0 - disable (mask) BUSIRQ - #0 - - - 1 - enable (unmask) BUSIRQ - #1 - - - - - DLISTIRQCLR - Clear display list interrupt DLISTIRQ - 3 - 3 - write-only - - - 0 - no DLISTRQCLR clear - #0 - - - 1 - clear DLISTRQCLR - #1 - - - - - ENUMIRQCLR - Clear enumeration interrupt ENUMIRQ - 2 - 2 - write-only - - - 0 - no ENUMIRQCLR clear - #0 - - - 1 - clear ENUMIRQCLR - #1 - - - - - DLISTIRQEN - DLISTIRQ interrupt mask enable - 1 - 1 - write-only - - - 0 - disable (mask) DLISTIRQ - #0 - - - 1 - enable (unmask) DLISTIRQ - #1 - - - - - ENUMIRQEN - ENUMIRQ interrupt mask enable - 0 - 0 - write-only - - - 0 - disable (mask) ENUMIRQ - #0 - - - 1 - enable (unmask) ENUMIRQ - #1 - - - - - - - CACHECTL - Cache Control Register - 0xC4 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - CFLUSHTX - Flush texture cache - 3 - 3 - write-only - - - 0 - do not flush the texture cache - #0 - - - 1 - flush the texture cache - #1 - - - - - CENABLETX - Texture cache enable - 2 - 2 - write-only - - - 0 - disable the texture cache - #0 - - - 1 - enable the texture cache - #1 - - - - - CFLUSHFX - Flush framebuffer cache - 1 - 1 - write-only - - - 0 - do not flush the framebuffer cache - #0 - - - 1 - flush the framebuffer cache - #1 - - - - - CENABLEFX - Framebuffer cache enable - 0 - 0 - write-only - - - 0 - disable the framebuffer cache - #0 - - - 1 - enable the framebuffer cache - #1 - - - - - - - STATUS - Status Control Register - CONTROL - 0x00 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - BUSERRMDL - display list bus error interrupt triggered - 10 - 10 - read-only - - - 0 - no display list bus error occurred or interrupt disabled - #0 - - - 1 - display list bus error interrupt triggered - #1 - - - - - BUSERRMTXMRL - texture bus error interrupt triggered - 9 - 9 - read-only - - - 0 - no texture bus error occurred or interrupt disabled - #0 - - - 1 - texture bus error interrupt triggered - #1 - - - - - BUSERRMFB - framebuffer bus error interrupt triggered - 8 - 8 - read-only - - - 0 - no framebuffer bus error occured or interrupt disabled - #0 - - - 1 - framebuffer bus error interrupt triggered - #1 - - - - - BUSIRQ - bus error interrupt triggered - 6 - 6 - read-only - - - 0 - no bus error occurred or interrupt disabled - #0 - - - 1 - bus error interrupt triggered - #1 - - - - - DLISTIRQ - display list finished interrupt triggered - 5 - 5 - read-only - - - 0 - display list not finished or interrupt disabled - #0 - - - 1 - display list finished interrupt triggered - #1 - - - - - ENUMIRQ - enumeration finished interrupt triggered - 4 - 4 - read-only - - - 0 - enumeration not finished or interrupt disabled - #0 - - - 1 - enumeration finished interrupt triggered - #1 - - - - - DLISTACTIVE - Display list reader status - 3 - 3 - read-only - - - 0 - display list reader is idle - #0 - - - 1 - display list reader busy, no direct write access to registers allowed - #1 - - - - - CACHEDIRTY - Framebuffer cache status - 2 - 2 - read-only - - - 0 - framebuffer cache is not dirty - #0 - - - 1 - framebuffer cache is dirty, frame should not be flipped - #1 - - - - - BUSYWRITE - Framebuffer writeback status - 1 - 1 - read-only - - - 0 - framebuffer writeback finished - #0 - - - 1 - framebuffer writeback busy, framebuffer type can not be changed - #1 - - - - - BUSYENUM - Enumeration unit status - 0 - 0 - read-only - - - 0 - enumeration unit idle - #0 - - - 1 - enumeration unit busy, new primitive can not be started - #1 - - - - - - - HWREVISION - Hardware Version and Feature Set ID Register - CONTROL2 - 0x04 - 32 - read-only - 0x0FBE0107 - 0xFFFFFFFF - - - ACBLEND - Alpha channel blending feature - 27 - 27 - read-only - - - 0 - Alpha channel blending unavailable - #0 - - - 1 - Alpha channel blending available - #1 - - - - - COLORKEY - Colorkey feature - 25 - 25 - read-only - - - 0 - Colorkey unavailable - #0 - - - 1 - Colorkey available - #1 - - - - - TEXCLUT256 - Texture CLUT feature - 24 - 24 - read-only - - - 0 - Texture CLUT unavailable - #0 - - - 1 - Texture CLUT available - #1 - - - - - RLEUNIT - RLE unit feature - 23 - 23 - read-only - - - 0 - RLE unit unavailable - #0 - - - 1 - RLE unit available - #1 - - - - - TEXCLU - Texture CLUT with 16 or 256 entries feature - 21 - 21 - read-only - - - 0 - Texture CLUT with 16 or 256 entries unavailable - #0 - - - 1 - Texture CLUT with 16 or 256 entries available - #1 - - - - - PERFCOUNT - Two performance counter feature - 20 - 20 - read-only - - - 0 - Two performance counter unavailable - #0 - - - 1 - Two performance counter available - #1 - - - - - TXCACHE - Texture cache feature - 19 - 19 - read-only - - - 0 - Texture cache unavailable - #0 - - - 1 - Texture cache available - #1 - - - - - FBCACHE - Framebuffer cache feature - 18 - 18 - read-only - - - 0 - Framebuffer cache unavailable - #0 - - - 1 - Framebuffer cache available - #1 - - - - - DLR - Display list reader feature - 17 - 17 - read-only - - - 0 - Display list reader unavailable - #0 - - - 1 - Display list reader available - #1 - - - - - REV - Revision number - 0 - 11 - read-only - - - - - COLOR1 - Base Color Register - 0x64 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - COLOR1A - Alpha channel of color 1(0x00: transparent. . . 0xFF: opaque) - 24 - 31 - write-only - - - COLOR1R - Red channel of color 1 - 16 - 23 - write-only - - - COLOR1G - Green channel of color 1 - 8 - 15 - write-only - - - COLOR1B - Blue channel of color 1 - 0 - 7 - write-only - - - - - COLOR2 - Secondary Color Register - 0x68 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - COLOR2A - Alpha channel of color 2(0x00: transparent. . . 0xFF: opaque) - 24 - 31 - write-only - - - COLOR2R - Red channel of color 2 - 16 - 23 - write-only - - - COLOR2G - Green channel of color 2 - 8 - 15 - write-only - - - COLOR2B - Blue channel of color 2 - 0 - 7 - write-only - - - - - PATTERN - Pattern Register - 0x74 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - PATTERN - Bitmap of the pattern - 0 - 7 - write-only - - - - - 6 - 0x4 - 1-6 - L%sSTART - Limiter %s Start Value Register - 0x10 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LSTART - Start value of the n'th limiter(n=1-6) - 0 - 31 - write-only - - - - - 6 - 0x4 - 1-6 - L%sXADD - Limiter %s X-Axis Increment Register - 0x28 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LXADD - X-axis increment - 0 - 31 - write-only - - - - - 6 - 0x4 - 1-6 - L%sYADD - Limiter %s Y-Axis Increment Register - 0x40 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LYADD - Y-axis increment - 0 - 31 - write-only - - - - - 2 - 0x4 - 1,2 - L%sBAND - Limiter %s Band Width Parameter Register - 0x58 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LBAND - Limiter m band width parameter - 0 - 31 - write-only - - - - - TEXORIGIN - Texture Base Address Register - 0xBC - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - TEXORIGIN - Texture base address - 0 - 31 - write-only - - - - - TEXPITCH - Texels Per Texture Line Register - 0xB4 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - TEXPITCH - Texels per texture linevalid range: 0 to 2048 - 0 - 31 - write-only - - - - - TEXMASK - Texture Size or Texture Address Mask Register - 0xB8 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - TEXVMASK - V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = 0): texture_height must be a power of 2In texture clamping mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 are allowed. - 11 - 31 - write-only - - - TEXUMASK - U maskSet TEXUMASK[10:0] = texture_width -1In texture wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX = 1):all widths up to 2048 are allowed. - 0 - 10 - write-only - - - - - LUSTART - U Limiter Start Value Register - 0x90 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LUSTART - U limiter start value - 0 - 31 - write-only - - - - - LUXADD - U Limiter X-Axis Increment Register - 0x94 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LUXADD - U limiter x-axis increment - 0 - 31 - write-only - - - - - LUYADD - U Limiter Y-Axis Increment Register - 0x98 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LUYADD - U limiter y-axis increment - 0 - 31 - write-only - - - - - LVSTARTI - V Limiter Start Value Integer Part Register - 0x9C - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LVSTARTI - V limiter start value integer part - 0 - 31 - write-only - - - - - LVSTARTF - V Limiter Start Value Fractional Part Register - 0xA0 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LVSTARTF - V limiter start value fractional part - 0 - 15 - write-only - - - - - LVXADDI - V Limiter X-Axis Increment Integer Part Register - 0xA4 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LVXADDI - V limiter x-axis increment integer part - 0 - 31 - write-only - - - - - LVYADDI - V Limiter Y-Axis Increment Integer Part Register - 0xA8 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LVYADDI - V limiter y-axis increment integer part - 0 - 31 - write-only - - - - - LVYXADDF - V Limiter Increment Fractional Parts Register - 0xAC - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LVYADDF - V y limiter increment fractional part - 16 - 31 - write-only - - - LVXADDF - V xlimiter increment fractional part - 0 - 15 - write-only - - - - - TEXCLADDR - CLUT Start Address Register - 0xDC - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - CLADDR - Texture CLUT start address for indexed texture format - 0 - 7 - write-only - - - - - TEXCLDATA - CLUT Data Register - 0xE0 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - CLDATA - Texture CLUT data for Indexed texture format - 0 - 31 - write-only - - - - - TEXCLOFFSET - CLUT Offset Register - 0xE4 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - CLOFFSET - Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] is or'ed with the original index - 0 - 7 - write-only - - - - - COLKEY - Color Key Register - 0xE8 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - COLKEYR - Red channel of color key - 16 - 23 - write-only - - - COLKEYG - Green channel of color key - 8 - 15 - write-only - - - COLKEYB - Blue channel of color key - 0 - 7 - write-only - - - - - SIZE - Bounding Box Dimension Register - 0x78 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - SIZEY - Height of the bounding box in pixelsvalid range: 0 to 1024 - 16 - 31 - write-only - - - SIZEX - Width of the bounding box in pixelsvalid range: 0 to 1024 - 0 - 15 - write-only - - - - - PITCH - Framebuffer Pitch And Spanstore Delay Register - 0x7C - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - SSD - Spanstore delay - 16 - 31 - write-only - - - PITCH - pitch of the framebuffer. A negative width can be used to render bottom-up instead of top-down - 0 - 15 - write-only - - - - - ORIGIN - Framebuffer Base Address Register - 0x80 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - ORIGIN - Address of the first pixel in framebuffer - 0 - 31 - write-only - - - - - DLISTSTART - Display List Start Address Register - 0xC8 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - DLISTSTART - Display list start address - 0 - 31 - write-only - - - - - PERFTRIGGER - Performance Counters Control Register - 0xD4 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - PERFTRIGGER2 - Selects the internal event that will increment PERFCOUNT2 register - 16 - 31 - write-only - - - 0x00 - disable performance counter - 0x00 - - - 0x01 - 2D Drawing Engine active cycles - 0x01 - - - 0x02 - framebuffer read access - 0x02 - - - 0x03 - framebuffer write access - 0x03 - - - 0x04 - texture read access - 0x04 - - - 0x05 - invisible pixels (enumerated but selected with alpha 0percent) - 0x05 - - - 0x06 - invisible pixels while internal FIFO is empty (lost cycles) - 0x06 - - - 0x07 - display list reader active cycles - 0x07 - - - 0x08 - framebuffer read hits - 0x08 - - - 0x09 - framebuffer read misses - 0x09 - - - 0x0A - framebuffer write hits - 0x0A - - - 0x0B - framebuffer write misses - 0x0B - - - 0x0C - texture read hits - 0x0C - - - 0x0D - texture read misses - 0x0D - - - 0x1F - every clock cycle (for use as timer) - 0x1F - - - others - Setting prohibited - true - - - - - PERFTRIGGER1 - Selects the internal event that will increment PERFCOUNT1 register. - 0 - 15 - write-only - - - 0x00 - disable performance counter - 0x00 - - - 0x01 - 2D Drawing Engine active cycles - 0x01 - - - 0x02 - framebuffer read access - 0x02 - - - 0x03 - framebuffer write access - 0x03 - - - 0x04 - texture read access - 0x04 - - - 0x05 - invisible pixels (enumerated but selected with alpha 0percent) - 0x05 - - - 0x06 - invisible pixels while internal FIFO is empty (lost cycles) - 0x06 - - - 0x07 - display list reader active cycles - 0x07 - - - 0x08 - framebuffer read hits - 0x08 - - - 0x09 - framebuffer read misses - 0x09 - - - 0x0A - framebuffer write hits - 0x0A - - - 0x0B - framebuffer write misses - 0x0B - - - 0x0C - texture read hits - 0x0C - - - 0x0D - texture read misses - 0x0D - - - 0x1F - every clock cycle (for use as timer) - 0x1F - - - others - Setting prohibited - true - - - - - - - 2 - 0x4 - 1,2 - PERFCOUNT%s - Performance Counter %s - 0xCC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PERFCOUNT - Counter value.The counter is reset by writing PERFCOUNT = 0000 0000H. - 0 - 31 - read-write - - - - - - - R_DTC - Data Transfer Controller - 0x40005400 - - 0x00000000 - 0x01 - registers - - - 0x00000004 - 0x04 - registers - - - 0x0000000C - 0x01 - registers - - - 0x0000000E - 0x02 - registers - - - - DTCCR - DTC Control Register - 0x00 - 8 - read-write - 0x08 - 0xFF - - - RRS - DTC Transfer Information Read Skip Enable. - 4 - 4 - read-write - - - 0 - Do not skip transfer information read - #0 - - - 1 - Skip transfer information read when vector numbers match - #1 - - - - - - - DTCVBR - DTC Vector Base Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DTCVBR - DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0. - 0 - 31 - read-write - - - - - DTCST - DTC Module Start Register - 0x0C - 8 - read-write - 0x00 - 0xFF - - - DTCST - DTC Module Start - 0 - 0 - read-write - - - 0 - DTC module stop - #0 - - - 1 - DTC module start - #1 - - - - - - - DTCSTS - DTC Status Register - 0x0E - 16 - read-only - 0x0000 - 0xFFFF - - - ACT - DTC Active Flag - 15 - 15 - read-only - - - 0 - DTC transfer operation is not in progress. - #0 - - - 1 - DTC transfer operation is in progress. - #1 - - - - - VECN - DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1) - 0 - 7 - read-only - - - - - - - R_ELC - Event Link Controller - 0x40041000 - - 0x00000000 - 0x01 - registers - - - 0x00000002 - 0x01 - registers - - - 0x00000004 - 0x01 - registers - - - 0x00000010 - 0x02 - registers - - - 0x00000014 - 0x02 - registers - - - 0x00000018 - 0x02 - registers - - - 0x0000001C - 0x02 - registers - - - 0x00000020 - 0x02 - registers - - - 0x00000024 - 0x02 - registers - - - 0x00000028 - 0x02 - registers - - - 0x0000002C - 0x02 - registers - - - 0x00000030 - 0x02 - registers - - - 0x00000034 - 0x02 - registers - - - 0x00000038 - 0x02 - registers - - - 0x0000003C - 0x02 - registers - - - 0x00000040 - 0x02 - registers - - - 0x00000044 - 0x02 - registers - - - 0x00000048 - 0x02 - registers - - - 0x0000004C - 0x02 - registers - - - 0x00000050 - 0x02 - registers - - - 0x00000054 - 0x02 - registers - - - 0x00000058 - 0x02 - registers - - - 0x0000005C - 0x02 - registers - - - 0x00000060 - 0x02 - registers - - - 0x00000064 - 0x02 - registers - - - 0x00000068 - 0x02 - registers - - - - 2 - 0x2 - ELSEGR[%s] - Event Link Software Event Generation Register - 0x02 - - BY - Event Link Software Event Generation Register - 0x00 - 8 - read-write - 0x80 - 0xFF - - - WI - ELSEGR Register Write Disable - 7 - 7 - write-only - - - 0 - Write to ELSEGR register is enabled. - #0 - - - 1 - Write to ELSEGR register is disabled. - #1 - - - - - WE - SEG Bit Write Enable - 6 - 6 - read-write - - - 0 - Write to SEG bit is disabled. - #0 - - - 1 - Write to SEG bit is enabled. - #1 - - - - - SEG - Software Event Generation - 0 - 0 - write-only - - - 0 - Normal operation - #0 - - - 1 - Software event is generated. - #1 - - - - - - - - 23 - 0x4 - - - GPTA - GPTA - 0 - - - GPTB - GPTB - 1 - - - GPTC - GPTC - 2 - - - GPTD - GPTD - 3 - - - GPTE - GPTE - 4 - - - GPTF - GPTF - 5 - - - GPTG - GPTG - 6 - - - GPTH - GPTH - 7 - - - ADCA0 - ADCA0 - 8 - - - ADCB0 - ADCB0 - 9 - - - ADCA1 - ADCA1 - 10 - - - ADCB1 - ADCB1 - 11 - - - DA0 - DA0 - 12 - - - DA1 - DA1 - 13 - - - PORT1 - PORT1 - 14 - - - PORT2 - PORT2 - 15 - - - PORT3 - PORT3 - 16 - - - PORT4 - PORT4 - 17 - - - CTSU - CTSU - 18 - - - DA80 - DA80 - 19 - - - DA81 - DA81 - 20 - - - DA82 - DA82 - 21 - - - SDADC0 - SDADC0 - 22 - - - ELSR[%s] - Event Link Setting Register %s - 0x10 - - HA - Event Link Setting Register - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - - ELS - Event Link Select - 0 - 8 - read-write - - - 0x000 - Event output to the corresponding peripheral module is disabled. - 0x000 - - - others - Set the number for the event signal to be linked. - true - - - - - - - - ELCR - Event Link Controller Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - - ELCON - All Event Link Enable - 7 - 7 - read-write - - - 0 - ELC function is disabled. - #0 - - - 1 - ELC function is enabled. - #1 - - - - - - - - - R_ETHERC0 - Ethernet MAC Controller - 0x40064100 - - 0x00000000 - 0x04 - registers - - - 0x00000008 - 0x04 - registers - - - 0x00000010 - 0x04 - registers - - - 0x00000018 - 0x04 - registers - - - 0x00000020 - 0x04 - registers - - - 0x00000028 - 0x04 - registers - - - 0x00000040 - 0x04 - registers - - - 0x00000050 - 0x00C - registers - - - 0x00000060 - 0x010 - registers - - - 0x000000C0 - 0x04 - registers - - - 0x000000C8 - 0x04 - registers - - - 0x000000D0 - 0x010 - registers - - - 0x000000E4 - 0x018 - registers - - - - ECMR - ETHERC Mode Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TPC - PAUSE Frame Transmit - 20 - 20 - read-write - - - 0 - PAUSE frame is transmitted even during a PAUSE period. - #0 - - - 1 - PAUSE frame is not transmitted during a PAUSE period. - #1 - - - - - ZPF - 0 Time PAUSE Frame Enable - 19 - 19 - read-write - - - 0 - PAUSE frame that contains the pause_time parameter of 0 is not used. - #0 - - - 1 - PAUSE frame that contains the pause_time parameter of 0 is used. - #1 - - - - - PFR - PAUSE Frame Receive Mode - 18 - 18 - read-write - - - 0 - PAUSE frame is not transferred to the EDMAC. - #0 - - - 1 - PAUSE frame is transferred to the EDMAC. - #1 - - - - - RXF - Receive Flow Control Operating Mode - 17 - 17 - read-write - - - 0 - PAUSE frame detection is disabled. - #0 - - - 1 - PAUSE frame detection is enabled. - #1 - - - - - TXF - Transmit Flow Control Operating Mode - 16 - 16 - read-write - - - 0 - Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.) - #0 - - - 1 - Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.) - #1 - - - - - PRCEF - CRC Error Frame Receive Mode - 12 - 12 - read-write - - - 0 - EDMAC is notified of a CRC error. - #0 - - - 1 - EDMAC is not notified of a CRC error. - #1 - - - - - MPDE - Magic Packet Detection Enable - 9 - 9 - read-write - - - 0 - Magic Packet detection is disabled. - #0 - - - 1 - Magic Packet detection is enabled. - #1 - - - - - RE - Reception Enable - 6 - 6 - read-write - - - 0 - Receive function is disabled. - #0 - - - 1 - Receive function is enabled. - #1 - - - - - TE - Transmission Enable - 5 - 5 - read-write - - - 0 - Transmit function is disabled. - #0 - - - 1 - Transmit function is enabled. - #1 - - - - - ILB - Internal Loopback Mode - 3 - 3 - read-write - - - 0 - Normal data transmission or reception is performed. - #0 - - - 1 - Data is looped back in the ETHERC when full-duplex mode is selected. - #1 - - - - - RTM - Bit Rate - 2 - 2 - read-write - - - 0 - 10 Mbps - #0 - - - 1 - 100 Mbps - #1 - - - - - DM - Duplex Mode - 1 - 1 - read-write - - - 0 - Half-duplex mode - #0 - - - 1 - Full-duplex mode - #1 - - - - - PRM - Promiscuous Mode - 0 - 0 - read-write - - - 0 - Promiscuous mode is disabled. - #0 - - - 1 - Promiscuous mode is enabled. - #1 - - - - - - - RFLR - Receive Frame Maximum Length Register - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RFL - Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes. - 0 - 11 - read-write - - - - - ECSR - ETHERC Status Register - 0x10 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BFR - Continuous Broadcast Frame Reception Flag - 5 - 5 - read-write - oneToClear - modify - - - 0 - Continuous reception of broadcast frames has not been detected. - #0 - - - 1 - Continuous reception of broadcast frames has been detected. - #1 - - - - - PSRTO - PAUSE Frame Retransmit Over Flag - 4 - 4 - read-write - oneToClear - modify - - - 0 - PAUSE frame retransmit count has not reached the upper limit. - #0 - - - 1 - PAUSE frame retransmit count has reached the upper limit. - #1 - - - - - LCHNG - LCHNG Link Signal Change Flag - 2 - 2 - read-write - oneToClear - modify - - - 0 - Change in the ETn_LINKSTA signal has not been detected. - #0 - - - 1 - Change in the ETn_LINKSTA signal has been detected (high to low, or low to high). - #1 - - - - - MPD - Magic Packet Detect Flag - 1 - 1 - read-write - oneToClear - modify - - - 0 - Magic Packet has not been detected. - #0 - - - 1 - Magic Packet has been detected. - #1 - - - - - ICD - False Carrier Detect Flag - 0 - 0 - read-write - oneToClear - modify - - - 0 - PHY-LSI has not detected a false carrier on the line. - #0 - - - 1 - PHY-LSI has detected a false carrier on the line. - #1 - - - - - - - ECSIPR - ETHERC Interrupt Enable Register - 0x18 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BFSIPR - Continuous Broadcast Frame Reception Interrupt Enable - 5 - 5 - read-write - - - 0 - Notification of continuous broadcast frame reception interrupt is disabled. - #0 - - - 1 - Notification of continuous broadcast frame reception interrupt is enabled. - #1 - - - - - PSRTOIP - PAUSE Frame Retransmit Over Interrupt Enable - 4 - 4 - read-write - - - 0 - Notification of PAUSE frame retransmit over interrupt is disabled. - #0 - - - 1 - Notification of PAUSE frame retransmit over interrupt is enabled. - #1 - - - - - LCHNGIP - LINK Signal Change Interrupt Enable - 2 - 2 - read-write - - - 0 - Notification of ETn_LINKSTA signal change interrupt is disabled. - #0 - - - 1 - Notification of ETn_LINKSTA signal change interrupt is enabled. - #1 - - - - - MPDIP - Magic Packet Detect Interrupt Enable - 1 - 1 - read-write - - - 0 - Notification of the Magic Packet detect interrupt is disabled. - #0 - - - 1 - Notification of the Magic Packet detect interrupt is enabled. - #1 - - - - - ICDIP - False Carrier Detect Interrupt Enable - 0 - 0 - read-write - - - 0 - Notification of the false carrier detect interrupt is disabled. - #0 - - - 1 - Notification of the false carrier detect interrupt is enabled. - #1 - - - - - - - PIR - PHY Interface Register - 0x20 - 32 - read-write - 0x00000000 - 0xFFFFFFF7 - - - MDI - MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0. - 3 - 3 - read-only - - - MDO - MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read). - 2 - 2 - read-write - - - MMD - MII/RMII Management Mode - 1 - 1 - read-write - - - 0 - Read - #0 - - - 1 - Write - #1 - - - - - MDC - MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII. - 0 - 0 - read-write - - - - - PSR - PHY Status Register - 0x28 - 32 - read-only - 0x00000000 - 0xFFFFFFFE - - - LMON - ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI. - 0 - 0 - read-only - - - - - RDMLR - Random Number Generation Counter Upper Limit Setting Register - 0x40 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RMD - Random Number Generation Counter - 0 - 19 - read-write - - - 00000h - Normal operation - 0x00000 - - - others - Setting prohibited - true - - - - - - - IPGR - IPG Register - 0x50 - 32 - read-write - 0x00000014 - 0xFFFFFFFF - - - IPG - Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" - 0 - 4 - read-write - - - 14h - 96 bit time (initial value) - 0x14 - - - others - (IPGx4+16) bit time - true - - - - - - - APR - Automatic PAUSE Frame Register - 0x54 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - AP - Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. - 0 - 15 - read-write - - - - - MPR - Manual PAUSE Frame Register - 0x58 - 32 - write-only - 0x00000000 - 0xFFFF0000 - - - MP - Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined. - 0 - 15 - write-only - - - - - RFCF - Received PAUSE Frame Counter - 0x60 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - RPAUSE - Received PAUSE Frame CountNumber of received PAUSE frames - 0 - 7 - read-only - - - - - TPAUSER - PAUSE Frame Retransmit Count Setting Register - 0x64 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TPAUSE - Automatic PAUSE Frame Retransmit Setting - 0 - 15 - read-write - - - 0x0000 - Number of retransmissions is unlimited - 0x0000 - - - others - Maximum number of retransmissions is (TPAUSE) - true - - - - - - - TPAUSECR - PAUSE Frame Retransmit Counter - 0x68 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - - BCFRR - Broadcast Frame Receive Count Setting Register - 0x6C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BCF - Broadcast Frame Continuous Receive Count Setting - 0 - 15 - read-write - - - 0000h - Number of receptions is unlimited. - 0x0000 - - - others - Receive (BFC) frame. - true - - - - - - - MAHR - MAC Address Upper Bit Register - 0xC0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MAHR - MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address. - 0 - 31 - read-write - - - - - MALR - MAC Address Lower Bit Register - 0xC8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MALR - MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address. - 0 - 15 - read-write - - - - - TROCR - Transmit Retry Over Counter Register - 0xD0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TROCR - Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted. - 0 - 31 - read-write - clear - - - - - CDCR - Late Collision Detect Counter Register - 0xD4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - LCCR - Lost Carrier Counter Register - 0xD8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - LCCR - Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission. - 0 - 31 - read-write - clear - - - - - CNDCR - Carrier Not Detect Counter Register - 0xDC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CNDCR - Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission. - 0 - 31 - read-write - clear - - - - - CEFCR - CRC Error Frame Receive Counter Register - 0xE4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CEFCR - CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected. - 0 - 31 - read-write - clear - - - - - FRECR - Frame Receive Error Counter Register - 0xE8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FRECR - Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred. - 0 - 31 - read-write - clear - - - - - TSFRCR - Too-Short Frame Receive Counter Register - 0xEC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TSFRCR - Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received. - 0 - 31 - read-write - clear - - - - - TLFRCR - Too-Long Frame Receive Counter Register - 0xF0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TLFRCR - Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received. - 0 - 31 - read-write - clear - - - - - RFCR - Received Alignment Error Frame Counter Register - 0xF4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RFCR - Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets). - 0 - 31 - read-write - clear - - - - - MAFCR - Multicast Address Frame Receive Counter Register - 0xF8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MAFCR - Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received. - 0 - 31 - read-write - clear - - - - - - - R_ETHERC_EDMAC - Ethernet DMA Controller - 0x40064000 - - 0x00000000 - 0x04 - registers - - - 0x00000008 - 0x04 - registers - - - 0x00000010 - 0x04 - registers - - - 0x00000018 - 0x04 - registers - - - 0x00000020 - 0x04 - registers - - - 0x00000028 - 0x04 - registers - - - 0x00000030 - 0x04 - registers - - - 0x00000038 - 0x04 - registers - - - 0x00000040 - 0x04 - registers - - - 0x00000048 - 0x04 - registers - - - 0x00000050 - 0x04 - registers - - - 0x00000058 - 0x04 - registers - - - 0x00000064 - 0x010 - registers - - - 0x00000078 - 0x008 - registers - - - 0x000000C8 - 0x008 - registers - - - 0x000000D4 - 0x008 - registers - - - - EDMR - EDMAC Mode Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DE - Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers. - 6 - 6 - read-write - - - 0 - Big endian mode - #0 - - - 1 - Little endian mode - #1 - - - - - DL - Transmit/Receive DescriptorLength - 4 - 5 - read-write - - - 00 - 16 bytes - #00 - - - 01 - 32 bytes - #01 - - - 10 - 64 bytes - #10 - - - 11 - 16 bytes - #11 - - - - - SWR - Software Reset - 0 - 0 - write-only - - - 0 - no effect. - #0 - - - 1 - the corresponding channels of the EDMAC and ETHERC are reset. Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset. - #1 - - - - - - - EDTRR - EDMAC Transmit Request Register - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TR - Transmit Request - 0 - 0 - write-only - - - 0 - no effect. - #0 - - - 1 - When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted. - #1 - - - - - - - EDRRR - EDMAC Receive Request Register - 0x10 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RR - Receive Request - 0 - 0 - read-write - - - 0 - Receive function is disabled. - #0 - - - 1 - Receive descriptor is read, and the receive function is enabled. - #1 - - - - - - - TDLAR - Transmit Descriptor List Start Address Register - 0x18 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TDLAR - The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b - 0 - 31 - read-write - - - - - RDLAR - Receive Descriptor List Start Address Register - 0x20 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RDLAR - The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b - 0 - 31 - read-write - - - - - EESR - ETHERC/EDMAC Status Register - 0x28 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TWB - Write-Back Complete Flag - 30 - 30 - read-write - oneToClear - modify - - - 0 - Write-back has not been completed, or no transmission has been requested. - #0 - - - 1 - Write-back to the transmit descriptor has been completed. - #1 - - - - - TABT - Transmit Abort Detect Flag - 26 - 26 - read-write - oneToClear - modify - - - 0 - Frame transmission has not been aborted or no transmission has been requested. - #0 - - - 1 - Frame transmission has been aborted. - #1 - - - - - RABT - Receive Abort Detect Flag - 25 - 25 - read-write - oneToClear - modify - - - 0 - Frame reception has not been aborted or no reception has been requested. - #0 - - - 1 - Frame reception has been aborted. - #1 - - - - - RFCOF - Receive Frame Counter Overflow Flag - 24 - 24 - read-write - oneToClear - modify - - - 0 - Receive frame counter has not overflowed. - #0 - - - 1 - Receive frame counter has overflowed. - #1 - - - - - ADE - Address Error Flag - 23 - 23 - read-write - oneToClear - modify - - - 0 - Invalid memory address has not been detected (normal operation). - #0 - - - 1 - Invalid memory address has been detected. - #1 - - - - - ECI - ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared. - 22 - 22 - read-only - - - 0 - ETHERC status interrupt source has not been detected. - #0 - - - 1 - ETHERC status interrupt source has been detected. - #1 - - - - - TC - Frame Transfer Complete Flag - 21 - 21 - read-write - oneToClear - modify - - - 0 - Transfer have not been completed, or no transfer has been requested. - #0 - - - 1 - All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO. - #1 - - - - - TDE - Transmit Descriptor Empty Flag - 20 - 20 - read-write - oneToClear - modify - - - 0 - The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1. - #0 - - - 1 - The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0. - #1 - - - - - TFUF - Transmit FIFO Underflow Flag - 19 - 19 - read-write - oneToClear - modify - - - 0 - Underflow has not occurred. - #0 - - - 1 - Underflow has occurred. - #1 - - - - - FR - Frame Receive Flag - 18 - 18 - read-write - oneToClear - modify - - - 0 - Frame has not been received. - #0 - - - 1 - Frame has been received. Update of the receive descriptor is complete. - #1 - - - - - RDE - Receive Descriptor Empty Flag - 17 - 17 - read-write - oneToClear - modify - - - 0 - The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1. - #0 - - - 1 - The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0. - #1 - - - - - RFOF - Receive FIFO Overflow Flag - 16 - 16 - read-write - oneToClear - modify - - - 0 - Overflow has not occurred. - #0 - - - 1 - Overflow has occurred. - #1 - - - - - CND - Carrier Not Detect Flag - 11 - 11 - read-write - oneToClear - modify - - - 0 - A carrier has been detected when transmission starts. - #0 - - - 1 - A carrier has not been detected during preamble transmission. - #1 - - - - - DLC - Loss of Carrier Detect Flag - 10 - 10 - read-write - oneToClear - modify - - - 0 - Loss of carrier has not been detected. - #0 - - - 1 - Loss of carrier has been detected during frame transmission. - #1 - - - - - CD - Late Collision Detect Flag - 9 - 9 - read-write - oneToClear - modify - - - 0 - Late collision has not been detected. - #0 - - - 1 - Late collision has been detected during frame transmission. - #1 - - - - - TRO - Transmit Retry Over Flag - 8 - 8 - read-write - oneToClear - modify - - - 0 - Transmit retry-over condition has not been detected. - #0 - - - 1 - Transmit retry-over condition has been detected. - #1 - - - - - RMAF - Multicast Address Frame Receive Flag - 7 - 7 - read-write - oneToClear - modify - - - 0 - Multicast address frame has not been received. - #0 - - - 1 - Multicast address frame has been received. - #1 - - - - - RRF - Alignment Error Flag - 4 - 4 - read-write - oneToClear - modify - - - 0 - Alignment error has not been detected. - #0 - - - 1 - Alignment error has been detected. - #1 - - - - - RTLF - Frame-Too-Long Error Flag - 3 - 3 - read-write - oneToClear - modify - - - 0 - Frame-too-long error has not been detected. - #0 - - - 1 - Frame-too-long error has been detected. - #1 - - - - - RTSF - Frame-Too-Short Error Flag - 2 - 2 - read-write - oneToClear - modify - - - 0 - Frame-too-short error has not been detected. - #0 - - - 1 - Frame-too-short error has been detected. - #1 - - - - - PRE - PHY-LSI Receive Error Flag - 1 - 1 - read-write - oneToClear - modify - - - 0 - PHY-LSI receive error has not been detected. - #0 - - - 1 - PHY-LSI receive error has been detected. - #1 - - - - - CERF - CRC Error Flag - 0 - 0 - read-write - oneToClear - modify - - - 0 - CRC error has not been detected. - #0 - - - 1 - CRC error has been detected. - #1 - - - - - - - EESIPR - ETHERC/EDMAC Status Interrupt Enable Register - 0x30 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TWBIP - Write-Back Complete Interrupt Request Enable - 30 - 30 - read-write - - - 0 - Write-back complete interrupt request is disabled. - #0 - - - 1 - Write-back complete interrupt request is enabled. - #1 - - - - - TABTIP - Transmit Abort Detect Interrupt Request Enable - 26 - 26 - read-write - - - 0 - Transmit abort detect interrupt request is disabled. - #0 - - - 1 - Transmit abort detect interrupt request is enabled. - #1 - - - - - RABTIP - Receive Abort Detect Interrupt Request Enable - 25 - 25 - read-write - - - 0 - Receive abort detect interrupt request is disabled. - #0 - - - 1 - Receive abort detect interrupt request is enabled. - #1 - - - - - RFCOFIP - Receive Frame Counter Overflow Interrupt Request Enable - 24 - 24 - read-write - - - 0 - Receive frame counter overflow interrupt request is disabled. - #0 - - - 1 - Receive frame counter overflow interrupt request is enabled. - #1 - - - - - ADEIP - Address Error Interrupt Request Enable - 23 - 23 - read-write - - - 0 - Address error interrupt request is disabled. - #0 - - - 1 - Address error interrupt request is enabled. - #1 - - - - - ECIIP - ETHERC Status Register Source Interrupt Request Enable - 22 - 22 - read-write - - - 0 - ETHERC status interrupt request is disabled. - #0 - - - 1 - ETHERC status interrupt request is enabled. - #1 - - - - - TCIP - Frame Transfer Complete Interrupt Request Enable - 21 - 21 - read-write - - - 0 - Frame transmission complete interrupt request is disabled. - #0 - - - 1 - Frame transmission complete interrupt request is enabled. - #1 - - - - - TDEIP - Transmit Descriptor Empty Interrupt Request Enable - 20 - 20 - read-write - - - 0 - Transmit descriptor empty interrupt request is disabled. - #0 - - - 1 - Transmit descriptor empty interrupt request is enabled. - #1 - - - - - TFUFIP - Transmit FIFO Underflow Interrupt Request Enable - 19 - 19 - read-write - - - 0 - Underflow interrupt request is disabled. - #0 - - - 1 - Underflow interrupt request is enabled. - #1 - - - - - FRIP - Frame Receive Interrupt Request Enable - 18 - 18 - read-write - - - 0 - Frame reception interrupt request is disabled. - #0 - - - 1 - Frame reception interrupt request is enabled. - #1 - - - - - RDEIP - Receive Descriptor Empty Interrupt Request Enable - 17 - 17 - read-write - - - 0 - Receive descriptor empty interrupt request is disabled. - #0 - - - 1 - Receive descriptor empty interrupt request is enabled. - #1 - - - - - RFOFIP - Receive FIFO Overflow Interrupt Request Enable - 16 - 16 - read-write - - - 0 - Overflow interrupt request is disabled. - #0 - - - 1 - Overflow interrupt request is enabled. - #1 - - - - - CNDIP - Carrier Not Detect Interrupt Request Enable - 11 - 11 - read-write - - - 0 - Carrier not detect interrupt request is disabled. - #0 - - - 1 - Carrier not detect interrupt request is enabled. - #1 - - - - - DLCIP - Loss of Carrier Detect Interrupt Request Enable - 10 - 10 - read-write - - - 0 - Loss of carrier detect interrupt request is disabled. - #0 - - - 1 - Loss of carrier detect interrupt request is enabled. - #1 - - - - - CDIP - Late Collision Detect Interrupt Request Enable - 9 - 9 - read-write - - - 0 - Late collision detect interrupt request is disabled. - #0 - - - 1 - Late collision detect interrupt request is enabled. - #1 - - - - - TROIP - Transmit Retry Over Interrupt Request Enable - 8 - 8 - read-write - - - 0 - Transmit retry over interrupt request is disabled. - #0 - - - 1 - Transmit retry over interrupt request is enabled. - #1 - - - - - RMAFIP - Multicast Address Frame Receive Interrupt Request Enable - 7 - 7 - read-write - - - 0 - Multicast address frame receive interrupt request is disabled. - #0 - - - 1 - Multicast address frame receive interrupt request is enabled. - #1 - - - - - RRFIP - Alignment Error Interrupt Request Enable - 4 - 4 - read-write - - - 0 - Alignment error interrupt request is disabled. - #0 - - - 1 - Alignment error interrupt request is enabled. - #1 - - - - - RTLFIP - Frame-Too-Long Error Interrupt Request Enable - 3 - 3 - read-write - - - 0 - Frame-too-long error interrupt request is disabled. - #0 - - - 1 - Frame-too-long error interrupt request is enabled. - #1 - - - - - RTSFIP - Frame-Too-Short Error Interrupt Request Enable - 2 - 2 - read-write - - - 0 - Frame-too-short error interrupt request is disabled. - #0 - - - 1 - Frame-too-short error interrupt request is enabled. - #1 - - - - - PREIP - PHY-LSI Receive Error Interrupt Request Enable - 1 - 1 - read-write - - - 0 - PHY-LSI receive error interrupt request is disabled. - #0 - - - 1 - PHY-LSI receive error interrupt request is enabled. - #1 - - - - - CERFIP - CRC Error Interrupt Request Enable - 0 - 0 - read-write - - - 0 - CRC error interrupt request is disabled. - #0 - - - 1 - CRC error interrupt request is enabled. - #1 - - - - - - - TRSCER - ETHERC/EDMAC Transmit/Receive Status Copy Enable Register - 0x38 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RMAFCE - RMAF Flag Copy Enable - 7 - 7 - read-write - - - 0 - The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor. - #0 - - - 1 - The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor. - #1 - - - - - RRFCE - RRF Flag Copy Enable - 4 - 4 - read-write - - - 0 - The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor. - #0 - - - 1 - The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor. - #1 - - - - - - - RMFCR - Missed-Frame Counter Register - 0x40 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MFC - Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception. - 0 - 15 - read-write - clear - - - - - TFTR - Transmit FIFO Threshold Register - 0x48 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TFT - Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4. Example: 00Dh: 52 bytes 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes - 0 - 10 - read-write - - - 0x000 - 0x200 - - - - - 0x000 - Store and forward mode - 0x000 - - - others - The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited) - true - - - - - - - FDR - Transmit FIFO Threshold Register - 0x50 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TFD - Receive FIFO Depth - 8 - 12 - read-write - - - 01111 - 4096 bytes - #01111 - - - others - Settings other than above are prohibited. - true - - - - - RFD - Transmit FIFO Depth - 0 - 4 - read-write - - - 00111 - 2048 bytes - #00111 - - - others - Settings other than above are prohibited. - true - - - - - - - RMCR - Receive Method Control Register - 0x58 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RNR - Receive Request Reset - 0 - 0 - read-write - - - 0 - EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received. - #0 - - - 1 - EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received. - #1 - - - - - - - TFUCR - Transmit FIFO Underflow Counter - 0x64 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - UNDER - Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh. - 0 - 15 - read-write - - - - - RFOCR - Receive FIFO Overflow Counter - 0x68 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - OVER - Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh. - 0 - 15 - read-write - - - - - IOSR - Independent Output Signal Setting Register - 0x6C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ELB - External Loopback Mode - 0 - 0 - read-write - - - 0 - The ETn_EXOUT pin outputs low. - #0 - - - 1 - The ETn_EXOUT pin outputs high. - #1 - - - - - - - FCFTR - Flow Control Start FIFO Threshold Setting Register - 0x70 - 32 - read-write - 0x00070007 - 0xFFFFFFFF - - - RFFO - Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.) - 16 - 18 - read-write - - - 000 - When 2 receive frames have been stored in the receive FIFO. - #000 - - - 001 - When 4 receive frames have been stored in the receive FIFO. - #001 - - - 010 - When 6 receive frames have been stored in the receive FIFO. - #010 - - - 011 - When 8 receive frames have been stored in the receive FIFO. - #011 - - - 100 - When 10 receive frames have been stored in the receive FIFO. - #100 - - - 101 - When 12 receive frames have been stored in the receive FIFO. - #101 - - - 110 - When 14 receive frames have been stored in the receive FIFO. - #110 - - - 111 - When 16 receive frames have been stored in the receive FIFO. - #111 - - - - - RFDO - Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.) - 0 - 2 - read-write - - - 000 - When 224 ( 256 - 32) bytes of data is stored in the receive FIFO. - #000 - - - 001 - When 480 ( 512 - 32) bytes of data is stored in the receive FIFO. - #001 - - - 010 - When 736 ( 768 - 32) bytes of data is stored in the receive FIFO. - #010 - - - 011 - When 992 (1024 - 32) bytes of data is stored in the receive FIFO. - #011 - - - 100 - When 1248 (1280 - 32) bytes of data is stored in the receive FIFO. - #100 - - - 101 - When 1504 (1536 - 32) bytes of data is stored in the receive FIFO. - #101 - - - 110 - When 1760 (1792 - 32) bytes of data is stored in the receive FIFO. - #110 - - - 111 - When 2016 (2048 - 32) bytes of data is stored in the receive FIFO. - #111 - - - - - - - RPADIR - Receive Data Padding Insert Register - 0x78 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PADS - Padding Size - 16 - 17 - read-write - - - 00 - No padding is inserted. - #00 - - - 01 - 1 byte is inserted. - #01 - - - 10 - 2 bytes are inserted. - #10 - - - 11 - 3 bytes are inserted. - #11 - - - - - PADR - Padding Slot - 0 - 5 - read-write - - - 00h - Padding is inserted at the head of received data. - 0x00 - - - others - Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data. - true - - - - - - - TRIMD - Transmit Interrupt Setting Register - 0x07C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TIM - Transmit Interrupt Mode - 4 - 4 - read-write - - - 0 - Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted. - #0 - - - 1 - Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed. - #1 - - - - - TIS - Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt. - 0 - 0 - read-write - - - 0 - Transmit Interrupt is disabled. - #0 - - - 1 - Transmit Interrupt is enabled. - #1 - - - - - - - RBWAR - Receive Buffer Write Address Register - 0xC8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RBWAR - Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception. - 0 - 31 - read-only - - - - - RDFAR - Receive Descriptor Fetch Address Register - 0xCC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RDFAR - Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception. - 0 - 31 - read-only - - - - - TBRAR - Transmit Buffer Read Address Register - 0x0D4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TBRAR - Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register. - 0 - 31 - read-only - - - - - TDFAR - Transmit Descriptor Fetch Address Register - 0xD8 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - TDFAR - Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register. - 0 - 31 - read-only - - - - - - - R_ETHERC_EPTPC - Ethernet PTP Controller - 0x40065800 - - 0x00000000 - 0x008 - registers - - - 0x00000010 - 0x010 - registers - - - 0x00000040 - 0x008 - registers - - - 0x00000050 - 0x01C - registers - - - 0x00000080 - 0x04 - registers - - - 0x00000090 - 0x00C - registers - - - 0x000000A0 - 0x00C - registers - - - 0x000000C0 - 0x018 - registers - - - 0x000000E0 - 0x018 - registers - - - 0x00000100 - 0x014 - registers - - - 0x00000120 - 0x024 - registers - - - 0x00000160 - 0x018 - registers - - - 0x000001C0 - 0x018 - registers - - - - 2 - 0x8 - F[%s] - Frame Reception Filter Setting Registers - 0x160 - - 2 - 0x8 - 0-1 - MACRU - Frame Reception Filter MAC Address Setting Registers - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FMACRU - These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames. - 0 - 23 - read-write - - - - - 2 - 0x8 - 0-1 - MACRL - Frame Reception Filter MAC Address Setting Registers - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FMACRL - These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames. - 0 - 23 - read-write - - - - - - SYSR - SYNFP Status Register - 0x000 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GENDN - Generation Stop Completion Detection Flag - 17 - 17 - read-write - oneToClear - modify - - - 0 - Stopping generation has not been completed. - #0 - - - 1 - Stopping generation has been completed. - #1 - - - - - RESDN - Response Stop Completion Detection Flag - 16 - 16 - read-write - oneToClear - modify - - - 0 - Stopping responses has not been completed. - #0 - - - 1 - Stopping responses has been completed. - #1 - - - - - INFABT - Control Information Abnormality Detection Flag - 14 - 14 - read-write - oneToClear - modify - - - 0 - No abnormality in control information - #0 - - - 1 - Abnormality in control information - #1 - - - - - RECLP - Loop Reception Detection Flag - 12 - 12 - read-write - oneToClear - modify - - - 0 - A received message has not returned through a loop. - #0 - - - 1 - A received message has returned through a loop. - #1 - - - - - DRQOVR - Delay_Req Reception FIFO Overflow Detection Flag - 6 - 6 - read-write - oneToClear - modify - - - 0 - The received Delay_Req has not caused the reception FIFO to overflow. - #0 - - - 1 - The received Delay_Req has caused the reception FIFO to overflow. - #1 - - - - - INTDEV - Receive logMessageInterval Value Out-of-Range Flag - 5 - 5 - read-write - oneToClear - modify - - - 0 - The received logMessageInterval value is within the range. - #0 - - - 1 - The received logMessageInterval value is out of the range. - #1 - - - - - DRPTO - Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag - 4 - 4 - read-write - oneToClear - modify - - - 0 - A Delay_Resp/Pdelay_Resp timeout has not occurred. - #0 - - - 1 - A Delay_Resp/Pdelay_Resp timeout has occurred. - #1 - - - - - MPDUD - meanPathDelay Value Update Flag - 2 - 2 - read-write - oneToClear - modify - - - 0 - The meanPathDelay value has not been updated. - #0 - - - 1 - The meanPathDelay value has been updated. - #1 - - - - - INTCHG - Receive logMessageInterval Value Change Detection Flag - 1 - 1 - read-write - oneToClear - modify - - - 0 - No change in the received logMessageInterval value. - #0 - - - 1 - A change in the received logMessageInterval value. - #1 - - - - - OFMUD - offsetFromMaster Value Update Flag - 0 - 0 - read-write - oneToClear - modify - - - 0 - The offsetFromMaster value has not been updated. - #0 - - - 1 - The offsetFromMaster value has been updated. - #1 - - - - - - - SYIPR - SYNFP Status Notification Permission Register - 0x004 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GENDN - SYSR.GENDN Status Notification Permission - 17 - 17 - read-write - - - 0 - Prohibits notification of the state of SYSR.GENDN. - #0 - - - 1 - Permits notification of the state of SYSR.GENDN. - #1 - - - - - RESDN - SYSR.RESDN Status Notification Permission - 16 - 16 - read-write - - - 0 - Prohibits notification of the state of SYSR.RESDN. - #0 - - - 1 - Permits notification of the state of SYSR.RESDN. - #1 - - - - - INFABT - SYSR.INFABT Status Notification Permission - 14 - 14 - read-write - - - 0 - Prohibits notification of the state of SYSR.INFABT. - #0 - - - 1 - Permits notification of the state of SYSR.INFABT. - #1 - - - - - RECLP - SYSR.RECLP Status Notification Permission - 12 - 12 - read-write - - - 0 - Prohibits notification of the state of SYSR.RECLP. - #0 - - - 1 - Permits notification of the state of SYSR.RECLP. - #1 - - - - - DRQOVR - SYSR.DRQOVR Status Notification Permission - 6 - 6 - read-write - - - 0 - Prohibits notification of the state of SYSR.DRQOVR. - #0 - - - 1 - Permits notification of the state of SYSR.DRQOVR. - #1 - - - - - INTDEV - SYSR.INTDEV Status Notification Permission - 5 - 5 - read-write - - - 0 - Prohibits notification of the state of SYSR.INTDEV. - #0 - - - 1 - Permits notification of the state of SYSR.INTDEV. - #1 - - - - - DRPTO - SYSR.DRPTO Status Notification Permission - 4 - 4 - read-write - - - 0 - Prohibits notification of the state of SYSR.DRPTO. - #0 - - - 1 - Permits notification of the state of SYSR.DRPTO. - #1 - - - - - MPDUD - SYSR.MPDUD Status Notification Permission - 2 - 2 - read-write - - - 0 - Prohibits notification of the state of SYSR.MPDUD. - #0 - - - 1 - Permits notification of the state of SYSR.MPDUD. - #1 - - - - - INTCHG - SYSR.INTCHG Status Notification Permission - 1 - 1 - read-write - - - 0 - Prohibits notification of the state of SYSR.INTCHG. - #0 - - - 1 - Permits notification of the state of SYSR.INTCHG. - #1 - - - - - OFMUD - SYSR.OFMUD Status Notification Permission - 0 - 0 - read-write - - - 0 - Prohibits notification of the state of SYSR.OFMUD. - #0 - - - 1 - Permits notification of the state of SYSR.OFMUD. - #1 - - - - - - - SYMACRU - SYNFP MAC Address Registers - 0x010 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYMACRU - These bits hold the setting for the higher-order 24 bits of the local MAC address. - 0 - 23 - read-write - - - - - SYMACRL - SYNFP MAC Address Registers - 0x014 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYMACRL - These bits hold the setting for the lower-order 24 bits of the local MAC address. - 0 - 23 - read-write - - - - - SYLLCCTLR - SYNFP LLC-CTL Value Register - 0x018 - 32 - read-write - 0x00000003 - 0xFFFFFFFF - - - CTL - LLC-CTL FieldThese bits specify the value used for the control field in the LLC sublayer when generating IEEE802.3 frames. - 0 - 7 - read-write - - - - - SYIPADDRR - SYNFP Local IP Address Register - 0x01C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYIPADDRR - These bits hold the setting for the local IP address. - 0 - 31 - read-write - - - - - SYSPVRR - SYNFP Specification Version Setting Register - 0x040 - 32 - read-write - 0x00000002 - 0xFFFFFFFF - - - TRSP - transportSpecific Field ValueThese bits are used to set the transportSpecific field value of the PTP v2 header.When a message is received, this value is compared with the transportSpecific field of the received frame.In generating messages, the value is used for the transportSpecific field of the frame for transmission.Set these bits to 0000b (IEEE 1588). - 4 - 7 - read-write - - - VER - versionPTP Field ValueThese bits are used to set the versionPTP field value of the PTP v2 header.When a message is received, this value is compared with the versionPTP field of the received frame.In generating messages, the value is used for the versionPTP field of the frame for transmission.Set these bits to 0010b (PTP v2). - 0 - 3 - read-write - - - - - SYDOMR - SYNFP Domain Number Setting Register - 0x044 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DNUM - domainNumber Field Value SettingThese bits are used to set the domainNumber field value of the PTP v2 header.When a message is received, this value is compared with the domainNumber field of the received frame as a condition for PTP reception processing.In generating messages, the value is used for the domainNumber field of the frame for transmission. - 0 - 7 - read-write - - - - - ANFR - Announce Message Flag Field Setting Register - 0x050 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FLAG14 - PTP profile Specific 2 - 14 - 14 - read-write - - - 0 - PTP profile Specific 2 is set to FALSE. - #0 - - - 1 - PTP profile Specific 2 is set to TRUE. - #1 - - - - - FLAG13 - PTP profile Specific 1 - 13 - 13 - read-write - - - 0 - PTP profile Specific 1 is set to FALSE. - #0 - - - 1 - PTP profile Specific 1 is set to TRUE. - #1 - - - - - FLAG10 - unicastFlag - 10 - 10 - read-write - - - 0 - unicastFlag is set to FALSE. - #0 - - - 1 - unicastFlag is set to TRUE. - #1 - - - - - FLAG8 - alternateMasterFlag - 8 - 8 - read-write - - - 0 - alternateMasterFlag is set to FALSE. - #0 - - - 1 - alternateMasterFlag is set to TRUE. - #1 - - - - - FLAG5 - frequencyTraceableThis bit is used to set the logical value of the frequencyTraceable member of timePropertiesDS. - 5 - 5 - read-write - - - 0 - frequencyTraceable is set to FALSE. - #0 - - - 1 - frequencyTraceable is set to TRUE. - #1 - - - - - FLAG4 - timeTraceableThis bit is used to set the logical value of the timeTraceable member of timePropertiesDS. - 4 - 4 - read-write - - - 0 - timeTraceable is set to FALSE. - #0 - - - 1 - timeTraceable is set to TRUE. - #1 - - - - - FLAG3 - ptpTimescaleThis bit is used to set the logical value of the ptpTimescale member of timePropertiesDS. - 3 - 3 - read-write - - - 0 - ptpTimescale is set to FALSE. - #0 - - - 1 - ptpTimescale is set to TRUE. - #1 - - - - - FLAG2 - currentUtcOffsetValidThis bit is used to set the logical value of the currentUtcOffsetValid member of timePropertiesDS. - 2 - 2 - read-write - - - 0 - currentUtcOffsetValid is set to FALSE. - #0 - - - 1 - currentUtcOffsetValid is set to TRUE. - #1 - - - - - FLAG1 - leap59This bit is used to set the logical value of the leap59 member of timePropertiesDS. - 1 - 1 - read-write - - - 0 - leap59 is set to FALSE. - #0 - - - 1 - leap59 is set to TRUE. - #1 - - - - - FLAG0 - leap61This bit is used to set the logical value of the leap61 member of timePropertiesDS. - 0 - 0 - read-write - - - 0 - leap61 is set to FALSE. - #0 - - - 1 - leap61 is set to TRUE. - #1 - - - - - - - SYNFR - Sync Message Flag Field Setting Register - 0x054 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FLAG14 - PTP profile Specific 2 - 14 - 14 - read-write - - - 0 - PTP profile Specific 2 is set to FALSE. - #0 - - - 1 - PTP profile Specific 2 is set to TRUE. - #1 - - - - - FLAG13 - PTP profile Specific 1 - 13 - 13 - read-write - - - 0 - PTP profile Specific 1 is set to FALSE. - #0 - - - 1 - PTP profile Specific 1 is set to TRUE. - #1 - - - - - FLAG10 - unicastFlag - 10 - 10 - read-write - - - 0 - unicastFlag is set to FALSE. - #0 - - - 1 - unicastFlag is set to TRUE. - #1 - - - - - FLAG9 - twoStepFlag - 9 - 9 - read-write - - - 0 - Set this bit to 0 (FALSE). - #0 - - - 1 - Setting prohibited - #1 - - - - - FLAG8 - alternateMasterFlag - 8 - 8 - read-write - - - 0 - alternateMasterFlag is set to FALSE. - #0 - - - 1 - alternateMasterFlag is set to TRUE. - #1 - - - - - - - DYRQFR - Delay_Req Message Flag Field Setting Register - 0x058 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FLAG14 - PTP profile Specific 2 - 14 - 14 - read-write - - - 0 - PTP profile Specific 2 is set to FALSE. - #0 - - - 1 - PTP profile Specific 2 is set to TRULE. - #1 - - - - - FLAG13 - PTP profile Specific 1 - 13 - 13 - read-write - - - 0 - PTP profile Specific 1 is set to FALSE. - #0 - - - 1 - PTP profile Specific 1 is set to TRULE. - #1 - - - - - FLAG10 - unicastFlag - 10 - 10 - read-write - - - 0 - unicastFlag is set to FALSE. - #0 - - - 1 - unicastFlag is set to TRULE. - #1 - - - - - - - DYRPFR - Delay_Resp Message Flag Field Setting Register - 0x05C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FLAG14 - PTP profile Specific 2 - 14 - 14 - read-write - - - 0 - PTP profile Specific 2 is set to FALSE. - #0 - - - 1 - PTP profile Specific 2 is set to TRUE. - #1 - - - - - FLAG13 - PTP profile Specific 1 - 13 - 13 - read-write - - - 0 - PTP profile Specific 1 is set to FALSE. - #0 - - - 1 - PTP profile Specific 1 is set to TRUE. - #1 - - - - - FLAG10 - unicastFlag - 10 - 10 - read-write - - - 0 - unicastFlag is set to FALSE. - #0 - - - 1 - unicastFlag is set to TRUE. - #1 - - - - - FLAG9 - woStepFlag - 9 - 9 - read-write - - - 0 - Set this bit to 0 (FALSE). - #0 - - - 1 - Setting prohibited - #1 - - - - - FLAG8 - alternateMasterFlag - 8 - 8 - read-write - - - 0 - alternateMasterFlag is set to FALSE. - #0 - - - 1 - alternateMasterFlag is set to TRUE. - #1 - - - - - - - SYCIDRU - SYNFP Local Clock ID Registers - 0x060 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYCIDRU - These bits hold the setting for the higher-order 32 bits of the clock-ID of your port. - 0 - 31 - read-write - - - - - SYCIDRL - SYNFP Local Clock ID Registers - 0x064 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYCIDRL - These bits hold the setting for the lower-order 32 bits of the clock-ID of your port. - 0 - 31 - read-write - - - - - SYPNUMR - SYNFP Local Port Number Register - 0x068 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PNUM - Local Port Number SettingThese bits hold the setting for the port number of the local port. - 0 - 15 - read-write - - - - - SYRVLDR - SYNFP Register Value Load Directive Register - 0x080 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - ANUP - Announce Message Generation Information Update - 2 - 2 - write-only - - - 0 - no effect - #0 - - - 1 - Setting this bit to 1 leads to simultaneous reflection in the Announce message generation block of the values of the registers required for the generation of Announce messages. - #1 - - - - - STUP - State Update - 1 - 1 - write-only - - - 0 - no effect - #0 - - - 1 - Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers related to the reception and transmission of PTP messages. - #1 - - - - - BMUP - BMC Update - 0 - 0 - write-only - - - 0 - no effect - #0 - - - 1 - Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers holding the MasterClock identifying information. - #1 - - - - - - - SYRFL1R - SYNFP Reception Filter Register 1 - 0x090 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDFUP2 - Pdelay_Resp_Follow_Up Message Processing - 30 - 30 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP does not process messages. - #1 - - - - - PDFUP1 - Pdelay_Resp_Follow_Up Message Processing - 29 - 29 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - PDFUP0 - Pdelay_Resp_Follow_Up Message Processing - 28 - 28 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - PDRP2 - Pdelay_Resp Message Processing - 26 - 26 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP processes messages. - #1 - - - - - PDRP1 - Pdelay_Resp Message Processing - 25 - 25 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - PDRP0 - Pdelay_Resp Message Processing - 24 - 24 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - PDRQ2 - Pdelay_Req Message Processing - 22 - 22 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP processes messages. - #1 - - - - - PDRQ1 - Pdelay_Req Message Processing - 21 - 21 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - PDRQ0 - Pdelay_Req Message Processing - 20 - 20 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - DRP2 - Delay_Resp Message Processing - 18 - 18 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP processes messages. - #1 - - - - - DRP1 - Delay_Resp Message Processing - 17 - 17 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - DRP0 - Delay_Resp Message Processing - 16 - 16 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - DRQ2 - Delay_Req Message Processing - 14 - 14 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP processes messages. - #1 - - - - - DRQ1 - Delay_Req Message Processing - 13 - 13 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - DRQ0 - Delay_Req Message Processing - 12 - 12 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - FUP2 - Follow_Up Message Processing - 10 - 10 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP processes messages. - #1 - - - - - FUP1 - Follow_Up Message Processing - 9 - 9 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - FUP0 - Follow_Up Message Processing - 8 - 8 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - SYNC2 - Sync Message Processing - 6 - 6 - read-write - - - 0 - The SYNFP does not process messages. - #0 - - - 1 - The SYNFP processes messages. - #1 - - - - - SYNC1 - Sync Message Processing - 5 - 5 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - SYNC0 - Sync Message Processing - 4 - 4 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - ANCE1 - Announce Message Processing - 1 - 1 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - ANCE0 - Announce Message Processing - 0 - 0 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - - - SYRFL2R - SYNFP Reception Filter Register 2 - 0x094 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ILL1 - Illegal Message Processing Setting - 29 - 29 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - ILL0 - Illegal Message Processing Setting - 28 - 28 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - SIG1 - Signaling Message Processing Setting - 5 - 5 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - SIG0 - Signaling Message Processing Setting - 4 - 4 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - MAN1 - Management Message Processing Setting - 1 - 1 - read-write - - - 0 - The PRC-TC does not relay messages between ports 0 and 1. - #0 - - - 1 - The PRC-TC relays messages between ports 0 and 1. - #1 - - - - - MAN0 - Management Message Processing Setting - 0 - 0 - read-write - - - 0 - Messages are not transferred to the PTPEDMAC. - #0 - - - 1 - Messages are transferred to the PTPEDMAC. - #1 - - - - - - - SYTRENR - SYNFP Transmission Enable Register - 0x098 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PDRQ - Pdelay_Req Message Transmission Enable - 12 - 12 - read-write - - - 0 - Pdelay_Req messages are not transmitted. - #0 - - - 1 - Pdelay_Req messages are transmitted. - #1 - - - - - DRQ - Delay_Req Message Transmission Enable - 8 - 8 - read-write - - - 0 - Delay_Req messages are not transmitted. - #0 - - - 1 - Delay_Req messages are transmitted. - #1 - - - - - SYNC - Sync Message Transmission Enable - 4 - 4 - read-write - - - 0 - Sync messages are not transmitted. - #0 - - - 1 - Sync messages are transmitted. - #1 - - - - - ANCE - Announce Message Transmission Enable - 0 - 0 - read-write - - - 0 - Announce messages are not transmitted. - #0 - - - 1 - Announce messages are transmitted. - #1 - - - - - - - MTCIDU - Master Clock ID Registers - 0x0A0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MTCIDU - These bits hold the setting for the higher-order 32 bits of the clock-ID of the master clock. - 0 - 31 - read-write - - - - - MTCIDL - Master Clock ID Registers - 0x0A4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MTCIDL - These bits hold the setting for the lower-order 32 bits of the clock-ID of the master clock. - 0 - 31 - read-write - - - - - MTPID - Master clock port number register - 0x0A8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PNUM - Master Clock Port Number SettingThese bits hold the setting for the port number of the master clock. - 0 - 15 - read-write - - - - - SYTLIR - SYNFP Transmission Interval Setting Register - 0x0C0 - 32 - read-write - 0x00000001 - 0xFFFFFFFF - - - DREQ - Delay_Req Transmission Interval Average Value/ Pdelay_Req Transmission Interval SettingThe bits set the average interval for the transmission of Delay_Req messages and the interval for the transmission of Pdelay_Req messages.The setting is also placed in the logMessageInterval field of Delay_Resp messages. - 16 - 23 - read-write - - - SYNC - Sync Message Transmission Interval SettingThese bits set the interval for the transmission of Sync messages. The setting is also placed in the logMessageInterval field of transmitted Sync messages. - 8 - 15 - read-write - - - ANCE - Announce Message Transmission Interval SettingThese bits set the interval for the transmission of Announce messages. - 0 - 7 - read-write - - - - - SYRLIR - SYNFP Received logMessageInterval Value Indication Register - 0x0C4 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - DRESP - Delay_Resp Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Delay_Resp message. - 16 - 23 - read-only - - - SYNC - Sync Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Sync message. - 8 - 15 - read-only - - - ANCE - Announce Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Announce message. - 0 - 7 - read-only - - - - - OFMRU - offsetFromMaster Value Registers - 0x0C8 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - OFMRU - These bits indicate the higher-order 32 bits of the calculated offsetFromMaster value. - 0 - 31 - read-only - - - - - OFMRL - offsetFromMaster Value Registers - 0x0CC - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - OFMRL - These bits indicate the lower-order 32 bits of the calculated offsetFromMaster value. - 0 - 31 - read-only - - - - - MPDRU - meanPathDelay Value Registers - 0x0D0 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - MPDRU - These bits indicate the higher-order 32 bits of the calculated meanPathDelay value. - 0 - 31 - read-only - - - - - MPDRL - meanPathDelay Value Registers - 0x0D4 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - MPDRL - These bits indicate the lower-order 32 bits of the calculated meanPathDelay value. - 0 - 31 - read-only - - - - - GMPR - grandmasterPriority Field Setting Register - 0x0E0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GMPR1 - grandmasterPriority1 Field Value SettingThese bits are used to set the value of the grandmasterPriority1 fields of Announce messages. - 16 - 23 - read-write - - - GMPR2 - grandmasterPriority2 Field Value SettingThese bits are used to set the value of the grandmasterPriority2 fields of Announce messages. - 0 - 7 - read-write - - - - - GMCQR - grandmasterClockQuality Field Setting Register - 0x0E4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GMCQR - These bits are used to set the value of the grandmasterClockQuality fields of Announce messages. The correspondence between bits and the grandmasterClockQuality fields is as listed below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 to b0: offsetScaledLogVariance - 0 - 31 - read-write - - - - - GMIDRU - grandmasterIdentity Field Setting Registers - 0x0E8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GMIDRU - These bits hold the setting for the higher-order 32 bits of the value of the grandmasterIdentity fields of Announce messages. - 0 - 31 - read-write - - - - - GMIDRL - grandmasterIdentity Field Setting Registers - 0x0EC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GMIDRL - These bits hold the setting for the lower-order 32 bits of the value of the grandmasterIdentity fields of Announce messages. - 0 - 31 - read-write - - - - - CUOTSR - currentUtcOffset/timeSource Field Setting Register - 0x0F0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CUTO - currentUtcOffset Field SettingThese bits set the value of the currentUtcOffset fields of Announce messages. - 16 - 31 - read-write - - - TSRC - timeSource Field SettingThese bits set the value of the timeSource fields of Announce messages. - 0 - 7 - read-write - - - - - SRR - stepsRemoved Field Setting Register - 0x0F4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SRMV - stepsRemoved Field Value SettingThese bits set the value of the stepsRemoved fields of Announce messages. - 0 - 15 - read-write - - - - - PPMACRU - PTP-primary Message Destination MAC Address Setting Registers - 0x100 - 32 - read-write - 0x00011B19 - 0xFFFFFFFF - - - PPMACRU - These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-primary messages. - 0 - 23 - read-write - - - - - PPMACRL - PTP-primary Message Destination MAC Address Setting Registers - 0x104 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PPMACRL - These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-primary messages. - 0 - 23 - read-write - - - - - PDMACRU - PTP-pdelay Message MAC Address Setting Registers - 0x108 - 32 - read-write - 0x000180C2 - 0xFFFFFFFF - - - PDMACRU - These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-pdelay messages. - 0 - 23 - read-write - - - - - PDMACRL - PTP-pdelay Message MAC Address Setting Registers - 0x10C - 32 - read-write - 0x0000000E - 0xFFFFFFFF - - - PDMACRL - These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-pdelay messages. - 0 - 23 - read-write - - - - - PETYPER - PTP Message EtherType Setting Register - 0x110 - 32 - read-write - 0x000088F7 - 0xFFFFFFFF - - - TYPE - PTP Message EtherType Value SettingThese bits hold the setting for the EtherType field value for frames in the Ethernet II format. - 0 - 15 - read-write - - - - - PPIPR - PTP-primary Message Destination IP Address Setting Register - 0x120 - 32 - read-write - 0xE0000181 - 0xFFFFFFFF - - - PPIPR - These bits hold the setting for the destination IP address for PTPprimary messages. - 0 - 31 - read-write - - - - - PDIPR - PTP-pdelay Message Destination IP Address Setting Register - 0x124 - 32 - read-write - 0xE000006B - 0xFFFFFFFF - - - PDIPR - These bits hold the setting for the destination IP address for PTPpdelay messages. - 0 - 31 - read-write - - - - - PETOSR - PTP Event Message TOS Setting Register - 0x128 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - EVTO - PTP Event Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP event messages. - 0 - 7 - read-write - - - - - PGTOSR - PTP general Message TOS Setting Register - 0x12C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GETO - PTP general Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP general messages. - 0 - 7 - read-write - - - - - PPTTLR - PTP-primary Message TTL Setting Register - 0x130 - 32 - read-write - 0x00000080 - 0xFFFFFFFF - - - PRTL - PTP-primary Message TTL Field Value SettingThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-primary messages. - 0 - 7 - read-write - - - - - PDTTLR - PTP-pdelay Message TTL Setting Register - 0x134 - 32 - read-write - 0x00000001 - 0xFFFFFFFF - - - PDTL - PTP-pdelay Message TTL Field ValueThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-pdelay messages. - 0 - 7 - read-write - - - - - PEUDPR - PTP Event Message UDP Destination Port Number Setting Register - 0x138 - 32 - read-write - 0x0000013F - 0xFFFFFFFF - - - EVUPT - PTP Event Message Destination Port Number SettingThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP event messages. - 0 - 15 - read-write - - - - - PGUDPR - PTP general Message UDP Destination Port Number Setting Register - 0x13C - 32 - read-write - 0x00000140 - 0xFFFFFFFF - - - GEUPT - PTP general Message Destination Port NumberThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP general messages. - 0 - 15 - read-write - - - - - FFLTR - Frame Reception Filter Setting Register - 0x140 - 32 - read-write - 0x00010000 - 0xFFFFFFFF - - - EXTPRM - Extended Promiscuous ModeSetting - 16 - 16 - read-write - - - 0 - Normal operation (unicast frames addressed to the EPTPC are received, filtering of PTP frames is applied, multicast filtering is applied, and all broadcast frames are received). - #0 - - - 1 - Extended promiscuous mode (all frames are received) - #1 - - - - - ENB - Reception Filter EnableNOTE: The setting of these bits is only effective when EXTPRM=0. - 2 - 2 - read-write - - - 0 - Filtering is disabled (all multicast frames are received). - #0 - - - 1 - See PRT and SEL bit. - #1 - - - - - PRT - Frame Reception EnableNOTE: The setting of these bits is only effective when EXTPRM=0 and ENB=1. - 1 - 1 - read-write - - - 0 - Do not receive multicast frames. - #0 - - - 1 - See SEL bit. - #1 - - - - - SEL - Receive MAC Address SelectNOTE: The setting of these bits is only effective when EXTPRM=0, ENB=1and RPT=1. - 0 - 0 - read-write - - - 0 - Only receive multicast frames matching the MAC address setting in FMAC0R(U/L). - #0 - - - 1 - Only receive multicast frames matching the MAC address setting in FMAC1R(U/L). - #1 - - - - - - - DASYMRU - Asymmetric Delay Setting Registers - 0x1C0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DASYMRU - These bits hold the setting for the higher-order 16 bits of the asymmetric delay value. - 0 - 15 - read-write - - - - - DASYMRL - Asymmetric Delay Setting Registers - 0x1C4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - DASYMRL - These bits hold the setting for the lower-order 32 bits of the asymmetric delay value. - 0 - 31 - read-write - - - - - TSLATR - Timestamp Latency Setting Register - 0x1C8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - INGP - Output Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the output ports. - 16 - 31 - read-write - - - EGP - Input Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the input ports. - 0 - 15 - read-write - - - - - SYCONFR - SYNFP Operation Setting Register - 0x1CC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TCMOD - TC Mode Setting - 20 - 20 - read-write - - - 0 - E2E TC - #0 - - - 1 - P2P TC - #1 - - - - - FILDIS - Receive Message domainNumber Filter Disable - 16 - 16 - read-write - - - 0 - Filtering conditions for the reception of PTP messages include comparison with the domainNumber field. - #0 - - - 1 - Filtering conditions for the reception of PTP messages do not include comparison with the domainNumber field. - #1 - - - - - SBDIS - Sync Message Transmission Bandwidth Securing Disable - 12 - 12 - read-write - - - 0 - Securing of the bandwidth for the transmission of SYNC messages is enabled (transfer by the EDMAC is given lower priority). - #0 - - - 1 - Securing of the bandwidth for the transmission of SYNC messages is disabled (transfer by the EDMAC is given higher priority). - #1 - - - - - TCYC - PTP Message Transmission Interval SettingThese bits are used to set the time from the completion of one transmission to the start of the next in cycles of the transmission clock. A value n in these bits means that a transmission interval of n cycles will be secured.No interval is secured if the setting is 00h.We recommend the setting 28h (40 cycles). - 0 - 7 - read-write - - - - - SYFORMR - SYNFP Frame Format Setting Register - 0x1D0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FORM1 - Ethernet Frame Format Setting - 1 - 1 - read-write - - - 0 - Set this bit to 0 (Ethernet II frame format). - #0 - - - 1 - Setting prohibited - #1 - - - - - FORM0 - Ethernet/UDP Encapsulation - 0 - 0 - read-write - - - 0 - PTP directly over Ethernet - #0 - - - 1 - PTP over UDP/IPv4 - #1 - - - - - - - RSTOUTR - Response Message Reception Timeout Register - 0x1D4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RSTOUTR - Response Message Reception Timeout Time SettingA response message not being received within n x 1024 (ns), where n is the setting, is judged to represent a timeout. - 0 - 31 - read-write - - - - - - - R_ETHERC_EPTPC1 - 0x40065C00 - - - R_ETHERC_EPTPC_CFG - Ethernet PTP Configuration - 0x40064500 - - 0x00000000 - 0x00C - registers - - - - PTRSTR - EPTPC Reset Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RESET - EPTPC Software Reset - 0 - 0 - read-write - - - 0 - Do not reset the EPTPC - #0 - - - 1 - Reset the EPTPC. Do not access the EPTPC-related registers other than this register while a software reset is being issued. - #1 - - - - - - - STCSELR - STCA Clock Select Register - 0x04 - 32 - read-write - 0x00000006 - 0xFFFFFFFF - - - SCLKSEL - STCA Clock Select - 8 - 10 - read-write - - - 000 - PCLKA clock divided by 1 to 6 - #000 - - - 010 - Input clock from the REF50CK0 pin - #010 - - - 011 - Input clock from the REF50CK1 pin - #011 - - - others - Settings other than above are prohibited. - true - - - - - SCLKDIV - PCLKA Clock Frequency Division - 0 - 2 - read-write - - - 001 - 1 - #001 - - - 010 - 1/2 - #010 - - - 011 - 1/3 - #011 - - - 100 - 1/4 - #100 - - - 101 - 1/5 - #101 - - - 110 - 1/6 - #110 - - - others - Settings other than above are prohibited. - true - - - - - - - BYPASS - Bypass 1588 module Register - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BYPASS1 - Bypass 1588 module for Ether 1ch - 16 - 16 - read-write - - - 0 - to use 1588 module for Ether 1ch - #0 - - - 1 - to bypass 1588 module for Ether 1ch - #1 - - - - - BYPASS0 - Bypass 1588 module for Ether 0ch - 0 - 0 - read-write - - - 0 - to use 1588 module for Ether 0ch - #0 - - - 1 - to bypass 1588 module for Ether 0ch - #1 - - - - - - - - - R_ETHERC_EPTPC_COMMON - Ethernet PTP Controller Common - 0x40065000 - - 0x00000000 - 0x008 - registers - - - 0x00000010 - 0x008 - registers - - - 0x00000040 - 0x008 - registers - - - 0x00000050 - 0x00C - registers - - - 0x00000060 - 0x010 - registers - - - 0x00000080 - 0x008 - registers - - - 0x00000090 - 0x010 - registers - - - 0x000000B0 - 0x00C - registers - - - 0x00000124 - 0x020 - registers - - - 0x00000170 - 0x00C - registers - - - 0x00000210 - 0x00C - registers - - - 0x000002D0 - 0x00C - registers - - - 0x00000300 - 0x060 - registers - - - 0x0000037C - 0x04 - registers - - - 0x00000400 - 0x008 - registers - - - 0x00000410 - 0x014 - registers - - - 0x00000430 - 0x008 - registers - - - - 6 - 0x10 - TM[%s] - Timer Setting Registers - 0x300 - - STTRU - Timer Start Time Setting Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TMSTTRU - These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds. - 0 - 31 - read-write - - - - - STTRL - Timer Start Time Setting Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TMSTTRL - These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds. - 0 - 31 - read-write - - - - - CYCR - Timer Cycle Setting Registers - 0x08 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TMCYCR - These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock. - 0 - 29 - read-write - - - - - PLSR - Timer Pulse Width Setting Register - 0x0C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TMPLSR - These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock. - 0 - 28 - read-write - - - - - - 2 - 0x8 - PR[%s] - Local MAC Address Registers - 0x410 - - MACRU - Channel Local MAC Address Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRMACRU - These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0. - 0 - 23 - read-write - - - - - MACRL - Channel Local MAC Address Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PRMACRL - These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0. - 0 - 23 - read-write - - - - - - MIESR - MINT Interrupt Source Status Register - 0x000 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CYC5 - Pulse Output Timer 5 Rising Edge Detection Flag - 21 - 21 - read-write - oneToClear - modify - - - 0 - A rising edge in the periodic pulse signal from pulse output timer 5 is not detected. - #0 - - - 1 - A rising edge in the periodic pulse signal from pulse output timer 5 is detected. - #1 - - - - - CYC4 - Pulse Output Timer 4 Rising Edge Detection Flag - 20 - 20 - read-write - oneToClear - modify - - - 0 - A rising edge in the periodic pulse signal from pulse output timer 4 is not detected. - #0 - - - 1 - A rising edge in the periodic pulse signal from pulse output timer 4 is detected. - #1 - - - - - CYC3 - Pulse Output Timer 3 Rising Edge Detection Flag - 19 - 19 - read-write - oneToClear - modify - - - 0 - A rising edge in the periodic pulse signal from pulse output timer 3 is not detected. - #0 - - - 1 - A rising edge in the periodic pulse signal from pulse output timer 3 is detected. - #1 - - - - - CYC2 - Pulse Output Timer 2 Rising Edge Detection Flag - 18 - 18 - read-write - oneToClear - modify - - - 0 - A rising edge in the periodic pulse signal from pulse output timer 2 is not detected. - #0 - - - 1 - A rising edge in the periodic pulse signal from pulse output timer 2 is detected. - #1 - - - - - CYC1 - Pulse Output Timer 1 Rising Edge Detection Flag - 17 - 17 - read-write - oneToClear - modify - - - 0 - A rising edge in the periodic pulse signal from pulse output timer 1 is not detected. - #0 - - - 1 - A rising edge in the periodic pulse signal from pulse output timer 1 is detected. - #1 - - - - - CYC0 - Pulse Output Timer 0 Rising Edge Detection Flag - 16 - 16 - read-write - oneToClear - modify - - - 0 - A rising edge in the periodic pulse signal from pulse output timer 0 is not detected. - #0 - - - 1 - A rising edge in the periodic pulse signal from pulse output timer 0 is detected. - #1 - - - - - PRC - PRC-TC Status Flag - 3 - 3 - read-only - - - 0 - No change in the state of the PRC-TC module - #0 - - - 1 - A change in the state of the PRC-TC module - #1 - - - - - SY1 - SYNFP1 Status Flag - 2 - 2 - read-only - - - 0 - No change in the state of the SYNFP1 module - #0 - - - 1 - A change in the state of the SYNFP1 module - #1 - - - - - SY0 - SYNFP0 Status Flag - 1 - 1 - read-only - - - 0 - No change in the state of the SYNFP0 module - #0 - - - 1 - A change in the state of the SYNFP0 module - #1 - - - - - ST - STCA Status Flag - 0 - 0 - read-only - - - 0 - No change in the state of the STCA module - #0 - - - 1 - A change in the state of the STCA module - #1 - - - - - - - MIEIPR - MINT Interrupt Request Permission Register - 0x004 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CYC5 - Pulse Output Timer 5 Rising Edge Detection Interrupt Request Permission - 21 - 21 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5. - #0 - - - 1 - Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5. - #1 - - - - - CYC4 - Pulse Output Timer 4 Rising Edge Detection Interrupt Request Permission - 20 - 20 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4. - #0 - - - 1 - Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4. - #1 - - - - - CYC3 - Pulse Output Timer 3 Rising Edge Detection Interrupt Request Permission - 19 - 19 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3. - #0 - - - 1 - Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3. - #1 - - - - - CYC2 - Pulse Output Timer 2 Rising Edge Detection Interrupt Request Permission - 18 - 18 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2. - #0 - - - 1 - Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2. - #1 - - - - - CYC1 - Pulse Output Timer 1 Rising Edge Detection Interrupt Request Permission - 17 - 17 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1. - #0 - - - 1 - Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1. - #1 - - - - - CYC0 - Pulse Output Timer 0 Rising Edge Detection Interrupt Request Permission - 16 - 16 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0. - #0 - - - 1 - Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0. - #1 - - - - - PRC - PRC-TC Status Interrupt Request Permission - 3 - 3 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests by the PRC-TC status flag. - #0 - - - 1 - Permits the generation of MINT interrupt requests by the PRCTC status flag. - #1 - - - - - SY1 - SYNFP1 Status Interrupt Request Permission - 2 - 2 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests by the SYNFP1 status flag. - #0 - - - 1 - Permits the generation of MINT interrupt requests by the SYNFP1 status flag. - #1 - - - - - SY0 - SYNFP0 Status Interrupt Request Permission - 1 - 1 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests by the SYNFP0 status flag. - #0 - - - 1 - Permits the generation of MINT interrupt requests by the SYNFP0 status flag. - #1 - - - - - ST - STCA Status Interrupt Request Permission - 0 - 0 - read-write - - - 0 - Prohibits the generation of MINT interrupt requests by the STCA status flag. - #0 - - - 1 - Permits the generation of MINT interrupt requests by the STCA status flag. - #1 - - - - - - - ELIPPR - ELC Output/ETHER_IPLS Interrupt Request Permission Register - 0x010 - 32 - read-write - 0x00003F3F - 0xFFFFFFFF - - - PLSN - Pulse Output Timer Falling Edge Detection IPLS Interrupt Request Permission - 24 - 24 - read-write - - - 0 - Prohibits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer. - #0 - - - 1 - Permits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer. - #1 - - - - - PLSP - Pulse Output Timer Rising Edge Detection IPLS Interrupt Request Permission - 16 - 16 - read-write - - - 0 - Prohibits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer. - #0 - - - 1 - Permits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer. - #1 - - - - - CYCN5 - Pulse Output Timer 5 Falling Edge Detection Event Output Enable - 13 - 13 - read-write - - - 0 - Falling edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals. - #0 - - - 1 - Falling edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals. - #1 - - - - - CYCN4 - Pulse Output Timer 4 Falling Edge Detection Event Output Enable - 12 - 12 - read-write - - - 0 - Falling edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals. - #0 - - - 1 - Falling edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals. - #1 - - - - - CYCN3 - Pulse Output Timer 3 Falling Edge Detection Event Output Enable - 11 - 11 - read-write - - - 0 - Falling edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals. - #0 - - - 1 - Falling edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals. - #1 - - - - - CYCN2 - Pulse Output Timer 2 Falling Edge Detection Event Output Enable - 10 - 10 - read-write - - - 0 - Falling edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals. - #0 - - - 1 - Falling edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals. - #1 - - - - - CYCN1 - Pulse Output Timer 1 Falling Edge Detection Event Output Enable - 9 - 9 - read-write - - - 0 - Falling edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals. - #0 - - - 1 - Falling edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals. - #1 - - - - - CYCN0 - Pulse Output Timer 0 Falling Edge Detection Event Output Enable - 8 - 8 - read-write - - - 0 - Falling edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals. - #0 - - - 1 - Falling edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals. - #1 - - - - - CYCP5 - Pulse Output Timer 5 Rising Edge Detection Event Output Enable - 5 - 5 - read-write - - - 0 - Rising edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals. - #0 - - - 1 - Rising edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals. - #1 - - - - - CYCP4 - Pulse Output Timer 4 Rising Edge Detection Event Output Enable - 4 - 4 - read-write - - - 0 - Rising edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals. - #0 - - - 1 - Rising edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals. - #1 - - - - - CYCP3 - Pulse Output Timer 3 Rising Edge Detection Event Output Enable - 3 - 3 - read-write - - - 0 - Rising edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals. - #0 - - - 1 - Rising edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals. - #1 - - - - - CYCP2 - Pulse Output Timer 2 Rising Edge Detection Event Output Enable - 2 - 2 - read-write - - - 0 - Rising edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals. - #0 - - - 1 - Rising edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals. - #1 - - - - - CYCP1 - Pulse Output Timer 1 Rising Edge Detection Event Output Enable - 1 - 1 - read-write - - - 0 - Rising edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals. - #0 - - - 1 - Rising edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals. - #1 - - - - - CYCP0 - Pulse Output Timer 0 Rising Edge Detection Event Output Enable - 0 - 0 - read-write - - - 0 - Rising edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals. - #0 - - - 1 - Rising edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals. - #1 - - - - - - - ELIPACR - ELC Output/IPLS Interrupt Permission Automatic Clearing Register - 0x014 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PLSN - ELIPPR.PLSN Bit Automatic Clearing - 24 - 24 - read-write - - - 0 - Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. - #0 - - - 1 - Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. - #1 - - - - - PLSP - ELIPPR.PLSP Bit Automatic Clearing - 16 - 16 - read-write - - - 0 - Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. - #0 - - - 1 - Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. - #1 - - - - - CYCN5 - ELIPPR.CYCN5 Bit Automatic Clearing - 13 - 13 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. - #1 - - - - - CYCN4 - ELIPPR.CYCN4 Bit Automatic Clearing - 12 - 12 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. - #1 - - - - - CYCN3 - ELIPPR.CYCN3 Bit Automatic Clearing - 11 - 11 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. - #1 - - - - - CYCN2 - ELIPPR.CYCN2 Bit Automatic Clearing - 10 - 10 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. - #1 - - - - - CYCN1 - ELIPPR.CYCN1 Bit Automatic Clearing - 9 - 9 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. - #1 - - - - - CYCN0 - ELIPPR.CYCN0 Bit Automatic Clearing - 8 - 8 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. - #1 - - - - - CYCP5 - ELIPPR.CYCP5 Bit Automatic Clearing - 5 - 5 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. - #1 - - - - - CYCP4 - ELIPPR.CYCP4 Bit Automatic Clearing - 4 - 4 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. - #1 - - - - - CYCP3 - ELIPPR.CYCP3 Bit Automatic Clearing - 3 - 3 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. - #1 - - - - - CYCP2 - ELIPPR.CYCP2 Bit Automatic Clearing - 2 - 2 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. - #1 - - - - - CYCP1 - ELIPPR.CYCP1 Bit Automatic Clearing - 1 - 1 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. - #1 - - - - - CYCP0 - ELIPPR.CYCP0 Bit Automatic Clearing - 0 - 0 - read-write - - - 0 - Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. - #0 - - - 1 - Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. - #1 - - - - - - - STSR - STCA Status Register - 0x040 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - W10D - Worst 10 Acquisition Completion Flag - 4 - 4 - read-write - oneToClear - - - 0 - Ten worst values not acquired yet - #0 - - - 1 - Ten worst values acquired - #1 - - - - - SYNTOUT - Sync Message Reception Timeout Detection Flag - 3 - 3 - read-write - oneToClear - - - 0 - Sync message reception timeout not detected - #0 - - - 1 - Sync message reception timeout detected - #1 - - - - - SYNCOUT - Synchronization Loss Detection Flag - 1 - 1 - read-write - oneToClear - - - 0 - Loss of synchronization not detected - #0 - - - 1 - Loss of synchronization detected - #1 - - - - - SYNC - Synchronized State Detection Flag - 0 - 0 - read-write - oneToClear - - - 0 - Synchronization not detected - #0 - - - 1 - Synchronization detected - #1 - - - - - - - STIPR - STCA Status Notification Permission Register - 0x044 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - W10D - W10D Status Notification Enable - 4 - 4 - read-write - - - 0 - Disable notification of the STSR.W10D state - #0 - - - 1 - Enable notification of the STSR.W10D state - #1 - - - - - SYNTOUT - SYNTOUT Status Notification Enable - 3 - 3 - read-write - - - 0 - Disable notification of the STSR.SYNTOUT state - #0 - - - 1 - Enable notification of the STSR.SYNTOUT state - #1 - - - - - SYNCOUT - SYNCOUT Status Notification Enable - 1 - 1 - read-write - - - 0 - Disable notification of the STSR.SYNCOUT state - #0 - - - 1 - Enable notification of the STSR.SYNCOUT state - #1 - - - - - SYNC - SYNC Status Notification Enable - 0 - 0 - read-write - - - 0 - Disable notification of the STSR.SYNC state - #0 - - - 1 - Enable notification of the STSR.SYNC state - #1 - - - - - - - STCFR - STCA Clock Frequency Setting Register - 0x050 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - STCF - STCA Clock Frequency - 0 - 1 - read-write - - - 00 - 20MHz - #00 - - - 01 - 25MHz - #01 - - - 10 - 50MHz - #10 - - - 11 - 100 MHz - #11 - - - - - - - STMR - STCA Operating Mode Register - 0x054 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ALEN1 - Alarm Detection Enable 1 - 29 - 29 - read-write - - - 0 - The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt. - #0 - - - 1 - The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt. - #1 - - - - - ALEN0 - Alarm Detection Enable 0 - 28 - 28 - read-write - - - 0 - The STSR.SYNC or SYNCOUT flag is not set to 1 on detection of synchronization or loss of synchronization. - #0 - - - 1 - The STSR.SYNC or SYNCOUT flag is set to 1 on detection of synchronization or loss of synchronization. - #1 - - - - - DVTH - Synchronization Loss Detection Threshold Setting - 20 - 23 - read-write - - - 0x0 - None - 0x0 - - - others - (DVTH) time - true - - - - - SYTH - Synchronized State Detection Threshold Setting - 16 - 19 - read-write - - - 0x0 - None - 0x0 - - - others - (SYTH) time - true - - - - - W10S - Worst 10 Acquisition Control Select - 15 - 15 - read-write - - - 0 - Measurement is started by hardware and the value acquired in the PW10VR or MW10R register is used as the limit for filtering. - #0 - - - 1 - Measurement is started by the GETW10R.GW10 bit. Also, the value set in the PLIMITR or MLIMITR register is used as the limit for filtering. - #1 - - - - - CMOD - Time Synchronization Correction Mode - 13 - 13 - read-write - - - 0 - Mode 1 - #0 - - - 1 - Mode 2 - #1 - - - - - WINT - Worst 10 Acquisition Time - 0 - 7 - read-write - - - 0x00 - The worst 10 values are not acquired. - 0x00 - - - others - Sync message reception: (WINT) time - true - - - - - - - SYNTOR - Sync Message Reception Timeout Register - 0x058 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYNTOR - A Sync message not being received within 1024 x n (ns), where n is the setting, leads to a timeout for reception of Sync messages, leading to the STSR.SYNTOUT flag being set to 1. - 0 - 31 - read-write - - - - - IPTSELR - IPLS Interrupt Request Timer Select Register - 0x060 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - IPTSEL5 - Pulse Output Timer 5 Select - 5 - 5 - read-write - - - 0 - Pulse output timer 5 is not selected as a source of IPLS interrupt requests. - #0 - - - 1 - Pulse output timer 5 is selected as a source of IPLS interrupt requests. - #1 - - - - - IPTSEL4 - Pulse Output Timer 4 Select - 4 - 4 - read-write - - - 0 - Pulse output timer 4 is not selected as a source of IPLS interrupt requests. - #0 - - - 1 - Pulse output timer 4 is selected as a source of IPLS interrupt requests. - #1 - - - - - IPTSEL3 - Pulse Output Timer 3 Select - 3 - 3 - read-write - - - 0 - Pulse output timer 3 is not selected as a source of IPLS interrupt requests. - #0 - - - 1 - Pulse output timer 3 is selected as a source of IPLS interrupt requests. - #1 - - - - - IPTSEL2 - Pulse Output Timer 2 Select - 2 - 2 - read-write - - - 0 - Pulse output timer 2 is not selected as a source of IPLS interrupt requests. - #0 - - - 1 - Pulse output timer 2 is selected as a source of IPLS interrupt requests. - #1 - - - - - IPTSEL1 - Pulse Output Timer 1 Select - 1 - 1 - read-write - - - 0 - Pulse output timer 1 is not selected as a source of IPLS interrupt requests. - #0 - - - 1 - Pulse output timer 1 is selected as a source of IPLS interrupt requests. - #1 - - - - - IPTSEL0 - Pulse Output Timer 0 Select - 0 - 0 - read-write - - - 0 - Pulse output timer 0 is not selected as a source of IPLS interrupt requests. - #0 - - - 1 - Pulse output timer 0 is selected as a source of IPLS interrupt requests. - #1 - - - - - - - MITSELR - MINT Interrupt Request Timer Select Register - 0x064 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MINTEN5 - Pulse Output Timer 5 MINT Interrupt Output Enable - 5 - 5 - read-write - - - 0 - Output of rising edges by pulse output timer 5 is not reflected by the MIESR.CYC5 flag as a MINT interrupt source. - #0 - - - 1 - Output of rising edges by pulse output timer 5 is reflected by the MIESR.CYC5 flag as a MINT interrupt source. - #1 - - - - - MINTEN4 - Pulse Output Timer 4 MINT Interrupt Output Enable - 4 - 4 - read-write - - - 0 - Output of rising edges by pulse output timer 4 is not reflected by the MIESR.CYC4 flag as a MINT interrupt source. - #0 - - - 1 - Output of rising edges by pulse output timer 4 is reflected by the MIESR.CYC4 flag as a MINT interrupt source. - #1 - - - - - MINTEN3 - Pulse Output Timer 3 MINT Interrupt Output Enable - 3 - 3 - read-write - - - 0 - Output of rising edges by pulse output timer 3 is not reflected by the MIESR.CYC3 flag as a MINT interrupt source. - #0 - - - 1 - Output of rising edges by pulse output timer 3 is reflected by the MIESR.CYC3 flag as a MINT interrupt source. - #1 - - - - - MINTEN2 - Pulse Output Timer 2 MINT Interrupt Output Enable - 2 - 2 - read-write - - - 0 - Output of rising edges by pulse output timer 2 is not reflected by the MIESR.CYC2 flag as a MINT interrupt source. - #0 - - - 1 - Output of rising edges by pulse output timer 2 is reflected by the MIESR.CYC2 flag as a MINT interrupt source. - #1 - - - - - MINTEN1 - Pulse Output Timer 1 MINT Interrupt Output Enable - 1 - 1 - read-write - - - 0 - Output of rising edges by pulse output timer 1 is not reflected by the MIESR.CYC1 flag as a MINT interrupt source. - #0 - - - 1 - Output of rising edges by pulse output timer 1 is reflected by the MIESR.CYC1 flag as a MINT interrupt source. - #1 - - - - - MINTEN0 - Pulse Output Timer 0 MINT Interrupt Output Enable - 0 - 0 - read-write - - - 0 - Output of rising edges by pulse output timer 0 is not reflected by the MIESR.CYC0 flag as a MINT interrupt source. - #0 - - - 1 - Output of rising edges by pulse output timer 0 is reflected by the MIESR.CYC0 flag as a MINT interrupt source. - #1 - - - - - - - ELTSELR - ELC Output Timer Select Register - 0x068 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ELTDIS5 - Pulse Output Timer 5 Event Generation Disable - 5 - 5 - read-write - - - 0 - Pulse output timer 5 is used for the generation of event signals for the ELC. - #0 - - - 1 - Pulse output timer 5 is not used for the generation of event signals for the ELC. - #1 - - - - - ELTDIS4 - Pulse Output Timer 4 Event Generation Disable - 4 - 4 - read-write - - - 0 - Pulse output timer 4 is used for the generation of event signals for the ELC. - #0 - - - 1 - Pulse output timer 4 is not used for the generation of event signals for the ELC. - #1 - - - - - ELTDIS3 - Pulse Output Timer 3 Event Generation Disable - 3 - 3 - read-write - - - 0 - Pulse output timer 3 is used for the generation of event signals for the ELC. - #0 - - - 1 - Pulse output timer 3 is not used for the generation of event signals for the ELC. - #1 - - - - - ELTDIS2 - Pulse Output Timer 2 Event Generation Disable - 2 - 2 - read-write - - - 0 - Pulse output timer 2 is used for the generation of event signals for the ELC. - #0 - - - 1 - Pulse output timer 2 is not used for the generation of event signals for the ELC. - #1 - - - - - ELTDIS1 - Pulse Output Timer 1 Event Generation Disable - 1 - 1 - read-write - - - 0 - Pulse output timer 1 is used for the generation of event signals for the ELC. - #0 - - - 1 - Pulse output timer 1 is not used for the generation of event signals for the ELC. - #1 - - - - - ELTDIS0 - Pulse Output Timer 0 Event Generation Disable - 0 - 0 - read-write - - - 0 - Pulse output timer 0 is used for the generation of event signals for the ELC. - #0 - - - 1 - Pulse output timer 0 is not used for the generation of event signals for the ELC. - #1 - - - - - - - STCHSELR - Time Synchronization Channel Select Register - 0x06C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYSEL - Timer Information Input SelectNOTE: Do not change the value of this bit while the SYNSTARTR.STR bit is 1. - 0 - 0 - read-write - - - 0 - Time information from synchronization from the SYNFP0 module is used. - #0 - - - 1 - Time information from synchronization from the SYNFP1 module is used. - #1 - - - - - - - SYNSTARTR - Slave Time Synchronization Start Register - 0x080 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - STR - Slave Time Synchronization Control - 0 - 0 - read-write - - - 0 - Slave time synchronization is stopped. - #0 - - - 1 - Slave time synchronization is started. - #1 - - - - - - - LCIVLDR - Local Time Counter Initial Value Load Directive Register - 0x084 - 32 - write-only - 0x00000000 - 0xFFFFFFFF - - - LOAD - Local Time Counter Initial Value Load Directive - 0 - 0 - write-only - - - 0 - The initial value is not loaded into the local time counter. - #0 - - - 1 - The initial value is loaded into the local time counter. - #1 - - - - - - - SYNTDARU - Synchronization Loss Detection Threshold Registers - 0x090 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYNTDARU - These bits hold the setting for the higher-order 32 bits of the threshold for detection of loss of synchronization. - 0 - 31 - read-write - - - - - SYNTDARL - Synchronization Loss Detection Threshold Registers - 0x094 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYNTDARL - These bits hold the setting for the lower-order 32 bits of the threshold for detection of loss of synchronization. - 0 - 31 - read-write - - - - - SYNTDBRU - Synchronization Detection Threshold Registers - 0x098 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYNTDBRU - These bits hold the setting for the higher-order 32 bits of the threshold for detection of synchronization. - 0 - 31 - read-write - - - - - SYNTDBRL - Synchronization Detection Threshold Registers - 0x09C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SYNTDBRL - These bits hold the setting for the lower-order 32 bits of the threshold for detection of synchronization. - 0 - 31 - read-write - - - - - LCIVRU - Local Time Counter Initial Value Registers - 0x0B0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - LCIVRU - These bits hold the setting for the higher-order 16 bits of the integer portion of the initial value for the local timer counter. - 0 - 15 - read-write - - - - - LCIVRM - Local Time Counter Initial Value Registers - 0x0B4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - LCIVRM - These bits hold the setting for the lower-order 32 bits of the integer portion of the initial value for the local timer counter. - 0 - 31 - read-write - - - - - LCIVRL - Local Time Counter Initial Value Registers - 0x0B8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - LCIVRL - These bits hold the setting for the fractional portion of the initial value of the local timer counter in nanoseconds. - 0 - 31 - read-write - - - - - GETW10R - Worst 10 Acquisition Directive Register - 0x124 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - GW10 - Worst 10 Acquisition Directive - 0 - 0 - read-write - - - 0 - The worst-10 values are not acquired. - #0 - - - 1 - Starts acquisition of the worst-10 values. - #1 - - - - - - - PLIMITRU - Positive Gradient Limit Registers - 0x128 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PLIMITRU - These bits hold the setting for the higher-order 31 bits of the limit for the positive gradient. - 0 - 30 - read-write - - - - - PLIMITRM - Positive Gradient Limit Registers - 0x12C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PLIMITRM - These bits hold the setting for the middle-order 32 bits of the limit for the positive gradient. - 0 - 31 - read-write - - - - - PLIMITRL - Positive Gradient Limit Registers - 0x130 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PLIMITRL - These bits hold the setting for the lower-order 32 bits of the limit for the positive gradient. - 0 - 31 - read-write - - - - - MLIMITRU - Negative Gradient Limit Registers - 0x134 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MLIMITRU - These bits hold the setting for the higher-order 31 bits of the limit for the negative gradient. - 0 - 30 - read-write - - - - - MLIMITRM - Negative Gradient Limit Registers - 0x138 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MLIMITRM - These bits hold the setting for the middle-order 32 bits of the limit for the negative gradient. - 0 - 31 - read-write - - - - - MLIMITRL - Negative Gradient Limit Registers - 0x13C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - MLIMITRL - These bits hold the setting for the lower-order 32 bits of the limit for the negative gradient. - 0 - 31 - read-write - - - - - GETINFOR - Statistical Information Retention Control Register - 0x140 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - INFO - Information Retention ControlNOTE: Once information fetching is directed, values of various statistical information read before completion of information fetching are not guaranteed. - 0 - 0 - read-write - - - 0 - Has no effects.(write) / Information retention is completed.(read) - #0 - - - 1 - Information is retained.(write) / Processing for information retention is in progress.(read) - #1 - - - - - - - LCCVRU - Local Time Counters - 0x170 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - LCCVRU - These bits are for reading the higher-order 16 bits of the integer portion of the local timer counter's value. - 0 - 15 - read-only - - - - - LCCVRM - Local Time Counters - 0x174 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - LCCVRM - These bits are for reading the lower-order 32 bits of the integer portion of the local timer counter's value. - 0 - 31 - read-only - - - - - LCCVRL - Local Time Counters - 0x178 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - LCCVRL - These bits are for reading the fractional portion of the local timer counter's value (in nanoseconds). - 0 - 31 - read-only - - - - - PW10VRU - Positive Gradient Worst 10 Value Registers - 0x210 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - PW10VRU - These bits are for reading the higher-order 32 bits of the positive gradient value. - 0 - 31 - read-only - - - - - PW10VRM - Positive Gradient Worst 10 Value Registers - 0x214 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - PW10VRM - These bits are for reading the middle-order 32 bits of the positive gradient value. - 0 - 31 - read-only - - - - - PW10VRL - Positive Gradient Worst 10 Value Registers - 0x218 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - PW10VRL - These bits are for reading the lower-order 32 bits of the positive gradient value. - 0 - 31 - read-only - - - - - MW10RU - Negative Gradient Worst 10 Value Registers - 0x2D0 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - MW10RU - These bits are for reading the higher-order 32 bits of the negative gradient value. - 0 - 31 - read-only - - - - - MW10RM - Negative Gradient Worst 10 Value Registers - 0x2D4 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - MW10RM - These bits are for reading the middle-order 32 bits of the negative gradient value. - 0 - 31 - read-only - - - - - MW10RL - Negative Gradient Worst 10 Value Registers - 0x2D8 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - MW10RL - These bits are for reading the lower-order 32 bits of the negative gradient value. - 0 - 31 - read-only - - - - - TMSTARTR - Timer Start Register - 0x37C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - EN5 - Pulse Output Timer 5 Start - 5 - 5 - read-write - - - 0 - Stops pulse output timer 5. - #0 - - - 1 - Starts pulse output timer 5. - #1 - - - - - EN4 - Pulse Output Timer 4 Start - 4 - 4 - read-write - - - 0 - Stops pulse output timer 4. - #0 - - - 1 - Starts pulse output timer 4. - #1 - - - - - EN3 - Pulse Output Timer 3 Start - 3 - 3 - read-write - - - 0 - Stops pulse output timer 3. - #0 - - - 1 - Starts pulse output timer 3. - #1 - - - - - EN2 - Pulse Output Timer 2 Start - 2 - 2 - read-write - - - 0 - Stops pulse output timer 2. - #0 - - - 1 - Starts pulse output timer 2. - #1 - - - - - EN1 - Pulse Output Timer 1 Start - 1 - 1 - read-write - - - 0 - Stops pulse output timer 1. - #0 - - - 1 - Starts pulse output timer 1. - #1 - - - - - EN0 - Pulse Output Timer 0 Start - 0 - 0 - read-write - - - 0 - Stops pulse output timer 0. - #0 - - - 1 - Starts pulse output timer 0. - #1 - - - - - - - PRSR - PRC-TC Status Register - 0x400 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - URE1 - Relay Packet Underflow Detection Flag 1 - 29 - 29 - read-write - oneToClear - - - 0 - No underflow in transfer of data from SYNFP0 to SYNFP1. - #0 - - - 1 - An underflow has been detected in transfer of data from SYNFP0 to SYNFP1. - #1 - - - - - URE0 - Relay Packet Underflow Detection Flag 0 - 28 - 28 - read-write - oneToClear - - - 0 - No underflow in transfer of data from SYNFP1 to SYNFP0. - #0 - - - 1 - An underflow has been detected in transfer of data from SYNFP1 to SYNFP0. - #1 - - - - - MACE - Originating MAC Address Mismatch Detection Flag - 8 - 8 - read-write - oneToClear - modify - - - 0 - A MAC address mismatch has not been detected. - #0 - - - 1 - A MAC address mismatch has been detected. - #1 - - - - - OVRE3 - Relay Packet Overflow Detection Flag 3 - 3 - 3 - read-write - oneToClear - modify - - - 0 - No overflow in transfer of data from SYNFP0 to SYNFP1. - #0 - - - 1 - An overflow has been detected in transfer of data from SYNFP0 to SYNFP1. - #1 - - - - - OVRE2 - Relay Packet Overflow Detection Flag 2 - 2 - 2 - read-write - oneToClear - modify - - - 0 - No overflow in transfer of data from SYNFP1 to SYNFP0. - #0 - - - 1 - An overflow has been detected in transfer of data from SYNFP1 to SYNFP0. - #1 - - - - - OVRE1 - Relay Packet Overflow Detection Flag 1 - 1 - 1 - read-write - oneToClear - modify - - - 0 - No overflow in transfer of data from SYNFP0 to PTPEDMAC. - #0 - - - 1 - An overflow has been detected in transfer of data from SYNFP0 to PTPEDMAC. - #1 - - - - - OVRE0 - Relay Packet Overflow Detection Flag 0 - 0 - 0 - read-write - oneToClear - modify - - - 0 - No overflow in transfer of data from SYNFP1 to PTPEDMAC. - #0 - - - 1 - An overflow has been detected in transfer of data from SYNFP1 to PTPEDMAC. - #1 - - - - - - - PRIPR - PRC-TC Status Notification Permission Register - 0x404 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - URE1 - PRSR.URE1 Status Notification Permission - 29 - 29 - read-write - - - 0 - Prohibits notification of the state of PRSR.URE1. - #0 - - - 1 - Permits notification of the state of PRSR.URE1. - #1 - - - - - URE0 - PRSR.URE0 Status Notification Permission - 28 - 28 - read-write - - - 0 - Prohibits notification of the state of PRSR.URE0. - #0 - - - 1 - Permits notification of the state of PRSR.URE0. - #1 - - - - - MACE - PRSR.MACE Status Notification Permission - 8 - 8 - read-write - - - 0 - Prohibits notification of the state of PRSR.MACE - #0 - - - 1 - Permits notification of the state of PRSR.MACE - #1 - - - - - OVRE3 - PRSR.OVRE3 Status Notification Permission - 3 - 3 - read-write - - - 0 - Prohibits notification of the state of PRSR.OVRE3. - #0 - - - 1 - Permits notification of the state of PRSR.OVRE3. - #1 - - - - - OVRE2 - PRSR.OVRE2 Status Notification Permission - 2 - 2 - read-write - - - 0 - Prohibits notification of the state of PRSR.OVRE2. - #0 - - - 1 - Permits notification of the state of PRSR.OVRE2. - #1 - - - - - OVRE1 - PRSR.OVRE1 Status Notification Permission - 1 - 1 - read-write - - - 0 - Prohibits notification of the state of PRSR.OVRE1. - #0 - - - 1 - Permits notification of the state of PRSR.OVRE1. - #1 - - - - - OVRE0 - PRSR.OVRE0 Status Notification Permission - 0 - 0 - read-write - - - 0 - Prohibits notification of the state of PRSR.OVRE0. - #0 - - - 1 - Permits notification of the state of PRSR.OVRE0. - #1 - - - - - - - TRNDISR - Packet Transmission Control Register - 0x420 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TDIS - Packet Transmission Control - 0 - 1 - read-write - - - 00 - PTP packets are transmitted through both Ethernet port 0 and Ethernet port 1. - #00 - - - 01 - PTP packets are only transmitted through Ethernet port 0. - #01 - - - 10 - PTP packets are only transmitted through Ethernet port 1. - #10 - - - 11 - Setting prohibited - #11 - - - - - - - TRNMR - Relay Mode Register - 0x430 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FWD1 - Channel 1 Relay Enable - 9 - 9 - read-write - - - 0 - Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 1 to port 0. - #0 - - - 1 - Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 1 to port 0. - #1 - - - - - FWD0 - Channel 0 Relay Enable - 8 - 8 - read-write - - - 0 - Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 0 to port 1. - #0 - - - 1 - Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 0 to port 1. - #1 - - - - - MOD - Cut-Through Mode - 0 - 0 - read-write - - - 0 - Store-and-forward - #0 - - - 1 - Cut-through - #1 - - - - - - - TRNCTTDR - Cut-Through Transfer Start Threshold Register - 0x434 - 32 - read-write - 0x00000060 - 0xFFFFFFFF - - - THVAL - FIFO Read Start ThresholdThreshold for starting to read data from the relay FIFO in cut-through mode (specified as the number of bytes)NOTE1: A value cannot be set in the lower-order 2 bits. These bits are fixed to 0.NOTE2: A value of less than 96 bytes cannot be set. - 0 - 10 - read-write - - - - - - - R_FACI_HP_CMD - Flash Application Command Interface Command-Issuing Area - 0x407E0000 - - 0x00000000 - 4 - registers - - - - FACI_CMD16 - FACI Command Issuing Area (halfword access) - 0 - 16 - read-write - 0x0000 - 0xFFFF - - - FACI_CMD8 - FACI Command Issuing Area (halfword access) - FACI_CMD16 - 0 - 8 - read-write - 0x00 - 0xFF - - - - - R_FACI_HP - Flash Application Command Interface - 0x407FE000 - - 0x00000000 - 0x100 - registers - - - - FASTAT - Flash Access Status - 0x0010 - 8 - read-write - 0x00 - 0xFF - - - CFAE - Code Flash Access Error - 7 - 7 - read-write - zeroToClear - modify - - - 0 - No code flash access error has occurred. - #0 - - - 1 - Code flash access error has occurred. - #1 - - - - - CMDLK - Command Lock - 4 - 4 - read-only - - - DFAE - Data Flash Access Error - 3 - 3 - read-write - zeroToClear - modify - - - ECRCT - 0 - 0 - read-only - - - - - FAEINT - Flash Access Error Interrupt Enable - 0x0014 - 8 - read-write - 0x99 - 0xFF - - - CFAEIE - Code Flash Access Error Interrupt Enable - 7 - 7 - read-write - - - 0 - Does not generate "intflerr" interrupt request when CFAE = "1". - #0 - - - 1 - Generates "intflerr" interrupt request when CFAE = "1". - #1 - - - - - CMDLKIE - Command Lock Interrupt Enable - 4 - 4 - read-write - - - 0 - Does not generate "intflerr" interrupt request when CMDLK = "1". - #0 - - - 1 - Generates "intflerr" interrupt request when CMDLK = "1". - #1 - - - - - DFAEIE - Data Flash Access Error Interrupt Enable - 3 - 3 - read-write - - - 0 - Does not generate "intflerr" interrupt request when DFAE = "1". - #0 - - - 1 - Generates "intflerr" interrupt request when DFAE = "1". - #1 - - - - - ECRCTIE - Error Correct Interrupt Enable - 0 - 0 - read-write - - - 0 - Does not generate "intflerr" interrupt request when ECRCT = "1". - #0 - - - 1 - Generates "intflerr" interrupt request when ECRCT = "1". - #1 - - - - - - - FRDYIE - Flash Ready Interrupt Enable - 0x0018 - 8 - read-write - 0x00 - 0xFF - - - FRDYIE - FRDY Interrupt Enable - 0 - 0 - read-write - - - 0 - Does not generate "intflend" interrupt request when FRDY is changed from "0" to "1". - #0 - - - 1 - Generates "intflend" interrupt request when FRDY is changed from "0" to "1". - #1 - - - - - - - FSADDR - Flash Start Address - 0x0030 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FSA - Start Address of Flash Sequencer Command Target Area - These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored. - 0 - 31 - read-write - - - others - Specifies start address for each command processing. - true - - - - - - - FEADDR - Flash End Address - 0x0034 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FEA - End Address of Flash Sequencer Command Target Area - Specifies end address of target area in "Blank Check" command. - These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored. - 0 - 31 - read-write - - - - - FSTATR - Flash Status - 0x0080 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - EBFULL - FDMYECC Buffer Full - 18 - 18 - read-only - - - 0 - ECC Buffer is not full - #0 - - - 1 - ECC Buffer is full - #1 - - - - - OTPDTCT - OTP Bit ECC 2-Bit Error Detection Monitoring Bit - 17 - 17 - read-only - - - 0 - No error has been detected. - #0 - - - 1 - An error has been detected. - #1 - - - - - OTPCRCT - OTP Bit ECC 1-Bit Error Correction Monitoring Bit - 16 - 16 - read-only - - - 0 - No error has been corrected. - #0 - - - 1 - An error has been corrected. - #1 - - - - - FRDY - Flash Ready - 15 - 15 - read-only - - - 0 - "Program", "DMA Program", "Erase", "Program" or "Erase" command suspension, "Forced Stop", "Blank Check", "Config Program", "Config Clear", "Lock Bit Program", "Lock Bit Read", or "OTP Program" is processing. - #0 - - - 1 - None of the above is in progress. - #1 - - - - - ILGLERR - Illegal Command Error - 14 - 14 - read-only - - - 0 - Flash sequencer has not detected any illegal command or illegal flash memory access. - #0 - - - 1 - Flash sequencer has detected an illegal command or illegal flash memory access - #1 - - - - - ERSERR - Erasure Error - 13 - 13 - read-only - - - 0 - Erasure processing has been completed successfully - #0 - - - 1 - An error has occurred during erasure - #1 - - - - - PRGERR - Programming Error - 12 - 12 - read-only - - - 0 - Programming has been completed successfully - #0 - - - 1 - An error has occurred during programming - #1 - - - - - SUSRDY - Suspend Ready - 11 - 11 - read-only - - - 0 - Flash sequencer cannot accept "Program/Erase Suspend" command. - #0 - - - 1 - Flash sequencer can accept "Program/Erase Suspend" command. - #1 - - - - - DBFULL - Data Buffer Full - 10 - 10 - read-only - - - 0 - Data Buffer is not full - #0 - - - - - ERSSPD - Erasure-Suspended Status - 9 - 9 - read-only - - - 0 - Flash sequencer is in status other than the below mentioned. - #0 - - - 1 - Flash sequencer is in erasure suspension process or erasure-suspended status. - #1 - - - - - PRGSPD - Programming-Suspended Status - 8 - 8 - read-only - - - 0 - Flash sequencer is in status other than the below mentioned. - #0 - - - 1 - Flash sequencer is in programming suspension process or programming-suspended status. - #1 - - - - - FCUERR - FCU Error - 7 - 7 - read-only - - - 0 - No error has occurred during FPCC processing. - #0 - - - 1 - An error has occurred during FPCC processing. - #1 - - - - - FHVEERR - "fhve" Error - 6 - 6 - read-only - - - 0 - No error has been detected. - #0 - - - 1 - An error has been detected. - #1 - - - - - CFGDTCT - Config Area ECC 2-Bit Error Detection Monitoring Bit - 5 - 5 - read-only - - - 0 - No error has been detected. - #0 - - - 1 - An error has been detected. - #1 - - - - - CFGCRCT - Config Area ECC 1-Bit Error Correction Monitoring Bit - 4 - 4 - read-only - - - 0 - No error has been corrected. - #0 - - - 1 - An error has been corrected. - #1 - - - - - TBLDTCT - Table Area ECC 2-Bit Error Detection Monitoring Bit - 3 - 3 - read-only - - - 0 - No error has been detected. - #0 - - - 1 - An error has been detected. - #1 - - - - - TBLCRCT - Table Area ECC 1-Bit Error Correction Monitoring Bit - 2 - 2 - read-only - - - 0 - No error has been corrected. - #0 - - - 1 - An error has been corrected. - #1 - - - - - - - FENTRYR - Program/Erase Mode Entry - 0x0084 - 16 - read-write - 0x0000 - 0xFFFF - - - KEY - KEY Code - 8 - 15 - write-only - - - 0xAA - Writing to the other bits in this register is enabled. - 0xAA - - - others - Writing to the other bits in this register is disabled. - true - - - - - FENTRYD - Data Flash P/E Mode Entry - These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. - Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits. - 7 - 7 - read-write - - - 0 - Data flash is in "Read Mode" - #0 - - - 1 - Data flash is in "P/E Mode" - #1 - - - - - FENTRYC - Code Flash P/E Mode Entry - These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. - Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits - 0 - 0 - read-write - - - 0 - Code flash is in "Read Mode" - #0 - - - 1 - Code flash is in "P/E Mode" - #1 - - - - - - - FSUINITR - Flash Sequencer Set-up Initialize - 0x008C - 16 - read-write - 0x0000 - 0xFFFF - - - KEY - KEY Code - 8 - 15 - write-only - - - 0x2D - Writing to the other bits in this register is enabled. - 0x2D - - - others - Writing to the other bits in this register is disabled. - true - - - - - SUINIT - Set-up Initialization - This bit can be written when FRDY bit of FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. - Writing to these bits is enabled only when this register is accessed in 16-bit size and H'2D is written to KEY bits. - 0 - 0 - read-write - - - 0 - Set-up registers keep its' value. - #0 - - - 1 - Set-up registers are initialized. - #1 - - - - - - - FCMDR - Flash Sequencer Command - 0x00A0 - 16 - read-only - 0x0000 - 0xFFFF - - - CMDR - Command Register - 8 - 15 - read-only - - - others - These bits store the latest command accepted by FACI. - true - - - - - PCMDR - Previous Command Register - 0 - 7 - read-only - - - others - These bits store previous command accepted by FACI. - true - - - - - - - FPESTAT - Program/Erase Error Status - 0x00C0 - 16 - read-only - 0x0000 - 0xFFFF - - - PEERRST - P/E Error Status - 0 - 7 - read-only - - - 0x01 - A write attempt made to an area protected by the lock bits - 0x01 - - - 0x02 - A write error caused by other source than the above - 0x02 - - - 0x11 - An erase attempt made to an area protected by the lock bits - 0x11 - - - 0x12 - An erase error caused by other source than the above - 0x12 - - - others - Reserved - true - - - - - - - FBCCNT - Blank Check Control - 0x00D0 - 8 - read-write - 0x00 - 0xFF - - - BCDIR - Blank Check Direction - 0 - 0 - read-write - - - 0 - Blank check is executed from smaller address to larger address. (Incremental mode) - #0 - - - 1 - Blank check is executed from larger address to smaller address. (Decremental mode) - #1 - - - - - - - FBCSTAT - Blank Check Status - 0x00D4 - 8 - read-only - 0x00 - 0xFF - - - BCST - Blank Check Status Bit - 0 - 0 - read-only - - - 0 - The target area is erased (blank). - #0 - - - 1 - The target area is filled with 0s and/or 1s. - #1 - - - - - - - FPSADDR - Programmed Area Start Address - 0x00D8 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - PSADR - Programmed Area Start Address - NOTE: Indicates address of the first programmed data which is found in "Blank Check" command execution. - 0 - 18 - read-only - - - - - FAWMON - Flash Access Window Monitor - 0x0DC - 32 - read-only - 0x00000000 - 0x00000000 - - - BTFLG - Flag of Start-Up area select for Boot Swap - 31 - 31 - read-only - - - 0 - The start-up area is the alternate area (sector 1) - #0 - - - 1 - The start-up area is the default area (sector 0) - #1 - - - - - FAWE - End Sector Address for Access Window - NOTE: These bits indicate the end sector address for setting the access window that is located in the configuration area. - 16 - 26 - read-only - - - FSPR - Protection Flag of programming the Access Window, Boot Flag and Temporary Boot Swap Control and "Config Clear" command execution - 15 - 15 - read-only - - - 0 - Protected state - #0 - - - 1 - Non-protected state - #1 - - - - - FAWS - Start Sector Address for Access Window - NOTE: These bits indicate the start sector address for setting the access window that is located in the configuration area. - 0 - 10 - read-only - - - - - FCPSR - FCU Process Switch - 0x00E0 - 16 - read-write - 0x0000 - 0xFFFF - - - ESUSPMD - Erasure-Suspended Mode - 0 - 0 - read-write - - - 0 - Suspension-priority mode - #0 - - - 1 - Erasure-priority mode - #1 - - - - - - - FPCKAR - Flash Sequencer Processing Clock Frequency Notification - 0x00E4 - 16 - read-write - 0x0000 - 0xFFFF - - - KEY - KEY Code - 8 - 15 - write-only - - - 0x1E - Writing to the other bits in this register is enabled. - 0x1E - - - others - Writing to the other bits in this register is disabled. - true - - - - - PCKA - Flash Sequencer Processing Clock Frequency - These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. - Writing to these bits is enabled only when this register is accessed in 16-bit size and H'1E is written to KEY bits. - 0 - 7 - read-write - - - others - Notifies operating frequency of clkf. - true - - - - - - - FSUACR - Flash Start-Up Area Control Register - 0x00E8 - 16 - read-write - 0x0000 - 0xFFFF - - - KEY - KEY Code - 8 - 15 - write-only - - - 0x66 - Writing to the other bits in this register is enabled. - 0x66 - - - others - Writing to the other bits in this register is disabled. - true - - - - - SAS - Start Up Area Select - These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. - Writing to these bits is enabled only when this register is accessed in 16-bit size and H'66 is written to KEY bits. - 0 - 1 - read-write - - - 10 - The start-up area is temporarily switched to the default area (sector 0) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit. - #10 - - - 11 - The start-up area is temporarily switched to the alternate area (sector 1) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit. - #11 - - - others - The start-up area is selected according to the start-up area setting of the configuration area (BTFLG bit). - true - - - - - - - - - R_FACI_LP - Flash Application Command Interface - 0x407EC000 - - 0x00000000 - 0x400 - registers - - - - DFLCTL - Flash P/E Mode Control Register - 0x090 - 8 - read-write - 0x00 - 0xFF - - - FPMCR - Flash P/E Mode Control Register - 0x100 - 8 - read-write - 0x08 - 0xFF - - - FMS2 - Flash Operating Mode Select 2. -Refer to the description of the FMS0 bit. - 7 - 7 - read-write - - - VLPE - Low-Voltage P/E Mode Enable - 6 - 6 - read-write - - - 0 - Low-voltage programming is disabled - #0 - - - 1 - Low-voltage programming is enabled - #1 - - - - - FMS1 - The bit to make data flash a programming mode -Refer to the description of the FMS0 bit. - 4 - 4 - read-write - - - RPDIS - Code Flash P/E Disable - 3 - 3 - read-write - - - 0 - The programming of the code flash is enabled - #0 - - - 1 - The programming of the code flash is disabled - #1 - - - - - FMS0 - Flash Operating Mode Select 0 -FMS2,1,0: - 000: Read mode - 011: Discharge mode 1 - 111: Discharge mode 2 - 101: Code Flash P/E mode - 010: Data flash P/E mode - Others: Setting prohibited. - 1 - 1 - read-write - - - - - FASR - Flash Area Select Register - 0x104 - 8 - read-write - 0x00 - 0xFF - - - EXS - Extra area select - 0 - 0 - read-write - - - 0 - User area or data area - #0 - - - 1 - Extra area - #1 - - - - - - - FSARL - Flash Processing Start Address Register L - 0x108 - 16 - read-write - 0x0000 - 0xFFFF - - - FSAR15_0 - Start address - 0 - 15 - read-write - - - - - FSARH - Flash Processing Start Address Register H - 0x110 - 16 - read-write - 0x0000 - 0xFFFF - - - FSAR31_25 - Start address - 9 - 15 - read-write - - - FSAR20_16 - Start address - 0 - 4 - read-write - - - - - FCR - Flash Control Register - 0x114 - 8 - read-write - 0x00 - 0xFF - - - OPST - Processing Start - 7 - 7 - read-write - - - 0 - Processing stops. - #0 - - - 1 - Processing starts. - #1 - - - - - STOP - Forced Processing Stop - 6 - 6 - read-write - - - DRC - Data Read Completion - 4 - 4 - read-write - - - 0 - Data is not read or next data is requested. - #0 - - - 1 - Data reading is completed. - #1 - - - - - CMD - Software Command Setting - 0 - 3 - read-write - - - 0001 - Program - #0001 - - - 0011 - Blank check - #0011 - - - 0100 - Block erase - #0100 - - - 0101 - Consecutive read - #0101 - - - 0111 - Chip erase - #0111 - - - others - Setting prohibited - true - - - - - - - FEARL - Flash Processing End Address Register L - 0x118 - 16 - read-write - 0x0000 - 0xFFFF - - - FEAR15_0 - End address - 0 - 15 - read-write - - - - - FEARH - Flash Processing End Address Register H - 0x120 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FEAR31_25 - End address - 9 - 15 - read-write - - - FEAR20_16 - End address - 0 - 4 - read-write - - - - - FRESETR - Flash Reset Register - 0x124 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FRESET - Software Reset of the registers - 0 - 0 - read-write - - - 0 - No effect - #0 - - - 1 - The registers relates to the flash programming are reset. - #1 - - - - - - - FSTATR00 - Flash Status Register00 - 0x128 - 32 - read-only - 0x00000000 - 0xFFFFFFEF - - - EILGLERR - Extra Area Illegal Command Error Flag - 5 - 5 - read-only - - - 0 - No illegal command or illegal access to the extra area is detected. - #0 - - - 1 - An illegal command or illegal access to the extra area is detected. - #1 - - - - - ILGLERR - Illegal Command Error Flag - 4 - 4 - read-only - - - 0 - No illegal software command or illegal access is detected. - #0 - - - 1 - An illegal command or illegal access is detected. - #1 - - - - - BCERR0 - Blank Check Error Flag0 - 3 - 3 - read-only - - - 0 - Blank checking terminates normally. - #0 - - - 1 - An error occurs during blank checking. - #1 - - - - - PRGERR01 - Program Error Flag 01 - 2 - 2 - read-only - - - 0 - Programming by the FEXCR register terminates normally. - #0 - - - 1 - An error occurs during programming. - #1 - - - - - PRGERR0 - Program Error Flag0 - 1 - 1 - read-only - - - 0 - Programming terminates normally. - #0 - - - 1 - An error occurs during programming. - #1 - - - - - ERERR0 - Erase Error Flag0 - 0 - 0 - read-only - - - 0 - Erasure terminates normally. - #0 - - - 1 - An error occurs during erasure. - #1 - - - - - - - FSTATR1 - Flash Status Register1 - 0x12C - 32 - read-only - 0x00000000 - 0xFFFFFFFB - - - EXRDY - End status signal of a Extra programming sequencer - 7 - 7 - read-only - - - 0 - Other than below - #0 - - - 1 - The software command of the FEXCR register is terminated. - #1 - - - - - FRDY - End status signal of a sequencer - 6 - 6 - read-only - - - 0 - Other than below - #0 - - - 1 - The software command of the FCR register is terminated. - #1 - - - - - DRRDY - Data read request - 1 - 1 - read-only - - - 0 - Other than below - #0 - - - 1 - The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers. - #1 - - - - - - - FWBL0 - Flash Write Buffer Register L0 - 0x130 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - WDATA - Program data of the program command - 0 - 15 - read-write - - - - - FWBH0 - Flash Write Buffer Register H0 - 0x138 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - WDATA - Program data of the program command - 0 - 15 - - - - - FSTATR01 - Flash Status Register01 - 0x13C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - BCERR1 - Blank Check Error Flag1 - 3 - 3 - - - 0 - Blank checking terminates normally. - #0 - - - 1 - An error occurs during blank checking. - #1 - - - - - PRGERR1 - Program Error Flag1 - 1 - 1 - - - 0 - Programming terminates normally. - #0 - - - 1 - An error occurs during programming. - #1 - - - - - ERERR1 - Erase Error Flag1 - 0 - 0 - - - 0 - Erasure terminates normally. - #0 - - - 1 - An error occurs during erasure. - #1 - - - - - - - FWBL1 - Flash Write Buffer Register L1 - 0x140 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - WDATA47_32 - Program data of the program command - 0 - 15 - read-write - - - - - FWBH1 - Flash Write Buffer Register H1 - 0x144 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - WDATA63_48 - Program data of the program command - 0 - 15 - - - - - FRBL1 - Flash Read Buffer Register L1 - 0x148 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - RDATA47_32 - Read data of the consecutive read command - 0 - 15 - read-only - - - - - FRBH1 - Flash Read Buffer Register H1 - 0x14C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - RDATA63_48 - Read data of the consecutive read command - 0 - 15 - read-only - - - - - FPR - Protection Unlock Register - 0x180 - 32 - write-only - 0x00000000 - 0xFFFFFF00 - - - FPR - Protection Unlock Register - 0 - 7 - write-only - - - - - FPSR - Protection Unlock Status Register - 0x184 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - PERR - Protect Error Flag - 0 - 0 - read-only - - - 0 - No error - #0 - - - 1 - An error occurs. - #1 - - - - - - - FRBL0 - Flash Read Buffer Register L0 - 0x188 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - RDATA - Read data of the consecutive read command - 0 - 15 - - - - - FRBH0 - Flash Read Buffer Register H0 - 0x190 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - RDATA - Read data of the consecutive read command - 0 - 15 - - - - - FSCMR - Flash Start-Up Setting Monitor Register - 0x1C0 - 32 - read-only - 0x00000000 - 0xFFFFBEFF - - - FSPR - Access Window Protection Flag - 14 - 14 - read-only - - - SASMF - Start-up Area Setting Monitor Flag - 8 - 8 - read-only - - - - - FAWSMR - Flash Access Window Start Address Monitor Register - 0x1C8 - 32 - read-only - 0x00000000 - 0xFFFFF000 - - - FAWS - Flash Access Window Start Address - 0 - 11 - read-only - - - - - FAWEMR - Flash Access Window End Address Monitor Register - 0x1D0 - 32 - read-only - 0x00000000 - 0xFFFFF000 - - - FAWE - Flash Access Window End Address - 0 - 11 - read-only - - - - - FISR - Flash Initial Setting Register - 0x1D8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SAS - Temporary boot swap mode - 6 - 7 - - - 10 - The start-up area is switched to the default area temporarily. - #10 - - - 11 - The start-up area is switched to the alternate area temporarily. - #11 - - - others - The start-up area is selected according to the start-up area settings of the extra area. - true - - - - - PCKA - Peripheral Clock Notification - 0 - 5 - - - - - FEXCR - Flash Extra Area Control Register - 0x1DC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - OPST - Software Command Setting - 7 - 7 - read-write - - - 0 - Processing stops. - #0 - - - 1 - Processing starts. - #1 - - - - - CMD - Processing Start) - 0 - 2 - read-write - - - 001 - Start-up area selection and security setting - #001 - - - 010 - Access window information program - #010 - - - 011 - OCDID1 program - #011 - - - 100 - OCDID2 program - #100 - - - 101 - OCDID3 program - #101 - - - 110 - OCDID4 program - #110 - - - 111 - Extra area clear - #111 - - - others - Setting prohibited - true - - - - - - - FEAML - Flash Error Address Monitor Register L - 0x1E0 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - FEAM - Flash Error Address Monitor Register - 0 - 15 - - - - - FEAMH - Flash Error Address Monitor Register H - 0x1E8 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - FEAM - Flash Error Address Monitor Register - 0 - 15 - - - - - FSTATR2 - Flash Status Register2 - 0x1F0 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - EILGLERR - Extra Area Illegal Command Error Flag - 5 - 5 - read-only - - - ILGLERR - Illegal Command Error Flag - 4 - 4 - read-only - - - BCERR - Blank Check Error Flag - 3 - 3 - read-only - - - PRGERR01 - Program Error Flag 01 - 2 - 2 - read-write - - - PRGERR1 - Program Error Flag - 1 - 1 - read-only - - - ERERR - Erase Error Flag - 0 - 0 - read-only - - - - - FENTRYR_MF4 - Flash P/E Mode Entry Register for MF4 - 0x3FB0 - 16 - read-write - 0x0000 - 0xFFFF - - - FENTRYR - Flash P/E Mode Entry Register - 0x3FB2 - 16 - read-write - 0x0000 - 0xFFFF - - - FLWAITR - Flash Wait Cycle Register - 0x3FC0 - 8 - read-write - 0x00 - 0xFF - - - PFBER - Prefetch Buffer Enable Register - 0x3FC8 - 8 - read-write - 0x00 - 0xFF - - - - - R_FCACHE - Flash Memory Cache - 0x4001C000 - - 0x00000100 - 0x02 - registers - - - 0x00000104 - 0x02 - registers - - - 0x0000011C - 0x01 - registers - - - - FCACHEE - Flash Cache Enable Register - 0x100 - 16 - read-write - 0x0000 - 0xFFFF - - - FCACHEEN - FCACHE Enable - 0 - 0 - read-write - - - 0 - Disable FCACHE - #0 - - - 1 - Enable FCACHE - #1 - - - - - - - FCACHEIV - Flash Cache Invalidate Register - 0x104 - 16 - read-write - 0x0000 - 0xFFFF - - - FCACHEIV - Flash Cache Invalidate Register - 0 - 0 - read-write - - - 0 - Do not invalidate reads, setting ignored on writes - #0 - - - 1 - Invalidate on reads and writes. - #1 - - - - - - - FLWT - Flash Wait Cycle Register - 0x11C - 8 - read-write - - - FLWT - Flash Wait Cycle - 0 - 2 - read-write - - - 000 - 0 waits (ICLK <= 80 MHz) - #000 - - - 001 - 1 wait (80 MHz < ICLK <= 160 MHz) - #001 - - - 010 - 2 waits (160 MHz < ICLK <= 240 MHz). - #010 - - - - - - - - - R_GLCDC - Graphics LCD Controller - 0x400E0000 - - 0x00000000 - 0x101C - registers - - - 0x00001100 - 0x014 - registers - - - 0x00001118 - 0x02C - registers - - - 0x0000114C - 0x00C - registers - - - 0x00001200 - 0x014 - registers - - - 0x00001218 - 0x02C - registers - - - 0x0000124C - 0x00C - registers - - - 0x00001300 - 0x03C - registers - - - 0x00001340 - 0x03C - registers - - - 0x00001380 - 0x03C - registers - - - 0x000013C0 - 0x018 - registers - - - 0x000013E4 - 0x04 - registers - - - 0x00001404 - 0x028 - registers - - - 0x00001440 - 0x014 - registers - - - - BG - Background Registers - 0x1000 - - EN - Background Plane Setting Operation Control Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SWRST - Entire module SW reset control - 16 - 16 - read-write - - - 1 - Releases the entire module from the SW reset state. - #1 - - - 0 - Places the entire module in the SW reset state. - #0 - - - - - VEN - Control of LCDC internal register value reflection to internal operations - 8 - 8 - read-write - oneToSet - modify - - - 1 - Enables - #1 - - - 0 - Disables(Cleared to 0 by an internal source) - #0 - - - - - EN - Background plane generation module operation enable - 0 - 0 - read-write - - - 1 - Enables operation. - #1 - - - 0 - Disables operation. - #0 - - - - - - - PERI - Background Plane Setting Free-Running Period Register - 0x04 - 32 - read-write - 0x00170017 - 0xFFFFFFFF - - - FV - Background plane vertical synchronization signal period on the basis of line. - 16 - 26 - read-write - - - 0x013 - 0x3FF - - - - - FV - FV lines.The valid range is 0x013 to 0x3FF. - true - - - - - FH - Background plane horizontal synchronization signal period on the basis of pixel clock (PXCLK). - 0 - 10 - read-write - - - 0x017 - 0x3FF - - - - - FH - FH lines. The valid range is 0x017 to 0x3FF. - true - - - - - - - SYNC - Background Plane Setting Synchronization Position Register - 0x08 - 32 - read-write - 0x00010001 - 0xFFFFFFFF - - - VP - Background plane vertical synchronization signal assertion position on the basis of line. - 16 - 19 - read-write - - - 0x0 - Setting prohibited - 0x0 - - - others - (VP)th line - true - - - - - HP - Background plane horizontal synchronization signal assertion position on the basis of pixel clock (PXCLK). - 0 - 3 - read-write - - - 0x0 - Setting prohibited - 0x0 - - - others - (HP)th line (pixels) - true - - - - - - - VSIZE - Background Plane Setting Full Image Vertical Size Register - 0x0C - 32 - read-write - 0x00070010 - 0xFFFFFFFF - - - VP - Background plane vertical valid pixel start position on the basis of line - 16 - 26 - read-write - - - 0x0003 - 0x3EF - - - - - VP - VP lines. The valid range is 0x003 to 0x3EF. - true - - - - - VW - Background plane vertical valid pixel width on the basis of line - 0 - 10 - read-write - - - 0x0010 - 0x03FC - - - - - VW - VW lines. The valid range is 0x010 to 0x3F0. - true - - - - - - - HSIZE - Background Plane Setting Full Image Horizontal Size Register - 0x10 - 32 - read-write - 0x00060010 - 0xFFFFFFFF - - - HP - Background plane horizontal valid pixel start position on the basis of pixel clock (PXCLK). - 16 - 26 - read-write - - - 0x006 - 0x3EE - - - - - HP - HP cycle(pixel). The valid range is 0x006 to 0x3EE. - true - - - - - HW - - Background plane horizontall valid pixel width on the basis of pixel clock (PXCLK) - Note: When serial RGB is selected as the output format for the output control block, add two to the horizontal enable signal width and set the resulting value to this field. - - 0 - 10 - read-write - - - 0x010 - 0x3F8 - - - - - HW - HW cycles. The valid range is 0x010 to 0x3F8. - true - - - - - - - BGC - Background Plane Setting Background Color Register - 0x14 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - R - - R value for background plane valid pixel area. - Unsigned; 8-bit integer. - - 16 - 23 - read-write - - - G - - G value for background plane valid pixel area - Unsigned; 8-bit integer - - 8 - 15 - read-write - - - B - - B value for background plane valid pixel area - Unsigned; 8-bit integer - - 0 - 7 - read-write - - - - - MON - Background Plane Setting Status Monitor Register - 0x18 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SWRST - Entire module SW reset state monitor. - 16 - 16 - read-only - - - 1 - The entire module is released from the SW reset state. - #1 - - - 0 - The entire module is in the SW reset state. - #0 - - - - - VEN - - Entire module internal operation reflection control signal monitor. - The signal state for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal. - - 8 - 8 - read-only - - - 1 - The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is asserted. - #1 - - - 0 - The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is negated. - #0 - - - - - EN - Background plane generation module operation state monitor. - 0 - 0 - read-only - - - 1 - Operation is in progress. - #1 - - - 0 - Operation is stopped. - #0 - - - - - - - - 2 - 0x100 - GR[%s] - Layer Registers - 0x1100 - - VEN - Graphics Register Update Control Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - PVEN - - Control of graphics n module register value reflection to internal operations. - Reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). - - 0 - 0 - read-write - zeroToClear - modify - - - 1 - Enables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). - #1 - - - 0 - Disables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). - #0 - - - - - - - FLMRD - Graphics Frame Buffer Read Control Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - RENB - Graphics data (frame buffer data) read enable. - 0 - 0 - read-write - - - 1 - Enables reading. - #1 - - - 0 - Disables reading. - #0 - - - - - - - FLM1 - Graphics Frame Buffer Control Register 1 - 0x08 - 32 - read-only - 0x00000003 - 0xFFFFFFFF - - - BSTMD - - Burst transfer control for graphics data (frame buffer data) - access - - 0 - 1 - read-only - - - 11 - 16-beat increment burst transfer (64-byte boundary) - #11 - - - others - Setting prohibited. - true - - - - - - - FLM2 - Graphics Frame Buffer Control Register 2 - 0x0C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BASE - - Base address for accessing graphics data (frame buffer data) - Set the head address in the frame buffer where graphics data is to be stored. GRn_FLM2.BASE[5:0] should be fixed to 0 during 64-byte burst transfer. - - 0 - 31 - read-write - - - - - FLM3 - Graphics Frame Buffer Control Register 3 - 0x10 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - LNOFF - - Macro line offset address for accessing graphics data - (frame buffer data) - Signed; 16-bit integer - - 16 - 31 - read-write - - - - - FLM5 - Graphics Frame Buffer Control Register 5 - 0x18 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - LNNUM - Number of lines per frame for accessing graphics data (frame buffer data). - 16 - 26 - read-write - - - 0x00F - 0x3FF - - - - - LNNUM - LNNUM lines. The valid range is 0x00F to 0x3FF. - true - - - - - DATANUM - Number of data transfer times per line for accessing graphics data (frame buffer data), where one transfer is defined as 16-beat burst access (64-byte boundary) - 0 - 15 - read-write - - - DATAUM - DATAUM+1 times. - true - - - - - - - FLM6 - Graphics Frame Buffer Control Register 6 - 0x1C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - FORMAT - Data format for accessing graphics data (frame buffer data). - 28 - 30 - read-write - - - 111 - CLUT11bit/pix) - #111 - - - 110 - CLUT4 (4 bits/pix) - #110 - - - 101 - CLUT8 (8 bits/pix) - #101 - - - 100 - ARGB8888 (32 bits/pix) - #100 - - - 011 - ARGB4444 (16 bits/pix) - #011 - - - 010 - ARGB1555 (16 bits/pix, 1 bit of A is LUT data) - #010 - - - 001 - RGB888 (32 bits/pix, 8 bits on the MSB side are invalid) - #001 - - - 000 - RGB565 (16 bits/pix) - #000 - - - others - Setting prohibited. - true - - - - - - - AB1 - Graphics Alpha Blending Control Register 1 - 0x20 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ARCON - Rectangular area alpha blending control. - 12 - 12 - read-write - - - 1 - On - #1 - - - 0 - Off - #0 - - - - - ARCDISPON - Image area border display control for rectangular area alpha blending. - 8 - 8 - read-write - - - 1 - Display on - #1 - - - 0 - Display off - #0 - - - - - GRCDISPON - Graphics image area border display control. - 4 - 4 - read-write - - - 1 - Display on - #1 - - - 0 - Display off - #0 - - - - - DISPSEL - Graphics display plane control. - 0 - 1 - read-write - - - 11 - Blended display of lower-layer graphics (input image from the previous stage) and current graphics (graphics data read from the AHB bus) - #11 - - - 10 - Current graphics display - #10 - - - 01 - Lower-layer graphics display - #01 - - - 00 - Background color display (value set by the GRn_BASE register). - #00 - - - - - - - AB2 - Graphics Alpha Blending Control Register 2 - 0x24 - 32 - read-write - 0x00060010 - 0xFFFFFFFF - - - GRCVS - Vertical start position of graphics image area. - 16 - 26 - read-write - - - 0x002 - 0x3EE - - - - - GRCVS - GRCVS lines. The valid range is 0x002 to 0x3EE. - true - - - - - GRCVW - Vertical width of graphics image area. - 0 - 10 - read-write - - - 0x010 - 0x3FC - - - - - GRCVW - GRCVW lines. The valid range is 0x010 to 0x3F0. - true - - - - - - - AB3 - Graphics Alpha Blending Control Register 3 - 0x28 - 32 - read-write - 0x00050010 - 0xFFFFFFFF - - - GRCHS - Horizontal start position of graphics image area. - 16 - 26 - read-write - - - 0x005 - 0x3ED - - - - - GRCHS - GRCHS lines. The valid range is 0x005 to 0x3ED. - true - - - - - GRCHW - Horizontal width of graphics image area. - 0 - 10 - read-write - - - 0x010 - 0x3F0 - - - - - GRCHW - GRCHW pixels. The valid range is 0x010 to 0x3F0. - true - - - - - - - AB4 - Graphics Alpha Blending Control Register 4 - 0x2C - 32 - read-write - 0x00060010 - 0xFFFFFFFF - - - ARCVS - Vertical start position of rectangular area alpha blending image area - 16 - 26 - read-write - - - 0x002 - 0x3EE - - - - - ARCVS - ARCVS linels. The valid range is 0x002 to 0x3EE. - true - - - - - ARCVW - Vertical width of rectangular area alpha blending image area. - 0 - 10 + + ADGSCS + A/D Conversion Channel Status Register (for Group Scan) + 0x082 + 16 + read-only + 0x8080 + 0xFFFF + + + CHSELGB + Channel status of Group B scan + 0 + 7 + read-only + + + 0x80 + Group B scan start + 0x80 + + + 0xFF + Group B scan end + 0xFF + + + + + CHSELGA + Channel status of Group A scan + 8 + 15 + read-only + + + 0x80 + Group A scan start + 0x80 + + + 0xFF + Group A scan end + 0xFF + + + + + + + ADSER + A/D Sampling Extension Register + 0x088 + 8 + read-write + 0x00 + 0xFF + + + Reserved + These bits are read as 0000000. The write value should be 0000000. + 0 + 6 + read-write + + + SMPEX + Sampling extension control + 7 + 7 + read-write + + + 0 + Not extend sampling period + #0 + + + 1 + Extending sampling period + #1 + + + + + + + 16 + 0x2 + 0-15 + ADBUF%s + A/D Data Buffer Register %s + 0x0B0 + 16 + read-only + 0x0000 + 0xFFFF + + + ADBUF + A/D data buffer registers (ADBUF) are 16-bit read-only registers that sequentially store all A/D converted values. The automatic clear function is not applied to these registers. + 0 + 15 + read-only + + + + + ADBUFEN + A/D Data Buffer Enable Register + 0x0D0 + 8 + read-write + 0x00 + 0xFF + + + BUFEN + Data Buffer Enable + 0 + 0 + read-write + + + 0 + The data buffer is not used. + #0 + + + 1 + The data buffer is used. + #1 + + + + + Reserved + These bits are read as 0000000. The write value should be 0000000. + 1 + 7 + read-write + + + + + ADBUFPTR + A/D Data Buffer Pointer Register + 0x0D2 + 8 + read-write + 0x00 + 0xFF + zeroToClear + modify + + + BUFPTR + Data Buffer PointerThese bits indicate the number of data buffer to which the next A/D converted data is transferred. + 0 + 3 + read-only + + + PTROVF + Pointer Overflow Flag + 4 + 4 + read-only + + + 0 + The data buffer pointer has not overflowed. + #0 + + + 1 + The data buffer pointer has overflowed. + #1 + + + + + Reserved + These bits are read as 000. The write value should be 000. + 5 + 7 + read-write + + + + + ADPGADBS0 + A/D Programmable Gain Amplifier Differential Input Bias Select Register 0 + 0x1B4 + 8 + read-write + 0x00 + 0xFF + + + P0BIAS + Programmable Gain Amplifiers P000 to P002 Bias Voltage SelectNOTE: This bit selects the input bias voltage value when differential inputs are used. + 0 + 0 + read-write + + + 0 + AVCC x 0.5 + #0 + + + 1 + AVCC x 0.6 + #1 + + + + + Reserved + These bits are read as 0000000. The write value should be 0000000. + 1 + 7 + read-write + + + + + ADPGADBS1 + A/D Programmable Gain Amplifier Differential Input Bias Select Register 1 + 0x1B5 + 8 + read-write + 0x00 + 0xFF + + + P3BIAS + Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: This bit selects the input bias voltage value when differential inputs are used. + 0 + 0 + read-write + + + 0 + AVCC x 0.5 + #0 + + + 1 + AVCC x 0.6 + #1 + + + + + Reserved + These bits are read as 0000000. The write value should be 0000000. + 1 + 7 + read-write + + + + + ADREFMON + A/D External Reference Voltage Monitor Register + 0x1E0 + 8 + read-write + 0x00 + 0xFF + + + PGAMON + PGA Monitor Output Enable + 0 + 2 + read-write + + + 000 + The monitor output is disabled. + #000 + + + 001 + The monitor output is enabled. + #001 + + + others + Setting prohibited. + true + + + + + Reserved + This bit is read as 0. The write value should be 0. + 3 + 3 + read-write + + + MONSEL + Monitor output selection bit. + 4 + 7 + read-write + + + 0000 + No monitor output is selected. + #0000 + + + 1000 + P000 is selected. + #1000 + + + 1001 + P001 is selected. + #1001 + + + 1010 + P002 is selected. + #1010 + + + 1011 + P003 is selected. + #1011 + + + others + Setting prohibited. + true + + + + + + + + + R_ADC1 + 0x4005C200 + + + R_PSCU + Peripheral Security Control Unit + 0x400E0000 + + 0x04 + 44 + registers + + + + PSARB + Peripheral Security Attribution Register B + 0x04 + 32 read-write - - - 0x001 - 0x3FC - - - - - ARCVW - ARCVW linels. The valid range is 0x001 to 0x3F0. - true - - - - - - - AB5 - Graphics Alpha Blending Control Register 5 - 0x30 - 32 - read-write - 0x00050010 - 0xFFFFFFFF - - - ARCHS - Horizontal start position of rectangular area alpha blending image area. - 16 - 26 + 0xffffffff + 0xffffffff + + + PSARB1 + CAN1 and the MSTPCRB.MSTPB1 bit security attribution + 1 + 1 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB2 + CAN0 and the MSTPCRB.MSTPB2 bit security attribution + 2 + 2 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB3 + CEC and the MSTPCRB.MSTPB3 bit security attribution + 3 + 3 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB6 + QSPI and the MSTPCRB.MSTPB6 bit security attribution + 6 + 6 + read-only + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB7 + IIC2 and the MSTPCRB.MSTPB7 bit security attribution + 7 + 7 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB8 + IIC1 and the MSTPCRB.MSTPB8 bit security attribution + 8 + 8 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB9 + IIC0 and the MSTPCRB.MSTPB9 bit security attribution + 9 + 9 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB11 + USBFS and the MSTPCRB.MSTPB11 bit security attribution + 11 + 11 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB12 + USBHS and the MSTPCRB.MSTPB12 bit security attribution + 12 + 12 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB15 + ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 bit security attribution + 15 + 15 + read-only + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB16 + OSPI and the MSTPCRB.MSTPB16 bit security attribution + 16 + 16 + read-only + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB18 + RSPI1 and the MSTPCRB.MSTPB18 bit security attribution + 18 + 18 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB19 + RSPI0 and the MSTPCRB.MSTPB19 bit security attribution + 19 + 19 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB22 + SCI9 and the MSTPCRB.MSTPB22 bit security attribution + 22 + 22 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB23 + SCI8 and the MSTPCRB.MSTPB23 bit security attribution + 23 + 23 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB24 + SCI7 and the MSTPCRB.MSTPB24 bit security attribution + 24 + 24 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB25 + SCI6 and the MSTPCRB.MSTPB25 bit security attribution + 25 + 25 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB26 + SCI5 and the MSTPCRB.MSTPB26 bit security attribution + 26 + 26 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB27 + SCI4 and the MSTPCRB.MSTPB27 bit security attribution + 27 + 27 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB28 + SCI3 and the MSTPCRB.MSTPB28 bit security attribution + 28 + 28 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB29 + SCI2 and the MSTPCRB.MSTPB29 bit security attribution + 29 + 29 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB30 + SCI1 and the MSTPCRB.MSTPB30 bit security attribution + 30 + 30 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARB31 + SCI0 and the MSTPCRB.MSTPB31 bit security attribution + 31 + 31 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + + + PSARC + Peripheral Security Attribution Register C + 0x08 + 32 read-write - - - 0x005 - 0x3ED - - - - - ARCHS - ARCHS pixel. The valid range is 0x005 to 0x3ED. - true - - - - - ARCHW - Horizontal width of rectangular area alpha blending image area. - 0 - 10 + 0xffffffff + 0xffffffff + + + PSARC0 + CAC and the MSTPCRC.MSTPC0 bit security attribution + 0 + 0 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC1 + CRC and the MSTPCRC.MSTPC1 bit security attribution + 1 + 1 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC3 + CTSU and the MSTPCRC.MSTPC3 bit security attribution + 3 + 3 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC8 + SSIE0 and the MSTPCRC.MSTPC8 bit security attribution + 8 + 8 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC12 + SDHI0 and the MSTPCRC.MSTPC12 bit security attribution + 12 + 12 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC13 + DOC and the MSTPCRC.MSTPC13 bit security attribution + 13 + 13 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC26 + CANFD1 and the MSTPCRC.MSTPC26 bit security attribution + 26 + 26 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC27 + CANFD0 and the MSTPCRC.MSTPC27 bit security attribution + 27 + 27 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARC31 + TSIP and the MSTPCRC.MSTPC31 bit security attribution + 31 + 31 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + + + PSARD + Peripheral Security Attribution Register D + 0x0C + 32 read-write - - - 0x001 - 0x3F8 - - - - - ARCHW - ARCHW pixels. The valid range is 0x001 to 0x3F0. - true - - - - - - - AB6 - Graphics Alpha Blending Control Register 6 - 0x34 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ARCCOEF - - Alpha coefficient for alpha blending in rectangular area (-255 to 255). - [8]: Sign (0: addition, 1: subtraction) - [7:0]: Variation (absolute value) - - 16 - 24 + 0xffffffff + 0xffffffff + + + PSARD0 + AGT3 and the MSTPCRD.MSTPD0 bit security attribution + 0 + 0 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD1 + AGT2 and the MSTPCRD.MSTPD1 bit security attribution + 1 + 1 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD2 + AGT1 and the MSTPCRD.MSTPD2 bit security attribution + 2 + 2 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD3 + AGT0 and the MSTPCRD.MSTPD3 bit security attribution + 3 + 3 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD11 + PGI3 and the MSTPCRD.MSTPD11 bit security attribution + 11 + 11 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD12 + PGI2 and the MSTPCRD.MSTPD12 bit security attribution + 12 + 12 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD13 + PGI1 and the MSTPCRD.MSTPD13 bit security attribution + 13 + 13 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD14 + PGI0 and the MSTPCRD.MSTPD14 bit security attribution + 14 + 14 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD15 + ADC1 and the MSTPCRD.MSTPD15 bit security attribution + 15 + 15 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD16 + ADC0 and the MSTPCRD.MSTPD16 bit security attribution + 16 + 16 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD20 + DAC12 and the MSTPCRD.MSTPD20 bit security attribution + 20 + 20 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARD22 + TSN and the MSTPCRD.MSTPD22 bit security attribution + 22 + 22 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + + + PSARE + Peripheral Security Attribution Register E + 0x10 + 32 read-write - - - ARCRATE - Frame rate for alpha blending in rectangular area. - 0 - 7 + 0xffffffff + 0xffffffff + + + PSARE0 + WDT security attribution + 0 + 0 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE1 + IWDT security attribution + 1 + 1 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE2 + RTC security attribution + 2 + 2 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE14 + AGT5 and the MSTPCRE.MSTPE14 bit security attribution + 14 + 14 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE15 + AGT4 and the MSTPCRE.MSTPE15 bit security attribution + 15 + 15 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE22 + GPT9 and the MSTPCRE.MSTPE22 bit security attribution + 22 + 22 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE23 + GPT8 and the MSTPCRE.MSTPE23 bit security attribution + 23 + 23 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE24 + GPT7 and the MSTPCRE.MSTPE24 bit security attribution + 24 + 24 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE25 + GPT6 and the MSTPCRE.MSTPE25 bit security attribution + 25 + 25 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE26 + GPT5 and the MSTPCRE.MSTPE26 bit security attribution + 26 + 26 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE27 + GPT4 and the MSTPCRE.MSTPE27 bit security attribution + 27 + 27 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE28 + GPT3 and the MSTPCRE.MSTPE28 bit security attribution + 28 + 28 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE29 + GPT2 and the MSTPCRE.MSTPE29 bit security attribution + 29 + 29 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE30 + GPT1 and the MSTPCRE.MSTPE30 bit security attribution + 30 + 30 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + PSARE31 + GPT0 and the MSTPCRE.MSTPE31 bit security attribution + 31 + 31 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + + + MSSAR + Module Stop Security Attribution Register + 0x14 + 32 read-write - - - ARCRATE - ARCRATE+1 frames - true - - - - - + 0xffffffff + 0xffffffff + + + MSSAR0 + The MSTPCRC.MSTPC14 bit security attribution + 0 + 0 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + MSSAR1 + The MSTPCRA.MSTPA22 bit security attribution + 1 + 1 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + MSSAR2 + The MSTPCRA.MSTPA7 bit security attribution + 2 + 2 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + MSSAR3 + The MSTPCRA.MSTPA0 bit security attribution + 3 + 3 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + + + + CFSAMONA + Code Flash Security Attribution Monitor Register A + 0x18 + 32 + read-only + + + CFS1 + Code Flash Secure area 1 + 15 + 23 + read-only + + + + + CFSAMONB + Code Flash Security Attribution Monitor Register B + 0x1C + 32 + read-only + + + CFS2 + Code Flash Secure area 2 + 10 + 23 + read-only + + + + + DFSAMON + Data Flash Security Attribution Monitor Register + 0x20 + 32 + read-only + + + DFS + Data flash Secure area + 10 + 15 + read-only + + + + + SSAMONA + SRAM Security Attribution Monitor Register A + 0x24 + 32 + read-only + + + SS1 + SRAM Secure area 1 + 13 + 20 + read-only + + + + + SSAMONB + SRAM Security Attribution Monitor Register B + 0x28 + 32 + read-only + + + SS2 + SRAM secure area 2 + 10 + 20 + read-only + + + + + DLMMON + Device Lifecycle Management State Monitor Register + 0x2C + 32 + read-only + + + DLMMON + Device Lifecycle Management State Monitor + 0 + 3 + read-only + + + 0x0 + CM + 0x0 + + + 0x1 + SHIPPED + 0x1 + + + 0x2 + SSD + 0x2 + + + 0x3 + NSECSD + 0x3 + + + 0x4 + DPL + 0x4 + + + 0x5 + LCK_DBG + 0x5 + + + 0x6 + LCK_BOOT + 0x6 + + + 0x7 + RMA_REQ + 0x7 + + + 0x8 + RMA_ACK + 0x8 + + + Others + Reserved + true + + + + + + + + + + R_AGT0 + Asynchronous General Purpose Timer + 0x40084000 + + 0x00000000 + 0x006 + registers + + + 0x00000008 + 0x003 + registers + + + 0x0000000C + 0x004 + registers + + + + AGT + AGT Counter Register + 0x00 + 16 + read-write + 0xFFFF + 0xFFFF + + + AGT + 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. + 0 + 15 + read-write + + + + + AGTCMA + AGT Compare Match A Register + 0x02 + 16 + read-write + 0xFFFF + 0xFFFF + + + AGTCMA + AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH + 0 + 15 + read-write + + + + + AGTCMB + AGT Compare Match B Register + 0x04 + 16 + read-write + 0xFFFF + 0xFFFF + + + AGTCMB + AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH + 0 + 15 + read-write + + + + + AGTCR + AGT Control Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + TCMBF + Compare match B flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + No match + #0 + + + 1 + Match. + #1 + + + + + TCMAF + Compare match A flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No match + #0 + + + 1 + Match. + #1 + + + + + TUNDF + Underflow flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No match + #0 + + + 1 + Match. + #1 + + + + + TEDGF + Active edge judgment flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No active edge received + #0 + + + 1 + Active edge received. + #1 + + + + + TSTOP + AGT count forced stop + 2 + 2 + write-only + + + 0 + Writing is invalid + #0 + + + 1 + The count is forcibly stopped. + #1 + + + + + TCSTF + AGT count status flag + 1 + 1 + read-only + + + 0 + Count stops + #0 + + + 1 + Count in progress. + #1 + + + + + TSTART + AGT count start + 0 + 0 + read-write + + + 0 + Count stops + #0 + + + 1 + Count starts. + #1 + + + + + + + AGTMR1 + AGT Mode Register 1 + 0x09 + 8 + read-write + 0x00 + 0xFF + + + TCK + Count source + 4 + 6 + read-write + + + 000 + PCLKB + #000 + + + 001 + PCLKB/8 + #001 + + + 011 + PCLKB/2 + #011 + + + 100 + Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register + #100 + + + 101 + Underflow event signal from AGT0*6 + #101 + + + 110 + Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. + #110 + + + others + settings are prohibited. + true + + + + + TEDGPL + Edge polarity + 3 + 3 + read-write + + + 0 + Single-edge + #0 + + + 1 + Both-edge. + #1 + + + + + TMOD + Operating mode + 0 + 2 + read-write + + + 000 + Timer mode + #000 + + + 001 + Pulse output mode + #001 + + + 010 + Event counter mode + #010 + + + 011 + Pulse width measurement mode + #011 + + + 100 + Pulse period measurement mode. + #100 + + + others + settings are prohibited + true + + + + + + + AGTMR2 + AGT Mode Register 2 + 0x0A + 8 + read-write + 0x00 + 0xFF + + + LPM + Low Power Mode + 7 + 7 + read-write + + + 0 + Normal mode + #0 + + + 1 + Low Power mode + #1 + + + + + CKS + AGTLCLK/AGTSCLK count source clock frequency division ratio + 0 + 2 + read-write + + + 000 + 1/1 + #000 + + + 001 + 1/2 + #001 + + + 010 + 1/4 + #010 + + + 011 + 1/8 + #011 + + + 100 + 1/16 + #100 + + + 101 + 1/32 + #101 + + + 110 + 1/64 + #110 + + + 111 + 1/128. + #111 + + + + + + + AGTIOC + AGT I/O Control Register + 0x0C + 8 + read-write + 0x00 + 0xFF + + + TIOGT + Count control + 6 + 7 + read-write + + + 00 + Event is always counted + #00 + + + 01 + Event is counted during polarity period specified for AGTEEn. + #01 + + + others + settings are prohibited. + true + + + + + TIPF + Input filter + 4 + 5 + read-write + + + 00 + No filter + #00 + + + 01 + Filter sampled at PCLKB + #01 + + + 10 + Filter sampled at PCLKB/8 + #10 + + + 11 + Filter sampled at PCLKB/32 + #11 + + + + + TOE + AGTOn output enable + 2 + 2 + read-write + + + 0 + AGTOn output disabled + #0 + + + 1 + AGTOn output enabled. + #1 + + + + + TEDGSEL + I/O polarity switchFunction varies depending on the operating mode. + 0 + 0 + read-write + + + + + AGTISR + AGT Event Pin Select Register + 0x0D + 8 + read-write + 0x00 + 0xFF + + + EEPS + AGTEE polarty selection + 2 + 2 + read-write + + + 0 + An event is counted during the low-level period + #0 + + + 1 + An event is counted during the high-level period + #1 + + + + + + + AGTCMSR + AGT Compare Match Function Select Register + 0x0E + 8 + read-write + 0x00 + 0xFF + + + TOPOLB + AGTOB polarity select + 6 + 6 + read-write + + + 0 + AGTOB Output is started at low + #0 + + + 1 + AGTOB Output is started at high + #1 + + + + + TOEB + AGTOB output enable + 5 + 5 + read-write + + + 0 + AGTOB output disabled (port) + #0 + + + 1 + AGTOB output enabled + #1 + + + + + TCMEB + Compare match B register enable + 4 + 4 + read-write + + + 0 + Disable compare match B register + #0 + + + 1 + Enable compare match B register + #1 + + + + + TOPOLA + AGTOA polarity select + 2 + 2 + read-write + + + 0 + AGTOA Output is started at low + #0 + + + 1 + AGTOA Output is started at high + #1 + + + + + TOEA + AGTOA output enable + 1 + 1 + read-write + + + 0 + AGTOA output disabled (port) + #0 + + + 1 + AGTOA output enabled + #1 + + + + + TCMEA + Compare match A register enable + 0 + 0 + read-write + + + 0 + Disable compare match A register + #0 + + + 1 + Enable compare match A register + #1 + + + + + + + AGTIOSEL + AGT Pin Select Register + 0x0F + 8 + read-write + 0x00 + 0xFF + + + TIES + AGTIO input enable + 4 + 4 + read-write + + + 0 + External event input is disabled during Software Standby mode + #0 + + + 1 + External event input is enabled during Software Standby mode. + #1 + + + + + SEL + AGTIO pin select + 0 + 1 + read-write + + + 00 + AGTIO_A can not be used as AGTIO input pin in deep software standby mode + #00 + + + 01 + Setting prohibited + #01 + + + 10 + AGTIO_B can be used as AGTIO input pin in deep software standby mode. AGTIO_B is input only. It is not possible to output. + #10 + + + 11 + AGTIO_C can be used as AGTIO input pin in deep software standby mode. AGTIO_C is input only. It is not possible to output. + #11 + + + + + + + + + R_AGT1 + 0x40084100 + + + R_BUS + Bus Interface + 0x40003000 + + 0x00000002 + 0x00A + registers + + + 0x00000012 + 0x00A + registers + + + 0x00000022 + 0x00A + registers + + + 0x00000032 + 0x00A + registers + + + 0x00000042 + 0x00A + registers + + + 0x00000052 + 0x00A + registers + + + 0x00000062 + 0x00A + registers + + + 0x00000072 + 0x00A + registers + + + 0x00000802 + 0x02 + registers + + + 0x0000080A + 0x02 + registers + + + 0x00000812 + 0x02 + registers + + + 0x0000081A + 0x02 + registers + + + 0x00000822 + 0x02 + registers + + + 0x0000082A + 0x02 + registers + + + 0x00000832 + 0x02 + registers + + + 0x0000083A + 0x02 + registers + + + 0x00000842 + 0x02 + registers + + + 0x0000084A + 0x02 + registers + + + 0x00000852 + 0x02 + registers + + + 0x0000085A + 0x02 + registers + + + 0x00000862 + 0x02 + registers + + + 0x0000086A + 0x02 + registers + + + 0x00000872 + 0x02 + registers + + + 0x0000087A + 0x02 + registers + + + 0x00000880 + 0x02 + registers + + + 0x00000C00 + 0x003 + registers + + + 0x00000C10 + 0x01 + registers + + + 0x00000C14 + 0x003 + registers + + + 0x00000C20 + 0x01 + registers + + + 0x00000C24 + 0x02 + registers + + + 0x00000C40 + 0x01 + registers + + + 0x00000C44 + 0x006 + registers + + + 0x00000C50 + 0x01 + registers + + + 0x00001000 + 0x02 + registers + + + 0x00001004 + 0x02 + registers + + + 0x00001008 + 0x02 + registers + + + 0x0000100C + 0x02 + registers + + + 0x00001010 + 0x02 + registers + + + 0x00001014 + 0x02 + registers + + + 0x00001100 + 0x02 + registers + + + 0x00001104 + 0x02 + registers + + + 0x00001108 + 0x02 + registers + + + 0x0000110C + 0x02 + registers + + + 0x00001110 + 0x02 + registers + + + 0x00001114 + 0x02 + registers + + + 0x00001118 + 0x02 + registers + + + 0x0000111C + 0x02 + registers + + + 0x00001120 + 0x02 + registers + + + 0x00001124 + 0x02 + registers + + + 0x00001128 + 0x02 + registers + + + 0x0000112C + 0x02 + registers + + + 0x00001130 + 0x02 + registers + + + 0x00001134 + 0x02 + registers + + + 0x00001138 + 0x02 + registers + + + 0x0000113C + 0x02 + registers + + + 0x00001800 + 0x005 + registers + + + 0x00001810 + 0x005 + registers + + + 0x00001820 + 0x005 + registers + + + 0x00001830 + 0x005 + registers + + + 0x00001840 + 0x005 + registers + + + 0x00001850 + 0x005 + registers + + + 0x00001860 + 0x005 + registers + + + 0x00001870 + 0x005 + registers + + + 0x00001880 + 0x005 + registers + + + 0x00001890 + 0x005 + registers + + + 0x000018A0 + 0x005 + registers + + + + 8 + 0x10 + CSa[%s] + CS Registers + 0x0000 - AB7 - Graphics Alpha Blending Control Register 7 - 0x38 - 32 + MOD + Mode Register + 0x0002 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - ARCDEF - Initial alpha value for alpha blending in rectangular area. - 16 - 23 - read-write - - - CKON - RGB-index chroma-key processing control. - 0 - 0 + PRMOD + Page Read Access Mode Select + 15 + 15 read-write + + 0 + Normal access compatible mode + #0 + 1 - Enables chroma-key processing + External data read continuous assertion mode #1 + + + + PWENB + Page Write Access Enable + 9 + 9 + read-write + 0 - Disables chroma-key processing + Disable #0 + + 1 + Enable + #1 + - - - - AB8 - Graphics Alpha Blending Control Register 8 - 0x3C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CKKG - - G signal for RGB-index chroma-key processing - Unsigned; 8 bits. - - 16 - 23 - read-write - - - CKKB - - B signal for RGB-index chroma-key processing - Unsigned; 8 bits. - - 8 - 15 - read-write - - - CKKR - - R signal for RGB-index chroma-key processing - Unsigned; 8 bits. - - 0 - 7 - read-write - - - - - AB9 - Graphics Alpha Blending Control Register 9 - 0x40 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CKA - A value after RGB-index chroma-key processing replacement. - 24 - 31 - read-write - - - CKG - - G value after RGB-index chroma-key processing replacement - Unsigned; 8 bits. - - 16 - 23 - read-write - - - CKB - - B value after RGB-index chroma-key processing replacement - Unsigned; 8 bits. - - 8 - 15 - read-write - - - CKR - - R value after RGB-index chroma-key processing replacement - Unsigned; 8 bits. - - 0 - 7 - read-write - - - - - BASE - Graphics Background Color Control Register - 0x4C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - G - - Background color G value - Unsigned; 8 bits - - 16 - 23 - read-write - - B - - Background color B value - Unsigned; 8 bits - + PRENB + Page Read Access Enable 8 - 15 - read-write - - - R - - Background color R value - Unsigned; 8 bits - - 0 - 7 - read-write - - - - - CLUTINT - Graphics CLUT Table Interrupt Control Register - 0x50 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SEL - CLUT table control - 16 - 16 + 8 read-write + + 0 + Disable + #0 + 1 - Uses CLUT1 plane for internal operations. + Enable #1 + + + + EWENB + External Wait Enable + 3 + 3 + read-write + 0 - Uses CLUT0 plane for internal operations. + Disable #0 - others - Setting prohibited - true + 1 + Enable + #1 - LINE - Number of detection lines + WRMOD + Write Access Mode Select 0 - 10 + 0 read-write - - - 0x000 - 0x400 - - - LINE - LINE+1 lines. The valid range is 0x000 to 0x400. - true + 0 + Byte strobe mode + #0 + + + 1 + Single write strobe mode + #1 - MON - Graphics Status Monitor Register - 0x54 + WCR1 + Wait Control Register 1 + 0x0004 32 - read-only - 0x00000000 + read-write + 0x07070707 0xFFFFFFFF - UNDFLST - Status monitor for underflow - 16 - 16 - read-only + CSRWAIT + Normal Read Cycle Wait Select + 24 + 28 + read-write - 1 - An underflow occurs in internal operations. - #1 + 0x00 + No wait is inserted. + 0x00 - 0 - No underflow occurs in internal operations. - #0 + others + Wait with a length of CSRWAIT clock cycle is inserted. + true - ARCST - Status monitor for alpha blending in rectangular area - 0 - 0 - read-only + CSWWAIT + Normal Write Cycle Wait Select + 16 + 20 + read-write - 1 - Fade-in/fade-out is in progress. - #1 + 0x00 + No wait is inserted. + 0x00 - 0 - Fade-in/fade-out is not in progress. - #0 + others + Wait with a length of CSWWAIT clock cycle is inserted. + true - - - - - 3 - 0x40 - GAM[%s] - Gamma Settings - 0x1300 - - LATCH - Gamma Register Update Control Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - VEN - - Control of gamma correction x module register value reflection to internal operations. - The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). - - 0 - 0 + CSPRWAIT + Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. + 8 + 10 read-write - zeroToClear - modify - 1 - Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). - #1 + 0x0 + No wait is inserted. + 0x0 - 0 - Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). - #0 + others + Wait with a length of CSPRWAIT clock cycle is inserted. + true - - - - GAM_SW - Gamma Correction Block Function Switch Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - GAMON - Gamma correction on/off control + CSPWWAIT + Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 - 0 + 2 read-write - 1 - Turns on gamma correction. - #1 + 0x0 + No wait is inserted. + 0x0 - 0 - Turns off gamma correction. - #0 + others + Wait with a length of CSPWWAIT clock cycle is inserted. + true - 8 - 0x04 - LUT[%s] - Gamma Correction Block Table Setting Register - 0x08 + WCR2 + Wait Control Register 2 + 0x0008 32 read-write - 0x00000000 + 0x00000007 0xFFFFFFFF - 2 - 16 - HIGH,LOW - _%s - - Gain value of area 0. - Unsigned 11-bit fixed point. - - 0 - 10 + CSON + CS Assert Wait Select + 28 + 30 read-write - GAIN00 - GAIN00/1024 + 0x0 + No wait is inserted. + 0x0 + + + others + Wait with a length of CSON clock cycle is inserted. true - - - - 5 - 0x04 - AREA[%s] - Gamma Correction Block Area Setting Register - 0x28 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - 3 - 10 - HIGH,MID,LOW - _%s - - Start threshold of area 1 - Unsigned 10-bit integer - - 0 - 9 - read-write - - - - - - OUT - Output Control Registers - 0x13C0 - - VLATCH - Output Control Block Register Update Control Register - 0x0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - VEN - - Control of output control module register value reflection to internal operations. - The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). - - 0 - 0 + WDON + Write Data Output Wait Select + 24 + 26 read-write - zeroToClear - modify - 1 - Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). - #1 + 0x0 + No wait is inserted. + 0x0 - 0 - Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). - #0 + others + Wait with a length of WDON clock cycle is inserted. + true - - - - SET - Output Control Block Output Interface Register - 0x4 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - ENDIANON - Bit endian change control - 28 - 28 + WRON + WR Assert Wait Select + 20 + 22 read-write - 1 - Ascending order (big endian) - #1 + 0x0 + No wait is inserted. + 0x0 - 0 - Descending order (little endian) - #0 + others + Wait with a length of WRON clock cycle is inserted. + true - - SWAPON - Pixel order control - 24 - 24 + + RDON + RD Assert Wait Select + 16 + 18 read-write - 1 - In the order of BGR - #1 + 0x0 + No wait is inserted. + 0x0 - 0 - In the order of RGB - #0 + others + Wait with a length of RDON clock cycle is inserted. + true - FORMAT - Output format select + AWAIT + CS Assert Wait Select 12 13 read-write - 11 - Serial RGB; select RGB888 as dither output format. - #11 + 0x0 + No wait is inserted. + 0x0 - 10 - RGB565; select RGB565 as dither output format. - #10 + others + Wait with a length of AWAIT clock cycle is inserted. + true + + + + WDOFF + Write Data Output Extension Cycle Select + 8 + 10 + read-write + - 01 - RGB666; select RGB666 as dither output format. - #01 + 0x0 + No wait is inserted. + 0x0 - 00 - RGB888; select RGB888 as dither output format. - #00 + others + Wait with a length of WDOFF clock cycle is inserted. + true - FRQSEL - Clock frequency division control - 8 - 9 + CSWOFF + Write-Access CS Extension Cycle Select + 4 + 6 read-write - 11 - Setting prohibited - #11 + 0x0 + No wait is inserted. + 0x0 - 10 - Quarter frequency (serial RGB) - #10 + others + Wait with a length of CSWOFF clock cycle is inserted. + true + + + + CSROFF + Read-Access CS Extension Cycle Select + 0 + 2 + read-write + - 01 - Setting prohibited - #01 + 0x0 + No wait is inserted. + 0x0 - 00 - No frequency division, parallel RGB - #00 + others + Wait with a length of CSROFF clock cycle is inserted. + true + + + + + 8 + 0x10 + CSb[%s] + CS Registers + 0x0800 + + CR + Control Register + 0x002 + 16 + read-write + 0x0000 + 0xFFFF + - DIRSEL - Invalid data position control in serial RGB format - 4 - 4 + MPXEN + Address/Data Multiplexed I/O Interface Select + 12 + 12 read-write + + 0 + Separate bus interface is selected for area n + #0 + 1 - Invalid data is output prior to valid (RGB) data. + Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7) #1 + + + + EMODE + Endian Mode + 8 + 8 + read-write + 0 - Invalid data is output following valid (RGB) data. + Little Endian #0 + + 1 + Big Endian + #1 + - PHASE - Data delay in serial RGB format (based on OUTCLK) - 0 - 1 + BSIZE + External Bus Width Select + 4 + 5 read-write - 11 - 3 cycles - #11 - - - 10 - 2 cycles - #10 + 00 + A 16-bit bus space + #00 01 - 1 cycle + Setting prohibited #01 - 00 - 0 cycle - #00 + 10 + An 8-bit bus space + #10 + + + 11 + Setting prohibited + #11 - - - - BRIGHT1 - Output Control Block Brightness Correction Register 1 - 0x8 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BRTG - - Brightness (DC) adjustment of G signal - Unsigned; 10 bits; +512 with offset; integer - - 0 - 9 - read-write - - - - - BRIGHT2 - Output Control Block Brightness Correction Register 2 - 0xC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BRTB - - Brightness (DC) adjustment of B signal - Unsigned; 10 bits; +512 with offset; integer - - 16 - 25 - read-write - - BRTR - - Brightness (DC) adjustment of R signal - Unsigned; 10 bits; +512 with offset; integer - + EXENB + Operation Enable 0 - 9 + 0 read-write + + + 0 + Disable operation + #0 + + + 1 + Enable operation + #1 + + - CONTRAST - Output Control Block Contrast Correction Register - 0x10 - 32 + REC + Recovery Cycle Register + 0x00A + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - CONTG - - Contrast (GAIN) adjustment of G signal - Unsigned; 8 bits fixed point. - - 16 - 23 + WRCV + Write Recovery + 8 + 11 read-write - CONTG - CONTG/128 - true + 0x0 + No recovery cycle is inserted. + 0x0 - - - - CONTB - - Contrast (GAIN) adjustment of B signal - Unsigned; 8 bits fixed point - - 8 - 15 - read-write - - CONTB - CONTB/128 + others + WRCV recovery cycle is inserted. true - CONTR - - Contrast (GAIN) adjustment of R signal - Unsigned; 8 bits fixed point - + RRCV + Read Recovery 0 - 7 + 3 read-write - CONTR - CONTR/128 + 0x0 + No recovery cycle is inserted. + 0x0 + + + others + RRCV recovery cycle is inserted. true + + + SDRAM + SDRAM Registers + 0x0C00 - PDTHA - Output Control Block Panel Dither Correction Register - 0x14 - 32 + SDCCR + SDC Control Register + 0x00 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - SEL - Operation mode - 20 - 21 + BSIZE + SDRAM Bus Width Select + 4 + 5 read-write - 11 + 00 + A 16-bit bus space + #00 + + + 01 Setting prohibited - #11 + #01 10 - 2x2 pattern dither + An 8-bit bus space #10 - 01 - Round-off - #01 - - - 00 - Truncate - #00 + 11 + Setting prohibited + #11 - FORM - Output format select - 16 - 17 + EXENB + Operation Enable + 0 + 0 read-write - 11 - Setting prohibited - #11 - - - 10 - RGB565; select RGB565 as output interface format. - #10 - - - 01 - RGB666; select RGB666 as output interface format. - #01 + 0 + Disable + #0 - 00 - RGB888; select RGB888 or serial RGB as output interface format. - #00 + 1 + Enable + #1 + + + + SDCMOD + SDC Mode Register + 0x01 + 8 + read-write + 0x00 + 0xFF + - PA - - Pattern value (A) of 2 x 2 pattern dither - Unsigned 2-bit integer - - 12 - 13 - read-write - - - PB - - Pattern value (B) of 2 x 2 pattern dither - Unsigned 2-bit integer - - 8 - 9 - read-write - - - PC - - Pattern value (C) of 2 x 2 pattern dither - Unsigned 2-bit integer - - 4 - 5 - read-write - - - PD - - Pattern value (D) of 2 x 2 pattern dither - Unsigned 2-bit integer - + EMODE + Endian Mode 0 - 1 + 0 read-write + + + 0 + Endian order of SDRAM address space is the same as the endian order of the operating mode + #0 + + + 1 + Endian order of SDRAM address space is not the endian order of the operating mode. + #1 + + - CLKPHASE - Output Control Block Output Phase Control Register - 0x24 - 32 + SDAMOD + SDRAM Access Mode Register + 0x02 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - FRONTGAM - Correction control - 12 - 12 + BE + Continuous Access Enable + 0 + 0 read-write + + 0 + Disable + #0 + 1 - Gamma correction is followed by brightness/contrast correction. + Enable. #1 + + + + + + SDSELF + SDRAM Self-Refresh Control Register + 0x10 + 8 + read-write + 0x00 + 0xFF + + + SFEN + SDRAM Self-Refresh Enable + 0 + 0 + read-write + 0 - Brightness/contrast correction is followed by gamma correction. + Disable #0 + + 1 + Enable + #1 + + + + + SDRFCR + SDRAM Refresh Control Register + 0x14 + 16 + read-write + 0x0001 + 0xFFFF + + + REFW + Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles ) + 12 + 15 + read-write + - LCDEDGE - LCD_DATA Output Phase Control - 8 - 8 + RFC + Auto-Refresh Request Interval Setting + 0 + 11 read-write - 0 - In synchronization with the rising edge of LCD_CLK. - #0 + 0x0 + Setting prohibited + 0x0 - 1 - In synchronization with the falling edge of LCD_CLK - #1 + others + RFC+1 cycles inserted + true + + + + SDRFEN + SDRAM Auto-Refresh Control Register + 0x16 + 8 + read-write + 0x00 + 0xFF + - TCON0EDGE - LCD_TCON0 Output Phase Control - 6 - 6 + RFEN + Auto-Refresh Operation Enable + 0 + 0 read-write - - 1 - In synchronization with the falling edge of LCD_CLK. - #1 - 0 - In synchronization with the rising edge of LCD_CLK. + Disable #0 - - - - TCON1EDGE - LCD_TCON1 Output Phase Control - 5 - 5 - read-write - 1 - In synchronization with the falling edge of LCD_CLK. + Enable #1 - - 0 - In synchronization with the rising edge of LCD_CLK. - #0 - + + + + SDICR + SDRAM Initialization Sequence Control Register + 0x20 + 8 + read-write + 0x00 + 0xFF + - TCON2EDGE - LCD_TCON2 Output Phase Control - 4 - 4 + INIRQ + Initialization Sequence Start + 0 + 0 read-write - - 1 - In synchronization with the falling edge of LCD_CLK. - #1 - 0 - In synchronization with the rising edge of LCD_CLK. + Invalid #0 - - - - TCON3EDGE - LCD_TCON3 Output Phase Control - 3 - 3 - read-write - 1 - In synchronization with the falling edge of LCD_CLK. + Initialization sequence starts #1 - - 0 - In synchronization with the rising edge of LCD_CLK. - #0 - - - - TCON - Timing Control Registers - 0x1400 - TIM - TCON Reference Timing Setting Register - 0x04 - 32 + SDIR + SDRAM Initialization Register + 0x24 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0010 + 0xFFFF - HALF - - Vertical synchronization signal generation change timing - Sets the delay from the assertion of the internal horizontal synchronization signal in terms of pixels. - - 16 - 26 + PRC + Initialization Precharge Cycle Count ( PRF+3 cycles ) + 8 + 10 + read-write + + + ARFC + Initialization Auto-Refresh Count + 4 + 7 read-write - - - 0x000 - 0x3FF - - - HALF - HALF pixels. The valid range is 0x000 to 0x3FF. + 0x0 + Setting prohibited + 0x0 + + + others + ARFC+1 times true - OFFSET - - Horizontal synchronization signal generation reference timing - Sets the offset from the assertion of the internal horizontal synchronization signal in terms of pixels. - + ARFI + Initialization Auto-Refresh Interval ( PRF+3 cycles ) 0 - 10 + 3 read-write - - - 0x000 - 0x3FF - - - - - OFFSET - OFFSET+1 pixels. The valid range is 0x000 to 0x3FF. - true - - - 2 - 0x8 - A,B - STV%s1 - TCON Vertical Timing Setting Register %s1 - 0x08 - 32 + SDADR + SDRAM Address Register + 0x40 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - VS - STVx1 first change timing - 16 - 26 + MXC + Address Multiplex Select + 0 + 1 read-write - - - 0x000 - 0x7FF - - - VS - VS pixels. The valid range is 0x000 to 0x3FF. - true + 00 + 8-bit shift + #00 - - - - VW - - STVx1 second change timing - Sets the signal assertion width. - - 0 - 10 - read-write - - - 0x000 - 0x7FF - - - - VW - VW pixels. The valid range is 0x000 to 0x3FF. - true + 01 + 9-bit shift + #01 + + + 10 + 10-bit shift + #10 + + + 11 + 11-bit shift + #11 - 2 - 0x8 - A,B - STV%s2 - TCON Vertical Timing Setting Register %s2 - 0x0C + SDTR + SDRAM Timing Register + 0x44 32 read-write - 0x00000000 + 0x00000002 0xFFFFFFFF - INV - STVx signal polarity inversion control - 4 - 4 + RAS + Row Active Interval + 16 + 18 read-write - 1 - Inverted - #1 - - - 0 - Not inverted - #0 + 000 + 1 cycle + #000 - - - - SEL - Output signal select control for VSOUT (controlled by TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 register) pin - 0 - 2 - read-write - - 111 - DE - #111 + 001 + 2 cycles + #001 - 110 - Setting prohibited - #110 + 010 + 3 cycles + #010 - 101 - Setting prohibited - #101 + 011 + 4 cycles + #011 100 - Setting prohibited + 5 cycles #100 - 011 - STHB - #011 - - - 010 - STHA - #010 + 101 + 6 cycles + #101 - 001 - STVB - #001 + 110 + 7 cycles + #110 - 000 - STVA - #000 + 111 + Setting prohibited + #111 - - - - 2 - 0x8 - A,B - STH%s1 - TCON Horizontal Timing Setting Register STH%s1 - 0x18 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - HS - STHx1 first change timing - 16 - 26 + RCD + Row Column Latency ( RCD+1 cycles ) + 12 + 13 read-write - - - 0x000 - 0x3FF - - - - - HS - HS lines. The valid range is 0x000 to 0x3FF. - true - - - HW - - STHx1 second change timing. - Sets the signal assertion width. - - 0 - 10 + RP + Row Precharge Interval ( RP+1 cycles ) + 9 + 11 read-write - - - 0x000 - 0x3FF - - - - - HW - HW pixels. The valid range is 0x000 to 0x3FF. - true - - - - - - 2 - 0x8 - A,B - STH%s2 - TCON Horizontal Timing Setting Register STH%s2 - 0x1C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - HSSEL - STHx signal generation reference timing control. + WR + Write Recovery Interval 8 8 read-write - - 1 - Reference timing is the offset set with the TCON_TIM.OFFSET[10:0] (horizontal synchronization generation reference timing) field - #1 - 0 - Reference timing is the input horizontal synchronization signal (HSIN) + 1 cycle #0 - - - - INV - STVx signal polarity inversion control. - 4 - 4 - read-write - 1 - Inverted + 2 cycles #1 - - 0 - Not inverted - #0 - - SEL - Output signal select control for LCD_TCON2 (controlled by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 register) pin. + CL + SDRAMC Column Latency 0 2 read-write - 111 - DE - #111 + 001 + 1 cycle + #001 - 110 - Setting prohibited - #110 + 010 + 2 cycles + #010 - 101 - Setting prohibited - #101 + 011 + 3 cycles + #011 - 100 + others Setting prohibited - #100 + true + + + + + + SDMOD + SDRAM Mode Register + 0x48 + 16 + read-write + 0x0000 + 0xFFFF + + + MR + Mode Register SettingWriting to these bits: Mode register set command is issued. + 0 + 14 + read-write + + + + + SDSR + SDRAM Status Register + 0x50 + 8 + read-only + 0x00 + 0xFF + + + SRFST + Self-Refresh Transition/Recovery Status + 4 + 4 + read-only + - 011 - STHB - #011 + 0 + Transition/recovery not in progress + #0 - 010 - STHA - #010 + 1 + Transition/recovery in progress + #1 + + + + INIST + Initialization Status + 3 + 3 + read-only + - 001 - STVB - #001 + 0 + Initialization sequence not in progress + #0 - 000 - STVA - #000 + 1 + Initialization sequence in progress + #1 - - - - DE - TCON Data Enable Polarity Setting Register - 0x28 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - INV - DE signal polarity inversion control. + MRSST + Mode Register Setting Status 0 0 - read-write + read-only - - 1 - Inverted - #1 - 0 - Not inverted + Mode register setting not in progress #0 + + 1 + Mode register setting in progress + #1 + - SYSCNT - GLCDC System Control Registers - 0x1440 + 11 + 0x10 + + + BUS1 + BUS1 + 0 + + + BUS2 + BUS2 + 1 + + + BUS3 + BUS3 + 2 + + + BUS4 + BUS4 + 3 + + + BUS5 + BUS5 + 4 + + + BUS6 + BUS6 + 5 + + + BUS7 + BUS7 + 6 + + + BUS8 + BUS8 + 7 + + + BUS9 + BUS9 + 8 + + + BUS10 + BUS10 + 9 + + + BUS11 + BUS11 + 10 + + + BUSERR[%s] + Bus Error Registers + 0x1800 - DTCTEN - System control block State Detection Control Register + ADD + Bus Error Address Register 0x00 32 - read-write + read-only 0x00000000 - 0xFFFFFFFF + 0x00000000 - L2UNDFDTC - Graphics 2 underflow detection control - 2 - 2 - read-write + BERAD + Bus Error AddressWhen a bus error occurs, It stores an error address. + 0 + 31 + read-only + + + + + STAT + Bus Error Status Register + 0x04 + 8 + read-only + 0x00 + 0xFE + + + ERRSTAT + Bus Error StatusWhen bus error assert, error flag occurs. + 7 + 7 + read-only - - 1 - Enables detection. - #1 - 0 - Disables detection. + No bus error occurred #0 - - - - L1UNDFDTC - Graphics 1 underflow detection control - 1 - 1 - read-write - 1 - Enables detection. + Bus error occurred #1 - - 0 - Disables detection. - #0 - - VPOSDTC - Specified line detection control + ACCSTAT + Error access statusThe status at the time of the error 0 0 - read-write + read-only - - 1 - Enables detection. - #1 - 0 - Disables detection. + Read access #0 + + 1 + Write Access + #1 + + + + 6 + 0x4 + + + M4I + M4I + 0 + + + M4D + M4D + 1 + + + SYS + SYS + 2 + + + DMA + DMA + 3 + + + EDM + EDM + 4 + + + GPX + GPX + 5 + + + BUSM[%s] + Master Bus Control Register Array + 0x1000 - INTEN - System control block Interrupt Request Enable Control Register - 0x04 - 32 + CNT + Master Bus Control Register + 0x0 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - L2UNDFINTEN - Interrupt request signal GLCDC_L2UNDF enable control. - 2 - 2 + IERES + Ignore Error Responses + 15 + 15 read-write - - 1 - Enables GLCDC_L2UNDF output - #1 - 0 - Disables GLCDC_L2UNDF output + Bus error will be reported. #0 - - - - L1UNDFINTEN - Interrupt request signal GLCDC_L1UNDF enable control. - 1 - 1 - read-write - 1 - Enables GLCDC_L1UNDF output + Bus error will not be reported. #1 - - 0 - Disables GLCDC_L1UNDF output - #0 - + + + + + 16 + 0x4 + + + FLI + FLI + 0 + + + RAMH + RAMH + 1 + + + MBIU + MBIU + 2 + + + RAM0 + RAM0 + 3 + + + RAM1 + RAM1 + 4 + + + P0B + P0B + 5 + + + P2B + P2B + 6 + + + P3B + P3B + 7 + + + P4B + P4B + 8 + + + PxB + PxB + 9 + + + P6B + P6B + 10 + + + P7B + P7B + 11 + + + FBU + FBU + 12 + + + EXT + EXT + 13 + + + EXT2 + EXT2 + 14 + + + GPX + GPX + 15 + + + BUSS[%s] + Slave Bus Control Register Array + 0x1100 + + CNT + Slave Bus Control Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + - VPOSINTEN - Interrupt request signal GLCDC_VPOS enable control. - 0 - 0 + ARBMET + Arbitration MethodSpecify the priority between groups + 4 + 5 read-write - 1 - Enables GLCDC_VPOS output - #1 + 00 + fixed priority + #00 - 0 - Disables GLCDC_VPOS output - #0 + 01 + round-robin + #01 + + + others + Setting prohibited + true + + + CSRECEN + CS Recovery Cycle Insertion Enable Register + 0x0880 + 16 + read-write + 0x3E3E + 0xFFFF + + + 8 + 1 + RCVENM%s + Multiplexed Bus Recovery Cycle Insertion Enable + 8 + 8 + read-write + + + 0 + Recovery cycle insertion is disabled. + #0 + + + 1 + Recovery cycle insertion is enabled. + #1 + + + + + 8 + 1 + RCVEN%s + Separate Bus Recovery Cycle Insertion Enable + 0 + 0 + read-write + + + 0 + Recovery cycle insertion is disabled. + #0 + + + 1 + Recovery cycle insertion is enabled. + #1 + + + + + + + + + R_CAC + Clock Frequency Accuracy Measurement Circuit + 0x40044600 + + 0x00000000 + 0x005 + registers + + + 0x00000006 + 0x006 + registers + + + + CACR0 + CAC Control Register 0 + 0x00 + 8 + read-write + 0x00 + 0xFF + + + CFME + Clock Frequency Measurement Enable. + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + CACR1 + CAC Control Register 1 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + EDGES + Valid Edge Select + 6 + 7 + read-write + + + 00 + Rising edge + #00 + + + 01 + Falling edge + #01 + + + 10 + Both rising and falling edges + #10 + + + 11 + Setting prohibited + #11 + + + + + TCSS + Measurement Target Clock Frequency Division Ratio Select + 4 + 5 + read-write + + + 00 + No division + #00 + + + 01 + x 1/4 clock + #01 + + + 10 + x 1/8 clock + #10 + + + 11 + x 1/32 clock + #11 + + + + + FMCS + Measurement Target Clock Select + 1 + 3 + read-write + + + 000 + Main clock + #000 + + + 001 + Sub-clock + #001 + + + 010 + HOCO clock + #010 + + + 011 + MOCO clock + #011 + + + 100 + LOCO clock + #100 + + + 101 + Peripheral module clock(PCLKB) + #101 + + + 110 + IWDTCLK clock + #110 + + + 111 + Setting prohibited + #111 + + + + + CACREFE + CACREF Pin Input Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + CACR2 + CAC Control Register 2 + 0x02 + 8 + read-write + 0x00 + 0xFF + + + DFS + Digital Filter Selection + 6 + 7 + read-write + + + 00 + Digital filtering is disabled. + #00 + + + 01 + The sampling clock for the digital filter is the frequency measuring clock. + #01 + + + 10 + The sampling clock for the digital filter is the frequency measuring clock divided by 4. + #10 + + + 11 + The sampling clock for the digital filter is the frequency measuring clock divided by 16. + #11 + + + + + RCDS + Measurement Reference Clock Frequency Division Ratio Select + 4 + 5 + read-write + + + 00 + 1/32 clock + #00 + + + 01 + 1/128 clock + #01 + + + 10 + 1/1024 clock + #10 + + + 11 + 1/8192 clock + #11 + + + + + RSCS + Measurement Reference Clock Select + 1 + 3 + read-write + + + 000 + Main clock + #000 + + + 001 + Sub-clock + #001 + + + 010 + HOCO clock + #010 + + + 011 + MOCO clock + #011 + + + 100 + LOCO clock + #100 + + + 101 + Peripheral module clock(PCLKB) + #101 + + + 110 + IWDTCLK clock + #110 + + + 111 + Setting prohibited + #111 + + + + + RPS + Reference Signal Select + 0 + 0 + read-write + + + 0 + CACREF pin input + #0 + + + 1 + Internal clock (internally generated signal) + #1 + + + + + + + CAICR + CAC Interrupt Control Register + 0x03 + 8 + read-write + 0x00 + 0xFF + + + OVFFCL + OVFF Clear + 6 + 6 + write-only + + + 0 + No effect on operations + #0 + + + 1 + Clears the OVFF flag + #1 + + + + + MENDFCL + MENDF Clear + 5 + 5 + write-only + + + 0 + No effect on operations + #0 + + + 1 + Clears the MENDF flag + #1 + + + + + FERRFCL + FERRF Clear + 4 + 4 + write-only + + + 0 + No effect on operations + #0 + + + 1 + Clears the FERRF flag + #1 + + + + + OVFIE + Overflow Interrupt Request Enable + 2 + 2 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + MENDIE + Measurement End Interrupt Request Enable + 1 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + FERRIE + Frequency Error Interrupt Request Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + CASTR + CAC Status Register + 0x04 + 8 + read-only + 0x00 + 0xFF + + + OVFF + Counter Overflow Flag + 2 + 2 + read-only + + + 0 + The counter has not overflowed. + #0 + + + 1 + The counter has overflowed. + #1 + + + + + MENDF + Measurement End Flag + 1 + 1 + read-only + + + 0 + Measurement is in progress. + #0 + + + 1 + Measurement has ended. + #1 + + + + + FERRF + Frequency Error Flag + 0 + 0 + read-only + + + 0 + The clock frequency is within the range corresponding to the settings. + #0 + + + 1 + The clock frequency has deviated beyond the range corresponding to the settings (frequency error). + #1 + + + + + + + CAULVR + CAC Upper-Limit Value Setting Register + 0x06 + 16 + read-write + 0x0000 + 0xFFFF + + + CAULVR + CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency. + 0 + 15 + read-write + + + + + CALLVR + CAC Lower-Limit Value Setting Register + 0x08 + 16 + read-write + 0x0000 + 0xFFFF + + + CALLVR + CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency. + 0 + 15 + read-write + + + + + CACNTBR + CAC Counter Buffer Register + 0x0A + 16 + read-only + 0x0000 + 0xFFFF + + + CACNTBR + CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input + 0 + 15 + read-only + + + + + + + R_CAN0 + Controller Area Network (CAN) Module + 0x40050000 + + 0x00000200 + 0x230 + registers + + + 0x00000820 + 0x039 + registers + + + + 32 + 0x10 + MB[%s] + Mailbox + 0x200 - STCLR - System control block Status Clear Register - 0x08 + ID + Mailbox ID Register + 0x0 32 read-write 0x00000000 - 0xFFFFFFFF + 0x00000000 - L2UNDFCLR - Graphics 2 underflow detection flag clear field - 2 - 2 + IDE + ID Extension + 31 + 31 read-write - - 1 - Clears the graphics 2 underflow detection flag. - #1 - 0 - No operation + Standard ID #0 - - - - L1UNDFCLR - Graphics 1 underflow detection flag clear field - 1 - 1 - read-write - 1 - Clears the graphics 1 underflow detection flag. + Extended ID #1 - - 0 - No operation - #0 - - VPOSCLR - Graphics 2 specified line detection flag clear field - 0 - 0 + RTR + Remote Transmission Request + 30 + 30 read-write - - 1 - Clears the specified line detection flag. - #1 - 0 - No operation + Data frame #0 + + 1 + Remote frame + #1 + + + SID + Standard ID + 18 + 28 + read-write + + + EID + Extended ID + 0 + 17 + read-write + - STMON - System control block Status Monitor Register - 0x0c - 32 - read-only - 0x00000000 - 0xFFFFFFFF + DL + Mailbox DLC Register + 0x4 + 16 + read-write + 0x0000 + 0x0000 - L2UNDF - Graphics 2 underflow detection flag - 2 - 2 - read-only + DLC + Data Length Code + 0 + 3 + read-write - 1 - An underflow has been detected in graphics 2. - #1 + 0000 + Data length = 0 byte + #0000 - 0 - No underflow has been detected in graphics 2. - #0 + 0001 + Data length = 1 byte + #0001 - - - - L1UNDF - Graphics 1 underflow detection flag - 1 - 1 - read-only - - 1 - An underflow has been detected in graphics 1. - #1 + 0010 + Data length = 2 bytes + #0010 - 0 - No underflow has been detected in graphics 1. - #0 + 0011 + Data length = 3 bytes + #0011 - - - - VPOS - Graphics 2 specified line detection flag - 0 - 0 - read-only - - 1 - A specified line notification has been detected in graphics 2. - #1 + 0100 + Data length = 4 bytes + #0100 - 0 - No specified line notification has been detected in graphics 2. - #0 + 0101 + Data length = 5 bytes + #0101 + + + 0110 + Data length = 6 bytes + #0110 + + + 0111 + Data length = 7 bytes + #0111 + + + others + Data length = 8 bytes + true - PANEL_CLK - System control block Version and Panel Clock Control Register - 0x10 - 32 + 8 + 0x01 + D[%s] + Mailbox Data Register + 0x6 + 8 read-write - 0x01000000 - 0xFFFFFFFF + 0x00 + 0x00 - VER - - Version information - Version information of the GLCDC - - 16 - 31 - read-only - - - PIXSEL - - Pixel clock select control. - Must be set to the same value as OUT_SET.FRQSEL[1]. - - 12 - 12 + DATA + DATA0 to DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB-first, and transmission or reception starts from bit 7 + 0 + 7 read-write - - - 0 - No frequency division, parallel RGB - #0 - - - 1 - Quarter frequency,serial RGB - #1 - - + + + + TS + Mailbox Timestamp Register + 0xE + 16 + read-write + 0x0000 + 0x0000 + - CLKSEL - Panel clock supply source select + TSH + Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 - 8 - read-write - - - 0 - External clock select - #0 - - - 1 - PLL output select - #1 - - - - - CLKEN - - Panel clock output enable control - Note: Before changing the PIXSEL,CLKSEL or DCDR bit, this bit must be set to 0. - - 6 - 6 + 15 read-write - - - 0 - Disable panel clock output - #0 - - - 1 - Enable panel clock output - #1 - - - DCDR - - Clock division ratio setting control - Refer toTable 2.7.1 for details about setting value. - Note: Settings that are not listed in table 2.7.1 are prohibited. - + TSL + Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 - 5 + 7 read-write - 256 - 0x4 - GR1_CLUT0[%s] - Color Palette 0 Plane for Graphics 1 Plane - 0x0000 - 32 + 8 + 0x4 + MKR[%s] + Mask Register + 0x400 + 32 + read-write + 0x00000000 + 0x00000000 + + + SID + Standard ID + 18 + 28 + read-write + + + EID + Extended ID + 0 + 17 + read-write + + + + + 2 + 0x4 + FIDCR[%s] + FIFO Received ID Compare Registers + 0x420 + 32 + read-write + 0x00000000 + 0x00000000 + + + IDE + ID Extension + 31 + 31 + read-write + + + 0 + Standard ID + #0 + + + 1 + Extended ID + #1 + + + + + RTR + Remote Transmission Request + 30 + 30 + read-write + + + 0 + Data frame + #0 + + + 1 + Remote frame + #1 + + + + + SID + Standard ID + 18 + 28 + read-write + + + EID + Extended ID + 0 + 17 + read-write + + + + + MKIVLR + Mask Invalid Register + 0x428 + 32 + read-write + 0x00000000 + 0x00000000 + + + MB31 + mailbox 31 Mask Invalid + 31 + 31 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB30 + mailbox 30 Mask Invalid + 30 + 30 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB29 + mailbox 29 Mask Invalid + 29 + 29 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB28 + mailbox 28 Mask Invalid + 28 + 28 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB27 + mailbox 27 Mask Invalid + 27 + 27 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB26 + mailbox 26 Mask Invalid + 26 + 26 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB25 + mailbox 25 Mask Invalid + 25 + 25 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB24 + mailbox 24 Mask Invalid + 24 + 24 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB23 + mailbox 23 Mask Invalid + 23 + 23 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB22 + mailbox 22 Mask Invalid + 22 + 22 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB21 + mailbox 21 Mask Invalid + 21 + 21 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB20 + mailbox 20 Mask Invalid + 20 + 20 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB19 + mailbox 19 Mask Invalid + 19 + 19 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB18 + mailbox 18 Mask Invalid + 18 + 18 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB17 + mailbox 17 Mask Invalid + 17 + 17 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB16 + mailbox 16 Mask Invalid + 16 + 16 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB15 + mailbox 15 Mask Invalid + 15 + 15 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB14 + mailbox 14 Mask Invalid + 14 + 14 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB13 + mailbox 13 Mask Invalid + 13 + 13 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB12 + mailbox 12 Mask Invalid + 12 + 12 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB11 + mailbox 11 Mask Invalid + 11 + 11 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB10 + mailbox 10 Mask Invalid + 10 + 10 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB9 + mailbox 9 Mask Invalid + 9 + 9 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB8 + mailbox 8 Mask Invalid + 8 + 8 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB7 + mailbox 7 Mask Invalid + 7 + 7 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB6 + mailbox 6 Mask Invalid + 6 + 6 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB5 + mailbox 5 Mask Invalid + 5 + 5 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB4 + mailbox 4 Mask Invalid + 4 + 4 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB3 + mailbox 3 Mask Invalid + 3 + 3 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB2 + mailbox 2 Mask Invalid + 2 + 2 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB1 + mailbox 1 Mask Invalid + 1 + 1 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + MB0 + mailbox 0 Mask Invalid + 0 + 0 + read-write + + + 0 + Mask valid + #0 + + + 1 + Mask invalid + #1 + + + + + + + MIER + Mailbox Interrupt Enable Register + 0x42C + 32 + read-write + 0x00000000 + 0x00000000 + + + MB31 + mailbox 31 Interrupt Enable + 31 + 31 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB30 + mailbox 30 Interrupt Enable + 30 + 30 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB29 + mailbox 29 Interrupt Enable + 29 + 29 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB28 + mailbox 28 Interrupt Enable + 28 + 28 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB27 + mailbox 27 Interrupt Enable + 27 + 27 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB26 + mailbox 26 Interrupt Enable + 26 + 26 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB25 + mailbox 25 Interrupt Enable + 25 + 25 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB24 + mailbox 24 Interrupt Enable + 24 + 24 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB23 + mailbox 23 Interrupt Enable + 23 + 23 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB22 + mailbox 22 Interrupt Enable + 22 + 22 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB21 + mailbox 21 Interrupt Enable + 21 + 21 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB20 + mailbox 20 Interrupt Enable + 20 + 20 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB19 + mailbox 19 Interrupt Enable + 19 + 19 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB18 + mailbox 18 Interrupt Enable + 18 + 18 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB17 + mailbox 17 Interrupt Enable + 17 + 17 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB16 + mailbox 16 Interrupt Enable + 16 + 16 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB15 + mailbox 15 Interrupt Enable + 15 + 15 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB14 + mailbox 14 Interrupt Enable + 14 + 14 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB13 + mailbox 13 Interrupt Enable + 13 + 13 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB12 + mailbox 12 Interrupt Enable + 12 + 12 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB11 + mailbox 11 Interrupt Enable + 11 + 11 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB10 + mailbox 10 Interrupt Enable + 10 + 10 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB9 + mailbox 9 Interrupt Enable + 9 + 9 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB8 + mailbox 8 Interrupt Enable + 8 + 8 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB7 + mailbox 7 Interrupt Enable + 7 + 7 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB6 + mailbox 6 Interrupt Enable + 6 + 6 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB5 + mailbox 5 Interrupt Enable + 5 + 5 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB4 + mailbox 4 Interrupt Enable + 4 + 4 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB3 + mailbox 3 Interrupt Enable + 3 + 3 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB2 + mailbox 2 Interrupt Enable + 2 + 2 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB1 + mailbox 1 Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB0 + mailbox 0 Interrupt Enable + 0 + 0 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + + + MIER_FIFO + Mailbox Interrupt Enable Register for FIFO Mailbox Mode + MIER + 0x42C + 32 + read-write + 0x00000000 + 0x00000000 + + + MB29 + Receive FIFO Interrupt Generation Timing Control + 29 + 29 + read-write + + + 0 + Every time reception is completed + #0 + + + 1 + When the receive FIFO becomes buffer warning by completion of reception + #1 + + + + + MB28 + Receive FIFO Interrupt Enable + 28 + 28 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB25 + Transmit FIFO Interrupt Generation Timing Control + 25 + 25 + read-write + + + 0 + Every time transmission is completed + #0 + + + 1 + When the transmit FIFO becomes empty due to completion of transmission + #1 + + + + + MB24 + Transmit FIFO Interrupt Enable + 24 + 24 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB23 + mailbox 23 Interrupt Enable + 23 + 23 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB22 + mailbox 22 Interrupt Enable + 22 + 22 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB21 + mailbox 21 Interrupt Enable + 21 + 21 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB20 + mailbox 20 Interrupt Enable + 20 + 20 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB19 + mailbox 19 Interrupt Enable + 19 + 19 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB18 + mailbox 18 Interrupt Enable + 18 + 18 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB17 + mailbox 17 Interrupt Enable + 17 + 17 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB16 + mailbox 16 Interrupt Enable + 16 + 16 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB15 + mailbox 15 Interrupt Enable + 15 + 15 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB14 + mailbox 14 Interrupt Enable + 14 + 14 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB13 + mailbox 13 Interrupt Enable + 13 + 13 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB12 + mailbox 12 Interrupt Enable + 12 + 12 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB11 + mailbox 11 Interrupt Enable + 11 + 11 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB10 + mailbox 10 Interrupt Enable + 10 + 10 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB9 + mailbox 9 Interrupt Enable + 9 + 9 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB8 + mailbox 8 Interrupt Enable + 8 + 8 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB7 + mailbox 7 Interrupt Enable + 7 + 7 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB6 + mailbox 6 Interrupt Enable + 6 + 6 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB5 + mailbox 5 Interrupt Enable + 5 + 5 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB4 + mailbox 4 Interrupt Enable + 4 + 4 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB3 + mailbox 3 Interrupt Enable + 3 + 3 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB2 + mailbox 2 Interrupt Enable + 2 + 2 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB1 + mailbox 1 Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + MB0 + mailbox 0 Interrupt Enable + 0 + 0 + read-write + + + 0 + Interrupt disabled + #0 + + + 1 + Interrupt enabled + #1 + + + + + + + 32 + 0x1 + MCTL_TX[%s] + Message Control Register for Transmit + 0x820 + 8 + read-write + 0x00 + 0xFF + + + TRMREQ + Transmit Mailbox Request + 7 + 7 + read-write + + + 0 + Not configured for transmission + #0 + + + 1 + Configured for transmission + #1 + + + + + RECREQ + Receive Mailbox Request + 6 + 6 + read-write + + + 0 + Not configured for reception + #0 + + + 1 + Configured for reception + #1 + + + + + ONESHOT + One-Shot Enable + 4 + 4 + read-write + + + 0 + One-shot reception or one-shot transmission disabled + #0 + + + 1 + One-shot reception or one-shot transmission enabled + #1 + + + + + TRMABT + Transmission Abort Complete Flag (Transmit mailbox setting enabled) + 2 + 2 + read-write + + + 0 + Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested + #0 + + + 1 + Transmission abort is completed + #1 + + + + + TRMACTIVE + Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) + 1 + 1 + read-only + + + 0 + Transmission is pending or transmission is not requested + #0 + + + 1 + From acceptance of transmission request to completion of transmission, or error/arbitration-lost + #1 + + + + + SENTDATA + Transmission Complete Flag + 0 + 0 + read-write + + + 0 + Transmission is not completed + #0 + + + 1 + Transmission is completed + #1 + + + + + + + 32 + 0x1 + MCTL_RX[%s] + Message Control Register for Receive + MCTL_TX[%s] + 0x820 + 8 + read-write + 0x00 + 0xFF + + + TRMREQ + Transmit Mailbox Request + 7 + 7 + read-write + + + 0 + Not configured for transmission + #0 + + + 1 + Configured for transmission + #1 + + + + + RECREQ + Receive Mailbox Request + 6 + 6 + read-write + + + 0 + Not configured for reception + #0 + + + 1 + Configured for reception + #1 + + + + + ONESHOT + One-Shot Enable + 4 + 4 + read-write + + + 0 + One-shot reception or one-shot transmission disabled + #0 + + + 1 + One-shot reception or one-shot transmission enabled + #1 + + + + + MSGLOST + Message Lost Flag(Receive mailbox setting enabled) + 2 + 2 + read-write + + + 0 + Message is not overwritten or overrun + #0 + + + 1 + Message is overwritten or overrun + #1 + + + + + INVALDATA + Reception-in-Progress Status Flag (Receive mailbox setting enabled) + 1 + 1 + read-only + + + 0 + Message valid + #0 + + + 1 + Message being updated + #1 + + + + + NEWDATA + Reception Complete Flag + 0 + 0 + read-write + + + 0 + No data has been received or 0 is written to the NEWDATA bit + #0 + + + 1 + A new message is being stored or has been stored to the mailbox + #1 + + + + + + + CTLR + Control Register + 0x840 + 16 + read-write + 0x0500 + 0xFFFF + + + RBOC + Forcible Return From Bus-Off + 13 + 13 + read-write + + + 0 + Nothing occurred + #0 + + + 1 + Forcible return from bus-off + #1 + + + + + BOM + Bus-Off Recovery Mode by a program request + 11 + 12 + read-write + + + 00 + Normal mode (ISO11898-1 compliant) + #00 + + + 01 + Entry to CAN halt mode automatically at bus-off entry + #01 + + + 10 + Entry to CAN halt mode automatically at bus-off end + #10 + + + 11 + Entry to CAN halt mode (during bus-off recovery period) + #11 + + + + + SLPM + CAN Sleep Mode + 10 + 10 + read-write + + + 0 + Other than CAN sleep mode + #0 + + + 1 + CAN sleep mode + #1 + + + + + CANM + CAN Operating Mode Select + 8 + 9 + read-write + + + 00 + CAN operation mode + #00 + + + 01 + CAN reset mode + #01 + + + 10 + CAN halt mode + #10 + + + 11 + CAN reset mode (forcible transition) + #11 + + + + + TSPS + Time Stamp Prescaler Select + 6 + 7 + read-write + + + 00 + Every bit time + #00 + + + 01 + Every 2-bit time + #01 + + + 10 + Every 4-bit time + #10 + + + 11 + Every 8-bit time + #11 + + + + + TSRC + Time Stamp Counter Reset Command + 5 + 5 + read-write + + + 0 + Nothing occurred + #0 + + + 1 + Reset + #1 + + + + + TPM + Transmission Priority Mode Select + 4 + 4 + read-write + + + 0 + ID priority transmit mode + #0 + + + 1 + Mailbox number priority transmit mode + #1 + + + + + MLM + Message Lost Mode Select + 3 + 3 + read-write + + + 0 + Overwrite mode + #0 + + + 1 + Overrun mode + #1 + + + + + IDFM + ID Format Mode Select + 1 + 2 + read-write + + + 00 + Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids. + #00 + + + 01 + Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. + #01 + + + 10 + Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO. + #10 + + + 11 + Do not use this combination + #11 + + + + + MBM + CAN Mailbox Mode Select + 0 + 0 + read-write + + + 0 + Normal mailbox mode + #0 + + + 1 + FIFO mailbox mode + #1 + + + + + + + STR + Status Register + 0x842 + 16 + read-only + 0x0500 + 0xFFFF + + + RECST + Receive Status Flag (receiver) + 14 + 14 + read-only + + + 0 + Bus idle or transmission in progress + #0 + + + 1 + Reception in progress + #1 + + + + + TRMST + Transmit Status Flag (transmitter) + 13 + 13 + read-only + + + 0 + Bus idle or reception in progress + #0 + + + 1 + Transmission in progress or in bus-off state + #1 + + + + + BOST + Bus-Off Status Flag + 12 + 12 + read-only + + + 0 + Not in bus-off state + #0 + + + 1 + In bus-off state + #1 + + + + + EPST + Error-Passive Status Flag + 11 + 11 + read-only + + + 0 + Not in error-passive state + #0 + + + 1 + In error-passive state + #1 + + + + + SLPST + CAN Sleep Status Flag + 10 + 10 + read-only + + + 0 + Not in CAN sleep mode + #0 + + + 1 + In CAN sleep mode + #1 + + + + + HLTST + CAN Halt Status Flag + 9 + 9 + read-only + + + 0 + Not in CAN halt mode + #0 + + + 1 + In CAN halt mode + #1 + + + + + RSTST + CAN Reset Status Flag + 8 + 8 + read-only + + + 0 + Not in CAN reset mode + #0 + + + 1 + In CAN reset mode + #1 + + + + + EST + Error Status Flag + 7 + 7 + read-only + + + 0 + No error occurred + #0 + + + 1 + Error occurred + #1 + + + + + TABST + Transmission Abort Status Flag + 6 + 6 + read-only + + + 0 + No mailbox with TRMABT bit = 1 + #0 + + + 1 + Mailbox(es) with TRMABT bit = 1 + #1 + + + + + FMLST + FIFO Mailbox Message Lost Status Flag + 5 + 5 + read-only + + + 0 + RFMLF bit = 0 + #0 + + + 1 + RFMLF bit = 1 + #1 + + + + + NMLST + Normal Mailbox Message Lost Status Flag + 4 + 4 + read-only + + + 0 + No mailbox with MSGLOST bit = 1 + #0 + + + 1 + Mailbox(es) with MSGLOST bit = 1 + #1 + + + + + TFST + Transmit FIFO Status Flag + 3 + 3 + read-only + + + 0 + Transmit FIFO is full + #0 + + + 1 + Transmit FIFO is not full + #1 + + + + + RFST + Receive FIFO Status Flag + 2 + 2 + read-only + + + 0 + No message in receive FIFO (empty) + #0 + + + 1 + Message in receive FIFO + #1 + + + + + SDST + SENTDATA Status Flag + 1 + 1 + read-only + + + 0 + No mailbox with SENTDATA bit = 1 + #0 + + + 1 + Mailbox(es) with SENTDATA bit = 1 + #1 + + + + + NDST + NEWDATA Status Flag + 0 + 0 + read-only + + + 0 + No mailbox with NEWDATA bit = 1 + #0 + + + 1 + Mailbox(es) with NEWDATA bit = 1 + #1 + + + + + + + BCR + Bit Configuration Register + 0x844 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSEG1 + Time Segment 1 Control + 28 + 31 + read-write + + + 0000 + Setting prohibited + #0000 + + + 0001 + Setting prohibited + #0001 + + + 0010 + Setting prohibited + #0010 + + + 0011 + 4 Tq + #0011 + + + 0100 + 5 Tq + #0100 + + + 0101 + 6 Tq + #0101 + + + 0110 + 7 Tq + #0110 + + + 0111 + 8 Tq + #0111 + + + 1000 + 9 Tq + #1000 + + + 1001 + 10 Tq + #1001 + + + 1010 + 11 Tq + #1010 + + + 1011 + 12 Tq + #1011 + + + 1100 + 13 Tq + #1100 + + + 1101 + 14 Tq + #1101 + + + 1110 + 15 Tq + #1110 + + + 1111 + 16 Tq + #1111 + + + + + BRP + Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). + 16 + 25 + read-write + + + SJW + Resynchronization Jump Width Control + 12 + 13 + read-write + + + 00 + 1 Tq + #00 + + + 01 + 2 Tq + #01 + + + 10 + 3 Tq + #10 + + + 11 + 4 Tq + #11 + + + + + TSEG2 + Time Segment 2 Control + 8 + 10 + read-write + + + 000 + Setting prohibited + #000 + + + 001 + 2 Tq + #001 + + + 010 + 3 Tq + #010 + + + 011 + 4 Tq + #011 + + + 100 + 5 Tq + #100 + + + 101 + 6 Tq + #101 + + + 110 + 7 Tq + #110 + + + 111 + 8 Tq + #111 + + + + + CCLKS + CAN Clock Source Selection + 0 + 0 + read-write + + + 0 + PCLK (generated by the PLL clock) + #0 + + + 1 + CANMCLK (generated by the main clock) + #1 + + + + + + + RFCR + Receive FIFO Control Register + 0x848 + 8 read-write - 0x00000000 - 0x00000000 + 0x80 + 0xFF - A - Alpha Blending Value of Color Palette n Plane for Graphics m Plane - 24 - 31 - read-write + RFEST + Receive FIFO Empty Status Flag + 7 + 7 + read-only + + + 0 + Unread message in receive FIFO + #0 + + + 1 + No unread message in receive FIFO + #1 + + - R - R Value of Color Palette n Plane for Graphics m Plane - 16 - 23 - read-write + RFWST + Receive FIFO Buffer Warning Status Flag + 6 + 6 + read-only + + + 0 + Receive FIFO is not buffer warning + #0 + + + 1 + Receive FIFO is buffer warning (3 unread messages) + #1 + + - G - G Value of Color Palette n Plane for Graphics m Plane - 8 - 15 + RFFST + Receive FIFO Full Status Flag + 5 + 5 + read-only + + + 0 + Receive FIFO is not full + #0 + + + 1 + Receive FIFO is full (4 unread messages) + #1 + + + + + RFMLF + Receive FIFO Message Lost Flag + 4 + 4 read-write + + + 0 + No receive FIFO message lost has occurred + #0 + + + 1 + Receive FIFO message lost has occurred + #1 + + - B - B Value of Color Palette n Plane for Graphics m Plane + RFUST + Receive FIFO Unread Message Number Status + 1 + 3 + read-only + + + 000 + No unread message + #000 + + + 001 + 1 unread message + #001 + + + 010 + 2 unread messages + #010 + + + 011 + 3 unread messages + #011 + + + 100 + 4 unread messages + #100 + + + others + Setting prohibited + true + + + + + RFE + Receive FIFO Enable 0 - 7 + 0 read-write + + + 0 + Receive FIFO disabled + #0 + + + 1 + Receive FIFO enabled + #1 + + - - GR1_CLUT1[%s] - Color Palette 1 Plane for Graphics 1 Plane - 0x0400 - - - - GR2_CLUT0[%s] - Color Palette 0 Plane for Graphics 2 Plane - 0x0800 - - - - GR2_CLUT1[%s] - Color Palette 1 Plane for Graphics 2 Plane - 0x0C00 - + + RFPCR + Receive FIFO Pointer Control Register + 0x849 + 8 + write-only + 0x00 + 0x00 + + + RFPCR + The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR. + 0 + 7 + write-only + + - - - - R_GPT0 - General PWM Timer - 0x40078000 - - 0x00000000 - 0x0A4 - registers - - - GTWP - General PWM Timer Write-Protection Register - 0x00 - 32 + TFCR + Transmit FIFO Control Register + 0x84A + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x80 + 0xFF - PRKEY - GTWP Key Code - 8 - 15 - write-only + TFEST + Transmit FIFO Empty Status + 7 + 7 + read-only - 0xA5 - Written to these bits, the WP bits write is permitted. - 0xA5 + 0 + Unsent message in transmit FIFO + #0 + + + 1 + No unsent message in transmit FIFO + #1 + + + + + TFFST + Transmit FIFO Full Status + 6 + 6 + read-only + + + 0 + Transmit FIFO is not full + #0 + + + 1 + Transmit FIFO is full (4 unsent messages) + #1 + + + + + TFUST + Transmit FIFO Unsent Message Number Status + 1 + 3 + read-only + + + 000 + No unsent message + #000 + + + 001 + 1 unsent message + #001 + + + 010 + 2 unsent messages + #010 + + + 011 + 3 unsent messages + #011 + + + 100 + 4 unsent messages + #100 others - The WP bits write is not permitted. + Setting prohibited true - WP - Register Write Disable - 0 - 0 + TFE + Transmit FIFO Enable + 0 + 0 + read-write + + + 0 + Transmit FIFO disabled + #0 + + + 1 + Transmit FIFO enabled + #1 + + + + + + + TFPCR + Transmit FIFO Pointer Control Register + 0x84B + 8 + write-only + 0x00 + 0x00 + + + TFPCR + The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR. + 0 + 7 + write-only + + + + + EIER + Error Interrupt Enable Register + 0x84C + 8 + read-write + 0x00 + 0xFF + + + BLIE + Bus Lock Interrupt Enable + 7 + 7 + read-write + + + 0 + Bus lock interrupt disabled + #0 + + + 1 + Bus lock interrupt enabled + #1 + + + + + OLIE + Overload Frame Transmit Interrupt Enable + 6 + 6 + read-write + + + 0 + Overload frame transmit interrupt disabled + #0 + + + 1 + Overload frame transmit interrupt enabled + #1 + + + + + ORIE + Overrun Interrupt Enable + 5 + 5 + read-write + + + 0 + Receive overrun interrupt disabled + #0 + + + 1 + Receive overrun interrupt enabled + #1 + + + + + BORIE + Bus-Off Recovery Interrupt Enable + 4 + 4 + read-write + + + 0 + Bus-off recovery interrupt disabled + #0 + + + 1 + Bus-off recovery interrupt enabled + #1 + + + + + BOEIE + Bus-Off Entry Interrupt Enable + 3 + 3 + read-write + + + 0 + Bus-off entry interrupt disabled + #0 + + + 1 + Bus-off entry interrupt enabled + #1 + + + + + EPIE + Error-Passive Interrupt Enable + 2 + 2 read-write 0 - Write to the register is enabled + Error-passive interrupt disabled #0 1 - Write to the register is disabled + Error-passive interrupt enabled #1 - - - - GTSTR - General PWM Timer Software Start Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - 14 - 1 - CSTRT%s - Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. - 0 - 0 + EWIE + Error-Warning Interrupt Enable + 1 + 1 read-write 0 - No effect (write) / counter stop (read) + Error-warning interrupt disabled #0 1 - GTCNT counter starts (write) / Counter running (read) + Error-warning interrupt enabled #1 - - - - GTSTP - General PWM Timer Software Stop Register - 0x08 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - 14 - 1 - CSTOP%s - Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. + BEIE + Bus Error Interrupt Enable 0 0 read-write 0 - No effect (write) / counter running (read) + Bus error interrupt disabled #0 1 - GPT GTCNT counter stops (write) / Counter stop (read) + Bus error interrupt enabled #1 @@ -35704,527 +13523,714 @@ FMS2,1,0: - GTCLR - General PWM Timer Software Clear Register - 0x0C - 32 - write-only - 0x00000000 - 0xFFFFFFFF + EIFR + Error Interrupt Factor Judge Register + 0x84D + 8 + read-write + 0x00 + 0xFF - 14 - 1 - CCLR%s - Channel GTCNT Count Clear - 0 - 0 - write-only + BLIF + Bus Lock Detect Flag + 7 + 7 + read-write 0 - No effect + No bus lock detected #0 1 - GPT GTCNT counter clears + Bus lock detected #1 - - - - GTSSR - General PWM Timer Start Source Select Register - 0x10 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - CSTRT - Software Source Counter Start Enable - 31 - 31 + OLIF + Overload Frame Transmission Detect Flag + 6 + 6 read-write 0 - Counter start is disable by the GTSTR register + No overload frame transmission detected #0 1 - Counter start is enable by the GTSTR register + Overload frame transmission detected #1 - 8 - 1 - A,B,C,D,E,F,G,H - SSELC%s - ELC_GPT Event Source Counter Start Enable - 16 - 16 + ORIF + Receive Overrun Detect Flag + 5 + 5 read-write 0 - Counter start is disable at the ELC_GPT input + No receive overrun detected #0 1 - Counter start is enable at the ELC_GPT input + Receive overrun detected #1 - SSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable - 15 - 15 + BORIF + Bus-Off Recovery Detect Flag + 4 + 4 read-write 0 - Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + No bus-off recovery detected #0 1 - Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + Bus-off recovery detected #1 - SSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable - 14 - 14 + BOEIF + Bus-Off Entry Detect Flag + 3 + 3 read-write 0 - Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + No bus-off entry detected #0 1 - Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Bus-off entry detected #1 - SSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable - 13 - 13 + EPIF + Error-Passive Detect Flag + 2 + 2 read-write 0 - Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + No error-passive detected #0 1 - Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + Error-passive detected #1 - SSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable - 12 - 12 + EWIF + Error-Warning Detect Flag + 1 + 1 read-write 0 - Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + No error-warning detected #0 1 - Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Error-warning detected #1 - SSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable - 11 - 11 + BEIF + Bus Error Detect Flag + 0 + 0 read-write 0 - Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + No bus error detected #0 1 - Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + Bus error detected #1 + + + + RECR + Receive Error Count Register + 0x84E + 8 + read-only + 0x00 + 0xFF + + + RECR + Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception. + 0 + 7 + read-only + + + + + TECR + Transmit Error Count Register + 0x84F + 8 + read-only + 0x00 + 0xFF + - SSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable - 10 - 10 + TECR + Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission. + 0 + 7 + read-only + + + + + ECSR + Error Code Store Register + 0x850 + 8 + read-write + 0x00 + 0xFF + + + EDPM + Error Display Mode Select + 7 + 7 read-write 0 - Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + Output of first detected error code #0 1 - Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Output of accumulated error code #1 - SSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable - 9 - 9 + ADEF + ACK Delimiter Error Flag + 6 + 6 read-write 0 - Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + No ACK delimiter error detected #0 1 - Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + ACK delimiter error detected #1 - SSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable - 8 - 8 + BE0F + Bit Error (dominant) Flag + 5 + 5 read-write 0 - Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + No bit error (dominant) detected #0 1 - Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Bit error (dominant) detected #1 - 4 - 2 - A,B,C,D - SSGTRG%sF - GTETRG Pin Falling Input Source Counter Start Enable - 1 - 1 + BE1F + Bit Error (recessive) Flag + 4 + 4 read-write 0 - Counter start is disable at the falling edge of GTETRG input + No bit error (recessive) detected #0 1 - Counter start is enable at the falling edge of GTETRG input + Bit error (recessive) detected #1 - 4 - 2 - A,B,C,D - SSGTRG%sR - GTETRG Pin Rising Input Source Counter Start Enable - 0 - 0 + CEF + CRC Error Flag + 3 + 3 read-write 0 - Counter start is disable at the rising edge of GTETRG input + No CRC error detected #0 1 - Counter start is enable at the rising edge of GTETRG input + CRC error detected #1 - - - - GTPSR - General PWM Timer Stop Source Select Register - 0x14 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - CSTOP - Software Source Counter Stop Enable - 31 - 31 + AEF + ACK Error Flag + 2 + 2 read-write 0 - Counter stop is disable by the GTSTP register + No ACK error detected #0 1 - Counter stop is enable by the GTSTP register + ACK error detected #1 - 8 - 1 - A,B,C,D,E,F,G,H - PSELC%s - ELC_GPTA Event Source Counter Stop Enable - 16 - 16 + FEF + Form Error Flag + 1 + 1 read-write 0 - Counter stop is disable at the ELC_GPTA input + No form error detected #0 1 - Counter stop is enable at the ELC_GPTA input + Form error detected #1 - PSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable - 15 - 15 + SEF + Stuff Error Flag + 0 + 0 read-write 0 - Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + No stuff error detected #0 1 - Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + Stuff error detected #1 + + + + CSSR + Channel Search Support Register + 0x851 + 8 + read-write + 0x00 + 0x00 + - PSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable - 14 - 14 + CSSR + When the value for the channel search is input, the channel number is output to MSSR. + 0 + 7 read-write + + + + + MSSR + Mailbox Search Status Register + 0x852 + 8 + read-only + 0x80 + 0xFF + + + SEST + Search Result Status + 7 + 7 + read-only 0 - Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + Search result found #0 1 - Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + No search result #1 - PSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable - 13 - 13 + MBNST + Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR. + 0 + 4 + read-only + + + + + MSMR + Mailbox Search Mode Register + 0x853 + 8 + read-write + 0x00 + 0xFF + + + MBSM + Mailbox Search Mode Select + 0 + 1 read-write - 0 - Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + 00 + Receive mailbox search mode + #00 - 1 - Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + 01 + Transmit mailbox search mode + #01 + + + 10 + Message lost search mode + #10 + + + 11 + Channel search mode + #11 + + + + TSR + Time Stamp Register + 0x854 + 16 + read-only + 0x0000 + 0xFFFF + + + TSR + Free-running counter value for the time stamp function + 0 + 15 + read-only + + + + + AFSR + Acceptance Filter Support Register + 0x856 + 16 + read-write + 0x0000 + 0x0000 + - PSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable - 12 - 12 + AFSR + After the standard ID of a received message is written, the value converted for data table search can be read. + 0 + 15 + read-write + + + + + TCR + Test Control Register + 0x858 + 8 + read-write + 0x00 + 0xFF + + + TSTM + CAN Test Mode Select + 1 + 2 read-write - 0 - Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 - #0 + 00 + Other than CAN test mode + #00 - 1 - Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 - #1 + 01 + Listen-only mode + #01 + + + 10 + Self-test mode 0 (external loopback) + #10 + + + 11 + Self-test mode 1 (internal loopback) + #11 - PSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable - 11 - 11 + TSTE + CAN Test Mode Enable + 0 + 0 read-write 0 - Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + CAN test mode disabled #0 1 - Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + CAN test mode enabled #1 + + + + + + R_CAN1 + 0x40051000 + + + R_CRC + Cyclic Redundancy Check (CRC) Calculator + 0x40074000 + + 0x00000000 + 0x002 + registers + + + 0x00000004 + 0x00A + registers + + + + CRCCR0 + CRC Control Register0 + 0x00 + 8 + read-write + 0x00 + 0xFF + - PSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable - 10 - 10 - read-write + DORCLR + CRCDOR Register Clear + 7 + 7 + write-only 0 - Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + No effect. #0 1 - Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Clears the CRCDOR register. #1 - PSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable - 9 - 9 + LMS + CRC Calculation Switching + 6 + 6 read-write 0 - Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + Generates CRC for LSB first communication. #0 1 - Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + Generates CRC for MSB first communication. #1 - PSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable - 8 - 8 + GPS + CRC Generating Polynomial Switching + 0 + 2 read-write - 0 - Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 - #0 + 000 + No calculation is executed. + #000 - 1 - Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 - #1 + 001 + 8-bit CRC-8 (X8 + X2 + X + 1) + #001 + + + 010 + 16-bit CRC-16 (X16 + X15 + X2 + 1) + #010 + + + 011 + 16-bit CRC-CCITT (X16 + X12 + X5 + 1) + #011 + + + 100 + 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) + #100 + + + 101 + 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) + #101 + + + others + No calculation is executed. + true + + + + CRCCR1 + CRC Control Register1 + 0x01 + 8 + read-write + 0x00 + 0xFF + - 4 - 2 - A,B,C,D - PSGTRG%sF - GTETRG Pin Falling Input Source Counter Stop Enable - 1 - 1 + CRCSEN + Snoop enable bit + 7 + 7 read-write 0 - Counter stop is disable at the falling edge of GTETRG input + Disabled #0 1 - Counter stop is enable at the falling edge of GTETRG input + Enabled #1 - 4 - 2 - A,B,C,D - PSGTRG%sR - GTETRG Pin Rising Input Source Counter Stop Enable - 0 - 0 + CRCSWR + Snoop-on-write/read switch bit + 6 + 6 read-write 0 - Counter stop is disable at the rising edge of GTETRG input + Snoop-on-read #0 1 - Counter stop is enable at the rising edge of GTETRG input + Snoop-on-write #1 @@ -36232,476 +14238,499 @@ FMS2,1,0: - GTCSR - General PWM Timer Clear Source Select Register - 0x18 + CRCDIR + CRC Data Input Register + 0x04 32 read-write 0x00000000 0xFFFFFFFF - CCLR - Software Source Counter Clear Enable - 31 + CRCDIR + Calculation input Data (Case of CRC-32, CRC-32C ) + 0 31 read-write - - - 0 - Counter clear is disable by the GTCLR register - #0 - - - 1 - Counter clear is enable by the GTCLR register - #1 - - + + + + CRCDIR_BY + CRC Data Input Register (byte access) + CRCDIR + 0x04 + 8 + read-write + 0x00 + 0xFF + + + CRCDIR_BY + Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) + 0 + 7 + read-write + + + + + CRCDOR + CRC Data Output Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - 8 - 1 - A,B,C,D,E,F,G,H - CSELC%s - ELC_GPTA Event Source Counter Clear Enable - 16 - 16 + CRCDOR + Calculation output Data (Case of CRC-32, CRC-32C ) + 0 + 31 read-write - - - 0 - Counter clear is disable at the ELC_GPTA input - #0 - - - 1 - Counter clear is enable at the ELC_GPTA input - #1 - - + + + + CRCDOR_HA + CRC Data Output Register (halfword access) + CRCDOR + 0x08 + 16 + read-write + 0x0000 + 0xFFFF + - CSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable - 15 + CRCDOR_HA + Calculation output Data (Case of CRC-16 or CRC-CCITT ) + 0 15 read-write + + + + + CRCDOR_BY + CRC Data Output Register(byte access) + CRCDOR + 0x08 + 8 + read-write + 0x00 + 0xFF + + + CRCDOR_BY + Calculation output Data (Case of CRC-8 ) + 0 + 7 + read-write + + + + + CRCSAR + Snoop Address Register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + CRCSA + snoop address bitSet the I/O register address to snoop + 0 + 13 + read-write - 0 - Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 - #0 + 0x0003 + SCI0.TDR + 0x0003 - 1 - Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 - #1 + 0x0005 + SCI0.RDR + 0x0005 - - - - CSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable - 14 - 14 - read-write - - 0 - Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 - #0 + 0x0023 + SCI1.TDR + 0x0023 - 1 - Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 - #1 + 0x0025 + SCI1.RDR + 0x0025 - - - - CSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable - 13 - 13 - read-write - - 0 - Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + 0x0043 + SCI2.TDR + 0x0043 - 1 - Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + 0x0045 + SCI2.RDR + 0x0045 - - - - CSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable - 12 - 12 - read-write - - 0 - Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 - #0 + 0x0063 + SCI3.TDR + 0x0063 - 1 - Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 - #1 + 0x0065 + SCI3.RDR + 0x0065 - - - - CSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable - 11 - 11 - read-write - - 0 - Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 - #0 + 0x0083 + SCI4.TDR + 0x0083 - 1 - Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 - #1 + 0x0085 + SCI4.RDR + 0x0085 - - - - CSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable - 10 - 10 - read-write - - 0 - Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 - #0 + 0x00A3 + SCI5.TDR + 0x00A3 - 1 - Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 - #1 + 0x00A5 + SCI5.RDR + 0x00A5 - - - - CSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable - 9 - 9 - read-write - - 0 - Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 - #0 + 0x00C3 + SCI6.TDR + 0x00C3 - 1 - Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 - #1 + 0x00C5 + SCI6.RDR + 0x00C5 - - - - CSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable - 8 - 8 - read-write - - 0 - Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 - #0 + 0x00E3 + SCI7.TDR + 0x00E3 - 1 - Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 - #1 + 0x00E5 + SCI7.RDR + 0x00E5 - - - - 4 - 2 - A,B,C,D - CSGTRG%sF - GTETRG Pin Falling Input Source Counter Clear Enable - 1 - 1 - read-write - - 0 - Counter clear is disable at the falling edge of GTETRG input - #0 + 0x0103 + SCI8.TDR + 0x0103 - 1 - Counter clear is enable at the falling edge of GTETRG input - #1 + 0x0105 + SCI8.RDR + 0x0105 + + + 0x0123 + SCI9.TDR + 0x0123 + + + 0x0125 + SCI9.RDR + 0x0125 + + + others + Settings other than above are prohibited. + true + + + + + + R_CTSU + Capacitive Touch Sensing Unit + 0x40081000 + + 0x00000000 + 0x01E + registers + + + + CTSUCR0 + CTSU Control Register 0 + 0x00 + 8 + read-write + 0x00 + 0xFF + - 4 - 2 - A,B,C,D - CSGTRG%sR - GTETRG Pin Rising Input Source Counter Clear Enable - 0 - 0 + CTSUTXVSEL + CTSU Transmission power supply selection + 7 + 7 read-write 0 - Counter clear is disable at the rising edge of GTETRG input + Select Vcc #0 1 - Counter clear is enable at the rising edge of GTETRG input + Select internal logic power supply #1 - - - - GTUPSR - General PWM Timer Up Count Source Select Register - 0x1C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - 8 - 1 - A,B,C,D,E,F,G,H - USELC%s - ELC_GPT Event Source Counter Count Up Enable - 16 - 16 + CTSUINIT + CTSU Control Block Initialization + 4 + 4 read-write 0 - Counter count up is disable at the ELC_GPT input + Writing a 0 has no effect, this bit is read as 0. #0 1 - Counter count up is enable at the ELC_GPT input + initializes the CTSU control block and registers. #1 - USCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable - 15 - 15 + CTSUIOC + CTSU Transmit Pin Control + 3 + 3 read-write 0 - Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + Low-level output from transmit channel non-measurement pin. #0 1 - Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + High-level output from transmit channel non-measurement pin. #1 - USCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable - 14 - 14 + CTSUSNZ + CTSU Wait State Power-Saving Enable + 2 + 2 read-write 0 - Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + Power-saving function during wait state is disabled. #0 1 - Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + Power-saving function during wait state is enabled. #1 - USCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable - 13 - 13 + CTSUCAP + CTSU Measurement Operation Start Trigger Select + 1 + 1 read-write 0 - Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + Software trigger. #0 1 - Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + External trigger. #1 - USCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable - 12 - 12 + CTSUSTRT + CTSU Measurement Operation Start + 0 + 0 read-write 0 - Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + Measurement operation stops. #0 1 - Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + Measurement operation starts. #1 + + + + CTSUCR1 + CTSU Control Register 1 + 0x01 + 8 + read-write + 0x00 + 0xFF + - USCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable - 11 - 11 + CTSUMD + CTSU Measurement Mode Select + 6 + 7 read-write - 0 - Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 - #0 + 00 + Self-capacitance single scan mode + #00 - 1 - Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 - #1 + 01 + Self-capacitance multi-scan mode + #01 + + + 10 + Mutual capacitance simple scan mode + #10 + + + 11 + Mutual capacitance full scan mode + #11 - USCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable - 10 - 10 + CTSUCLK + CTSU Operating Clock Select + 4 + 5 read-write - 0 - Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 - #0 + 00 + PCLK + #00 - 1 - Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 - #1 + 01 + PCLK/2 (PCLK divided by 2) + #01 + + + 10 + PCLK/2 (PCLK divided by 4) + #10 + + + 11 + Setting prohibited + #11 - USCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable - 9 - 9 + CTSUATUNE1 + CTSU Power Supply Capacity Adjustment + 3 + 3 read-write 0 - Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + Normal output #0 1 - Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + High-current output #1 - USCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable - 8 - 8 + CTSUATUNE0 + CTSU Power Supply Operating Mode Setting + 2 + 2 read-write 0 - Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + Normal operating mode #0 1 - Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + Low-voltage operating mode #1 - 4 - 2 - A,B,C,D - USGTRG%sF - GTETRG Pin Falling Input Source Counter Count Up Enable + CTSUCSW + CTSU LPF Capacitance Charging Control 1 1 read-write 0 - Counter count up is disable at the falling edge of GTETRG input + Turned off capacitance switch #0 1 - Counter count up is enable at the falling edge of GTETRG input + Turned on capacitance switch #1 - 4 - 2 - A,B,C,D - USGTRG%sR - GTETRG Pin Rising Input Source Counter Count Up Enable + CTSUPON + CTSU Power Supply Enable 0 0 read-write 0 - Counter count up is disable at the rising edge of GTETRG input + Powered off the CTSU #0 1 - Counter count up is enable at the rising edge of GTETRG input + Powered on the CTSU #1 @@ -36709,844 +14738,1038 @@ FMS2,1,0: - GTDNSR - General PWM Timer Down Count Source Select Register - 0x20 - 32 + CTSUSDPRS + CTSU Synchronous Noise Reduction Setting Register + 0x02 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - 8 - 1 - A,B,C,D,E,F,G,H - DSELC%s - ELC_GPT Event Source Counter Count Down Enable - 16 - 16 + CTSUSOFF + CTSU High-Pass Noise Reduction Function Off Setting + 6 + 6 read-write 0 - Counter count down is disable at the ELC_GPT input + High-pass noise reduction function turned on #0 1 - Counter count down is enable at the ELC_GPT input + High-pass noise reduction function turned off #1 - DSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable - 15 - 15 + CTSUPRMODE + CTSU Base Period and Pulse Count Setting + 4 + 5 read-write - 0 - Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 - #0 + 00 + 510 pulses + #00 - 1 - Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 - #1 + 01 + 126 pulses + #01 - - - - DSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable - 14 - 14 - read-write - - 0 - Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 - #0 + 10 + 62 pulses (recommended setting value) + #10 - 1 - Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 - #1 + 11 + Setting prohibited + #11 - DSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable - 13 - 13 + CTSUPRRATIO + CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b) + 0 + 3 + read-write + + + + + CTSUSST + CTSU Sensor Stabilization Wait Control Register + 0x03 + 8 + read-write + 0x00 + 0xFF + + + CTSUSST + CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b. + 0 + 7 + read-write + + + + + CTSUMCH0 + CTSU Measurement Channel Register 0 + 0x04 + 8 + read-write + 0x3F + 0xFF + + + CTSUMCH0 + CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan mode, the measurement is stopped. + 0 + 5 read-write - 0 - Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + TS0 + measured TS0 + 0 - 1 - Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + TS1 + measured TS1 + 1 - - - - DSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable - 12 - 12 - read-write - - 0 - Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 - #0 + TS2 + measured TS2 + 2 - 1 - Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 - #1 + TS3 + measured TS3 + 3 - - - - DSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable - 11 - 11 - read-write - - 0 - Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 - #0 + TS4 + measured TS4 + 4 - 1 - Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 - #1 + TS5 + measured TS5 + 5 - - - - DSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable - 10 - 10 - read-write - - 0 - Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 - #0 + TS6 + measured TS6 + 6 - 1 - Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 - #1 + TS7 + measured TS7 + 7 - - - - DSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable - 9 - 9 - read-write - - 0 - Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 - #0 + TS8 + measured TS8 + 8 + + + TS9 + measured TS9 + 9 + + + TS10 + measured TS10 + 10 + + + TS11 + measured TS11 + 11 + + + TS12 + measured TS12 + 12 + + + TS13 + measured TS13 + 13 + + + TS14 + measured TS14 + 14 + + + TS15 + measured TS15 + 15 + + + TS16 + measured TS16 + 16 + + + TS17 + measured TS17 + 17 + + + TS18 + measured TS18 + 18 + + + TS19 + measured TS19 + 19 + + + TS20 + measured TS20 + 20 + + + TS21 + measured TS21 + 21 + + + TS22 + measured TS22 + 22 + + + TS23 + measured TS23 + 23 + + + TS24 + measured TS24 + 24 + + + TS25 + measured TS25 + 25 + + + TS26 + measured TS26 + 26 + + + TS27 + measured TS27 + 27 + + + TS28 + measured TS28 + 28 + + + TS29 + measured TS29 + 29 - 1 - Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 - #1 + TS30 + measured TS30 + 30 - - - - DSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable - 8 - 8 - read-write - - 0 - Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 - #0 + TS31 + measured TS31 + 31 - 1 - Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 - #1 + TS32 + measured TS32 + 32 - - - - 4 - 2 - A,B,C,D - DSGTRG%sF - GTETRG Pin Falling Input Source Counter Count Down Enable - 1 - 1 - read-write - - 0 - Counter count down is disable at the falling edge of GTETRG input - #0 + TS33 + measured TS33 + 33 - 1 - Counter count down is enable at the falling edge of GTETRG input - #1 + TS34 + measured TS34 + 34 - - - - 4 - 2 - A,B,C,D - DSGTRG%sR - GTETRG Pin Rising Input Source Counter Count Down Enable - 0 - 0 - read-write - - 0 - Counter count down is disable at the rising edge of GTETRG input - #0 + TS35 + measured TS35 + 35 - 1 - Counter count down is enable at the rising edge of GTETRG input - #1 + STOP + Conversion Stopped + #111111 - GTICASR - General PWM Timer Input Capture Source Select Register A - 0x24 - 32 + CTSUMCH1 + CTSU Measurement Channel Register 1 + 0x05 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x3F + 0xFF - 8 - 1 - A,B,C,D,E,F,G,H - ASELC%s - ELC_GPT Event Source GTCCRA Input Capture Enable - 16 - 16 - read-write + CTSUMCH1 + CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 was set to b'111111, the measurement is stopped. + 0 + 5 + read-only - 0 - GTCCRA input capture is disable at the ELC_GPT input - #0 + TS0 + measured TS0 + 0 - 1 - GTCCRA input capture is enable at the ELC_GPT input - #1 + TS1 + measured TS1 + 1 - - - - ASCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable - 15 - 15 - read-write - - 0 - GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 - #0 + TS2 + measured TS2 + 2 - 1 - GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 - #1 + TS3 + measured TS3 + 3 - - - - ASCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable - 14 - 14 - read-write - - 0 - GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 - #0 + TS4 + measured TS4 + 4 - 1 - GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 - #1 + TS5 + measured TS5 + 5 - - - - ASCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable - 13 - 13 - read-write - - 0 - GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + TS6 + measured TS6 + 6 - 1 - GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + TS7 + measured TS7 + 7 - - - - ASCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable - 12 - 12 - read-write - - 0 - GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 - #0 + TS8 + measured TS8 + 8 - 1 - GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 - #1 + TS9 + measured TS9 + 9 - - - - ASCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable - 11 - 11 - read-write - - 0 - GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 - #0 + TS10 + measured TS10 + 10 - 1 - GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 - #1 + TS11 + measured TS11 + 11 - - - - ASCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable - 10 - 10 - read-write - - 0 - GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 - #0 + TS12 + measured TS12 + 12 - 1 - GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 - #1 + TS13 + measured TS13 + 13 - - - - ASCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable - 9 - 9 - read-write - - 0 - GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 - #0 + TS14 + measured TS14 + 14 - 1 - GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 - #1 + TS15 + measured TS15 + 15 - - - - ASCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable - 8 - 8 - read-write - - 0 - GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 - #0 + TS16 + measured TS16 + 16 - 1 - GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 - #1 + TS17 + measured TS17 + 17 - - - - 4 - 2 - A,B,C,D - ASGTRG%sF - GTETRG Pin Falling Input Source GTCCRA Input Capture Enable - 1 - 1 - read-write - - 0 - GTCCRA input capture is disable at the falling edge of GTETRG input - #0 + TS18 + measured TS18 + 18 - 1 - GTCCRA input capture is enable at the falling edge of GTETRG input - #1 + TS19 + measured TS19 + 19 - - - - 4 - 2 - A,B,C,D - ASGTRG%sR - GTETRG Pin Rising Input Source GTCCRA Input Capture Enable - 0 - 0 - read-write - - 0 - GTCCRA input capture is disable at the rising edge of GTETRG input - #0 + TS20 + measured TS20 + 20 - 1 - GTCCRA input capture is enable at the rising edge of GTETRG input - #1 + TS21 + measured TS21 + 21 - - - - - - GTICBSR - General PWM Timer Input Capture Source Select Register B - 0x28 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - 8 - 1 - A,B,C,D,E,F,G,H - BSELC%s - ELC_GPT Event Source GTCCRB Input Capture Enable - 16 - 16 - read-write - - 0 - GTCCRB input capture is disable at the ELC_GPT input - #0 + TS22 + measured TS22 + 22 - 1 - GTCCRB input capture is enable at the ELC_GPT input - #1 + TS23 + measured TS23 + 23 - - - - BSCBFAH - GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable - 15 - 15 - read-write - - 0 - GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 - #0 + TS24 + measured TS24 + 24 - 1 - GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 - #1 + TS25 + measured TS25 + 25 - - - - BSCBFAL - GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable - 14 - 14 - read-write - - 0 - GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 - #0 + TS26 + measured TS26 + 26 - 1 - GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 - #1 + TS27 + measured TS27 + 27 - - - - BSCBRAH - GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable - 13 - 13 - read-write - - 0 - GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 - #0 + TS28 + measured TS28 + 28 - 1 - GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 - #1 + TS29 + measured TS29 + 29 + + + TS30 + measured TS30 + 30 + + + TS31 + measured TS31 + 31 + + + TS32 + measured TS32 + 32 + + + TS33 + measured TS33 + 33 + + + TS34 + measured TS34 + 34 + + + TS35 + measured TS35 + 35 + + + STOP + Conversion Stopped + #111111 + + + + 5 + 1 + CTSUCHAC[%s] + CTSU Channel Enable Control Register + 0x06 + 8 + read-write + 0x00 + 0xFF + - BSCBRAL - GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable - 12 - 12 + 8 + 1 + TS%s + CTSU Channel Enable Control + 0 + 0 read-write 0 - GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 - #0 + Do not measure + 0 1 - GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 - #1 + Measure + 1 + + + + 5 + 1 + CTSUCHTRC[%s] + CTSU Channel Transmit/Receive Control Register + 0x0B + 8 + read-write + 0x00 + 0xFF + - BSCAFBH - GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable - 11 - 11 + 8 + 1 + TS%s + CTSU Channel Transmit/Receive Control + 0 + 0 read-write 0 - GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + Reception #0 1 - GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + Transmission #1 + + + + CTSUDCLKC + CTSU High-Pass Noise Reduction Control Register + 0x10 + 8 + read-write + 0x00 + 0xFF + + + CTSUSSCNT + CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b. + 4 + 5 + read-write + - BSCAFBL - GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable - 10 - 10 + CTSUSSMOD + CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b. + 0 + 1 read-write + + + + + CTSUST + CTSU Status Register + 0x11 + 8 + read-write + 0x00 + 0xFF + + + CTSUPS + CTSU Mutual Capacitance Status Flag + 7 + 7 + read-only 0 - GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + First measurement #0 1 - GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + Second measurement #1 - BSCARBH - GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable - 9 - 9 + CTSUROVF + CTSU Reference Counter Overflow Flag + 6 + 6 read-write 0 - GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + No overflow #0 1 - GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + An overflow #1 - BSCARBL - GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable - 8 - 8 + CTSUSOVF + CTSU Sensor Counter Overflow Flag + 5 + 5 read-write 0 - GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + No overflow #0 1 - GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + An overflow #1 - 4 - 2 - A,B,C,D - BSGTRG%sF - GTETRG Pin Falling Input Source GTCCRB Input Capture Enable - 1 - 1 - read-write + CTSUDTSR + CTSU Data Transfer Status Flag + 4 + 4 + read-only 0 - GTCCRB input capture is disable at the falling edge of GTETRG input + Measurement result has been read #0 1 - GTCCRB input capture is enable at the falling edge of GTETRG input + Measurement result has not been read #1 - 4 - 2 - A,B,C,D - BSGTRG%sR - GTETRG Pin Rising Input Source GTCCRB Input Capture Enable + CTSUSTC + CTSU Measurement Status Counter 0 - 0 - read-write + 2 + read-only - 0 - GTCCRB input capture is disable at the rising edge of GTETRG input - #0 + 000 + Status 0 + #000 - 1 - GTCCRB input capture is enable at the rising edge of GTETRG input - #1 + 001 + Status 1 + #001 + + + 010 + Status 2 + #010 + + + 011 + Status 3 + #011 + + + 100 + Status 4 + #100 + + + 101 + Status 5 + #101 - GTCR - General PWM Timer Control Register - 0x2C - 32 + CTSUSSC + CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register + 0x12 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - TPCS - Timer Prescaler Select - 24 - 26 + CTSUSSDIV + CTSU Spectrum Diffusion Frequency Division Setting + 8 + 11 read-write 0000 - PCLK/1 + 4.00 <= fb #0000 0001 - PCLK/2 + 2.00 <= fb < 4.00 #0001 0010 - PCLK/4 + 1.33 <= fb < 2.00 #0010 0011 - PCLK/8 + 1.00 <= fb < 1.33 #0011 0100 - PCLK/16 + 0.80 <= fb < 1.00 #0100 0101 - PCLK/32 + 0.67 <= fb < 0.80 #0101 0110 - PCLK/64 + 0.57 <= fb < 0.67 #0110 + + 0111 + 0.50 <= fb < 0.57 + #0111 + 1000 - PCLK/256 + 0.44 <= fb < 0.50 #1000 + + 1001 + 0.40 <= fb < 0.44 + #1001 + 1010 - PCLK/1024 + 0.36 <= fb < 0.40 #1010 + + 1011 + 0.33 <= fb < 0.36 + #1011 + 1100 - GTETRGA + 0.31 <= fb < 0.33 #1100 1101 - GTETRGB + 0.29 <= fb < 0.31 #1101 1110 - GTETRGC + 0.27 <= fb < 0.29 #1110 1111 - GTETRGD + fb < 0.27 #1111 + + + + + + CTSUSO0 + CTSU Sensor Offset Register 0 + 0x14 + 16 + read-write + 0x0000 + 0xFFFF + + + CTSUSNUM + CTSU Measurement Count Setting + 10 + 15 + read-write + + + CTSUSO + CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 ) + 0 + 9 + read-write + + + + + CTSUSO1 + CTSU Sensor Offset Register 1 + 0x16 + 16 + read-write + 0x0000 + 0xFFFF + + + CTSUICOG + CTSU ICO Gain Adjustment + 13 + 14 + read-write + + + 00 + 100 percent gain + #00 + - others - Setting prohibied - true + 01 + 66 percent gain + #01 + + + 10 + 50 percent gain + #10 + + + 11 + 40 percent gain + #11 - MD - Mode Select - 16 - 18 + CTSUSDPA + CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2 + 8 + 12 + read-write + + + CTSURICOA + CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 ) + 0 + 7 read-write + + + + + CTSUSC + CTSU Sensor Counter + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + CTSUSC + CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs. + 0 + 15 + read-only + + + + + CTSURC + CTSU Reference Counter + 0x1A + 16 + read-only + 0x0000 + 0xFFFF + + + CTSURC + CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs. + 0 + 15 + read-only + + + + + CTSUERRS + CTSU Error Status Register + 0x1C + 16 + read-only + 0x0000 + 0xFFFF + + + CTSUICOMP + TSCAP Voltage Error Monitor + 15 + 15 + read-only - 000 - Saw-wave PWM mode (single buffer or double buffer possible) - #000 + 0 + Normal TSCAP voltage + #0 - 001 - Saw-wave one-shot pulse mode (fixed buffer operation) - #001 + 1 + Abnormal TSCAP voltage + #1 + + + + CTSUSPMD + Calibration Mode + 0 + 1 + read-write + - 010 - Setting prohibited - #010 + 00 + Capacitance measurement mode + #00 - 011 - Setting prohibited - #011 + 10 + Calibration mode + #10 - 100 - Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) - #100 + Others + Seting prohibited + true + + + + CTSUTSOD + TS Pin Fixed Output + 2 + 2 + read-write + - 101 - Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) - #101 + 0 + Capacitance measurement mode + #0 - 110 - Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) - #110 + 1 + TS pins are forced to be high or low + #1 + + + + + CTSUDRV + Calibration Setting 1 + 3 + 3 + read-write + + + 0 + Capacitance measurement mode + #0 - 111 - Setting prohibited - #111 + 1 + Calibration setting 1 + #1 - CST - Count Start - 0 - 0 + CTSUTSOC + Calibration Setting 2 + 7 + 7 read-write 0 - Count operation is stopped + Capacitance measurement mode #0 1 - Count operation is performed + Calibration setting 2 #1 @@ -37554,1767 +15777,1753 @@ FMS2,1,0: - GTUDDTYC - General PWM Timer Count Direction and Duty Setting Register - 0x30 + CTSUTRMR + CTSU Reference Current Calibration Register + 0x20 + 8 + read-write + 0x00 + 0x00 + + + + + R_CTSU2 + Capacitive Touch Sensing Unit + 0x40082000 + + 0x00 + 12 + registers + + + 0x0C + 8 + registers + + + 0x14 + 8 + registers + + + 0x1C + 4 + registers + + + 0x20 + 8 + registers + + + 0x28 + 16 + registers + + + + CTSUCRA + CTSU Control Register A + 0x00 32 read-write - 0x00000001 - 0xFFFFFFFF + 0x00000000 + 0xffffffff - OBDTYR - GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting - 27 - 27 + STRT + CTSU Measurement Operation Start + 0 + 0 read-write 0 - Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + Stop measurement operation #0 1 - Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. + Start measurement operation #1 - OBDTYF - Forcible GTIOCB Output Duty Setting - 26 - 26 + CAP + CTSU Measurement Operation Start Trigger Select + 1 + 1 read-write 0 - Not forcibly set + Software trigger #0 1 - Forcibly set + External trigger #1 - OBDTY - GTIOCB Output Duty Setting - 24 - 25 + SNZ + CTSU Wait State Power-Saving Enable + 2 + 2 read-write - 00 - GTIOCB pin duty is depend on compare match - #00 - - - 01 - GTIOCB pin duty is depend on compare match - #01 - - - 10 - GTIOCB pin duty 0 percent - #10 + 0 + Disable power-saving function during wait state + #0 - 11 - GTIOCB pin duty 100 percent - #11 + 1 + Enable power-saving function during wait state + #1 - OADTYR - GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting - 19 - 19 + CFCON + CTSU CFC Power on Control + 3 + 3 read-write 0 - Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + CFC power off #0 1 - Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. + CFC power on #1 - OADTYF - Forcible GTIOCA Output Duty Setting - 18 - 18 + INIT + CTSU Control Block Initialization + 4 + 4 + write-only + + + PUMPON + CTSU Boost Circuit Control + 5 + 5 read-write 0 - Not forcibly set + Boost circuit off #0 1 - Forcibly set + Boost circuit on #1 - OADTY - GTIOCA Output Duty Setting - 16 - 17 + TXVSEL + CTSU Transmission Power Supply Selection + 6 + 7 read-write 00 - GTIOCA pin duty is depend on compare match + VCC is selected as the power supply for the transmit pins in measurement methods other than self-capacitance method. #00 01 - GTIOCA pin duty is depend on compare match + VCC is selected as the power supply for the transmit pins in self-capacitance method. #01 10 - GTIOCA pin duty 0 percent + VCL is selected as the power-supply voltage for the transmit pins. #10 11 - GTIOCA pin duty 100 percent + Setting prohibited #11 - UDF - Forcible Count Direction Setting - 1 - 1 + PON + CTSU Power Supply Enable + 8 + 8 read-write 0 - Not forcibly set + Power off the CTSU #0 1 - Forcibly set + Power on the CTSU #1 - UD - Count Direction Setting - 0 - 0 + CSW + CTSU LPF Capacitance Charging Control + 9 + 9 read-write 0 - GTCNT counts down. + Turn off capacitance switch #0 1 - GTCNT counts up. + Turn on capacitance switch #1 - - - - GTIOR - General PWM Timer I/O Control Register - 0x34 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - NFCSB - Noise Filter B Sampling Clock Select - 30 - 31 + ATUNE0 + CTSU Power Supply Operating Mode Setting + 10 + 10 read-write - 00 - PCLK/1 - #00 - - - 01 - PCLK/4 - #01 - - - 10 - PCLK/16 - #10 + 0 + VCC ≥ 2.4 V: Normal operating mode + VCC < 2.4 V: Setting prohibited + + #0 - 11 - PCLK/64 - #11 + 1 + Low-voltage operating mode + #1 - NFBEN - Noise Filter B Enable - 29 - 29 + ATUNE1 + CTSU Current Range Adjustment + 11 + 11 read-write 0 - The noise filter for the GTIOCB pin is disabled. + 40 µA when CTSUATUNE2 = 0 + 20 µA when CTSUATUNE2 = 1 + #0 1 - The noise filter for the GTIOCB pin is enabled. + 80 µA when CTSUATUNE2 = 0 + 160 µA when CTSUATUNE2 = 1 + #1 - OBDF - GTIOCB Pin Disable Value Setting - 25 - 26 + CLK + CTSU Operating Clock Select + 12 + 13 read-write 00 - Output disable is prohibited. + PCLKB #00 01 - GTIOCB pin is set to Hi-Z when output disable is performed. + PCLKB/2 (PCLKB divided by 2) #01 10 - GTIOCB pin is set to 0 when output disable is performed. + PCLKB/4 (PCLKB divided by 4) #10 11 - GTIOCB pin is set to 1 when output disable is performed. + PCLKB/8 (PCLKB divided by 8) #11 - OBE - GTIOCB Pin Output Enable - 24 - 24 + MD0 + CTSU Measurement Mode Select 0 + 14 + 14 read-write 0 - Output is disabled + Single scan mode #0 1 - Output is enabled + Multi-scan mode #1 - OBHLD - GTIOCB Pin Output Setting at the Start/Stop Count - 23 - 23 + MD1 + CTSU Measurement Mode Select 1 + 15 + 15 read-write 0 - The GTIOCB pin output level at start/stop of counting depends on the register setting. + Single scan mode #0 1 - The GTIOCB pin output level is retained at start/stop of counting. + Multi-scan mode #1 - OBDFLT - GTIOCB Pin Output Value Setting at the Count Stop - 22 - 22 + MD2 + CTSU Measurement Mode Select 2 + 16 + 16 read-write 0 - The GTIOCB pin outputs low when counting is stopped. + Measure the current that flows through the switched capacitor. #0 1 - The GTIOCB pin outputs high when counting is stopped. + Measure the transfer charge in CFC circuit (high speed measurement) #1 - GTIOB - GTIOCB Pin Function Select - 16 - 20 + ATUNE2 + CTSU Current Range Adjustment + 17 + 17 read-write - 00000 - Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. - #00000 - - - 00001 - Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. - #00001 - - - 00010 - Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. - #00010 - - - 00011 - Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. - #00011 - - - 00100 - Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. - #00100 - - - 00101 - Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. - #00101 - - - 00110 - Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. - #00110 - - - 00111 - Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. - #00111 - - - 01000 - Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. - #01000 - - - 01001 - Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. - #01001 - - - 01010 - Initial output is Low. High output at cycle end. High output at GTCCRB compare match. - #01010 - - - 01011 - Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. - #01011 - - - 01100 - Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. - #01100 - - - 01101 - Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. - #01101 - - - 01110 - Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. - #01110 - - - 01111 - Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. - #01111 - - - 10000 - Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. - #10000 - - - 10001 - Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. - #10001 - - - 10010 - Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. - #10010 - - - 10011 - Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. - #10011 - - - 10100 - Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. - #10100 + 0 + 40 µA when CTSUATUNE1 = 0 + 80 µA when CTSUATUNE2 = 1 + + #0 - 10101 - Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. - #10101 + 1 + 20 µA when CTSUATUNE1 = 0 + 160 µA when CTSUATUNE2 = 1 + + #1 + + + + LOAD + CTSU Measurement Load Control + 18 + 19 + read-write + - 10110 - Initial output is High. Low output at cycle end. High output at GTCCRB compare match. - #10110 + 00 + Normal measurement mode + #00 - 10111 - Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. - #10111 + 01 + Load off mode + #01 - 11000 - Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. - #11000 + 10 + Current load mode + #10 - 11001 - Initial output is High. High output at cycle end. Low output at GTCCRB compare match. - #11001 + 11 + Resistance load mode + #11 + + + + POSEL + CTSU Non-measured Channel Output Select + 20 + 21 + read-write + - 11010 - Initial output is High. High output at cycle end. High output at GTCCRB compare match. - #11010 + 00 + Output low through GPIO + #00 - 11011 - Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. - #11011 + 01 + Hi-Z + #01 - 11100 - Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. - #11100 + 10 + Output low through the power setting in the TXVSEL[1:0] bits + #10 - 11101 - Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. - #11101 + 11 + Same phase pulse output as transmission channel through the power setting in the TXVSEL[1:0] bits + #11 + + + + SDPSEL + CTSU Sensor Drive Pulse Select + 22 + 22 + read-write + - 11110 - Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. - #11110 + 0 + Random pulse mode + #0 - 11111 - Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. - #11111 + 1 + High resolution pulse mode + #1 - NFCSA - Noise Filter A Sampling Clock Select - 14 - 15 + FCMODE + CTSU SUCLK Control + 23 + 23 read-write - 00 - PCLK/1 - #00 + 0 + SUCLK is used as frequency diffusion clock + #0 - 01 - PCLK/4 - #01 + 1 + SUCLK is used as recovery clock for multi-clock measurement + #1 + + + + STCLK + CTSU STCLK Select + 24 + 29 + read-write + + + DCMODE + CTSU Current Measurement Mode Select + 30 + 30 + read-write + - 10 - PCLK/16 - #10 + 0 + Normal mode + #0 - 11 - PCLK/64 - #11 + 1 + Current measurement mode + #1 - NFAEN - Noise Filter A Enable - 13 - 13 + DCBACK + CTSU Current Measurement Feedback Select + 31 + 31 read-write 0 - The noise filter for the GTIOCA pin is disabled. + TSCAP pin is selected #0 1 - The noise filter for the GTIOCA pin is enabled. + Measurement pin is selected #1 + + + + CTSUCRAL + CTSU Control Register A + CTSUCRA + 0x00 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCR0 + CTSU Control Register A + CTSUCRA + 0x00 + 8 + read-write + 0x00 + 0xff + + + CTSUCR1 + CTSU Control Register A + CTSUCRA + 0x01 + 8 + read-write + 0x00 + 0xff + + + CTSUCR2 + CTSU Control Register A + CTSUCRAH + 0x02 + 8 + read-write + 0x00 + 0xff + + + CTSUCR3 + CTSU Control Register A + CTSUCRA + 0x03 + 8 + read-write + 0x00 + 0xff + + + CTSUCRB + CTSU Control Register B + 0x04 + 32 + read-write + 0x00000000 + 0xffffffff + + + PRRATIO + CTSU Measurement Time and Pulse Count Adjustment + 0 + 3 + read-write + - OADF - GTIOCA Pin Disable Value Setting - 9 - 10 + PRMODE + CTSU Base Period and Pulse Count Setting + 4 + 5 read-write 00 - Output disable is prohibited. + 510 pulses (512 pulses when PROFF bit is 1) #00 01 - GTIOCA pin is set to Hi-Z when output disable is performed. + 126 pulses (128 pulses when PROFF bit is 1) #01 10 - GTIOCA pin is set to 0 when output disable is performed. + 62 pulses (recommended setting) (64 pulses when PROFF bit is 1) #10 11 - GTIOCA pin is set to 1 when output disable is performed. + Setting prohibited #11 - OAE - GTIOCA Pin Output Enable - 8 - 8 + SOFF + CTSU High-Pass Noise Reduction Function Off Setting + 6 + 6 read-write 0 - Output is disabled + Turn spectrum diffusion on. #0 1 - Output is enabled + Turn spectrum diffusion off. #1 - OAHLD - GTIOCA Pin Output Setting at the Start/Stop Count + PROFF + CTSU Random Number Off Control 7 7 read-write 0 - The GTIOCA pin output level at start/stop of counting depends on the register setting. + There is random number control. #0 1 - The GTIOCA pin output level is retained at start/stop of counting. + There is no random number control. #1 - OADFLT - GTIOCA Pin Output Value Setting at the Count Stop - 6 - 6 + SST + CTSU Sensor Stabilization Wait Control + 8 + 15 read-write - - - 0 - The GTIOCA pin outputs low when counting is stopped. - #0 - - - 1 - The GTIOCA pin outputs high when counting is stopped. - #1 - - - GTIOA - GTIOCA Pin Function Select + SSMOD + CTSU SUCLK Diffusion Mode Select + 24 + 26 + read-write + + + SSCNT + CTSU SUCLK Diffusion Control + 28 + 29 + read-write + + + + + CTSUCRBL + CTSU Control Register B + CTSUCRB + 0x04 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSDPRS + CTSU Control Register B + CTSUCRB + 0x04 + 8 + read-write + 0x00 + 0xff + + + CTSUSST + CTSU Control Register B + CTSUCRB + 0x05 + 8 + read-write + 0x00 + 0xff + + + CTSUCRBH + CTSU Control Register B + CTSUCRB + 0x06 + 16 + read-write + 0x0000 + 0xffff + + + CTSUDCLKC + CTSU Control Register B + CTSUCRB + 0x07 + 8 + read-write + 0x00 + 0xff + + + CTSUMCH + CTSU Measurement Channel Register + 0x08 + 32 + read-write + 0x00003f3f + 0xffffffff + + + MCH0 + CTSU Measurement Channel 0 0 - 4 + 5 read-write - 00000 - Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. - #00000 + 0x00 + TS00 + 0x00 - 00001 - Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. - #00001 + 0x02 + TS02 + 0x02 - 00010 - Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. - #00010 + 0x04 + TS04 + 0x04 - 00011 - Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. - #00011 + 0x05 + TS05 + 0x05 - 00100 - Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. - #00100 + 0x06 + TS06 + 0x06 - 00101 - Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. - #00101 + 0x07 + TS07 + 0x07 - 00110 - Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. - #00110 + 0x08 + TS08 + 0x08 - 00111 - Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. - #00111 + 0x09 + TS09 + 0x09 - 01000 - Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. - #01000 + 0x0A + TS10 + 0x0a - 01001 - Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. - #01001 + 0x0B + TS11 + 0x0b - 01010 - Initial output is Low. High output at cycle end. High output at GTCCRA compare match. - #01010 + 0x0C + TS12 + 0x0c - 01011 - Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. - #01011 + 0x0D + TS13 + 0x0d - 01100 - Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. - #01100 + 0x0E + TS14 + 0x0e - 01101 - Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. - #01101 + 0x0F + TS15 + 0x0f - 01110 - Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. - #01110 + 0x10 + TS16 + 0x10 - 01111 - Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. - #01111 + 0x11 + TS17 + 0x11 - 10000 - Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. - #10000 + 0x12 + TS18 + 0x12 - 10001 - Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. - #10001 + 0x15 + TS21 + 0x15 - 10010 - Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. - #10010 + 0x16 + TS22 + 0x16 - 10011 - Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. - #10011 + 0x17 + TS23 + 0x17 - 10100 - Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. - #10100 + 0x18 + TS24 + 0x18 - 10101 - Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. - #10101 + 0x19 + TS25 + 0x19 - 10110 - Initial output is High. Low output at cycle end. High output at GTCCRA compare match. - #10110 + 0x1A + TS26 + 0x1a - 10111 - Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. - #10111 + 0x1B + TS27 + 0x1b - 11000 - Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. - #11000 + 0x1C + TS28 + 0x1c - 11001 - Initial output is High. High output at cycle end. Low output at GTCCRA compare match. - #11001 + 0x1D + TS29 + 0x1d - 11010 - Initial output is High. High output at cycle end. High output at GTCCRA compare match. - #11010 + 0x1E + TS30 + 0x1e - 11011 - Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. - #11011 + 0x1F + TS31 + 0x1f - 11100 - Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. - #11100 + 0x20 + TS32 + 0x20 - 11101 - Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. - #11101 + 0x21 + TS33 + 0x21 - 11110 - Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. - #11110 + 0x22 + TS34 + 0x22 - 11111 - Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. - #11111 + 0x23 + TS35 + 0x23 + + + 0x3F + Measurement is being stopped. + 0x3f - - - - GTINTAD - General PWM Timer Interrupt Output Setting Register - 0x38 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - GRPABL - Same Time Output Level Low Disable Request Enable - 30 - 30 + MCH1 + CTSU Measurement Channel 1 + 8 + 13 read-write - 0 - Same time output level low disable request is disabled. - #0 + 0x00 + TS00 + 0x00 - 1 - Same time output level low disable request is enabled. - #1 + 0x02 + TS02 + 0x02 - - - - GRPABH - Same Time Output Level High Disable Request Enable - 29 - 29 - read-write - - 0 - Same time output level high disable request is disabled. - #0 + 0x04 + TS04 + 0x04 - 1 - Same time output level high disable request is enabled. - #1 + 0x05 + TS05 + 0x05 - - - - GRPDTE - Dead Time Error Output Disable Request Enable - 28 - 28 - read-write - - 0 - Disable dead time error output disable request - #0 + 0x06 + TS06 + 0x06 - 1 - Enable dead time error output disable request - #1 + 0x07 + TS07 + 0x07 - - - - GRP - Output Disable Source Select - 24 - 25 - read-write - - 00 - Group A output disable request - #00 + 0x08 + TS08 + 0x08 - 01 - Group B output disable request - #01 + 0x09 + TS09 + 0x09 - 10 - Group C output disable request - #10 + 0x0A + TS10 + 0x0a - 11 - Group D output disable request - #11 + 0x0B + TS11 + 0x0b - others - Setting prohibited - true + 0x0C + TS12 + 0x0c + + + 0x0D + TS13 + 0x0d + + + 0x0E + TS14 + 0x0e + + + 0x0F + TS15 + 0x0f + + + 0x10 + TS16 + 0x10 + + + 0x11 + TS17 + 0x11 + + + 0x12 + TS18 + 0x12 + + + 0x15 + TS21 + 0x15 + + + 0x16 + TS22 + 0x16 - - - - - - GTST - General PWM Timer Status Register - 0x3C - 32 - read-write - 0x00008000 - 0xFFFFFFFF - - - OABLF - Same Time Output Level Low Disable Request Enable - 30 - 30 - read-only - - 0 - GTIOCA pin and GTIOCB pin don't output 0 at the same time. - #0 + 0x17 + TS23 + 0x17 - 1 - GTIOCA pin and GTIOCB pin output 0 at the same time. - #1 + 0x18 + TS24 + 0x18 - - - - OABHF - Same Time Output Level High Disable Request Enable - 29 - 29 - read-only - - 0 - GTIOCA pin and GTIOCB pin don't output 1 at the same time. - #0 + 0x19 + TS25 + 0x19 - 1 - GTIOCA pin and GTIOCB pin output 1 at the same time. - #1 + 0x1A + TS26 + 0x1a - - - - DTEF - Dead Time Error Flag - 28 - 28 - read-only - - 0 - No dead time error has occurred. - #0 + 0x1B + TS27 + 0x1b - 1 - A dead time error has occurred. - #1 + 0x1C + TS28 + 0x1c - - - - ODF - Output Disable Flag - 24 - 24 - read-only - - 0 - No output disable request is generated. - #0 + 0x1D + TS29 + 0x1d - 1 - An output disable request is generated. - #1 + 0x1E + TS30 + 0x1e - - - - ADTRBDF - GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag - 19 - 19 - read-write - - 0 - No compare match of GTADTRB at down-counting is generated. - #0 + 0x1F + TS31 + 0x1f - 1 - A compare match of GTADTRB at down-counting is generated. - #1 + 0x20 + TS32 + 0x20 - - - - ADTRBUF - GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag - 18 - 18 - read-write - - 0 - No compare match of GTADTRB at up-counting is generated. - #0 + 0x21 + TS33 + 0x21 - 1 - A compare match of GTADTRB at up-counting is generated. - #1 + 0x22 + TS34 + 0x22 - - - - ADTRADF - GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag - 17 - 17 - read-write - - 0 - No compare match of GTADTRA at down-counting is generated. - #0 + 0x23 + TS35 + 0x23 - 1 - A compare match of GTADTRA at down-counting is generated. - #1 + 0x3F + Measurement is being stopped. + 0x3f - ADTRAUF - GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable + MCA0 + CTSU Multiple Valid Clock Control 16 16 read-write 0 - No compare match of GTADTRA at up-counting is generated. + Valid #0 1 - A compare match of GTADTRA at up-counting is generated. + Invalid #1 - TUCF - Count Direction Flag - 15 - 15 - read-only + MCA1 + CTSU Multiple Valid Clock Control + 17 + 17 + read-write 0 - The GTCNT counter counts downward. + Valid #0 1 - The GTCNT counter counts upward. + Invalid #1 - ITCNT - GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.) - 8 - 10 - read-only - - - TCFPU - Underflow Flag - 7 - 7 + MCA2 + CTSU Multiple Valid Clock Control + 18 + 18 read-write 0 - No underflow (trough) has occurred. + Valid #0 1 - An underflow (trough) has occurred. + Invalid #1 - TCFPO - Overflow Flag - 6 - 6 + MCA3 + CTSU Multiple Valid Clock Control + 19 + 19 read-write 0 - No overflow (crest) has occurred. + Valid #0 1 - An overflow (crest) has occurred. + Invalid #1 + + + + CTSUMCHL + CTSU Measurement Channel Register + CTSUMCH + 0x08 + 16 + read-write + 0x0000 + 0xffff + + + CTSUMCH0 + CTSU Measurement Channel Register + CTSUMCH + 0x08 + 8 + read-write + 0x00 + 0xff + + + CTSUMCH1 + CTSU Measurement Channel Register + CTSUMCH + 0x09 + 8 + read-write + 0x00 + 0xff + + + CTSUMCHH + CTSU Measurement Channel Register + CTSUMCH + 0x0A + 16 + read-write + 0x3f3f + 0xffff + + + CTSUMFAF + CTSU Measurement Channel Register + CTSUMCHH + 0x0A + 8 + read-write + 0x3f + 0xff + + + CTSUCHACA + CTSU Channel Enable Control Register A + 0x0C + 32 + read-write + 0x00000000 + 0xffffffff + - TCFF - Input Compare Match Flag F - 5 - 5 + CHAC00 + CTSU Channel Enable Control A + 0 + 0 read-write 0 - No compare match of GTCCRF is generated. + Do not measure. #0 1 - A compare match of GTCCRF is generated. + Measure. #1 - TCFE - Input Compare Match Flag E - 4 - 4 + CHAC02 + CTSU Channel Enable Control A + 2 + 2 read-write 0 - No compare match of GTCCRE is generated. + Do not measure. #0 1 - A compare match of GTCCRE is generated. + Measure. #1 - TCFD - Input Compare Match Flag D - 3 - 3 + CHAC04 + CTSU Channel Enable Control A + 4 + 4 read-write 0 - No compare match of GTCCRD is generated. + Do not measure. #0 1 - A compare match of GTCCRD is generated. + Measure. #1 - TCFC - Input Compare Match Flag C - 2 - 2 + CHAC05 + CTSU Channel Enable Control A + 5 + 5 read-write 0 - No compare match of GTCCRC is generated. + Do not measure. #0 1 - A compare match of GTCCRC is generated. + Measure. #1 - TCFB - Input Capture/Compare Match Flag B - 1 - 1 + CHAC06 + CTSU Channel Enable Control A + 6 + 6 read-write 0 - No input capture/compare match of GTCCRB is generated. + Do not measure. #0 1 - An input capture/compare match of GTCCRB is generated. + Measure. #1 - TCFA - Input Capture/Compare Match Flag A - 0 - 0 + CHAC07 + CTSU Channel Enable Control A + 7 + 7 read-write 0 - No input capture/compare match of GTCCRA is generated. + Do not measure. #0 1 - An input capture/compare match of GTCCRA is generated. + Measure. #1 - - - - GTBER - General PWM Timer Buffer Enable Register - 0x40 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - ADTDB - GTADTRB Double Buffer Operation - 30 - 30 + CHAC08 + CTSU Channel Enable Control A + 8 + 8 read-write 0 - Single buffer operation (GTADTBRB --> GTADTRB) + Do not measure. #0 1 - Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB) + Measure. #1 - ADTTB - GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. - 28 - 29 - read-write - - - 00 - No transfer - #00 - - - 01 - Transfer at crest - #01 - - - 10 - Transfer at trough - #10 - - - 11 - Transfer at both crest and trough - #11 - - - - - ADTDA - GTADTRA Double Buffer Operation - 26 - 26 + CHAC09 + CTSU Channel Enable Control A + 9 + 9 read-write 0 - Single buffer operation (GTADTBRA --> GTADTRA) + Do not measure. #0 1 - Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA) + Measure. #1 - ADTTA - GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. - 24 - 25 + CHAC10 + CTSU Channel Enable Control A + 10 + 10 read-write - - - 00 - No transfer - #00 - - - 01 - Transfer at crest - #01 - - - 10 - Transfer at trough - #10 - - - 11 - Transfer at both crest and trough - #11 - - - - - CCRSWT - GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. - 22 - 22 - write-only 0 - no effect + Do not measure. #0 1 - Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. + Measure. #1 - PR - GTPR Buffer Operation - 20 - 21 - read-write - - - 00 - Buffer operation is not performed - #00 - - - 01 - Single buffer operation (GTPBR --> GTPR) - #01 - - - others - Setting prohibited - true - - - - - CCRB - GTCCRB Buffer Operation - 18 - 19 - read-write - - - 00 - Buffer operation is not performed - #00 - - - 01 - Single buffer operation (GTCCRB <--> GTCCRE) - #01 - - - 10 - Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) - #10 - - - 11 - Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) - #11 - - - - - CCRA - GTCCRA Buffer Operation - 16 - 17 + CHAC11 + CTSU Channel Enable Control A + 11 + 11 read-write - 00 - Buffer operation is not performed - #00 - - - 01 - Single buffer operation (GTCCRA <--> GTCCRC) - #01 - - - 10 - Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) - #10 + 0 + Do not measure. + #0 - 11 - Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) - #11 + 1 + Measure. + #1 - BD3 - BD[3]: GTDV Buffer Operation DisableBD[2] - 3 - 3 + CHAC12 + CTSU Channel Enable Control A + 12 + 12 read-write 0 - Enable buffer operation + Do not measure. #0 1 - Disable buffer operation + Measure. #1 - BD2 - BD[2]: GTADTR Buffer Operation DisableBD - 2 - 2 + CHAC13 + CTSU Channel Enable Control A + 13 + 13 read-write 0 - Enable buffer operation + Do not measure. #0 1 - Disable buffer operation + Measure. #1 - BD1 - BD[1]: GTPR Buffer Operation Disable - 1 - 1 + CHAC14 + CTSU Channel Enable Control A + 14 + 14 read-write 0 - Buffer operation is enabled + Do not measure. #0 1 - Buffer operation is disabled + Measure. #1 - BD0 - BD[0]: GTCCR Buffer Operation Disable - 0 - 0 + CHAC15 + CTSU Channel Enable Control A + 15 + 15 read-write 0 - Buffer operation is enabled + Do not measure. #0 1 - Buffer operation is disabled + Measure. #1 - - - - GTITC - General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register - 0x44 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - ADTBL - GTADTRB A/D Converter Start Request Link - 14 - 14 + CHAC16 + CTSU Channel Enable Control A + 16 + 16 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 - ADTAL - GTADTRA A/D Converter Start Request Link - 12 - 12 + CHAC17 + CTSU Channel Enable Control A + 17 + 17 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function + Measure. #1 - IVTT - GPT_OVF/GPT_UDF Interrupt Skipping Count Select - 8 - 10 + CHAC18 + CTSU Channel Enable Control A + 18 + 18 read-write - 000 - No skipping - #000 + 0 + Do not measure. + #0 - 001 - Skipping count of 1 - #001 + 1 + Measure. + #1 + + + + CHAC21 + CTSU Channel Enable Control A + 21 + 21 + read-write + - 010 - Skipping count of 2 - #010 + 0 + Do not measure. + #0 - 011 - Skipping count of 3 - #011 + 1 + Measure. + #1 + + + + CHAC22 + CTSU Channel Enable Control A + 22 + 22 + read-write + - 100 - Skipping count of 4 - #100 + 0 + Do not measure. + #0 - 101 - Skipping count of 5 - #101 + 1 + Measure. + #1 + + + + CHAC23 + CTSU Channel Enable Control A + 23 + 23 + read-write + - 110 - Skipping count of 6 - #110 + 0 + Do not measure. + #0 - 111 - Skipping count of 7. - #111 + 1 + Measure. + #1 - IVTC - GPT_OVF/GPT_UDF Interrupt Skipping Function Select - 6 - 7 + CHAC24 + CTSU Channel Enable Control A + 24 + 24 read-write - 00 - Do not perform skipping - #00 + 0 + Do not measure. + #0 - 01 - Count and skip both overflow and underflow for saw waves and crest for triangle waves - #01 + 1 + Measure. + #1 + + + + CHAC25 + CTSU Channel Enable Control A + 25 + 25 + read-write + - 10 - Count and skip both overflow and underflow for saw waves and trough for triangle waves - #10 + 0 + Do not measure. + #0 - 11 - Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves. - #11 + 1 + Measure. + #1 - ITLF - GTCCRF Compare Match Interrupt Link - 5 - 5 + CHAC26 + CTSU Channel Enable Control A + 26 + 26 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 - ITLE - GTCCRE Compare Match Interrupt Link - 4 - 4 + CHAC27 + CTSU Channel Enable Control A + 27 + 27 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 - ITLD - GTCCRD Compare Match Interrupt Link - 3 - 3 + CHAC28 + CTSU Channel Enable Control A + 28 + 28 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 - ITLC - GTCCRC Compare Match Interrupt Link - 2 - 2 + CHAC29 + CTSU Channel Enable Control A + 29 + 29 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 - ITLB - GTCCRB Compare Match/Input Capture Interrupt Link - 1 - 1 + CHAC30 + CTSU Channel Enable Control A + 30 + 30 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 - ITLA - GTCCRA Compare Match/Input Capture Interrupt Link - 0 - 0 + CHAC31 + CTSU Channel Enable Control A + 31 + 31 read-write 0 - Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + Do not measure. #0 1 - Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + Measure. #1 @@ -39322,1699 +17531,1815 @@ FMS2,1,0: - GTCNT - General PWM Timer Counter - 0x48 - 32 + CTSUCHACAL + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0C + 16 read-write - 0x00000000 - 0xFFFFFFFF - - - GTCNT - Counter - 0 - 31 - read-write - - + 0x0000 + 0xffff - 6 - 4 - - - A - A - 0 - - - B - B - 1 - - - C - C - 2 - - - E - E - 3 - - - D - D - 4 - - - F - F - 5 - - - GTCCR[%s] - General PWM Timer Compare Capture Register - 0x4C - 32 + CTSUCHAC0 + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0C + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTCCR - Compare Capture Register A - 0 - 31 - read-write - - + 0x00 + 0xff - GTPR - General PWM Timer Cycle Setting Register - 0x64 - 32 + CTSUCHAC1 + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0D + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTPR - Cycle Setting Register - 0 - 31 - read-write - - + 0x00 + 0xff - GTPBR - General PWM Timer Cycle Setting Buffer Register - 0x68 - 32 + CTSUCHACAH + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0E + 16 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTPBR - Cycle Setting Buffer Register - 0 - 31 - read-write - - + 0x0000 + 0xffff - GTPDBR - General PWM Timer Cycle Setting Double-Buffer Register - 0x6C - 32 + CTSUCHAC2 + CTSU Channel Enable Control Register A + CTSUCHACAH + 0x0E + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTPDBR - Cycle Setting Double-Buffer Register - 0 - 31 - read-write - - + 0x00 + 0xff - GTADTRA - A/D Converter Start Request Timing Register A - 0x70 - 32 + CTSUCHAC3 + CTSU Channel Enable Control Register A + CTSUCHACA + 0x0F + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTRA - A/D Converter Start Request Timing Register A - 0 - 31 - read-write - - + 0x00 + 0xff - GTADTRB - A/D Converter Start Request Timing Register B - 0x7C + CTSUCHACB + CTSU Channel Enable Control Register B + 0x10 32 read-write - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0xffffffff - GTADTRB - A/D Converter Start Request Timing Register B + CHAC32 + CTSU Channel Enable Control B 0 - 31 + 0 read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + - - - - GTADTBRA - A/D Converter Start Request Timing Buffer Register A - 0x74 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTADTBRA - A/D Converter Start Request Timing Buffer Register A - 0 - 31 + CHAC33 + CTSU Channel Enable Control B + 1 + 1 + read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + + + + CHAC34 + CTSU Channel Enable Control B + 2 + 2 read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + - - - - GTADTBRB - A/D Converter Start Request Timing Buffer Register B - 0x80 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTADTBRB - A/D Converter Start Request Timing Buffer Register B - 0 - 31 + CHAC35 + CTSU Channel Enable Control B + 3 + 3 read-write + + + 0 + Do not measure. + #0 + + + 1 + Measure. + #1 + + - GTADTDBRA - A/D Converter Start Request Timing Double-Buffer Register A - 0x78 - 32 + CTSUCHACBL + CTSU Channel Enable Control Register B + CTSUCHACB + 0x10 + 16 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTDBRA - A/D Converter Start Request Timing Double-Buffer Register A - 0 - 31 - read-write - - + 0x0000 + 0xffff - GTADTDBRB - A/D Converter Start Request Timing Double-Buffer Register B - 0x84 - 32 + CTSUCHAC4 + CTSU Channel Enable Control Register B + CTSUCHACB + 0x10 + 8 read-write - 0xFFFFFFFF - 0xFFFFFFFF - - - GTADTDBRB - A/D Converter Start Request Timing Double-Buffer Register B - 0 - 31 - read-write - - + 0x00 + 0xff - GTDTCR - General PWM Timer Dead Time Control Register - 0x88 + CTSUCHTRCA + CTSU Channel Transmit/Receive Control Register A + 0x14 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - TDFER - GTDVD Setting - 8 - 8 + CHTRC + CTSU Channel Transmit/Receive Control A + 0 + 0 read-write 0 - Set GTDVU and GTDVD separately + Reception #0 1 - Automatically set the value written to GTDVU to GTDVD + Transmission #1 - TDBDE - GTDVD Buffer Operation Enable - 5 - 5 + CHTRC02 + CTSU Channel Transmit/Receive Control A + 2 + 2 read-write 0 - Disable GTDVD buffer operation + Reception #0 1 - Enable GTDVD buffer operation + Transmission #1 - TDBUE - GTDVU Buffer Operation Enable + CHTRC04 + CTSU Channel Transmit/Receive Control A 4 4 read-write 0 - Disable GTDVU buffer operation + Reception #0 1 - Enable GTDVU buffer operation + Transmission #1 - TDE - Negative-Phase Waveform Setting - 0 - 0 + CHTRC05 + CTSU Channel Transmit/Receive Control A + 5 + 5 read-write 0 - GTCCRB is set without using GTDVU and GTDVD. + Reception #0 1 - GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. + Transmission #1 - - - - GTDVU - General PWM Timer Dead Time Value Register U - 0x8C - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTDVU - Dead Time Value Register U - 0 - 31 + CHTRC06 + CTSU Channel Transmit/Receive Control A + 6 + 6 read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + - - - - GTDVD - General PWM Timer Dead Time Value Register D - 0x90 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTDVD - Dead Time Value Register D - 0 - 31 + CHTRC07 + CTSU Channel Transmit/Receive Control A + 7 + 7 read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + - - - - GTDBU - General PWM Timer Dead Time Buffer Register U - 0x94 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTDVU - Dead Time Buffer Register U - 0 - 31 + CHTRC08 + CTSU Channel Transmit/Receive Control A + 8 + 8 read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + - - - - GTDBD - General PWM Timer Dead Time Buffer Register D - 0x98 - 32 - read-write - 0xFFFFFFFF - 0xFFFFFFFF - - GTDBD - Dead Time Buffer Register D - 0 - 31 + CHTRC09 + CTSU Channel Transmit/Receive Control A + 9 + 9 read-write + + + 0 + Reception + #0 + + + 1 + Transmission + #1 + + - - - - GTSOS - General PWM Timer Output Protection Function Status Register - 0x9C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - SOS - Output Protection Function Status - 0 - 1 - read-only + CHTRC10 + CTSU Channel Transmit/Receive Control A + 10 + 10 + read-write - 00 - Normal operation - #00 + 0 + Reception + #0 - 01 - Protected state (GTCCRA = 0 is set during transfer at trough or crest) - #01 + 1 + Transmission + #1 + + + + CHTRC11 + CTSU Channel Transmit/Receive Control A + 11 + 11 + read-write + - 10 - Protected state (GTCCRA >= GTPR is set during transfer at trough) - #10 + 0 + Reception + #0 - 11 - Protected state (GTCCRA >= GTPR is set during transfer at crest) - #11 + 1 + Transmission + #1 - - - - GTSOTR - General PWM Timer Output Protection Function Temporary Release Register - 0xA0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - SOTR - Output Protection Function Temporary Release - 0 - 0 + CHTRC12 + CTSU Channel Transmit/Receive Control A + 12 + 12 read-write 0 - Do not release protected state + Reception #0 1 - Release protected state + Transmission #1 - - - - - - R_GPT1 - 0x40078100 - - - R_GPT2 - 0x40078200 - - - R_GPT3 - 0x40078300 - - - R_GPT4 - 0x40078400 - - - R_GPT5 - 0x40078500 - - - R_GPT6 - 0x40078600 - - - R_GPT7 - 0x40078700 - - - R_GPT8 - 0x40078800 - - - R_GPT9 - 0x40078900 - - - R_GPT10 - 0x40078A00 - - - R_GPT11 - 0x40078B00 - - - R_GPT12 - 0x40078C00 - - - R_GPT13 - 0x40078D00 - - - R_GPT_ODC - PWM Delay Generation Circuit - 0x4007B000 - - 0x00000000 - 0x004 - registers - - - 0x00000018 - 0x020 - registers - - - - 4 - 4 - GTDLYR[%s] - PWM DELAY RISING - 0x18 - - A - GTIOCA Output Delay Register - 0 - 16 - read-write - 0x0000 - 0xFFFF - - - DLY - GTIOCnA Output Rising Edge Delay Setting - 0 - 4 - read-write - - - 00000 - No delay on rising edges - #00000 - - - others - Delay of DLY/32 times the PCLKD period is applied. - true - - - - - - - B - GTIOCB Output Delay Register - 2 - 16 - read-write - 0x0000 - 0xFFFF - - - DLY - GTIOCnA Output Rising Edge Delay Setting - 0 - 4 - read-write - - - 00000 - No delay on rising edges - #00000 - - - others - Delay of DLY/32 times the PCLKD period is applied. - true - - - - - - - - GTDLYF[%s] - PWM DELAY FALLING - 0x28 - - - GTDLYCR1 - PWM Output Delay Control Register1 - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - DLLMOD - DLL Mode Select - 8 - 8 + CHTRC13 + CTSU Channel Transmit/Receive Control A + 13 + 13 read-write 0 - 5 bit-mode + Reception #0 1 - 4 bit-mode + Transmission #1 - DLYRST - PWM Delay Generation Circuit Reset - 1 - 1 + CHTRC14 + CTSU Channel Transmit/Receive Control A + 14 + 14 read-write 0 - Normal operation + Reception #0 1 - Reset + Transmission #1 - DLLEN - DLL Operation Enable - 0 - 0 + CHTRC15 + CTSU Channel Transmit/Receive Control A + 15 + 15 read-write 0 - DLL operation is disabled + Reception #0 1 - DLL operation is enabled + Transmission #1 - - - - GTDLYCR2 - PWM Output Delay Control Register2 - 0x02 - 16 - read-write - 0x0000 - 0xFFFF - - 1 - 1 - DLYDENB%s - PWM Delay Generation Circuit Disenable for GTIOCB - 12 - 12 + CHTRC16 + CTSU Channel Transmit/Receive Control A + 16 + 16 read-write 0 - Delay generation circuit of GTIOCB is based on DLYEN1. + Reception #0 1 - Delay generation circuit of GTIOCB is disabled. + Transmission #1 - 1 - 1 - DLYEN%s - PWM Delay Generation Circuit enable - 8 - 8 + CHTRC17 + CTSU Channel Transmit/Receive Control A + 17 + 17 read-write 0 - Delay generation circuit of channel is enabled + Reception #0 1 - Delay generation circuit of channel is disabled. + Transmission #1 - 4 - 1 - DLYBS%s - PWM Delay Generation Circuit bypass - 0 - 0 + CHTRC18 + CTSU Channel Transmit/Receive Control A + 18 + 18 read-write 0 - Delay generation circuit of channel is bypassed. + Reception #0 1 - Delay generation circuit of channel is not bypassed. + Transmission #1 - - - - - - R_GPT_OPS - Output Phase Switching for GPT - 0x40078FF0 - - 0x00000000 - 0x04 - registers - - - - OPSCR - Output Phase Switching Control Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - NFCS - External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. - 30 - 31 + CHTRC21 + CTSU Channel Transmit/Receive Control A + 21 + 21 read-write - 00 - PCLK/1 - #00 - - - 01 - PCLK/4 - #01 - - - 10 - PCLK/16 - #10 + 0 + Reception + #0 - 11 - PCLK/64 - #11 + 1 + Transmission + #1 - NFEN - External Input Noise Filter Enable - 29 - 29 + CHTRC22 + CTSU Channel Transmit/Receive Control A + 22 + 22 read-write 0 - Do not use a noise filter to the external input. + Reception #0 1 - Use a noise filter to the external input. + Transmission #1 - GODF - Group output disable function - 26 - 26 + CHTRC23 + CTSU Channel Transmit/Receive Control A + 23 + 23 read-write 0 - This bit function is ignored. + Reception #0 1 - Group disable will clear OPSCR.EN Bit. + Transmission #1 - GRP - Output disabled source selection + CHTRC24 + CTSU Channel Transmit/Receive Control A 24 - 25 + 24 read-write - 00 - Select Group A output disable source - #00 - - - 01 - Select Group B output disable source - #01 - - - 10 - Select Group C output disable source - #10 + 0 + Reception + #0 - 11 - Select Group D output disable source - #11 + 1 + Transmission + #1 - ALIGN - Input phase alignment - 21 - 21 + CHTRC25 + CTSU Channel Transmit/Receive Control A + 25 + 25 read-write 0 - Input phase is aligned to PCLK. + Reception #0 1 - Input phase is aligned PWM. + Transmission #1 - RV - Output phase rotation direction reversal - 20 - 20 + CHTRC26 + CTSU Channel Transmit/Receive Control A + 26 + 26 read-write 0 - U/V/W-Phase output + Reception #0 1 - Output to reverse the V / W-phase + Transmission #1 - INV - Invert-Phase Output Control - 19 - 19 + CHTRC27 + CTSU Channel Transmit/Receive Control A + 27 + 27 read-write 0 - Positive Logic (Active High)output + Reception #0 1 - Negative Logic (Active Low)output + Transmission #1 - N - Negative-Phase Output (N) Control - 18 - 18 + CHTRC28 + CTSU Channel Transmit/Receive Control A + 28 + 28 read-write 0 - Level signal output + Reception #0 1 - PWM signal output (PWM of GPT0) + Transmission #1 - P - Positive-Phase Output (P) Control - 17 - 17 + CHTRC29 + CTSU Channel Transmit/Receive Control A + 29 + 29 read-write 0 - Level signal output + Reception #0 1 - PWM signal output (PWM of GPT0) + Transmission #1 - FB - External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. - 16 - 16 + CHTRC30 + CTSU Channel Transmit/Receive Control A + 30 + 30 read-write 0 - Select the external input. + Reception #0 1 - Select the soft setting(OPSCR.UF, VF, WF). + Transmission #1 - EN - Enable-Phase Output Control - 8 - 8 + CHTRC31 + CTSU Channel Transmit/Receive Control A + 31 + 31 read-write 0 - Not Output(Hi-Z external terminals). + Reception #0 1 - Output + Transmission #1 - - W - Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) - 6 - 6 - read-only - - - V - Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) - 5 - 5 - read-only - - - U - Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) - 4 - 4 - read-only - - - WF - Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. - 2 - 2 - read-write - - - VF - Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. - 1 - 1 - read-write - - - UF - Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. - 0 - 0 - read-write - - - - - R_GPT_POEG0 - Port Output Enable for GPT - 0x40042000 - - 0x00000000 - 0x04 - registers - - - POEGG - POEG Group Setting Register - 0x00 + CTSUCHTRCAL + CTSU Channel Transmit/Receive Control Register A + CTSUCHTRCA + 0x14 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHTRC0 + CTSU Channel Transmit/Receive Control Register A + CTSUCHTRCA + 0x14 + 8 + read-write + 0x00 + 0xff + + + CTSUCHTRC1 + CTSU Channel Transmit/Receive Control Register A + CTSUCHTRCA + 0x15 + 8 + read-write + 0x00 + 0xff + + + CTSUCHTRCAH + CTSU Channel Transmit/Receive Control Register A + CTSUCHTRCA + 0x16 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHTRC2 + CTSU Channel Transmit/Receive Control Register A + CTSUCHTRCAH + 0x16 + 8 + read-write + 0x00 + 0xff + + + CTSUCHTRC3 + CTSU Channel Transmit/Receive Control Register A + CTSUCHTRCA + 0x17 + 8 + read-write + 0x00 + 0xff + + + CTSUCHTRCB + CTSU Channel Transmit/Receive Control Register B + 0x18 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - NFCS - Noise Filter Clock Select - 30 - 31 + CHTRC32 + CTSU Channel Transmit/Receive Control B + 0 + 0 read-write - 00 - Sampling GTETRG pin input level for three times in every PCLKB. - #00 - - - 01 - Sampling GTETRG pin input level for three times in every PCLKB /8. - #01 - - - 10 - Sampling GTETRG pin input level for three times in every PCLKB /32. - #10 + 0 + Reception + #0 - 11 - Sampling GTETRG pin input level for three times in every PCLKB /128. - #11 + 1 + Transmission + #1 - NFEN - Noise Filter Enable - 29 - 29 + CHTRC33 + CTSU Channel Transmit/Receive Control B + 1 + 1 read-write 0 - Filtering noise disabled + Reception #0 1 - Filtering noise enabled + Transmission #1 - INV - GTETRG Input Reverse - 28 - 28 + CHTRC34 + CTSU Channel Transmit/Receive Control B + 2 + 2 read-write 0 - GTETRG Input + Reception #0 1 - GTETRG Input Reversed. + Transmission #1 - ST - GTETRG Input Status Flag - 16 - 16 - read-only + CHTRC35 + CTSU Channel Transmit/Receive Control B + 3 + 3 + read-write 0 - GTETRG input after filtering is 0. + Reception #0 1 - GTETRG input after filtering is 1. + Transmission #1 + + + + CTSUCHTRCBL + CTSU Channel Transmit/Receive Control Register B + CTSUCHTRCB + 0x18 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCHTRC4 + CTSU Channel Transmit/Receive Control Register B + CTSUCHTRCB + 0x18 + 8 + read-write + 0x00 + 0xff + + + CTSUSR + CTSU Status Register + 0x1C + 32 + read-write + 0x00000000 + 0xffffffff + - 6 - 1 - CDRE%s - Comparator Disable Request Enable. Note: Can be modified only once after a reset. - 8 - 8 + MFC + CTSU Multi-clock Counter + 0 + 1 read-write - 0 - A disable request of comparator 0 disabled. - #0 + 00 + Multi-clock 0 + #00 - 1 - A disable request of comparator 0 enabled. - #1 + 01 + Multi-clock 1 + #01 + + + 10 + Multi-clock 2 + #10 + + + 11 + Multi-clock 3 + #11 - OSTPE - Oscillation Stop Detection EnableNote: Can be modified only once after a reset. + ICOMPRST + CTSU CTSUICOMP1 Flag Reset + 5 + 5 + write-only + + + ICOMP1 + CTSU Sense Current Error Monitor 6 6 - read-write + read-only 0 - A output-disable request from the oscillation stop detection disabled. + Normal sensor current #0 1 - A output-disable request from the oscillation stop detection enabled. + Abnormal sensor current #1 - IOCE - Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset. - 5 - 5 - read-write + ICOMP0 + TSCAP Voltage Error Monitor + 7 + 7 + read-only 0 - Disable output-disable requests from GPT disable request + Normal TSCAP voltage #0 1 - Enable output-disable requests from GPT disable request + Abnormal TSCAP voltage #1 - PIDE - Port Input Detection EnableNote: Can be modified only once after a reset. - 4 - 4 - read-write + STC + CTSU Measurement Status Counter + 8 + 10 + read-only - 0 - A output-disable request from the GTETRG pins disabled. - #0 + 000 + Status 0 + #000 - 1 - A output-disable request from the GTETRG pins enabled. - #1 + 001 + Status 1 + #001 + + + 010 + Status 2 + #010 + + + 011 + Status 3 + #011 + + + 100 + Status 4 + #100 + + + 101 + Status 5 + #101 - SSF - Software Stop Flag - 3 - 3 - read-write + DTSR + CTSU Data Transfer Status Flag + 12 + 12 + read-only 0 - A output-disable request from software has not been generated. + Read #0 1 - A output-disable request from software has been generated. + Not read #1 - OSTPF - Oscillation Stop Detection Flag - 2 - 2 + SENSOVF + CTSU Sensor Counter Overflow Flag + 13 + 13 read-write - zeroToClear - modify 0 - A output-disable request from the oscillation stop detection has not been generated. + No overflow occurred #0 1 - A output-disable request from the oscillation stop detection has been generated. + Overflow occurred #1 - IOCF - Real Time Overcurrent Detection Flag - 1 - 1 - read-write - zeroToClear - modify + PS + CTSU Mutual Capacitance Status Flag + 15 + 15 + read-only 0 - A output-disable request from GPT disable request or comparator interrupt has not been generated. + First measurement #0 1 - A output-disable request from GPT disable request or comparator interrupt has been generated. + Second measurement #1 - PIDF - Port Input Detection Flag - 0 - 0 + CFCRDCH + CTSU CFC Read Channel Select + 16 + 21 read-write - zeroToClear - modify - 0 - A output-disable request from the GTETRG pin has not been generated. - #0 + 0x00 + TS00 + 0x00 - 1 - A output-disable request from the GTETRG pin has been generated. - #1 + 0x02 + TS02 (CFC) + 0x02 + + + 0x04 + TS04 + 0x04 + + + 0x05 + TS05 + 0x05 + + + 0x06 + TS06 + 0x06 + + + 0x07 + TS07 + 0x07 + + + 0x08 + TS08 (CFC) + 0x08 + + + 0x09 + TS09 (CFC) + 0x09 + + + 0x0A + TS10 (CFC) + 0x0a + + + 0x0B + TS11 (CFC) + 0x0b + + + 0x0C + TS12 (CFC) + 0x0c + + + 0x0D + TS13 (CFC) + 0x0d + + + 0x0E + TS14 (CFC) + 0x0e + + + 0x0F + TS15 (CFC) + 0x0f + + + 0x10 + TS16 (CFC) + 0x10 + + + 0x11 + TS17 + 0x11 + + + 0x12 + TS18 + 0x12 + + + 0x15 + TS21 + 0x15 + + + 0x16 + TS22 + 0x16 + + + 0x17 + TS23 + 0x17 + + + 0x18 + TS24 + 0x18 + + + 0x19 + TS25 + 0x19 + + + 0x1A + TS26 (CFC) + 0x1a + + + 0x1B + TS27 (CFC) + 0x1b + + + 0x1C + TS28 (CFC) + 0x1c + + + 0x1D + TS29 (CFC) + 0x1d + + + 0x1E + TS30 (CFC) + 0x1e + + + 0x1F + TS31 (CFC) + 0x1f + + + 0x20 + TS32 (CFC) + 0x20 + + + 0x21 + TS33 (CFC) + 0x21 + + + 0x22 + TS34 (CFC) + 0x22 + + + 0x23 + TS35 (CFC) + 0x23 - - - - R_GPT_POEG1 - 0x40042100 - - - R_GPT_POEG2 - 0x40042200 - - - R_GPT_POEG3 - 0x40042300 - - - R_ICU - Interrupt Controller Unit - 0x40006000 - - 0x00000000 - 0x010 - registers - - - 0x00000100 - 0x01 - registers - - - 0x00000120 - 0x02 - registers - - - 0x00000130 - 0x02 - registers - - - 0x00000140 - 0x02 - registers - - - 0x000001A0 - 0x04 - registers - - - 0x00000200 - 0x02 - registers - - - 0x00000280 - 0x020 - registers - - - 0x00000300 - 0x180 - registers - - - 16 - 0x1 - IRQCR[%s] - IRQ Control Register %s - 0x000 + CTSUSRL + CTSU Status Register + CTSUSR + 0x1C + 16 + read-write + 0x0000 + 0xffff + + + CTSUSR0 + CTSU Status Register + CTSUSR + 0x1C 8 read-write 0x00 - 0xFF + 0xff + + + CTSUST + CTSU Status Register + CTSUSR + 0x1D + 8 + read-write + 0x00 + 0xff + + + CTSUSRH + CTSU Status Register + CTSUSR + 0x1E + 16 + read-write + 0x0000 + 0xffff + + + CTSUSR2 + CTSU Status Register + CTSUSRH + 0x1E + 8 + read-write + 0x00 + 0xff + + + CTSUSO + CTSU Sensor Offset Register + 0x20 + 32 + read-write + 0x00000000 + 0xffffffff - FLTEN - IRQ Digital Filter Enable - 7 - 7 + SO + CTSU Sensor Offset Adjustment + 0 + 9 + read-write + + + SNUM + CTSU Measurement Count Setting + 10 + 17 + read-write + + + SSDIV + CTSU Spectrum Diffusion Frequency Division Setting + 20 + 23 + read-write + + + SDPA + CTSU Base Clock Setting + 24 + 31 + read-write + + + + + CTSUSO0 + CTSU Sensor Offset Register + CTSUSO + 0x20 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSO1 + CTSU Sensor Offset Register + CTSUSO + 0x22 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSCNT + CTSU Sensor Counter Register + 0x24 + 32 + read-only + 0x00000000 + 0xffffffff + + + SENSCNT + CTSU Sensor Counter + 0 + 15 + read-only + + + + + CTSUSC + CTSU Sensor Counter Register + CTSUSCNT + 0x24 + 16 + read-only + 0x0000 + 0xffff + + + CTSUCALIB + CTSU Calibration Register + 0x28 + 32 + read-write + 0x00000000 + 0xffffffff + + + TSOD + CTSU TS Pins Fixed Output Select + 2 + 2 read-write 0 - Digital filter disabled. + Electrostatic capacitance measurement mode #0 1 - Digital filter enabled. + TS pins fix output (High output/Low output). #1 - FCLKSEL - IRQ Digital Filter Sampling Clock Select - 4 - 5 + DRV + CTSU Calibration Setting Bit 1 + 3 + 3 read-write - 00 - PCLKB - #00 - - - 01 - PCLKB/8 - #01 - - - 10 - PCLKB/32 - #10 + 0 + Electrostatic capacitance measurement mode + #0 - 11 - PCLKB/64 - #11 + 1 + Calibration setting 1 + #1 - IRQMD - IRQ Detection Sense Select - 0 - 1 + SUCLKEN + CTSU SUCLK Enable Control + 6 + 6 read-write - 00 - Falling edge - #00 - - - 01 - Rising edge - #01 - - - 10 - Rising and falling edges - #10 + 0 + SUCLK operation is disabled. + #0 - 11 - Low level - #11 + 1 + SUCLK operation is enabled. + #1 - - - - NMISR - Non-Maskable Interrupt Status Register - 0x140 - 16 - read-only - 0x0000 - 0xFFFF - - SPEST - CPU Stack pointer monitor Interrupt Status Flag - 12 - 12 - read-only + TSOC + CTSU Calibration Setting Bit 2 + 7 + 7 + read-write 0 - Interrupt not requested + Electrostatic capacitance measurement mode #0 1 - Interrupt requested. + Calibration setting 2 #1 - BUSMST - MPU Bus Master Error Interrupt Status Flag - 11 - 11 - read-only + IOC + CTSU Transfer Pins Control + 9 + 9 + read-write 0 - Interrupt not requested + Low level #0 1 - Interrupt requested. + High level #1 - BUSSST - MPU Bus Slave Error Interrupt Status Flag + CFCRDMD + CTSU CFC Counter Read Mode Select 10 10 - read-only + read-write 0 - Interrupt not requested + Read by DTC #0 1 - Interrupt requested. + Read by CPU #1 - RECCST - RAM ECC Error Interrupt Status Flag - 9 - 9 - read-only + DCOFF + CTSU Down Converter Control + 11 + 11 + read-write 0 - Interrupt not requested + Normal operation mode #0 1 - Interrupt requested. + The down converter is off. #1 - RPEST - RAM Parity Error Interrupt Status Flag - 8 - 8 - read-only + CFCMODE + CTSU CFC Current Source Switching + 22 + 22 + read-write 0 - Interrupt not requested + CFC current measurement (normal mode) #0 1 - Interrupt requested. + External current measurement for calibration #1 - NMIST - NMI Status Flag - 7 - 7 - read-only + DACCARRY + CTSU DAC Upper Current Source Carry Control + 25 + 25 + read-write 0 - Interrupt not requested + Do not carry #0 1 - Interrupt requested. + Carry #1 - OSTST - Oscillation Stop Detection Interrupt Status Flag - 6 - 6 - read-only + SUCARRY + CTSU CCO Carry Control + 27 + 27 + read-write 0 - Interrupt not requested for main oscillation stop + Do not carry #0 1 - Interrupt requested for main oscillation stop. + Carry #1 - VBATTST - VBATT monitor Interrupt Status Flag - 4 - 4 - read-only + DACCLK + CTSU DAC Modulation Circuit Clock Select + 28 + 28 + read-write 0 - Interrupt not requested + Divided PCLK specified by CTSUCRA.CLK[1:0] bits #0 1 - Interrupt requested. + SUCLK #1 - LVD2ST - Voltage-Monitoring 2 Interrupt Status Flag - 3 - 3 - read-only + CCOCLK + CTSU CCO Modulation Circuit Clock Select + 29 + 29 + read-write 0 - Interrupt not requested + Divided PCLK specified by CTSUCRA.CLK[1:0] bits #0 1 - Interrupt requested. + SUCLK #1 - LVD1ST - Voltage-Monitoring 1 Interrupt Status Flag - 2 - 2 - read-only + CCOCALIB + CTSU CCO Calibration Mode Select + 30 + 30 + read-write 0 - Interrupt not requested + Normal mode #0 1 - Interrupt requested. + Oscillator calibration mode #1 + + + + CTSUDBGR0 + CTSU Calibration Register + CTSUCALIB + 0x28 + 16 + read-write + 0x0000 + 0xffff + + + CTSUDBGR1 + CTSU Calibration Register + CTSUCALIB + 0x2A + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLKA + CTSU Sensor Unit Clock Control Register A + 0x2C + 32 + read-write + 0x00000000 + 0xffffffff + + + CTSUSUCLK0 + CTSU Sensor Unit Clock Control Register A + CTSUSUCLKA + 0x2C + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLK1 + CTSU Sensor Unit Clock Control Register A + CTSUSUCLKA + 0x2E + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLKB + CTSU Sensor Unit Clock Control Register B + 0x30 + 32 + read-write + 0x00000000 + 0xffffffff + + + SUADJ2 + CTSU SUCLK Frequency Adjustment + 0 + 7 + read-write + - WDTST - WDT Underflow/Refresh Error Status Flag - 1 - 1 + SUMULTI2 + CTSU SUCLK Multiplier Rate Setting + 8 + 15 + read-write + + + SUADJ3 + CTSU SUCLK Frequency Adjustment + 16 + 23 + read-write + + + SUMULTI3 + CTSU SUCLK Multiplier Rate Setting + 24 + 31 + read-write + + + + + CTSUSUCLK2 + CTSU Sensor Unit Clock Control Register B + CTSUSUCLKB + 0x30 + 16 + read-write + 0x0000 + 0xffff + + + CTSUSUCLK3 + CTSU Sensor Unit Clock Control Register B + CTSUSUCLKB + 0x32 + 16 + read-write + 0x0000 + 0xffff + + + CTSUCFCCNT + CTSU CFC Counter Register + 0x34 + 32 + read-only + 0x00000000 + 0xffffffff + + + CFCCNT + CTSU CFC Counter + 0 + 15 read-only + + + + + CTSUCFCCNTL + CTSU CFC Counter Register + CTSUCFCCNT + 0x34 + 16 + read-only + 0x0000 + 0xffff + + + + + R_DAC + D/A Converter + 0x4005E000 + + 0x00000000 + 0x00A + registers + + + + DACR + D/A Control Register + 0x04 + 8 + read-write + 0x1F + 0xFF + + + DAE + D/A Enable + 5 + 5 + read-write 0 - Interrupt not requested + Control D/A conversion of channels 0 and 1 individually #0 - - 1 - Interrupt requested. - #1 - - IWDTST - IWDT Underflow/Refresh Error Status Flag - 0 - 0 - read-only + 2 + 1 + DAOE%s + D/A Output Enable 0 + 6 + 6 + read-write 0 - Interrupt not requested + Analog output of channel 0 (DA0) is disabled. #0 1 - Interrupt requested. + D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. #1 @@ -41022,238 +19347,369 @@ FMS2,1,0: - NMIER - Non-Maskable Interrupt Enable Register - 0x120 + 2 + 2 + DADR[%s] + D/A Data Register + 0x00 16 read-write 0x0000 0xFFFF - SPEEN - CPU Stack pointer monitor Interrupt Enable - 12 - 12 + DADR + D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format. + 0 + 15 + read-write + + + + + DADPR + DADR0 Format Select Register + 0x05 + 8 + read-write + 0x00 + 0xFF + + + DPSEL + DADRm Format Select + 7 + 7 read-write 0 - Disabled + Right justified format. #0 1 - Enabled. + Left justified format. #1 + + + + DAADSCR + D/A-A/D Synchronous Start Control Register + 0x06 + 8 + read-write + 0x00 + 0xFF + - BUSMEN - MPU Bus Master Error Interrupt Enable - 11 - 11 + DAADST + D/A-A/D Synchronous Conversion + 7 + 7 read-write 0 - Disabled + D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled). #0 1 - Enabled. + D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled). #1 + + + + DAVREFCR + D/A VREF Control Register + 0x07 + 8 + read-write + 0x00 + 0xFF + - BUSSEN - MPU Bus Slave Error Interrupt Enable - 10 - 10 + REF + D/A Reference Voltage Select + 0 + 2 read-write - 0 - Disabled - #0 + 000 + Not selected + #000 - 1 - Enabled. - #1 + 001 + AVCC0/AVSS0 + #001 + + + 011 + Internal reference voltage/AVSS0 + #011 + + + 110 + VREFH/VREFL + #110 + + + others + Setting prohibited + true + + + + DAPC + D/A Switch Charge Pump Control Register + 0x09 + 8 + read-write + 0x00 + 0xFF + - RECCEN - RAM ECC Error Interrupt Enable - 9 - 9 + PUMPEN + Charge Pump Enable + 0 + 0 read-write 0 - Disabled + Charge pump disabled #0 1 - Enabled. + Charge pump enabled #1 + + + + DAAMPCR + D/A Output Amplifier Control Register + 0x08 + 8 + read-write + 0x1F + 0xFF + - RPEEN - RAM Parity Error Interrupt Enable - 8 - 8 + 2 + 1 + DAAMP%s + Amplifier Control + 6 + 6 read-write 0 - Disabled + Do not use channel output amplifier #0 - - 1 - Enabled. - #1 - + + + + DAASWCR + D/A Amplifier Stabilization Wait Control Register + 0x1C + 8 + read-write + 0x00 + 0xFF + - NMIEN - NMI Pin Interrupt Enable + DAASW1 + Set the DAASW1 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 1. When DAASW1 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 1. When the DAASW1 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 1 is output through the output amplifier. 7 7 read-write 0 - Disabled + Amplifier stabilization wait off (output) for channel 1 #0 1 - Enabled. + Amplifier stabilization wait on (high-Z) for channel 1 #1 - OSTEN - Oscillation Stop Detection Interrupt Enable + DAASW0 + Set the DAASW0 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 0. When DAASW0 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 0. When the DAASW0 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 0 is output through the output amplifier. 6 6 read-write 0 - Disabled + Amplifier stabilization wait off (output) for channel 0 #0 1 - Enabled. + Amplifier stabilization wait on (high-Z) for channel 0 #1 + + + + DAADUSR + D/A A/D Synchronous Unit Select Register + 0x10C0 + 8 + read-write + 0x00 + 0xFF + - VBATTEN - VBATT monitor Interrupt Enable - 4 - 4 + AMADSEL1 + The DAADUSR register selects the target ADC12 unit for D/A and A/D synchronous conversions. Set bit [1] to 1 to select unit 1 as the target synchronous unit for the MCU. When setting the DAADSCR.DAADST bit to 1 for synchronous conversions, select the target unit in this register in advance. Only set the DAADUSR register while the ADCSR.ADST bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit is set to 0. + 6 + 6 read-write 0 - Disabled + Do not select unit 1 #0 1 - Enabled. + Select unit 1 #1 + + + + + + R_DAC8 + 8-Bit D/A Converter + 0x4009E000 + + 0x00000000 + 0x002 + registers + + + 0x00000003 + 0x01 + registers + + + 0x00000006 + 0x002 + registers + + + + DAM + D/A Converter Mode Register + 0x03 + 8 + read-write + 0x00 + 0xFF + - LVD2EN - Voltage-Monitoring 2 Interrupt Enable - 3 - 3 + DACE1 + D/A operation enable 1 + 5 + 5 read-write 0 - Disabled + D/A conversion disabled for channel 1 #0 1 - Enabled. + D/A conversion enabled for channel 1 #1 - LVD1EN - Voltage-Monitoring 1 Interrupt Enable - 2 - 2 + DACE0 + D/A operation enable 0 + 4 + 4 read-write 0 - Disabled + D/A conversion disabled for channel 0 #0 1 - Enabled. + D/A conversion enabled for channel 0 #1 - WDTEN - WDT Underflow/Refresh Error Interrupt Enable + DAMD1 + D/A operation mode select 1 1 1 read-write 0 - Disabled + Channel 1 for normal operation mode #0 1 - Enabled. + Channel 1 for real-time output mode(event link) #1 - IWDTEN - IWDT Underflow/Refresh Error Interrupt Enable + DAMD0 + D/A operation mode select 0 0 0 read-write 0 - Disabled + Channel 0 for normal operation mode #0 1 - Enabled. + Channel 0 for real-time output mode(event link) #1 @@ -41261,238 +19717,536 @@ FMS2,1,0: - NMICLR - Non-Maskable Interrupt Status Clear Register - 0x130 - 16 + 2 + 0x01 + DACS[%s] + D/A Conversion Value Setting Register %s + 0x00 + 8 read-write - 0x0000 - 0xFFFF + 0x00 + 0xFF - SPECLR - CPU Stack Pointer Monitor Interrupt Clear - 12 - 12 - write-only + DACS + DACS D/A conversion store data + 0 + 7 + read-write + + + + + DACADSCR + D/A A/D Synchronous Start Control Register + 0x06 + 8 + read-write + 0x00 + 0xFF + + + DACADST + D/A A/D Synchronous Conversion + 0 + 0 + read-write 0 - No effect. + Do not synchronize DAC8 with ADC16 operation (disable interference reduction between D/A and A/D conversion) #0 1 - Clear the NMISR.SPEST flag. + Synchronize DAC8 with ADC16 operation (enable interference reduction between D/A and A/D conversion). #1 + + + + DACPC + D/A SW Charge Pump Control Register + 0x07 + 8 + read-write + 0x00 + 0xFF + - BUSMCLR - Bus Master Error Clear - 11 - 11 - write-only + PUMPEN + Charge pump enable + 0 + 0 + read-write 0 - No effect. + Charge pump disable #0 1 - Clear the NMISR.BUSMST flag. + Charge pump enable #1 + + + + + + R_DALI0 + Digital Addressable Lighting Interface + 0x4008F000 + + 0x00000000 + 0x018 + registers + + + 0x0000001E + 0x006 + registers + + + 0x00000026 + 0x004 + registers + + + 0x0000002E + 0x006 + registers + + + 0x00000036 + 0x02 + registers + + + 0x0000003A + 0x004 + registers + + + + BTVTHR1 + DALI Bit Timing Violation Threshold Register 1 + 0x000 + 16 + read-write + 0x4F00 + 0xFFFF + + + BTV2 + Bit Timing Violation Threshold 2Specifies the bit timing violation threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 15 + read-write + - BUSSCLR - Bus Slave Error Clear - 10 - 10 - write-only + BTV1 + Bit Timing Violation Threshold 1Specifies the bit timing violation threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 6 + read-write + + + + + BTVTHR2 + DALI Bit Timing Violation Threshold Register 2 + 0x002 + 16 + read-write + 0x654F + 0xFFFF + + + BTV4 + Bit Timing Violation Threshold 4Specifies the bit timing violation threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 15 + read-write + + + BTV3 + Bit Timing Violation Threshold 3Specifies the bit timing violation threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + BTVTHR3 + DALI Bit Timing Violation Threshold Register 3 + 0x004 + 16 + read-write + 0x009D + 0xFFFF + + + BTV5 + Bit Timing Violation Threshold 5Specifies the bit timing violation threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + BTVTHR4 + DALI Bit Timing Violation Threshold Register 4 + 0x006 + 16 + read-write + 0x00DB + 0xFFFF + + + BTV6 + Bit Timing Violation Threshold 6Specifies the bit timing violation threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 8 + read-write + + + + + COLTHR1 + DALI Collision Threshold Register 1 + 0x008 + 16 + read-write + 0x380F + 0xFFFF + + + COL2 + Collision Threshold 2Specifies the collision threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 13 + read-write + + + COL1 + Collision Threshold 1Specifies the collision threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 5 + read-write + + + + + COLTHR2 + DALI Collision Threshold Register 2 + 0x00A + 16 + read-write + 0x443C + 0xFFFF + + + COL4 + Collision Threshold 4Specifies the collision threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 14 + read-write + + + COL3 + Collision Threshold 3Specifies the collision threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 6 + read-write + + + + + COLTHR3 + DALI Collision Threshold Register 3 + 0x00C + 16 + read-write + 0x7148 + 0xFFFF + + + COL6 + Collision Threshold 6Specifies the collision threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 14 + read-write + + + COL5 + Collision Threshold 5Specifies the collision threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 6 + read-write + + + + + COLTHR4 + DALI Collision Threshold Register 4 + 0x00E + 16 + read-write + 0x8879 + 0xFFFF + + + COL8 + Collision Threshold 8Specifies the collision threshold value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 8 + 15 + read-write + + + COL7 + Collision Threshold 7Specifies the collision threshold value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + COLTHR5 + DALI Collision Threshold Register 5 + 0x010 + 16 + read-write + 0x008E + 0xFFFF + + + COL9 + Collision Threshold 9Specifies the collision threshold value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0. + 0 + 7 + read-write + + + + + CNFR1 + DALI Configuration Register 1 + 0x012 + 16 + read-write + 0x00FF + 0xFFFF + + + CHL + Character Length + 12 + 14 + read-write - 0 - No effect. - #0 + 000 + 8 bits + #000 + + + 001 + 16 bits + #001 + + + 010 + 24 bits + #010 + + + 011 + 32 bits + #011 - 1 - Clear the NMISR.BUSSST flag. - #1 + 100 + 20 bits + #100 - - - - RECCCLR - SRAM ECC Error Clear - 9 - 9 - write-only - - 0 - No effect. - #0 + 101 + 17 bits + #101 - 1 - Clear the NMISR.RECCST flag. - #1 + others + Setting prohibited + true - RPECLR - SRAM Parity Error Clear + CKS + Clock Select 8 - 8 - write-only + 9 + read-write - 0 - No effect. - #0 + 00 + PCLK clock (x = 0) + #00 - 1 - Clear the NMISR.RPEST flag. - #1 + 01 + PCLK/4 clock (x = 1) + #01 - - - - NMICLR - NMI Clear - 7 - 7 - write-only - - 0 - No effect. - #0 + 10 + PCLK/16 clock (x = 2) + #10 - 1 - Clear the NMISR.NMIST flag. - #1 + 11 + PCLK/64 clock (x = 3) + #11 - OSTCLR - OST Clear - 6 - 6 - write-only + BR + Clock SelectBit rate setting example is shown in Table + 0 + 7 + read-write + + + + + CNFR2 + DALI Configuration Register 2 + 0x014 + 16 + read-write + 0x0000 + 0xFFFF + + + CDM0 + Collision Detect ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. + 5 + 5 + read-write 0 - No effect. + Destroy area #0 1 - Clear the NMISR.OSTST flag. + Destroy area and avoidance area (edge) #1 - VBATTCLR - VBATT Clear + CDE + Collision Detect EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. 4 4 - write-only + read-write 0 - No effect. + Collision detection is disabled. #0 1 - Clear the NMISR.VBATTST flag. + Collision detection is enabled. #1 - LVD2CLR - LVD2 Clear + TXWE + DTX Width Modulation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. 3 3 - write-only + read-write 0 - No effect. + The width of DTX0 waveform is not modulated. #0 1 - Clear the NMISR.LVD2ST flag. + The width of DTX0 waveform is modulated. #1 - LVD1CLR - LVD1 Clear + SGA + Save an Edge of Gray Area ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. 2 2 - write-only + read-write 0 - No effect. + The edge allowable area of the DRX0 input signal is the default. #0 1 - Clear the NMISR.LVD1ST flag. + The edge allowable area of the DRX0 input signal is extended. #1 - WDTCLR - WDT Clear + BTVM + Bit Timing Violation ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. 1 1 - write-only + read-write 0 - No effect. + Edge in gray area between half bit and 2-half bit is not detected as bit timing violation. #0 1 - Clear the NMISR.WDTST flag. + Edge in gray area between half bit and 2-half bit is detected as bit timing violation. #1 - IWDTCLR - IWDT Clear + BTVE + Bit Timing Violation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0. 0 0 - write-only + read-write 0 - No effect. + Bit timing violation function is disabled. #0 1 - Clear the NMISR.IWDTST flag. + Bit timing violation function is enabled. #1 @@ -41500,77 +20254,84 @@ FMS2,1,0: - NMICR - NMI Pin Interrupt Control Register - 0x100 - 8 + TXWR1 + DALI DTX Width Register 1 + 0x016 + 16 read-write - 0x00 - 0xFF + 0x003F + 0xFFFF - NFLTEN - NMI Digital Filter Enable - 7 - 7 + TXLW + DTX Low WidthDTX0 pin low level width + 0 + 6 read-write - - - 0 - Digital filter is disabled. - #0 - - - 1 - Digital filter is enabled. - #1 - - + + + + TDR1H + DALI Transmit Data Register 1H + 0x01E + 16 + read-write + 0x0000 + 0xFFFF + - NFCLKSEL - NMI Digital Filter Sampling Clock Select - 4 - 5 + DTDR + Upper 16-bit DALI transmit data + 0 + 15 read-write - - - 00 - PCLKB - #00 - - - 01 - PCLKB/8 - #01 - - - 10 - PCLKB/32 - #10 - - - 11 - PCLKB/64 - #11 - - + + + + TDR1L + DALI Transmit Data Register 1L + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + - NMIMD - NMI Detection Set + DTDR + Lower 16-bit DALI transmit data 0 - 0 + 15 read-write + + + + + TRSTR1 + DALI Transmit Control Register 1 + SPDR + 0x022 + 16 + write-only + 0x0000 + 0xFFFF + + + TRST + Transmission Start Trigger + 0 + 0 + write-only 0 - Falling edge + No effect #0 1 - Rising edge + Transmission Start #1 @@ -41578,1437 +20339,1320 @@ FMS2,1,0: - 96 - 0x4 - IELSR[%s] - ICU Event Link Setting Register %s - 0x300 - 32 + CTR1 + DALI Control Register 1 + 0x026 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - DTCE - DTC Activation Enable - 24 - 24 + FEIE + DALI_FEI Output Enabling + 12 + 12 read-write 0 - DTC activation is disabled + DALI_FEI output is disabled. #0 1 - DTC activation is enabled + DALI_FEI output is enabled. #1 - IR - Interrupt Status Flag - 16 - 16 + BPIE + DALI_BPI Output Enabling + 11 + 11 read-write 0 - No interrupt request is generated + DALI_BPI output is disabled. #0 1 - An interrupt request is generated ( 1 write to the IR bit is prohibited. ) + DALI_BPI output is enabled. #1 - IELS - ICU Event selection to NVICSet the number for the event signal to be linked . - 0 - 8 - read-write - - - 0x000 - Nothing is selected - 0x000 - - - others - See Event Table - true - - - - - - - 8 - 0x4 - DELSR[%s] - DMAC Event Link Setting Register - 0x280 - 32 - read-write - 0x0000 - 0xFFFF - - - IR - Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited. - 16 - 16 + CLIE + DALI_CLI Output Enabling + 10 + 10 read-write - 0x0 - No interrupt request is generated. + 0 + DALI_CLI output is disabled. #0 - 0x1 - An interrupt request is generated. + 1 + DALI_CLI output is enabled. #1 - DELS - Event selection to DMAC Start request - 0 - 8 + DEIE + DALI_DEI Output Enabling + 9 + 9 read-write - 0x000 - Nothing is selected. - 0x000 + 0 + DALI_DEI output is disabled. + #0 - others - See Event Table - true + 1 + DALI_DEI output is enabled. + #1 - - - - SELSR0 - Snooze Event Link Setting Register - 0x200 - 16 - read-write - 0x0000 - 0xFFFF - - SELS - SYS Event Link Select - 0 + SDIE + DALI_SDI Output Enabling + 8 8 read-write - - - 0x000 - Nothing is selected - 0x000 - - - - - - - WUPEN - Wake Up Interrupt Enable Register - 0x1A0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - IIC0WUPEN - IIC0 address match interrupt S/W standby returns enable - 31 - 31 - read-write 0 - S/W standby returns by IIC0 address match interrupt is disabled + DALI_SDI output is disabled. #0 1 - S/W standby returns by IIC0 address match interrupt is enabled + DALI_SDI output is enabled. #1 - AGT1CBWUPEN - AGT1 compare match B interrupt S/W standby returns enable - 30 - 30 + RE + Receive Enabling + 1 + 1 read-write 0 - S/W standby returns by AGT1 compare match B interrupt is disabled + Storing received data is disabled. #0 1 - S/W standby returns by AGT1 compare match B interrupt is enabled + Storing received data is enabled. #1 - AGT1CAWUPEN - AGT1 compare match A interrupt S/W standby returns enable - 29 - 29 + TE + Transmit Enabling + 0 + 0 read-write 0 - S/W standby returns by AGT1 compare match A interrupt is disabled + Transmit operation is disabled. #0 1 - S/W standby returns by AGT1 compare match A interrupt is enabled + Transmit operation is enabled. #1 + + + + TXDCTR1 + DALI DTX Control Register 1 + 0x028 + 16 + read-write + 0x0000 + 0xFFFF + - AGT1UDWUPEN - AGT1 underflow interrupt S/W standby returns enable - 28 - 28 + TXASE + DTX Assert EnablingNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0. + 1 + 1 read-write 0 - S/W standby returns by AGT1 underflow interrupt is disabled + An internal transmit data is output to the DTX0 pin. #0 1 - S/W standby returns by AGT1 underflow interrupt is enabled + The level specified by TXAS bit is output to the DTX0 pin. #1 - USBFSWUPEN - USBFS interrupt S/W standby returns enable - 27 - 27 + TXAS + DTX Assert LevelNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0. + 0 + 0 read-write 0 - S/W standby returns by USBFS interrupt is disabled + The DTX0 pin is driven low. #0 1 - S/W standby returns by USBFS interrupt is enabled + The DTX0 pin is driven high. #1 + + + + RDR1H + DALI Reception Data Register 1H + 0x02E + 16 + read-only + 0x0000 + 0xFFFF + + + DRDR + Upper 16-bit of DALI receive data + 0 + 15 + read-only + + + + + RDR1L + DALI Reception Data Register 1L + 0x030 + 16 + read-only + 0x0000 + 0xFFFF + + + DRDR + Lower 16-bit of DALI receive data + 0 + 15 + read-only + + + + + STR1 + DALI Status Register 1 + 0x032 + 16 + read-only + 0x0000 + 0xFFFF + - USBHSWUPEN - USBHS interrupt S/W standby returns enable bit - 26 - 26 - read-write - - - 0 - S/W standby returns by USBHS interrupt is disabled - #0 - - - 1 - S/W standby returns by USBHS interrupt is enabled - #1 - - + RDBL + Receive Data Bit LengthThese bits store the bit length for data received successfully + 10 + 15 + read-only - RTCPRDWUPEN - RCT period interrupt S/W standby returns enable - 25 - 25 - read-write + DAF + Destroy Area Flag + 9 + 9 + read-only 0 - S/W standby returns by RTC period interrupt is disabled + The collision did not occur in the destroy area or 1 was written to the DALI0.FECR1.DAFC bit. #0 1 - S/W standby returns by RTC period interrupt is enabled + The collision occurred in the destroy area. #1 - RTCALMWUPEN - RTC alarm interrupt S/W standby returns enable - 24 - 24 - read-write + CDF + Collision Detect Flag + 8 + 8 + read-only 0 - S/W standby returns by RTC alarm interrupt is disabled + No collision occurred or 1 was written to the DALI0.FECR1.CDFC bit. #0 1 - S/W standby returns by RTC alarm interrupt is enabled + A collision occurred. #1 - ACMPLP0WUPEN - ACMPLP0 interrupt S/W standby returns enable - 23 - 23 - read-write + O32F + Over 32-Bit Data Reception Flag + 7 + 7 + read-only 0 - S/W standby returns by ACMPLP0 interrupt is disabled + Receive data is 32 bits or less, or 1 was written to the DALI0.FECR1.O32FC bit. #0 1 - S/W standby returns by ACMPLP0 interrupt is enabled + Receive data is 33 bits or more. #1 - ACMPHS0WUPEN - ACMPHS0 interrupt S/W standby returns enable bit - 22 - 22 - read-write + BPDF + Bus Power Down Flag + 6 + 6 + read-only 0 - S/W standby returns by ACMPHS0 interrupt is disabled + No effected #0 1 - S/W standby returns by ACMPHS0 interrupt is enabled + Bus power down detected #1 - VBATTWUPEN - VBATT monitor interrupt S/W standby returns enable - 20 - 20 - read-write + BBF + Bus BUSY Flag + 5 + 5 + read-only 0 - S/W standby returns by VBATT monitor interrupt is disabled + DALI bus is IDLE #0 1 - S/W standby returns by VBATT monitor interrupt is enabled + DALI bus is BUSY #1 - LVD2WUPEN - LVD2 interrupt S/W standby returns enable - 19 - 19 - read-write + TENDF + Transmit End Flag + 4 + 4 + read-only 0 - S/W standby returns by LVD2 interrupt is disabled + 1 was written to the DALI0.FECR1.TENDFC bit. #0 1 - S/W standby returns by LVD2 interrupt is enabled + Frame transmission has been completed. #1 - LVD1WUPEN - LVD1 interrupt S/W standby returns enable - 18 - 18 - read-write + RDRF + Receive Data Register Full Flag + 3 + 3 + read-only 0 - S/W standby returns by LVD1 interrupt is disabled + The DALI0.RDR1L register was read or 1 was written to the DALI0.FECR1.RDRFC. #0 1 - S/W standby returns by LVD1 interrupt is enabled + Receive data is stored in the DALI0.RDR1L or DALI0.RDR1H register. #1 - KEYWUPEN - Key interrupt S/W standby returns enable - 17 - 17 - read-write + BTVF + Bit Timing Violation Flag + 2 + 2 + read-only 0 - S/W standby returns by KEY interrupt is disabled + No bit timing violation occurred or 1 was written to the DALI0.FECR1.BTVFC bit. #0 1 - S/W standby returns by KEY interrupt is enabled + Bit timing violation occurred #1 - IWDTWUPEN - IWDT interrupt S/W standby returns enable - 16 - 16 - read-write + OVF + Overrun Error Flag + 1 + 1 + read-only 0 - S/W standby returns by IWDT interrupt is disabled + No overrun error occurred or 1 was written to the DALI0.FECR1.OVFC bit. #0 1 - S/W standby returns by IWDT interrupt is enabled + An overrun error occurred. #1 - 16 - 0x01 - IRQWUPEN%s - IRQ interrupt S/W standby returns enable + MFEF + Manchester Flaming Error Flag 0 0 - read-write + read-only 0 - S/W standby returns by IRQ interrupt is disabled + No MFE occurred or 1 was written to the DALI0.FECR1.MFEFC bit. #0 1 - S/W standby returns by IRQ interrupt is enabled + An MFE occurred. #1 - - - - R_IIC0 - I2C Bus Interface - 0x40053000 - - 0x00000000 - 0x014 - registers - - - 0x00000016 - 0x002 - registers - - - - 3 - 0x2 - SAR[%s] - Slave Address Registers - 0x0A - 16 - - L - Slave Address Register L - 0x0 - 8 - read-write - 0x00 - 0xFF - - - SVA - A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } - 0 - 7 - read-write - - - - - U - Slave Address Register U - 0x01 - 8 - read-write - 0x00 - 0xFF - - - SVA9 - 10-Bit Address(bit9) - 2 - 2 - read-write - - - SVA8 - 10-Bit Address(bit8) - 1 - 1 - read-write - - - FS - 7-Bit/10-Bit Address Format Selection - 0 - 0 - read-write - - - 0 - The 7-bit address format is selected. - #0 - - - 1 - The 10-bit address format is selected. - #1 - - - - - - - ICCR1 - I2C Bus Control Register 1 - 0x00 - 8 - read-write - 0x1F - 0xFF + COLR1 + DALI Collision Register 1 + 0x036 + 16 + read-only + 0x0800 + 0xFFFF - ICE - I2C Bus Interface Enable - 7 - 7 - read-write + TXDCV + DTX Collision Value + 13 + 13 + read-only 0 - Disable (SCLn and SDAn pins in inactive state) + Low #0 1 - Enable (SCLn and SDAn pins in active state) + High #1 - IICRST - I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). - 6 - 6 - read-write + RXDCEG + DRX Collision Edge + 12 + 12 + read-only 0 - Releases the RIIC reset or internal reset. + Falling edge #0 1 - Initiates the RIIC reset or internal reset. + Rising edge #1 - CLO - Extra SCL Clock Cycle Output - 5 - 5 - read-write + RXDMON + DRX MonitorThis bit monitors the DRX0 pin value after the DRX0 pin is synchronized + 11 + 11 + read-only + + + CLDAF + Collision Last Destroy Area Flag + 10 + 10 + read-only 0 - Does not output an extra SCL clock cycle. + Collision detected is caused by a DRX0 edge occurrence. #0 1 - Outputs an extra SCL clock cycle. + Collision detected is not caused by a DRX0 edge occurrence. (Last destroy area) #1 - SOWP - SCLO/SDAO Write Protect + CDTF1 + Collision Detect Timing Flag 1 4 4 - read-write + read-only 0 - Bits SCLO and SDAO can be written + Collision detection started at the edge on a bit period boundary. #0 1 - Bits SCLO and SDAO are protected. + Collision detection started at the edge in the middle of a bit period. #1 - SCLO - SCL Output Control/Monitor - 3 + CFTF2 + Collision Detect Timing Flag 2 + 0 3 - read-write + read-only - 0 - (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. - #0 + 0000 + After reset is released + #0000 - 1 - (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. - #1 + 0001 + Collision detection timing 1 + #0001 - - - - SDAO - SDA Output Control/Monitor - 2 - 2 - read-write - - 0 - (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. - #0 + 0010 + Collision detection timing 2 + #0010 - 1 - (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. - #1 + 0011 + Collision detection timing 3 + #0011 + + + 0100 + Collision detection timing 4 + #0100 + + + 0101 + Collision detection timing 5 + #0101 + + + 0110 + Collision detection timing 6 + #0110 + + + 0111 + Collision detection timing 7 *1 + #0111 + + + 1000 + Collision detection timing 8 *1 + #1000 + + + 1001 + Collision detection timing 9 *1 + #1001 + + + 1010 + Collision detection timing 10 *1 + #1010 + + + others + Setting prohibited + true + + + + FECR1 + DALI Flag Error Clear Register 1 + 0x03A + 16 + write-only + 0x0000 + 0xFFFF + - SCLI - SCL Line Monitor - 1 - 1 - read-only + DAFC + Destroy Area Flag Clear + 9 + 9 + write-only 0 - SCLn line is low. + DALI0.STR1.DAF bit is not cleared. #0 1 - SCLn line is high. + DALI0.STR1.DAF bit is cleared. #1 - SDAI - SDA Line Monitor - 0 - 0 - read-only + CDFC + Collision Detect Flag Clear + 8 + 8 + write-only 0 - SDAn line is low. + DALI0.STR1.CDF bit is not cleared. #0 1 - SDAn line is high. + DALI0.STR1.CDF bit is cleared. #1 - - - - ICCR2 - I2C Bus Control Register 2 - 0x01 - 8 - read-write - 0x00 - 0xFF - - BBSY - Bus Busy Detection Flag + O32FC + Over 32-Bit Data Reception Flag Clear 7 7 - read-only + write-only 0 - The I2C bus is released (bus free state). + DALI0.STR1.O32F bit is not cleared. #0 1 - The I2C bus is occupied (bus busy state). + DALI0.STR1.O32F bit is cleared #1 - MST - Master/Slave Mode + BPDFC + Bus Power Down Flag Clear 6 6 - read-write + write-only 0 - Slave mode + DALI0.STR1.BPDF bit is not cleared. #0 1 - Master mode + DALI0.STR1.BPDF bit is cleared. #1 - TRS - Transmit/Receive Mode + BBFC + Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1. 5 5 - read-write - - - 0 - Receive mode - #0 - - - 1 - Transmit mode - #1 - - - - - SP - Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. - 3 - 3 - read-write + write-only 0 - Does not request to issue a stop condition. + DALI0.STR1.BBF bit is not cleared. #0 1 - Requests to issue a stop condition. + DALI0.STR1.BBF bit is cleared #1 - RS - Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. - 2 - 2 - read-write + TENDFC + Transmit End Flag Clear + 4 + 4 + write-only 0 - Does not request to issue a restart condition. + DALI0.STR1.TENDF bit is not cleared. #0 1 - Requests to issue a restart condition. + DALI0.STR1.TENDF bit is cleared #1 - ST - Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). - 1 - 1 - read-write + RDRFC + Receive Data Register Full Flag Clear + 3 + 3 + write-only 0 - Does not request to issue a start condition. + DALI0.STR1.RDRF bit is not cleared. #0 1 - Requests to issue a start condition. + DALI0.STR1.RDRF bit is cleared. #1 - - - - ICMR1 - I2C Bus Mode Register 1 - 0x02 - 8 - read-write - 0x08 - 0xFF - - MTWP - MST/TRS Write Protect - 7 - 7 - read-write + BTVFC + Bit Timing Violation Flag Clear + 2 + 2 + write-only 0 - Disables writing to the MST and TRS bits in ICCR2. + DALI0.STR1.BTVF bit is not cleared. #0 1 - Enables writing to the MST and TRS bits in ICCR2. + DALI0.STR1.BTVF bit is cleared. #1 - CKS - Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) - 4 - 6 - read-write + OVFC + Overrun Error Flag Clear + 1 + 1 + write-only - 000 - PCLKB/1 clock - #000 - - - 001 - PCLKB/2 clock - #001 - - - 010 - PCLKB/4 clock - #010 - - - 011 - PCLKB/8 clock - #011 - - - 100 - PCLKB/16 clock - #100 - - - 101 - PCLKB/32 clock - #101 - - - 110 - PCLKB/64 clock - #110 + 0 + DALI0.STR1.OVF bit is not cleared. + #0 - 111 - PCLKB/128 clock - #111 + 1 + DALI0.STR1.OVF bit is cleared + #1 - BCWP - BC Write Protect(This bit is read as 1.) - 3 - 3 + MFEFC + Manchester Flaming Error Flag Clear + 0 + 0 write-only 0 - Enables a value to be written in the BC[2:0] bits. + DALI0.STR1.MFEF bit is not cleared. #0 1 - Disables a value to be written in the BC[2:0] bits. + DALI0.STR1.MFEF bit is cleared #1 + + + + SWRR1 + DALI Software Reset Register 1 + 0x03C + 16 + write-only + 0x0000 + 0xFFFF + - BC - Bit Counter + SWR + Software ResetWriting 1 to this bit causes a software reset. 0 - 2 - read-write - - - 000 - 9 bits - #000 - - - 001 - 2 bits - #001 - - - 010 - 3 bits - #010 - - - 011 - 4 bits - #011 - - - 100 - 5 bits - #100 - - - 101 - 6 bits - #101 - - - 110 - 7 bits - #110 - - - 111 - 8 bits - #111 - - + 0 + write-only + + + + R_DEBUG + Debug Function + 0x4001B000 + + 0x00000000 + 0x04 + registers + + + 0x00000010 + 0x04 + registers + + - ICMR2 - I2C Bus Mode Register 2 - 0x03 - 8 - read-write - 0x06 - 0xFF + DBGSTR + Debug Status Register + 0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF - DLCS - SDA Output Delay Clock Source Select - 7 - 7 - read-write + CDBGPWRUPREQ + Debug power-up request + 28 + 28 + read-only 0 - The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. + 0: OCD is not requesting debug power up #0 1 - The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. + 0: OCD is requesting debug power up #1 - SDDL - SDA Output Delay Counter - 4 - 6 - read-write - - - 000 - No output delay - #000 - - - 001 - 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) - #001 - - - 010 - 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) - #010 - - - 011 - 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) - #011 - - - 100 - 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) - #100 - - - 101 - 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) - #101 - - - 110 - 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) - #110 - - - 111 - 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) - #111 - - - - - TMOH - Timeout H Count Control - 2 - 2 - read-write + CDBGPWRUPACK + Debug power-up acknowledge + 29 + 29 0 - Count is disabled while the SCLn line is at a high level. + Debug power-up request is not acknowledged #0 1 - Count is enabled while the SCLn line is at a high level. + Debug power-up request is acknowledged #1 + + + + DBGSTOPCR + Debug Stop Control Register + 0x10 + 32 + read-write + 0x00000003 + 0xFFFFFFFF + - TMOL - Timeout L Count Control - 1 - 1 + DBGSTOP_RPER + Mask bit for SRAM parity error + 24 + 24 + + + 3 + 1 + DBGSTOP_LVD%s + Mask bit for LVD reset/interupt + 16 + 16 read-write 0 - Count is disabled while the SCLn line is at a low level. + Enable reset/interupt on corresponding LVD #0 1 - Count is enabled while the SCLn line is at a low level. + Mask reset/interupt on corresponding LVD #1 - TMOS - Timeout Detection Time Select + DBGSTOP_RECCR + Mask bit for SRAM ECC error + 25 + 25 + + + DBGSTOP_IWDT + Mask bit for IWDT reset/interrupt 0 0 + + + DBGSTOP_WDT + Mask bit for WDT reset/interrupt + 1 + 1 + + + DBGSTOP_CPER + Mask bit for Cache SRAM parity error reset/interrupt + 31 + 31 read-write 0 - Long mode is selected. + Enable Cache SRAM parity error reset/interrupt #0 1 - Short mode is selected. + Mask Cache SRAM parity error reset/interrupt #1 + + + + R_DMA + DMA Controller Common + 0x40005200 + + 0x00000000 + 0x01 + registers + + - ICMR3 - I2C Bus Mode Register 3 - 0x04 + DMAST + DMAC Module Activation Register + 0x00 8 read-write 0x00 0xFF - SMBS - SMBus/I2C Bus Selection - 7 - 7 + DMST + DMAC Operation Enable + 0 + 0 read-write 0 - The I2C bus is selected. + Disabled. #0 1 - The SMBus is selected. + Enabled. #1 + + + + DMECHR + DMAC Error Channel Register + 0x40 + 32 + read-write + 0x00000000 + 0xffffffff + - WAIT - WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. - 6 - 6 - read-write + DMECH + DMAC Error channel + 0 + 2 + read-only + + + DMECHSAM + DMAC Error channel Security Attribution Monitor + 8 + 8 + read-only 0 - No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) + secure channel #0 1 - WAIT (The period between ninth clock cycle and first clock cycle is held low.) + non-secure channel #1 - RDRFS - RDRF Flag Set Timing Selection - 5 - 5 + DMESTA + DMAC Error Status + 16 + 16 read-write 0 - The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) + No DMA transfer error occurred #0 1 - The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) + DMA transfer error occurred #1 + + + + + + R_DMAC0 + DMA Controller + 0x40005000 + + 0x00000000 + 0x00E + registers + + + 0x00000010 + 0x02 + registers + + + 0x00000013 + 0x003 + registers + + + 0x00000018 + 0x007 + registers + + + + DMSAR + DMA Source Address Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - ACKWP - ACKBT Write Protect - 4 - 4 + DMSAR + Specifies the transfer source start address. + 0 + 31 read-write - - - 0 - Modification of the ACKBT bit is disabled. - #0 - - - 1 - Modification of the ACKBT bit is enabled. - #1 - - + + + + DMDAR + DMA Destination Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - ACKBT - Transmit Acknowledge - 3 - 3 + DMDAR + Specifies the transfer destination start address. + 0 + 31 + read-write + + + + + DMCRA + DMA Transfer Count Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMCRAH + Upper bits of transfer count + 16 + 25 read-write - - - 0 - A 0 is sent as the acknowledge bit (ACK transmission). - #0 - - - 1 - A 1 is sent as the acknowledge bit (NACK transmission). - #1 - - - ACKBR - Receive Acknowledge - 2 - 2 - read-only + DMCRAL + Lower bits of transfer count + 0 + 15 + read-write + + + + + DMCRB + DMA Block Transfer Count Register + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + DMCRB + Specifies the number of block transfer operations or repeat transfer operations. + 0 + 15 + read-write - 0 - A 0 is received as the acknowledge bit (ACK reception). - #0 + 0000 + 65,536 blocks + #0000 - 1 - A 1 is received as the acknowledge bit (NACK reception). - #1 + others + DMCRB blocks + true + + + + DMTMD + DMA Transfer Mode Register + 0x10 + 16 + read-write + 0x0000 + 0xFFFF + - NF - Noise Filter Stage Selection - 0 - 1 + MD + Transfer Mode Select + 14 + 15 read-write 00 - Noise of up to one fIIC cycle is filtered out (single-stage filter). + Normal transfer #00 01 - Noise of up to two fIIC cycles is filtered out (2-stage filter). + Repeat transfer #01 10 - Noise of up to three fIIC cycles is filtered out (3-stage filter). + Block transfer #10 11 - Noise of up to four fIIC cycles is filtered out (4-stage filter) + Setting prohibited #11 - - - - ICFER - I2C Bus Function Enable Register - 0x05 - 8 - read-write - 0x72 - 0xFF - - - FMPE - Fast-mode Plus Enable - 7 - 7 - read-write - - - 0 - No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. - #0 - - - 1 - An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. - #1 - - - - SCLE - SCL Synchronous Circuit Enable - 6 - 6 + DTS + Repeat Area Select + 12 + 13 read-write - 0 - No SCL synchronous circuit is used. - #0 + 00 + The destination is specified as the repeat area or block area. + #00 - 1 - An SCL synchronous circuit is used. - #1 + 01 + The source is specified as the repeat area or block area. + #01 - - - - NFE - Digital Noise Filter Circuit Enable - 5 - 5 - read-write - - 0 - No digital noise filter circuit is used. - #0 + 10 + The repeat area or block area is not specified. + #10 - 1 - A digital noise filter circuit is used. - #1 + 11 + Setting prohibited + #11 - NACKE - NACK Reception Transfer Suspension Enable - 4 - 4 + SZ + Transfer Data Size Select + 8 + 9 read-write - 0 - Transfer operation is not suspended during NACK reception (transfer suspension disabled). - #0 + 00 + 8 bits + #00 - 1 - Transfer operation is suspended during NACK reception (transfer suspension enabled). - #1 + 01 + 16 bits + #01 - - - - SALE - Slave Arbitration-Lost Detection Enable - 3 - 3 - read-write - - 0 - Slave arbitration-lost detection is disabled. - #0 + 10 + 32 bits + #10 - 1 - Slave arbitration-lost detection is enabled. - #1 + 11 + Setting prohibited + #11 - NALE - NACK Transmission Arbitration-Lost Detection Enable - 2 - 2 + DCTG + Transfer Request Source Select + 0 + 1 read-write - 0 - NACK transmission arbitration-lost detection is disabled. - #0 + 00 + Software + #00 - 1 - NACK transmission arbitration-lost detection is enabled. - #1 + 01 + Interrupts*1 from peripheral modules or external interrupt input pins + #01 - - - - MALE - Master Arbitration-Lost Detection Enable - 1 - 1 - read-write - - 0 - Master arbitration-lost detection is disabled. - #0 + 10 + Setting prohibited + #10 - 1 - Master arbitration-lost detection is enabled. - #1 + 11 + Setting prohibited + #11 - TMOE - Timeout Function Enable - 0 - 0 + TKP + Transfer Keeping + 10 + 10 read-write 0 - The timeout function is disabled. + Transfer is stopped by completion of specified total number of transfer operations. #0 1 - The timeout function is enabled. + Transfer is not stopped by completion of specified total number of transfer operations. (free-running) #1 @@ -43016,124 +21660,105 @@ FMS2,1,0: - ICSER - I2C Bus Status Enable Register - 0x06 + DMINT + DMA Interrupt Setting Register + 0x13 8 read-write - 0x09 + 0x00 0xFF - HOAE - Host Address Enable - 7 - 7 - read-write - - - 0 - Host address detection is disabled. - #0 - - - 1 - Host address detection is enabled. - #1 - - - - - DIDE - Device-ID Address Detection Enable - 5 - 5 + DTIE + Transfer End Interrupt Enable + 4 + 4 read-write 0 - Device-ID address detection is disabled. + Disabled #0 1 - Device-ID address detection is enabled. + Enabled #1 - GCAE - General Call Address Enable + ESIE + Transfer Escape End Interrupt Enable 3 3 read-write 0 - General call address detection is disabled. + Disabled #0 1 - General call address detection is enabled. + Enabled #1 - SAR2E - Slave Address Register 2 Enable + RPTIE + Repeat Size End Interrupt Enable 2 2 read-write 0 - Slave address in SARL2 and SARU2 is disabled. + Disabled #0 1 - Slave address in SARL2 and SARU2 is enabled + Enabled #1 - SAR1E - Slave Address Register 1 Enable + SARIE + Source Address Extended Repeat Area Overflow Interrupt Enable 1 1 read-write 0 - Slave address in SARL1 and SARU1 is disabled. + Disabled #0 1 - Slave address in SARL1 and SARU1 is enabled. + Enabled #1 - SAR0E - Slave Address Register 0 Enable + DARIE + Destination Address Extended Repeat Area Overflow Interrupt Enable 0 0 read-write 0 - Slave address in SARL0 and SARU0 is disabled. + Disabled #0 1 - Slave address in SARL0 and SARU0 is enabled. + Enabled #1 @@ -43141,162 +21766,219 @@ FMS2,1,0: - ICIER - I2C Bus Interrupt Enable Register - 0x07 - 8 + DMAMD + DMA Address Mode Register + 0x14 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - TIE - Transmit Data Empty Interrupt Request Enable - 7 - 7 + SM + Source Address Update Mode + 14 + 15 read-write - 0 - Transmit data empty interrupt request (IIC_TXI) is disabled. - #0 + 00 + Fixed address + #00 - 1 - Transmit data empty interrupt request (IIC_TXI) is enabled. - #1 + 01 + Offset addition + #01 + + + 10 + Incremented address + #10 + + + 11 + Decremented address. + #11 - TEIE - Transmit End Interrupt Request Enable + SARA + Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. + 8 + 12 + read-write + + + DM + Destination Address Update Mode 6 - 6 + 7 read-write - 0 - Transmit end interrupt request (IIC_TEI) is disabled. - #0 + 00 + Fixed address + #00 - 1 - Transmit end interrupt request (IIC_TEI) is enabled. - #1 + 01 + Offset addition + #01 - - - - RIE - Receive Data Full Interrupt Request Enable - 5 - 5 - read-write - - 0 - Receive data full interrupt request (IIC_RXI) is disabled. - #0 + 10 + Incremented address + #10 - 1 - Receive data full interrupt request (IIC_RXI) is enabled. - #1 + 11 + Decremented address. + #11 - NAKIE - NACK Reception Interrupt Request Enable - 4 + DARA + Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. + 0 4 read-write + + + DADR + Destination Address Update Select After Reload + 5 + 5 + read-write 0 - NACK reception interrupt request (NAKI) is disabled. + Only reloading #0 1 - NACK reception interrupt request (NAKI) is enabled. + Add index after reloading #1 - SPIE - Stop Condition Detection Interrupt Request Enable - 3 - 3 + SADR + Source Address Update Select After Reload + 13 + 13 read-write 0 - Stop condition detection interrupt request (SPI) is disabled. + Only reloading #0 1 - Stop condition detection interrupt request (SPI) is enabled. + Add index after reloading #1 + + + + DMOFR + DMA Offset Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DMOFR + Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. + 0 + 31 + read-write + + + + + DMCNT + DMA Transfer Enable Register + 0x1C + 8 + read-write + 0x00 + 0xFF + - STIE - Start Condition Detection Interrupt Request Enable - 2 - 2 + DTE + DMA Transfer Enable + 0 + 0 read-write + modify 0 - Start condition detection interrupt request (STI) is disabled. + Disabled #0 1 - Start condition detection interrupt request (STI) is enabled. + Enabled. #1 + + + + DMREQ + DMA Software Start Register + 0x1D + 8 + read-write + 0x00 + 0xFF + - ALIE - Arbitration-Lost Interrupt Request Enable - 1 - 1 + CLRS + DMA Software Start Bit Auto Clear Select + 4 + 4 read-write 0 - Arbitration-lost interrupt request (ALI) is disabled. + SWREQ bit is cleared after DMA transfer is started by software. #0 1 - Arbitration-lost interrupt request (ALI) is enabled. + SWREQ bit is not cleared after DMA transfer is started by software. #1 - TMOIE - Timeout Interrupt Request Enable + SWREQ + DMA Software Start 0 0 read-write + modify 0 - Timeout interrupt request (TMOI) is disabled. + DMA transfer is not requested. #0 1 - Timeout interrupt request (TMOI) is enabled. + DMA transfer is requested. #1 @@ -43304,1413 +21986,1497 @@ FMS2,1,0: - ICSR1 - I2C Bus Status Register 1 - 0x08 + DMSTS + DMA Status Register + 0x1E 8 read-write 0x00 0xFF - HOA - Host Address Detection Flag + ACT + DMA Active Flag 7 7 + read-only + + + 0 + DMAC operation suspended + #0 + + + 1 + DMAC operating. + #1 + + + + + DTIF + Transfer End Interrupt Flag + 4 + 4 read-write zeroToClear modify 0 - Host address is not detected. + No interrupt #0 1 - Host address is detected. + Interrupt occurred. #1 - DID - Device-ID Address Detection Flag - 5 - 5 + ESIF + Transfer Escape End Interrupt Flag + 0 + 0 read-write + zeroToClear + modify 0 - Device-ID command is not detected. + No interrupt #0 1 - Device-ID command is detected. + Interrupt occurred. #1 + + + + DMSRR + DMA Source Reload Address Register + 0x20 + 32 + read-write + 0x00000000 + 0xffffffff + + + DMDRR + DMA Destination Reload Address Register + 0x24 + 32 + read-write + 0x00000000 + 0xffffffff + + + DMSBS + DMA Source Buffer Size Register + 0x28 + 32 + read-write + 0x00000000 + 0xffffffff + + + DMSBSL + Functions as data transfer counter in repeat-block transfer mode + 0 + 15 + read-write + - GCA - General Call Address Detection Flag - 3 - 3 + DMSBSH + Specifies the repeat-area size in repeat-block transfer mode + 16 + 31 + read-write + + + + + DMDBS + DMA Destination Buffer Size Register + 0x2C + 32 + read-write + 0x00000000 + 0xffffffff + + + DMDBSL + Functions as data transfer counter in repeat-block transfer mode + 0 + 15 + read-write + + + DMDBSH + Specifies the repeat-area size in repeat-block transfer mode + 16 + 31 + read-write + + + + + DMBWR + DMA Bufferable Write Enable Register + 0x30 + 8 + read-write + 0x00 + 0xff + + + BWE + Bufferable Write Enable + 0 + 0 read-write 0 - General call address is not detected. + Disables Bufferable Write #0 1 - General call address is detected. + Enables Bufferable Write #1 + + + + + + R_DMAC1 + 0x40005040 + + + R_DMAC2 + 0x40005080 + + + R_DMAC3 + 0x400050C0 + + + R_DMAC4 + 0x40005100 + + + R_DMAC5 + 0x40005140 + + + R_DMAC6 + 0x40005180 + + + R_DMAC7 + 0x400051C0 + + + R_DOC + Data Operation Circuit + 0x40054100 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x004 + registers + + + + DOCR + DOC Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + - AAS2 - Slave Address 2 Detection Flag - 2 - 2 + DOPCFCL + DOPCF Clear + 6 + 6 read-write - zeroToClear - modify 0 - Slave address 2 is not detected. + Maintains the DOPCF flag state. #0 1 - Slave address 2 is detected + Clears the DOPCF flag. #1 - AAS1 - Slave Address 1 Detection Flag - 1 - 1 + DOPCF + Data Operation Circuit Flag + 5 + 5 + read-only + + + DCSEL + Detection Condition Select + 2 + 2 read-write - zeroToClear - modify 0 - Slave address 1 is not detected. + DOPCF is set when data mismatch is detected. #0 1 - Slave address 1 is detected. + DOPCF is set when data match is detected. #1 - AAS0 - Slave Address 0 Detection Flag + OMS + Operating Mode Select 0 - 0 + 1 read-write - zeroToClear - modify - 0 - Slave address 0 is not detected. - #0 + 00 + Data comparison mode + #00 - 1 - Slave address 0 is detected. - #1 + 01 + Data addition mode + #01 + + + 10 + Data subtraction mode + #10 + + + 11 + Setting prohibited + #11 - ICSR2 - I2C Bus Status Register 2 - 0x09 - 8 + DODIR + DOC Data Input Register + 0x02 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - TDRE - Transmit Data Empty Flag - 7 - 7 - read-only + DODIR + 16-bit read-write register in which 16-bit data for use in the operations are stored. + 0 + 15 + read-write + + + + + DODSR + DOC Data Setting Register + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + DODSR + This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes. + 0 + 15 + read-write + + + + + + + R_DRW + 2D Drawing Engine + 0x400E4000 + + 0x00000000 + 0x008 + registers + + + 0x00000010 + 0x050 + registers + + + 0x00000064 + 0x008 + registers + + + 0x00000074 + 0x010 + registers + + + 0x00000090 + 0x020 + registers + + + 0x000000B4 + 0x024 + registers + + + 0x000000DC + 0x010 + registers + + + + CONTROL + Geometry Control Register + 0x00 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + SPANSTORE + Nextline span start is always equal or left to current-line span start + 23 + 23 + write-only 0 - ICDRT contains transmit data. + disabled #0 1 - ICDRT contains no transmit data. + enabled #1 - TEND - Transmit End Flag - 6 - 6 - read-write - zeroToClear - modify + SPANABORT + Shape is horizontally convex, only a single span per scanline + 22 + 22 + write-only 0 - Data is being transmitted. + disabled #0 1 - Data has been transmitted. + enabled #1 - RDRF - Receive Data Full Flag - 5 - 5 - read-write - zeroToClear - modify + UNIONCD + Combine outputs C & D as union (output is final) + 21 + 21 + write-only 0 - ICDRR contains no receive data. + minimum/intersect #0 1 - ICDRR contains receive data. + maximum/union #1 - NACKF - NACK Detection Flag - 4 - 4 - read-write - zeroToClear - modify + UNIONAB + Combine outputs A & B as union (output is called C) + 20 + 20 + write-only 0 - NACK is not detected. + minimum/intersect #0 1 - NACK is detected. + maximum/union #1 - STOP - Stop Condition Detection Flag - 3 - 3 - read-write - zeroToClear - modify + UNION56 + Combine limter 5 & 6 as union (output is called D) + 19 + 19 + write-only 0 - Stop condition is not detected. + minimum/intersect #0 1 - Stop condition is detected. + maximum/union #1 - START - Start Condition Detection Flag - 2 - 2 - read-write - zeroToClear - modify + UNION34 + Combine limter 3 & 4 as union (output is called B) + 18 + 18 + write-only 0 - Start condition is not detected. + minimum/intersect #0 1 - Start condition is detected. + maximum/union #1 - AL - Arbitration-Lost Flag - 1 - 1 - read-write - zeroToClear - modify + UNION12 + Combine limter 1 & 2 as union (output is called A) + 17 + 17 + write-only 0 - Arbitration is not lost. + minimum/intersect #0 1 - Arbitration is lost. + maximum/union #1 - TMOF - Timeout Detection Flag - 0 - 0 - read-write - zeroToClear - modify + BAND2ENABLE + Enable band postprocess for limiter 1 (see L1BAND) + 16 + 16 + write-only 0 - Timeout is not detected. + disabled #0 1 - Timeout is detected. - #1 - - - - - - - ICBRL - I2C Bus Bit Rate Low-Level Register - 0x10 - 8 - read-write - 0xFF - 0xFF - - - BRL - Bit Rate Low-Level Period(Low-level period of SCL clock) - 0 - 4 - read-write - - - - - ICBRH - I2C Bus Bit Rate High-Level Register - 0x11 - 8 - read-write - 0xFF - 0xFF - - - BRH - Bit Rate High-Level Period(High-level period of SCL clock) - 0 - 4 - read-write - - - - - ICDRT - I2C Bus Transmit Data Register - 0x12 - 8 - read-write - 0xFF - 0xFF - - - ICDRT - 8-bit read-write register that stores transmit data. - 0 - 7 - read-write - - - - - ICDRR - I2C Bus Receive Data Register - 0x13 - 8 - read-only - 0x00 - 0xFF - - - ICDRR - 8-bit register that stores the received data - 0 - 7 - read-only - - - - - ICWUR - I2C Bus Wake Up Unit Register - 0x16 - 8 - read-write - 0x10 - 0xFF - + enabled + #1 + + + - WUE - Wakeup Function Enable - 7 - 7 - read-write + BAND1ENABLE + Enable band postprocess for limiter 1 (see L1BAND) + 15 + 15 + write-only 0 - Wakeup function disabled + disabled #0 1 - Wakeup function enabled. + enabled #1 - WUIE - Wakeup Interrupt Request Enable - 6 - 6 - read-write + LIM6THRESHOLD + Enable limiter 6 threshold mode + 14 + 14 + write-only 0 - Wakeup Interrupt Request (IIC0_WUI) disabled + disabled #0 1 - Wakeup Interrupt Request (IIC0_WUI) enabled. + enabled #1 - WUF - Wakeup Event Occurrence Flag - 5 - 5 - read-write + LIM5THRESHOLD + Enable limiter 5 threshold mode + 13 + 13 + write-only 0 - Slave address does not match during wakeup function + disabled #0 1 - Slave address matches during wakeup function. + enabled #1 - WUACK - ACK bit for Wakeup Mode - 4 - 4 - read-write + LIM4THRESHOLD + Enable limiter 4 threshold mode + 12 + 12 + write-only 0 - State of synchronous operation + disabled #0 1 - State of asynchronous operation + enabled #1 - WUAFA - Wakeup Analog Filter Additional Selection - 0 - 0 - read-write + LIM3THRESHOLD + Enable limiter 3 threshold mode + 11 + 11 + write-only 0 - Do not add the wakeup analog filter + disabled #0 1 - Add the wakeup analog filter. + enabled #1 - - - - ICWUR2 - I2C Bus Wake up Unit Register 2 - 0x17 - 8 - read-write - 0xFD - 0xFF - - WUSYF - Wake-up Function Synchronous Operation Status Flag - 2 - 2 - read-only + LIM2THRESHOLD + Enable limiter 2 threshold mode + 10 + 10 + write-only 0 - IIC asynchronous circuit enable condition + disabled #0 1 - IIC synchronous circuit enable condition. + enabled #1 - WUASYF - Wake-up Function Asynchronous Operation Status Flag - 1 - 1 - read-only + LIM1THRESHOLD + Enable limiter 1 threshold mode + 9 + 9 + write-only 0 - IIC synchronous circuit enable condition + disabled #0 1 - IIC asynchronous circuit enable condition. + enabled #1 - WUSEN - Wake-up Function Synchronous Enable - 0 - 0 - read-only + QUAD3ENABLE + Enable quadratic coupling of limiters 5 and 6 + 8 + 8 + write-only 0 - IIC asynchronous circuit enable + disabled #0 1 - IIC synchronous circuit enable + enabled #1 - - - - - - R_IIC1 - 0x40053100 - - - R_IIC2 - 0x40053200 - - - R_IRDA - IrDA Interface - 0x40070F00 - - 0x00000000 - 0x01 - registers - - - - IRCR - IrDA Control Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - IRE - IrDA Enable + QUAD2ENABLE + Enable quadratic coupling of limiters 3 and 4 7 7 - read-write + write-only 0 - Serial I/O pins are used for normal serial communication. + disabled #0 1 - Serial I/O pins are used for IrDA data communication. + enabled #1 - IRTXINV - IRTXD Polarity Switching - 3 - 3 - read-write + QUAD1ENABLE + Enable quadratic coupling of limiters 1 and 2 + 6 + 6 + write-only 0 - Data to be transmitted is output to IRTXD as is. + disabled #0 1 - Data to be transmitted is output to IRTXD after the polarity is inverted. + enabled #1 - IRRXINV - IRRXD Polarity Switching - 2 - 2 - read-write + LIM6ENABLE + Enable limiter 6 + 5 + 5 + write-only 0 - IRRXD input is used as received data as is. + disabled #0 1 - IRRXD input is used as received data after the polarity is inverted. + enabled #1 - - - - - - R_IWDT - Independent Watchdog Timer - 0x40044400 - - 0x00000000 - 0x01 - registers - - - 0x00000004 - 0x02 - registers - - - - IWDTRR - IWDT Refresh Register - 0x00 - 8 - read-write - 0xFF - 0xFF - - IWDTRR - The counter is refreshed by writing 0x00 and then writing 0xFF to this register. - 0 - 7 - read-write + LIM5ENABLE + Enable limiter 5 + 4 + 4 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + - - - - IWDTSR - IWDT Status Register - 0x04 - 16 - read-write - 0x0000 - 0xFFFF - - REFEF - Refresh Error Flag - 15 - 15 - read-write - zeroToClear - modify + LIM4ENABLE + Enable limiter 4 + 3 + 3 + write-only 0 - Refresh error not occurred + disabled #0 1 - Refresh error occurred + enabled #1 - UNDFF - Underflow Flag - 14 - 14 - read-write - zeroToClear - modify + LIM3ENABLE + Enable limiter 3 + 2 + 2 + write-only 0 - Underflow not occurred + disabled #0 1 - Underflow occurred + enabled #1 - CNTVAL - Counter ValueValue counted by the counter - 0 - 13 - read-only + LIM2ENABLE + Enable limiter 2 + 1 + 1 + write-only + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + - - - - - - R_JPEG - JPEG Codec - 0x400E6000 - - 0x00000000 - 0x002 - registers - - - 0x00000003 - 0x00F - registers - - - 0x00000040 - 0x014 - registers - - - 0x00000058 - 0x01C - registers - - - 0x0000008C - 0x008 - registers - - - 0x00000100 - 0x11C - registers - - - 0x00000220 - 0x0B2 - registers - - - 0x00000300 - 0x01C - registers - - - 0x00000320 - 0x0B2 - registers - - - - JCMOD - JPEG Code Mode Register - 0x000 - 8 - read-write - 0x00 - 0xFF - - DSP - Compression/Decompression Set Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-downmodes. - 3 - 3 - read-write + LIM1ENABLE + Enable limiter 1 + 0 + 0 + write-only 0 - Compression process + disabled #0 1 - Decompression process + enabled #1 + + + + CONTROL2 + Surface Control Register + 0x04 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + - REDU - Pixel FormatNOTE: Read-only in Decompression. - 0 - 2 - read-write + RLEPIXELWIDTH + Texel width for RLE unit + 30 + 31 + write-only - 001 - YCbCr422(Compression) / YCbCr422(Decompression) - #001 + 00 + 1 byte per texel + #00 - 000 - Setting prohibited(Compression) / YCbCr444(Decompression) - #000 + 01 + 2 byte per texel + #01 - 110 - Setting prohibited(Compression) / YCbCr411/[Decompression] - #110 + 10 + 3 byte per texel + #10 - 010 - Setting prohibited(Compression) / YCbCr420/[Decompression] - #010 + 11 + 4 byte per texel + #11 + + + + BDIA + Blend destination factor inverted in alpha channel (USEACB = 1) + 29 + 29 + write-only + - others - Setting prohibited(Compression) / Error (this module cannot process normally.)(Decompression]) - true + 0 + use blend factor as specified through BDFA + #0 + + + 1 + invert blend destination factor (1-x) + #1 - - - - JCCMD - JPEG Code Command Register - 0x001 - 8 - write-only - 0x00 - 0x00 - - BRST - Bus Reset. NOTE: When this module is in operation, the bus reset command should not be issued. - 7 - 7 + BSIA + Blend source factor inverted in alpha channel (USEACB = 1) + 28 + 28 write-only 0 - No effect. + use blend factor as specified through BSFA #0 1 - Resets the JCDTCU, JCDTCM, JCDTCD, JCDERR and JCRST registers. + invert blend source factor (1-x) #1 - JEND - Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1 - 2 - 2 + CLUTFORMAT + Format of the CLUT + 27 + 27 write-only 0 - No effect. + aRGB(8888) #0 1 - Clear all bits in JINTE0. + RGB(565) #1 - JRST - JPEG Core Process Stop Clear CommandTo clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1. - 1 - 1 + COLKEYENABLE + color keying enable + 26 + 26 + write-only + + + 0 + color keying disabled + #0 + + + 1 + color keying enabled + #1 + + + + + CLUTENABLE + CLUT enable + 25 + 25 write-only 0 - No effect. + CLUT disabled #0 1 - Clear the process-stopped state caused by requests to read the image size and pixel format(enabled by the INT3 bit in JINTE0). + CLUT enabled #1 - JSRT - JPEG Core Process Start CommandTo start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation. - 0 - 0 + RLEENABLE + RLE enable + 24 + 24 write-only 0 - No effect. + RLE disabled #0 1 - Start JPEG core processing + RLE enabled #1 - - - - JCQTN - JPEG Code Quantization Table Number Register - 0x003 - 8 - read-write - 0x00 - 0xFF - - QT3 - Quantization table number for the third color component NOTE: Read-only in Decompression. - 4 - 5 - read-write + WRITEALPHA + Writeback alpha source for framebufferSet the 'alpha source' for the framebuffer(USEACB = 0)Blend alpha in color 2 instead of framebuffer alpha((USEACB = 1))In not alpha channel blending mode (USEACB = 0):Set the 'alpha source' for the framebuffer.In alpha channel blending mode (USEACB = 1):Blend alpha in color 2 instead of framebuffer alpha00B: BC2A = 1: use alpha from framebuffer as destination (DST_A)else: BC2A = 0: use alpha in color 2 as destination (DST_A) + 22 + 23 + write-only 00 - Use quantization table No.0 (JCQTBL0) as the third color component. + use alpha from color 2 #00 01 - Use quantization table No.1 (JCQTBL1) as the third color component. + use source alpha (pixel coverage) #01 10 - Use quantization table No.2 (JCQTBL2) as the third color component. + use 0.0 as alpha #10 11 - Use quantization table No.3 (JCQTBL3) as the third color component. + use alpha from framebuffer #11 - QT2 - Quantization table number for the second color component NOTE: Read-only in Decompression. - 2 - 3 - read-write + WRITEFORMAT10 + Pixel format of the framebuffer + 20 + 21 + write-only 00 - Use quantization table No.0 (JCQTBL0) as the second color component. + 8bpp a(8)0 #00 01 - Use quantization table No.1 (JCQTBL1) as the second color component. + 16bpp RGB(565) #01 10 - Use quantization table No.2 (JCQTBL2) as the second color component. + 32bpp aRGB(8888) #10 11 - Use quantization table No.3 (JCQTBL3) as the second color component. + 16bpp aRGB(4444) #11 - QT1 - Quantization table number for the first color componentNOTE: Read-only in Decompression. - 0 - 1 - read-write + READFORMAT10 + Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance + 18 + 19 + write-only 00 - Use quantization table No.0 (JCQTBL0) as the first color component. + 8 bpp a(8) (READFORMAT32=00) / 16 bpp aRGB(1555) (READFORMAT32=01) / 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance (READFORMAT32=11) #00 01 - Use quantization table No.1 (JCQTBL1) as the first color component. + 16 bpp RGB(565) (READFORMAT32=00) / 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color (READFORMAT32=01) / 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance (READFORMAT32=10) #01 10 - Use quantization table No.2 (JCQTBL2) as the first color component. + 32 bpp aRGB(8888) (READFORMAT32=00) / 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance (READFORMAT32=10) #10 11 - Use quantization table No.3 (JCQTBL3) as the first color component. + 16 bpp aRGB(4444) (READFORMAT32=00) / 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance (READFORMAT32=10) #11 - - - - JCHTN - JPEG Code Huffman Table Number Register - 0x004 - 8 - read-write - 0x00 - 0xFF - - HTA3 - Huffman table number (AC) for the third color componentNOTE: Read-only in Decompression. - 5 - 5 - read-write + TEXTUREFILTERY + Linear filtering on texture V axis + 17 + 17 + write-only 0 - AC Huffman table 0(HTD3=0)/Setting prohibited(HTD3=1) + no filtering on texture V axis #0 1 - AC Huffman table 1(HTD3=1)/Setting prohibited(HTD3=0) + linear filtering on texture V axis #1 - HTD3 - Huffman table number (DC) for the third color component NOTE: Read-only in Decompression. - 4 - 4 - read-write + TEXTUREFILTERX + Linear filtering on texture U axis + 16 + 16 + write-only 0 - DC Huffman table 0(HTA3=0)/Setting prohibited(HTA3=1) + no filtering on texture U axis #0 1 - DC Huffman table 1(HTA3=1)/Setting prohibited(HTA3=0) + linear filtering on texture U axis #1 - HTA2 - Huffman table number (AC) for the second color componentNOTE: Read-only in Decompression. - 3 - 3 - read-write + TEXTURECLAMPY + Calculating V limiter outside use textureThe bit describes what happens if the V limiter (y direction in texture space) calculates a V value outside of the used texture + 15 + 15 + write-only 0 - AC Huffman table 0(HTD2=0)/Setting prohibited(HTD2=1) + Texture wrap mode: The integer part of the calculated value from the v limiter is anded with TEXVMASK. This results in a repetition of the texture in y/v direction. #0 1 - AC Huffman table 1(HTD2=1)/Setting prohibited(HTD2=0) + Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in y/v direction. #1 - HTD2 - Huffman table number (DC) for the second color component NOTE: Read-only in Decompression. - 2 - 2 - read-write + TEXTURECLAMPX + Calculating U limiter outside use textureThe bit describes what happens if the U limiter (x direction in texture space) calculates a U value outside of the used texture + 14 + 14 + write-only 0 - DC Huffman table 0(HTA2=0)/Setting prohibited(HTA2=1) + Texture wrap mode: The integer part of the calculated value from the u limiter is anded with TEXUMASK. This results in a repetition of the texture in x/u direction. #0 1 - DC Huffman table 1(HTA2=1)/Setting prohibited(HTA2=0) + Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in x/u direction. #1 - HTA1 - Huffman table number (AC) for the first color componentNOTE: Read-only in Decompression. - 1 - 1 - read-write + BC2 + Blend color 2 instead of framebuffer pixel + 13 + 13 + write-only 0 - AC Huffman table 0(HTD1=0)/Setting prohibited(HTD1=1) + use pixel from framebuffer as destination (DST) #0 1 - AC Huffman table 1(HTD1=1)/Setting prohibited(HTD1=0) + use color 2 as destination (DST) #1 - HTD1 - Huffman table number (DC) for the first color component NOTE: Read-only in Decompression. - 0 - 0 - read-write + BDI + Blend destination factor is inverteddst factor will be inverted (meaning 1-a or 1-1 depending on BDF) + 12 + 12 + write-only 0 - DC Huffman table 0(HTA1=0)/Setting prohibited(HTA1=1) + use blend factor as specified through BDF #0 1 - DC Huffman table 1(HTA1=1)/Setting prohibited(HTA1=0) + invert blend destinationfactor (1-x) #1 - - - - JCDRIU - JPEG Code DRI Upper Register - 0x005 - 8 - read-write - 0x00 - 0xFF - - DRIU - Upper Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. - 0 - 7 - read-write + BSI + Blend source factor is invertedsrc factor will be inverted (meaning 1-a or 1-1 depending on BSF) + 11 + 11 + write-only + + + 0 + use blend factor as specified through BSF + #0 + + + 1 + invert blend source factor (1-x) + #1 + + - - - - JCDRID - JPEG Code DRI Lower Register - 0x006 - 8 - read-write - 0x00 - 0xFF - - DRID - Lower Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. - 0 - 7 - read-write + BDF + Blend destination factordst factor is alpha (factor is 1 per default) + 10 + 10 + write-only + + + 0 + use 1.0 as blend destination factor + #0 + + + 1 + use alpha as blend destination factor + #1 + + - - - - JCVSZU - JPEG Code Vertical Size Upper Register - 0x007 - 8 - read-write - 0x00 - 0xFF - - VSZU - Upper Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write + BSF + Blend source factorsrc factor is alpha (factor is 1 per default) + 9 + 9 + write-only + + + 0 + use 1.0 as blend source factor + #0 + + + 1 + use alpha as blend source factor + #1 + + - - - - JCVSZD - JPEG Code Vertical Size Lower Register - 0x008 - 8 - read-write - 0x00 - 0xFF - - VSZD - Lower Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write + WRITEFORMAT2 + Bit 3 of framebuffer pixel formatSee WRITEFORMAT above description. + 8 + 8 + write-only - - - - JCHSZU - JPEG Code Horizontal Size Upper Register - 0x009 - 8 - read-write - 0x00 - 0xFF - - HSZU - Upper Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 + BDFA + Blend destinetion factor for alpha channel in alpha channel blending mode (USEACB = 1) + 7 7 - read-write + write-only + + + 0 + use 1.0 as blend destination factor for alpha channel + #0 + + + 1 + use alpha as blend destination factor for alpha channel + #1 + + - - - - JCHSZD - JPEG Coded Horizontal Size Lower Register - 0x00A - 8 - read-write - 0x00 - 0xFF - - HSZD - Lower Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. - 0 - 7 - read-write + BSFA + Blend source factor for alpha channel in alpha channel blending mode (USEACB = 1) + 6 + 6 + write-only + + + 0 + use 1.0 as blend source factor for alpha channel + #0 + + + 1 + use alpha as blend source factor for alpha channel + #1 + + - - - - JCDTCU - JPEG Code Data Count Upper Register - 0x00B - 8 - read-only - 0x00 - 0xFF - - DCU - Upper bytes of the counted amount of data to be compressed The values of this register are reset before compression starts.NOTE: Read-only in Decompression. - 0 - 7 - read-only + READFORMAT32 + Bit 4 and 3 of the texture buffer format.See READFORMAT above for description + 4 + 5 + write-only - - - - JCDTCM - JPEG Code Data Count Middle Register - 0x00C - 8 - read-only - 0x00 - 0xFF - - DCM - Middle bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts. NOTE: Read-only in Decompression. + USEACB + Alpha blend mode + 3 + 3 + write-only + + + 0 + use WRITEALPHA[1:0] mode + #0 + + + 1 + use full alpha channel blending mode + #1 + + + + + PATTERNSOURCEL5 + Limiter 5 is used as pattern index instead of the default U limiter.Limiter 5 can be combined with limiter 6 to form a quadratic limiter which can be used to make quadratic pattern functions to draw radial patterns. + 2 + 2 + write-only + + + TEXTUREENABLE + Pixel source is read from texture and used as an alpha to blend between COLOR1 and COLOR2 + 1 + 1 + write-only + + + 0 + disabled texture + #0 + + + 1 + enabled texture + #1 + + + + + PATTERNENABLE + Pixel source is a pattern color (blend of COLOR1 and COLOR2 depending on PATTERN and pattern index) 0 - 7 - read-only + 0 + write-only + + + 0 + disabled pattern + #0 + + + 1 + enabled pattern + #1 + + - JCDTCD - JPEG Code Data Count Lower Register - 0x00D - 8 - read-only - 0x00 - 0xFF + IRQCTL + Interrupt Control Register + 0xC0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF - DCD - Lower bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts.NOTE: Read-only in Decompression. - 0 - 7 - read-only + BUSIRQCLR + Clear bus error interrupt BUSIRQ + 5 + 5 + write-only + + + 0 + no BUSIRQCLR clear + #0 + + + 1 + clear BUSIRQCLR + #1 + + + + + BUSIRQEN + BUSIRQ interrupt mask enable + 4 + 4 + write-only + + + 0 + disable (mask) BUSIRQ + #0 + + + 1 + enable (unmask) BUSIRQ + #1 + + - - - - JINTE0 - JPEG Interrupt Enable Register 0 - 0x00E - 8 - read-write - 0x00 - 0xFF - - INT7 - This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression.When this bit is not set to enable interrupt generation, an error code is not returned. - 7 - 7 - read-write + DLISTIRQCLR + Clear display list interrupt DLISTIRQ + 3 + 3 + write-only 0 - Disabled + no DLISTRQCLR clear #0 1 - Enabled + clear DLISTRQCLR #1 - INT6 - This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. - 6 - 6 - read-write + ENUMIRQCLR + Clear enumeration interrupt ENUMIRQ + 2 + 2 + write-only 0 - Disabled + no ENUMIRQCLR clear #0 1 - Enabled + clear ENUMIRQCLR #1 - INT5 - This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. - 5 - 5 - read-write + DLISTIRQEN + DLISTIRQ interrupt mask enable + 1 + 1 + write-only 0 - Disabled + disable (mask) DLISTIRQ #0 1 - Enabled + enable (unmask) DLISTIRQ #1 - INT3 - This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. - 3 - 3 - read-write + ENUMIRQEN + ENUMIRQ interrupt mask enable + 0 + 0 + write-only 0 - Disabled + disable (mask) ENUMIRQ #0 1 - Enabled + enable (unmask) ENUMIRQ #1 @@ -44718,167 +23484,86 @@ FMS2,1,0: - JINTS0 - JPEG Interrupt Status Register 0 - 0x00F - 8 - read-write - 0x00 - 0xFF + CACHECTL + Cache Control Register + 0xC4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF - INS6 - This bit is set to 1 when this module completes compression process normally. - 6 - 6 - read-write - zeroToClear - modify - - - INS5 - This bit is set to 1 when a compressed data error occurs. - 5 - 5 - read-write - zeroToClear - modify - - - INS3 - This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. + CFLUSHTX + Flush texture cache 3 3 - read-write - zeroToClear - modify - - - - - JCDERR - JPEG Code Decode Error Register - 0x010 - 8 - read-write - 0x0A - 0xFF - - - ERR - Error Code (See tables )Identify the type of the error which has occurred in the compressed data analysis for decompression. - 0 - 3 - read-write + write-only - 0000 - Normal(Decompression error codes)/Normal(Segment error codes) - #0000 - - - 0001 - SOI not detected(Decompression error codes) - #0001 - - - 0010 - SOF1 to SOFF detected(Decompression error codes) - #0010 - - - 0011 - Unprovided pixel format detected(Decompression error codes) - #0011 - - - 0100 - SOF accuracy error(Decompression error codes) - #0100 - - - 0101 - DQT accuracy error(Decompression error codes) - #0101 - - - 0110 - Component error 1(Decompression error codes) - #0110 - - - 0111 - Component error 2(Decompression error codes) - #0111 - - - 1000 - SOF0, DQT, and DHT not detected when SOS detected(Decompression error codes) - #1000 - - - 1001 - SOS not detected(Decompression error codes) - #1001 - - - 1010 - EOI not detected (default)(Decompression error codes) - #1010 + 0 + do not flush the texture cache + #0 - 1011 - Restart interval data number error detected(Decompression error codes)/Restart interval data number error(Segment error codes) - #1011 + 1 + flush the texture cache + #1 + + + + CENABLETX + Texture cache enable + 2 + 2 + write-only + - 1100 - Image size error detected(Decompression error codes)/Image size error(Segment error codes) - #1100 + 0 + disable the texture cache + #0 - 1101 - Last MCU data number error detected(Decompression error codes)/Last MCU data number error(Segment error codes) - #1101 + 1 + enable the texture cache + #1 + + + + CFLUSHFX + Flush framebuffer cache + 1 + 1 + write-only + - 1110 - Block data number error detected(Decompression error codes)/Block data number error(Segment error codes) - #1110 + 0 + do not flush the framebuffer cache + #0 - others - Setting prohibited - true + 1 + flush the framebuffer cache + #1 - - - - JCRST - JPEG Code Reset Register - 0x011 - 8 - read-only - 0x00 - 0xFF - - RST - Operating State + CENABLEFX + Framebuffer cache enable 0 0 - read-only + write-only 0 - State other than below + disable the framebuffer cache #0 1 - Suspended state caused by interrupt sources of JINTE0 + enable the framebuffer cache #1 @@ -44886,3913 +23571,10527 @@ FMS2,1,0: - JIFECNT - JPEG Interface Compression Control Register - 0x040 + STATUS + Status Control Register + CONTROL + 0x00 32 - read-write + read-only 0x00000000 0xFFFFFFFF - JOUTSWAP - Byte/Halfword/Word Swap Output coded data in compression is swapped. - 8 + BUSERRMDL + display list bus error interrupt triggered + 10 10 - read-write + read-only - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 + 0 + no display list bus error occurred or interrupt disabled + #0 - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 + 1 + display list bus error interrupt triggered + #1 + + + + BUSERRMTXMRL + texture bus error interrupt triggered + 9 + 9 + read-only + - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 + 0 + no texture bus error occurred or interrupt disabled + #0 - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 + 1 + texture bus error interrupt triggered + #1 + + + + BUSERRMFB + framebuffer bus error interrupt triggered + 8 + 8 + read-only + - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] - #110 + 0 + no framebuffer bus error occured or interrupt disabled + #0 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Word - byte swap] - #111 + 1 + framebuffer bus error interrupt triggered + #1 - DINRINI - Address Initialization when Resuming Input of Image Data Lines This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. + BUSIRQ + bus error interrupt triggered 6 6 - read-write + read-only 0 - The transfer address is not initialized when the input of image data lines is restarted + no bus error occurred or interrupt disabled #0 1 - The transfer address is initialized when the input of image data lines is restarted + bus error interrupt triggered #1 - DINRCMD - Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. + DLISTIRQ + display list finished interrupt triggered 5 5 - write-only - - - DINLC - Count Mode Setting for Stopping Input Image Data Lines - 4 - 4 - read-write + read-only 0 - Count mode for stopping the input of image data lines is off + display list not finished or interrupt disabled #0 1 - Count mode for stopping the input of image data lines is on + display list finished interrupt triggered #1 - DINSWAP - Byte/Halfword Swap - 0 - 2 - read-write + ENUMIRQ + enumeration finished interrupt triggered + 4 + 4 + read-only - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 - - - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 - - - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 + 0 + enumeration not finished or interrupt disabled + #0 - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 + 1 + enumeration finished interrupt triggered + #1 + + + + DLISTACTIVE + Display list reader status + 3 + 3 + read-only + - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] - #110 + 0 + display list reader is idle + #0 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] - #111 + 1 + display list reader busy, no direct write access to registers allowed + #1 - - - - JIFESA - JPEG Interface Compression Source Address Register - 0x044 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ESA - Input Image Data Source Address (in 8-byte units) The lower three bits should be set to 0. - 0 - 31 - read-write - - - - - JIFESOFST - JPEG Interface Compression Line Offset Register - 0x048 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ESMW - Input Image Data Lines Offset(in 8-byte units)The lower three bits should be set to 0. - 0 - 14 - read-write - - - - - JIFEDA - JPEG Interface Compression Destination Address Register - 0x04C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - EDA - Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. - 0 - 31 - read-write - - - - - JIFESLC - JPEG Interface Compression Source Line Count Register - 0x050 - 32 - read-write - 0xFFF8FFF8 - 0xFFFFFFFF - - - LINES - Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. - 0 - 15 - read-write - - - - - JIFDCNT - JPEG Interface Decompression Control Register - 0x058 - 32 - read-write - 0x01000000 - 0xFFFFFFFF - - VINTER - Vertical SubsamplingSubsamples vertical output image data. - 28 - 29 - read-write + CACHEDIRTY + Framebuffer cache status + 2 + 2 + read-only - 00 - No subsampling - #00 + 0 + framebuffer cache is not dirty + #0 - 01 - Subsamples output data into 1/2. - #01 + 1 + framebuffer cache is dirty, frame should not be flipped + #1 + + + + BUSYWRITE + Framebuffer writeback status + 1 + 1 + read-only + - 10 - Subsamples output data into 1/4. - #10 + 0 + framebuffer writeback finished + #0 - 11 - Subsamples output data into 1/8. - #11 + 1 + framebuffer writeback busy, framebuffer type can not be changed + #1 - HINTER - Horizontal Subsampling Subsamples horizontal output image data. - 26 - 27 - read-write + BUSYENUM + Enumeration unit status + 0 + 0 + read-only - 00 - No subsampling - #00 + 0 + enumeration unit idle + #0 - 01 - Subsamples output data into 1/2. - #01 + 1 + enumeration unit busy, new primitive can not be started + #1 + + + + + + HWREVISION + Hardware Version and Feature Set ID Register + CONTROL2 + 0x04 + 32 + read-only + 0x0FBE0107 + 0xFFFFFFFF + + + ACBLEND + Alpha channel blending feature + 27 + 27 + read-only + - 10 - Subsamples output data into 1/4. - #10 + 0 + Alpha channel blending unavailable + #0 - 11 - Subsamples output data into 1/8. - #11 + 1 + Alpha channel blending available + #1 - OPF - Specifies output image data pixel format. - 24 + COLORKEY + Colorkey feature + 25 25 - read-write + read-only - 01 - ARGB8888 - #01 - - - 10 - RGB565 - #10 + 0 + Colorkey unavailable + #0 - others - Setting prohibited - true + 1 + Colorkey available + #1 - JINRINI - Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. - 14 - 14 - read-write + TEXCLUT256 + Texture CLUT feature + 24 + 24 + read-only 0 - The transfer address is not initialized when the input of coded data is restarted. + Texture CLUT unavailable #0 1 - The transfer address is initialized when the input of coded data is restarted. + Texture CLUT available #1 - JINRCMD - Input Coded Data Resume CommandThis bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0. - 13 - 13 - write-only - - - JINC - Count Mode Setting for Stopping Input Coded Data - 12 - 12 - read-write + RLEUNIT + RLE unit feature + 23 + 23 + read-only 0 - Count mode for stopping the input of coded data is off. + RLE unit unavailable #0 1 - Count mode for stopping the input of coded data is on + RLE unit available #1 - JINSWAP - Byte/Word/Longword Swap Input coded data in decompression is swapped. - 8 - 10 - read-write + TEXCLU + Texture CLUT with 16 or 256 entries feature + 21 + 21 + read-only - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 + 0 + Texture CLUT with 16 or 256 entries unavailable + #0 - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 + 1 + Texture CLUT with 16 or 256 entries available + #1 + + + + PERFCOUNT + Two performance counter feature + 20 + 20 + read-only + - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 + 0 + Two performance counter unavailable + #0 - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 + 1 + Two performance counter available + #1 + + + + TXCACHE + Texture cache feature + 19 + 19 + read-only + - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word -Halfword swap] - #110 + 0 + Texture cache unavailable + #0 - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] - #111 + 1 + Texture cache available + #1 - DOUTRINI - Address Initialization when Resuming Output of Image Data Lines This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. - 6 - 6 - read-write + FBCACHE + Framebuffer cache feature + 18 + 18 + read-only 0 - The transfer address is not initialized when the output of lines of image data is restarted. + Framebuffer cache unavailable #0 1 - The transfer address is initialized when the output of lines of image data is restarted + Framebuffer cache available #1 - DOUTRCMD - Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. - 5 - 5 - write-only - - - DOUTLC - Count Mode for Stopping Output Image Data Lines - 4 - 4 - read-write + DLR + Display list reader feature + 17 + 17 + read-only 0 - Count mode for stopping the output of image data lines is off. + Display list reader unavailable #0 1 - Count mode for stopping the output of image data lines is on + Display list reader available #1 - DOUTSWAP - Byte/Word Swap Output image data in decompression is swapped. + REV + Revision number + 0 + 11 + read-only + + + + + COLOR1 + Base Color Register + 0x64 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + COLOR1A + Alpha channel of color 1(0x00: transparent. . . 0xFF: opaque) + 24 + 31 + write-only + + + COLOR1R + Red channel of color 1 + 16 + 23 + write-only + + + COLOR1G + Green channel of color 1 + 8 + 15 + write-only + + + COLOR1B + Blue channel of color 1 + 0 + 7 + write-only + + + + + COLOR2 + Secondary Color Register + 0x68 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + COLOR2A + Alpha channel of color 2(0x00: transparent. . . 0xFF: opaque) + 24 + 31 + write-only + + + COLOR2R + Red channel of color 2 + 16 + 23 + write-only + + + COLOR2G + Green channel of color 2 + 8 + 15 + write-only + + + COLOR2B + Blue channel of color 2 + 0 + 7 + write-only + + + + + PATTERN + Pattern Register + 0x74 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + PATTERN + Bitmap of the pattern + 0 + 7 + write-only + + + + + 6 + 0x4 + 1-6 + L%sSTART + Limiter %s Start Value Register + 0x10 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LSTART + Start value of the n'th limiter(n=1-6) + 0 + 31 + write-only + + + + + 6 + 0x4 + 1-6 + L%sXADD + Limiter %s X-Axis Increment Register + 0x28 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LXADD + X-axis increment + 0 + 31 + write-only + + + + + 6 + 0x4 + 1-6 + L%sYADD + Limiter %s Y-Axis Increment Register + 0x40 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LYADD + Y-axis increment + 0 + 31 + write-only + + + + + 2 + 0x4 + 1,2 + L%sBAND + Limiter %s Band Width Parameter Register + 0x58 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LBAND + Limiter m band width parameter + 0 + 31 + write-only + + + + + TEXORIGIN + Texture Base Address Register + 0xBC + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + TEXORIGIN + Texture base address + 0 + 31 + write-only + + + + + TEXPITCH + Texels Per Texture Line Register + 0xB4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + TEXPITCH + Texels per texture linevalid range: 0 to 2048 + 0 + 31 + write-only + + + + + TEXMASK + Texture Size or Texture Address Mask Register + 0xB8 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + TEXVMASK + V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = 0): texture_height must be a power of 2In texture clamping mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 are allowed. + 11 + 31 + write-only + + + TEXUMASK + U maskSet TEXUMASK[10:0] = texture_width -1In texture wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX = 1):all widths up to 2048 are allowed. + 0 + 10 + write-only + + + + + LUSTART + U Limiter Start Value Register + 0x90 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + LUSTART + U limiter start value 0 - 2 - read-write - - - 000 - (1) (2) (3) (4) (5) (6) (7) (8) - #000 - - - 001 - (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] - #001 - - - 010 - (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] - #010 - - - 011 - (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] - #011 - - - 100 - (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] - #100 - - - 101 - (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] - #101 - - - 110 - (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] - #110 - - - 111 - (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] - #111 - - + 31 + write-only - JIFDSA - JPEG Interface Decompression Source Address Register - 0x05C + LUXADD + U Limiter X-Axis Increment Register + 0x94 32 - read-write + write-only 0x00000000 0xFFFFFFFF - DSA - Input Coded Data Source AddressInput Coded Data Source Address (in 8-byte units) The lower three bits should be set to 0. + LUXADD + U limiter x-axis increment 0 31 - read-write + write-only - JIFDDOFST - JPEG Interface Decompression Line Offset Register - 0x060 + LUYADD + U Limiter Y-Axis Increment Register + 0x98 32 - read-write + write-only 0x00000000 0xFFFFFFFF - DDMW - Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + LUYADD + U limiter y-axis increment 0 - 14 - read-write + 31 + write-only - JIFDDA - JPEG Interface Decompression Destination Address Register - 0x064 + LVSTARTI + V Limiter Start Value Integer Part Register + 0x9C 32 - read-write + write-only 0x00000000 0xFFFFFFFF - DDA - Output Image Data Destination Address (in 8-byte units) The lower three bits should be set to 0. + LVSTARTI + V limiter start value integer part 0 31 - read-write + write-only - JIFDSDC - JPEG Interface Decompression Source Data Count Register - 0x068 + LVSTARTF + V Limiter Start Value Fractional Part Register + 0xA0 32 - read-write - 0xFFF8FFF8 + write-only + 0x00000000 0xFFFFFFFF - JDATAS - Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. + LVSTARTF + V limiter start value fractional part 0 15 - read-write + write-only - JIFDDLC - JPEG Interface Decompression Destination Line Count Register - 0x06C + LVXADDI + V Limiter X-Axis Increment Integer Part Register + 0xA4 32 - read-write - 0xFFF8FFF8 + write-only + 0x00000000 0xFFFFFFFF - LINES - Number of Input Image Lines to Be ReadThe lower three bits should be set to 0. These bits are read as0.Number of input image data lines to be read, in 8-line units. + LVXADDI + V limiter x-axis increment integer part 0 - 15 - read-write + 31 + write-only - JIFDADT - JPEG Interface Decompression alpha Set Register - 0x070 + LVYADDI + V Limiter Y-Axis Increment Integer Part Register + 0xA8 32 - read-write + write-only 0x00000000 0xFFFFFFFF - ALPHA - Setting of the alpha value for output in ARGB8888 format. + LVYADDI + V limiter y-axis increment integer part 0 - 7 - read-write + 31 + write-only - JINTE1 - JPEG Interrupt Enable Register 1 - 0x08C + LVYXADDF + V Limiter Increment Fractional Parts Register + 0xAC 32 - read-write + write-only 0x00000000 0xFFFFFFFF - CBTEN - Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. - 6 - 6 - read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - + LVYADDF + V y limiter increment fractional part + 16 + 31 + write-only - DINLEN - Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1. - 5 - 5 - read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - + LVXADDF + V xlimiter increment fractional part + 0 + 15 + write-only + + + + TEXCLADDR + CLUT Start Address Register + 0xDC + 32 + write-only + 0x00000000 + 0xFFFFFFFF + - DBTEN - Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1. - 2 - 2 - read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - + CLADDR + Texture CLUT start address for indexed texture format + 0 + 7 + write-only + + + + TEXCLDATA + CLUT Data Register + 0xE0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + - JINEN - Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1. - 1 - 1 - read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - + CLDATA + Texture CLUT data for Indexed texture format + 0 + 31 + write-only + + + + TEXCLOFFSET + CLUT Offset Register + 0xE4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + - DOUTLEN - Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1 + CLOFFSET + Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] is or'ed with the original index 0 - 0 - read-write - - - 0 - Disables an interrupt request. - #0 - - - 1 - Enables an interrupt request. - #1 - - + 7 + write-only - JINTS1 - JPEG Interrupt Status Register 1 - 0x090 + COLKEY + Color Key Register + 0xE8 32 - read-write + write-only 0x00000000 0xFFFFFFFF - CBTF - This bit is set to 1 when the last output coded data is written in compression. - 6 - 6 - read-write - modify + COLKEYR + Red channel of color key + 16 + 23 + write-only - DINLF - This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression. This bit is valid only when the DINLC bit in JIFECNT is set to 1. - 5 - 5 - read-write - modify + COLKEYG + Green channel of color key + 8 + 15 + write-only - DBTF - This bit is set to 1 when the last output image data is written in decompression. - 2 - 2 - read-write - modify + COLKEYB + Blue channel of color key + 0 + 7 + write-only + + + + SIZE + Bounding Box Dimension Register + 0x78 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + - JINF - This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression. This bit is valid only when the JINC bit in JIFDCNT is set to 1. - 1 - 1 - read-write - modify + SIZEY + Height of the bounding box in pixelsvalid range: 0 to 1024 + 16 + 31 + write-only - DOUTLF - In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. + SIZEX + Width of the bounding box in pixelsvalid range: 0 to 1024 0 - 0 - read-write - modify + 15 + write-only - 64 - 0x1 - JCQTBL0[%s] - Quantization Table 0 - 0x0100 - 8 + PITCH + Framebuffer Pitch And Spanstore Delay Register + 0x7C + 32 write-only - 0x00 - 0x00 - - - JCQTBL1[%s] - Quantization Table 1 - 0x0140 - - - JCQTBL2[%s] - Quantization Table 2 - 0x0180 - - - JCQTBL3[%s] - Quantization Table 3 - 0x01C0 + 0x00000000 + 0xFFFFFFFF + + + SSD + Spanstore delay + 16 + 31 + write-only + + + PITCH + pitch of the framebuffer. A negative width can be used to render bottom-up instead of top-down + 0 + 15 + write-only + + - 28 - 0x1 - JCHTBD0[%s] - DC Huffman Table 0 - 0x0200 - 8 - read-write - 0x00 - 0x00 - - - JCHTBD1[%s] - DC Huffman Table 1 - 0x0300 + ORIGIN + Framebuffer Base Address Register + 0x80 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + ORIGIN + Address of the first pixel in framebuffer + 0 + 31 + write-only + + - 178 - 0x1 - JCHTBA0[%s] - AC Huffman Table 0 - 0x0220 - 8 - read-write - 0x00 - 0x00 - - - JCHTBA1[%s] - DC Huffman Table 1 - 0x0320 + DLISTSTART + Display List Start Address Register + 0xC8 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + DLISTSTART + Display list start address + 0 + 31 + write-only + + - - - - R_KINT - Key Interrupt Function - 0x40080000 - - 0x00000000 - 0x01 - registers - - - 0x00000004 - 0x01 - registers - - - 0x00000008 - 0x01 - registers - - - KRCTL - KEY Return Control Register - 0x00 - 8 - read-write - 0x00 - 0xFF + PERFTRIGGER + Performance Counters Control Register + 0xD4 + 32 + write-only + 0x00000000 + 0xFFFFFFFF - KRMD - Usage of Key Interrupt Flags(KR0 to KR7) - 7 - 7 - read-write + PERFTRIGGER2 + Selects the internal event that will increment PERFCOUNT2 register + 16 + 31 + write-only - 0 - Do not use key interrupt flags - #0 + 0x00 + disable performance counter + 0x00 - 1 - Use key interrupt flags. - #1 + 0x01 + 2D Drawing Engine active cycles + 0x01 - - - - KREG - Detection Edge Selection (KRF0 to KRF7) - 0 - 0 - read-write - - 0 - Falling edge - #0 + 0x02 + framebuffer read access + 0x02 - 1 - Rising edge - #1 + 0x03 + framebuffer write access + 0x03 - - - - - - KRF - KEY Return Flag Register - 0x04 - 8 - read-write - 0x00 - 0xFF - zeroToClear - modify - - - KRF7 - Key interrupt flag 7 - 7 - 7 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x04 + texture read access + 0x04 - 1 - Interrupt detected. - #1 + 0x05 + invisible pixels (enumerated but selected with alpha 0percent) + 0x05 - - - - KRF6 - Key interrupt flag 6 - 6 - 6 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x06 + invisible pixels while internal FIFO is empty (lost cycles) + 0x06 - 1 - Interrupt detected. - #1 + 0x07 + display list reader active cycles + 0x07 - - - - KRF5 - Key interrupt flag 5 - 5 - 5 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x08 + framebuffer read hits + 0x08 - 1 - Interrupt detected. - #1 + 0x09 + framebuffer read misses + 0x09 - - - - KRF4 - Key interrupt flag 4 - 4 - 4 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x0A + framebuffer write hits + 0x0A - 1 - Interrupt detected. - #1 + 0x0B + framebuffer write misses + 0x0B - - - - KRF3 - Key interrupt flag 3 - 3 - 3 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x0C + texture read hits + 0x0C - 1 - Interrupt detected. - #1 + 0x0D + texture read misses + 0x0D - - - - KRF2 - Key interrupt flag 2 - 2 - 2 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x1F + every clock cycle (for use as timer) + 0x1F - 1 - Interrupt detected. - #1 + others + Setting prohibited + true - KRF1 - Key interrupt flag 1 - 1 - 1 - read-write - zeroToClear - modify + PERFTRIGGER1 + Selects the internal event that will increment PERFCOUNT1 register. + 0 + 15 + write-only - 0 - No interrupt detected - #0 + 0x00 + disable performance counter + 0x00 - 1 - Interrupt detected. - #1 + 0x01 + 2D Drawing Engine active cycles + 0x01 - - - - KRF0 - Key interrupt flag 0 - 0 - 0 - read-write - zeroToClear - modify - - 0 - No interrupt detected - #0 + 0x02 + framebuffer read access + 0x02 - 1 - Interrupt detected. - #1 + 0x03 + framebuffer write access + 0x03 - - - - - - KRM - KEY Return Mode Register - 0x08 - 8 - read-write - 0x00 - 0xFF - - - KRM7 - Key interrupt mode control 7 - 7 - 7 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x04 + texture read access + 0x04 - 1 - Detect key interrupt signal. - #1 + 0x05 + invisible pixels (enumerated but selected with alpha 0percent) + 0x05 - - - - KRM6 - Key interrupt mode control 6 - 6 - 6 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x06 + invisible pixels while internal FIFO is empty (lost cycles) + 0x06 - 1 - Detect key interrupt signal. - #1 + 0x07 + display list reader active cycles + 0x07 - - - - KRM5 - Key interrupt mode control 5 - 5 - 5 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x08 + framebuffer read hits + 0x08 - 1 - Detect key interrupt signal. - #1 + 0x09 + framebuffer read misses + 0x09 - - - - KRM4 - Key interrupt mode control 4 - 4 - 4 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x0A + framebuffer write hits + 0x0A - 1 - Detect key interrupt signal. - #1 + 0x0B + framebuffer write misses + 0x0B - - - - KRM3 - Key interrupt mode control 3 - 3 - 3 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x0C + texture read hits + 0x0C - 1 - Detect key interrupt signal. - #1 + 0x0D + texture read misses + 0x0D - - - - KRM2 - Key interrupt mode control 2 - 2 - 2 - read-write - - 0 - Does not detect key interrupt signal - #0 + 0x1F + every clock cycle (for use as timer) + 0x1F - 1 - Detect key interrupt signal. - #1 + others + Setting prohibited + true + + + + 2 + 0x4 + 1,2 + PERFCOUNT%s + Performance Counter %s + 0xCC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PERFCOUNT + Counter value.The counter is reset by writing PERFCOUNT = 0000 0000H. + 0 + 31 + read-write + + + + + + + R_DTC + Data Transfer Controller + 0x40005400 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x04 + registers + + + 0x0000000C + 0x01 + registers + + + 0x0000000E + 0x02 + registers + + + + DTCCR + DTC Control Register + 0x00 + 8 + read-write + 0x08 + 0xFF + - KRM1 - Key interrupt mode control 1 - 1 - 1 + RRS + DTC Transfer Information Read Skip Enable. + 4 + 4 read-write 0 - Does not detect key interrupt signal + Do not skip transfer information read #0 1 - Detect key interrupt signal. + Skip transfer information read when vector numbers match #1 + + + + DTCVBR + DTC Vector Base Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - KRM0 - Key interrupt mode control 0 + DTCVBR + DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0. + 0 + 31 + read-write + + + + + DTCST + DTC Module Start Register + 0x0C + 8 + read-write + 0x00 + 0xFF + + + DTCST + DTC Module Start 0 0 read-write 0 - Does not detect key interrupt signal + DTC module stop #0 1 - Detect key interrupt signal. + DTC module start #1 - - - - R_MMF - Memory Mirror Function - 0x40001000 - - 0x00000000 - 0x008 - registers - - - MMSFR - MemMirror Special Function Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF + DTCSTS + DTC Status Register + 0x0E + 16 + read-only + 0x0000 + 0xFFFF - KEY - MMSFR Key Code - 24 - 31 - write-only + ACT + DTC Active Flag + 15 + 15 + read-only - 0xDB - Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB. - 0xDB + 0 + DTC transfer operation is not in progress. + #0 - others - Writing to the MEMMIRADDR bits are invalid. - true + 1 + DTC transfer operation is in progress. + #1 - MEMMIRADDR - Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0. - 7 - 22 - read-write + VECN + DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1) + 0 + 7 + read-only - MMEN - MemMirror Enable Register - 0x04 - 32 + DTCCR_SEC + DTC Control Register for secure Region + 0x10 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x08 + 0xff - KEY - MMEN Key Code - 24 - 31 - write-only + RRSS + DTC Transfer Information Read Skip Enable for Secure + 4 + 4 + read-write - 0xDB - Writing to the EN bit is valid, when the KEY bits are written 0xDB. - 0xDB - - - others - Writing to the EN bit is invalid. - true + 0 + Transfer information read is not skipped. + #0 - - - - EN - Memory Mirror Function Enable - 0 - 0 - read-write - 1 - Memory Mirror Function is enabled. + Transfer information read is skipped when vector numbers match. #1 - - 0 - Memory Mirror Function is disabled. - #0 - - - - - R_MPU_MMPU - Bus Master MPU - 0x40000000 - - 0x00000000 - 0x02 - registers - - - 0x00000102 - 0x02 - registers - - - 0x00000200 - 0x02 - registers - - - 0x00000204 - 0x008 - registers - - - 0x00000210 - 0x02 - registers - - - 0x00000214 - 0x008 - registers - - - 0x00000220 - 0x02 - registers - - - 0x00000224 - 0x008 - registers - - - 0x00000230 - 0x02 - registers - - - 0x00000234 - 0x008 - registers - - - 0x00000240 - 0x02 - registers - - - 0x00000244 - 0x008 - registers - - - 0x00000250 - 0x02 - registers - - - 0x00000254 - 0x008 - registers - - - 0x00000260 - 0x02 - registers - - - 0x00000264 - 0x008 - registers - - - 0x00000270 - 0x02 - registers - - - 0x00000274 - 0x008 - registers - - - 0x00000280 - 0x02 - registers - - - 0x00000284 - 0x008 - registers - - - 0x00000290 - 0x02 - registers - - - 0x00000294 - 0x008 - registers - - - 0x000002A0 - 0x02 - registers - - - 0x000002A4 - 0x008 - registers - - - 0x000002B0 - 0x02 - registers - - - 0x000002B4 - 0x008 - registers - - - 0x000002C0 - 0x02 - registers - - - 0x000002C4 - 0x008 - registers - - - 0x000002D0 - 0x02 - registers - - - 0x000002D4 - 0x008 - registers - - - 0x000002E0 - 0x02 - registers - - - 0x000002E4 - 0x008 - registers - - - 0x000002F0 - 0x02 - registers - - - 0x000002F4 - 0x008 - registers - - - 0x00000300 - 0x02 - registers - - - 0x00000304 - 0x008 - registers - - - 0x00000310 - 0x02 - registers - - - 0x00000314 - 0x008 - registers - - - 0x00000320 - 0x02 - registers - - - 0x00000324 - 0x008 - registers - - - 0x00000330 - 0x02 - registers - - - 0x00000334 - 0x008 - registers - - - 0x00000340 - 0x02 - registers - - - 0x00000344 - 0x008 - registers - - - 0x00000350 - 0x02 - registers - - - 0x00000354 - 0x008 - registers - - - 0x00000360 - 0x02 - registers - - - 0x00000364 - 0x008 - registers - - - 0x00000370 - 0x02 - registers - - - 0x00000374 - 0x008 - registers - - - 0x00000380 - 0x02 - registers - - - 0x00000384 - 0x008 - registers - - - 0x00000390 - 0x02 - registers - - - 0x00000394 - 0x008 - registers - - - 0x000003A0 - 0x02 - registers - - - 0x000003A4 - 0x008 - registers - - - 0x000003B0 - 0x02 - registers - - - 0x000003B4 - 0x008 - registers - - - 0x000003C0 - 0x02 - registers - - - 0x000003C4 - 0x008 - registers - - - 0x000003D0 - 0x02 - registers - - - 0x000003D4 - 0x008 - registers - - - 0x000003E0 - 0x02 - registers - - - 0x000003E4 - 0x008 - registers - - - 0x000003F0 - 0x02 - registers - - - 0x000003F4 - 0x008 - registers - - - 0x00000400 - 0x02 - registers - - - 0x00000502 - 0x02 - registers - - - 0x00000600 - 0x02 - registers - - - 0x00000604 - 0x008 - registers - - - 0x00000610 - 0x02 - registers - - - 0x00000614 - 0x008 - registers - - - 0x00000620 - 0x02 - registers - - - 0x00000624 - 0x008 - registers - - - 0x00000630 - 0x02 - registers - - - 0x00000634 - 0x008 - registers - - - 0x00000640 - 0x02 - registers - - - 0x00000644 - 0x008 - registers - - - 0x00000650 - 0x02 - registers - - - 0x00000654 - 0x008 - registers - - - 0x00000660 - 0x02 - registers - - - 0x00000664 - 0x008 - registers - - - 0x00000670 - 0x02 - registers - + + DTCVBR_SEC + DTC Vector Base Register for secure Region + 0x14 + 32 + read-write + 0x00000000 + 0xffffffff + + + DTEVR + DTC Error Vector Register + 0x20 + 32 + read-write + 0x00000000 + 0xffffffff + + + DTEV + DTC Error Vector Number + 0 + 7 + read-only + + + DTEVSAM + DTC Error Vector Number SA Monitor + 8 + 8 + read-only + + + 0 + Secure vector number + #0 + + + 1 + Non-Secure vector number + #1 + + + + + DTESTA + DTC Error Status Flag + 16 + 16 + read-write + + + 0 + No DTC transfer error occurred + #0 + + + 1 + DTC transfer error occurred + #1 + + + + + + + + + R_ELC + Event Link Controller + 0x40041000 - 0x00000674 - 0x008 + 0x00000000 + 0x01 registers - 0x00000680 - 0x02 + 0x00000002 + 0x01 registers - 0x00000684 - 0x008 + 0x00000004 + 0x01 registers - 0x00000690 + 0x00000010 0x02 registers - 0x00000694 - 0x008 - registers - - - 0x000006A0 + 0x00000014 0x02 registers - 0x000006A4 - 0x008 - registers - - - 0x000006B0 + 0x00000018 0x02 registers - 0x000006B4 - 0x008 - registers - - - 0x000006C0 + 0x0000001C 0x02 registers - 0x000006C4 - 0x008 - registers - - - 0x000006D0 + 0x00000020 0x02 registers - 0x000006D4 - 0x008 - registers - - - 0x000006E0 + 0x00000024 0x02 registers - 0x000006E4 - 0x008 - registers - - - 0x000006F0 + 0x00000028 0x02 registers - 0x000006F4 - 0x008 - registers - - - 0x00000700 + 0x0000002C 0x02 registers - 0x00000704 - 0x008 - registers - - - 0x00000710 + 0x00000030 0x02 registers - 0x00000714 - 0x008 - registers - - - 0x00000720 + 0x00000034 0x02 registers - 0x00000724 - 0x008 - registers - - - 0x00000730 + 0x00000038 0x02 registers - 0x00000734 - 0x008 - registers - - - 0x00000740 + 0x0000003C 0x02 registers - 0x00000744 - 0x008 - registers - - - 0x00000750 + 0x00000040 0x02 registers - 0x00000754 - 0x008 - registers - - - 0x00000760 + 0x00000044 0x02 registers - 0x00000764 - 0x008 - registers - - - 0x00000770 + 0x00000048 0x02 registers - 0x00000774 - 0x008 - registers - - - 0x00000780 + 0x0000004C 0x02 registers - 0x00000784 - 0x008 - registers - - - 0x00000790 + 0x00000050 0x02 registers - 0x00000794 - 0x008 - registers - - - 0x000007A0 + 0x00000054 0x02 registers - 0x000007A4 - 0x008 - registers - - - 0x000007B0 + 0x00000058 0x02 registers - 0x000007B4 - 0x008 - registers - - - 0x000007C0 + 0x0000005C 0x02 registers - 0x000007C4 - 0x008 - registers - - - 0x000007D0 + 0x00000060 0x02 registers - 0x000007D4 - 0x008 - registers - - - 0x000007E0 + 0x00000064 0x02 registers - 0x000007E4 - 0x008 - registers - - - 0x000007F0 + 0x00000068 0x02 registers + + + 2 + 0x2 + ELSEGR[%s] + Event Link Software Event Generation Register + 0x02 + + BY + Event Link Software Event Generation Register + 0x00 + 8 + read-write + 0x80 + 0xFF + + + WI + ELSEGR Register Write Disable + 7 + 7 + write-only + + + 0 + Write to ELSEGR register is enabled. + #0 + + + 1 + Write to ELSEGR register is disabled. + #1 + + + + + WE + SEG Bit Write Enable + 6 + 6 + read-write + + + 0 + Write to SEG bit is disabled. + #0 + + + 1 + Write to SEG bit is enabled. + #1 + + + + + SEG + Software Event Generation + 0 + 0 + write-only + + + 0 + Normal operation + #0 + + + 1 + Software event is generated. + #1 + + + + + + + + 23 + 0x4 + + + GPTA + GPTA + 0 + + + GPTB + GPTB + 1 + + + GPTC + GPTC + 2 + + + GPTD + GPTD + 3 + + + GPTE + GPTE + 4 + + + GPTF + GPTF + 5 + + + GPTG + GPTG + 6 + + + GPTH + GPTH + 7 + + + ADCA0 + ADCA0 + 8 + + + ADCB0 + ADCB0 + 9 + + + ADCA1 + ADCA1 + 10 + + + ADCB1 + ADCB1 + 11 + + + DA0 + DA0 + 12 + + + DA1 + DA1 + 13 + + + PORT1 + PORT1 + 14 + + + PORT2 + PORT2 + 15 + + + PORT3 + PORT3 + 16 + + + PORT4 + PORT4 + 17 + + + CTSU + CTSU + 18 + + + DA80 + DA80 + 19 + + + DA81 + DA81 + 20 + + + DA82 + DA82 + 21 + + + SDADC0 + SDADC0 + 22 + + + ELSR[%s] + Event Link Setting Register %s + 0x10 + + HA + Event Link Setting Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + ELS + Event Link Select + 0 + 8 + read-write + + + 0x000 + Event output to the corresponding peripheral module is disabled. + 0x000 + + + others + Set the number for the event signal to be linked. + true + + + + + + + + ELCR + Event Link Controller Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + ELCON + All Event Link Enable + 7 + 7 + read-write + + + 0 + ELC function is disabled. + #0 + + + 1 + ELC function is enabled. + #1 + + + + + + + ELCSARA + Event Link Controller Security Attribution Register A + 0x74 + 16 + read-write + 0xFFFF + 0xFFFF + + + ELSEGR0 + Event Link Software Event Generation Register 0 Security Attribution + 0 + 0 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSEGR1 + Event Link Software Event Generation Register 1Security Attribution + 1 + 1 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELCR + Event Link Controller RegisterSecurity Attribution + 2 + 2 + read-write + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + Reserved + These bits are read as 1111111111111. The write value should be 1111111111111. + 3 + 15 + read-write + + + + + ELCSARB + Event Link Controller Security Attribution Register B + 0x78 + 16 + read-write + 0xFFFF + 0xFFFF + + + ELSR0 + Event Link Setting Register 0Security Attribution + 0 + 0 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR1 + Event Link Setting Register 1Security Attribution + 1 + 1 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR2 + Event Link Setting Register 2Security Attribution + 2 + 2 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR3 + Event Link Setting Register 3Security Attribution + 3 + 3 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR4 + Event Link Setting Register 4Security Attribution + 4 + 4 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR5 + Event Link Setting Register 5Security Attribution + 5 + 5 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR6 + Event Link Setting Register 6Security Attribution + 6 + 6 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR7 + Event Link Setting Register 7Security Attribution + 7 + 7 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR8 + Event Link Setting Register 8Security Attribution + 8 + 8 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR9 + Event Link Setting Register 9Security Attribution + 9 + 9 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR10 + Event Link Setting Register 10Security Attribution + 10 + 10 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR11 + Event Link Setting Register 11Security Attribution + 11 + 11 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR12 + Event Link Setting Register 12Security Attribution + 12 + 12 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR13 + Event Link Setting Register 13Security Attribution + 13 + 13 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR14 + Event Link Setting Register 14Security Attribution + 14 + 14 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR15 + Event Link Setting Register 15Security Attribution + 15 + 15 + read-write + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + + + ELCSARC + Event Link Controller Security Attribution Register C + 0x7C + 16 + read-write + 0xFFFF + 0xFFFF + + + ELSR16 + Event Link Setting Register 16Security Attribution + 0 + 0 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR17 + Event Link Setting Register 17Security Attribution + 1 + 1 + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + ELSR18 + Event Link Setting Register 18Security Attribution + 2 + 2 + read-write + + + 0 + Secure + #0 + + + 1 + NonSecure + #1 + + + + + Reserved + These bits are read as 1111111111111. The write value should be 1111111111111. + 3 + 15 + read-write + + + + + + + R_ETHERC0 + Ethernet MAC Controller + 0x40064100 - 0x000007F4 - 0x008 + 0x00000000 + 0x04 registers - 0x00000800 - 0x02 + 0x00000008 + 0x04 registers - 0x00000902 - 0x02 + 0x00000010 + 0x04 registers - 0x00000A00 - 0x02 + 0x00000018 + 0x04 registers - 0x00000A04 - 0x008 + 0x00000020 + 0x04 registers - 0x00000A10 - 0x02 + 0x00000028 + 0x04 registers - 0x00000A14 - 0x008 + 0x00000040 + 0x04 registers - 0x00000A20 - 0x02 + 0x00000050 + 0x00C registers - 0x00000A24 - 0x008 + 0x00000060 + 0x010 registers - 0x00000A30 - 0x02 + 0x000000C0 + 0x04 registers - 0x00000A34 - 0x008 + 0x000000C8 + 0x04 registers - 0x00000A40 - 0x02 + 0x000000D0 + 0x010 registers - 0x00000A44 - 0x008 + 0x000000E4 + 0x018 registers + + + ECMR + ETHERC Mode Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TPC + PAUSE Frame Transmit + 20 + 20 + read-write + + + 0 + PAUSE frame is transmitted even during a PAUSE period. + #0 + + + 1 + PAUSE frame is not transmitted during a PAUSE period. + #1 + + + + + ZPF + 0 Time PAUSE Frame Enable + 19 + 19 + read-write + + + 0 + PAUSE frame that contains the pause_time parameter of 0 is not used. + #0 + + + 1 + PAUSE frame that contains the pause_time parameter of 0 is used. + #1 + + + + + PFR + PAUSE Frame Receive Mode + 18 + 18 + read-write + + + 0 + PAUSE frame is not transferred to the EDMAC. + #0 + + + 1 + PAUSE frame is transferred to the EDMAC. + #1 + + + + + RXF + Receive Flow Control Operating Mode + 17 + 17 + read-write + + + 0 + PAUSE frame detection is disabled. + #0 + + + 1 + PAUSE frame detection is enabled. + #1 + + + + + TXF + Transmit Flow Control Operating Mode + 16 + 16 + read-write + + + 0 + Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.) + #0 + + + 1 + Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.) + #1 + + + + + PRCEF + CRC Error Frame Receive Mode + 12 + 12 + read-write + + + 0 + EDMAC is notified of a CRC error. + #0 + + + 1 + EDMAC is not notified of a CRC error. + #1 + + + + + MPDE + Magic Packet Detection Enable + 9 + 9 + read-write + + + 0 + Magic Packet detection is disabled. + #0 + + + 1 + Magic Packet detection is enabled. + #1 + + + + + RE + Reception Enable + 6 + 6 + read-write + + + 0 + Receive function is disabled. + #0 + + + 1 + Receive function is enabled. + #1 + + + + + TE + Transmission Enable + 5 + 5 + read-write + + + 0 + Transmit function is disabled. + #0 + + + 1 + Transmit function is enabled. + #1 + + + + + ILB + Internal Loopback Mode + 3 + 3 + read-write + + + 0 + Normal data transmission or reception is performed. + #0 + + + 1 + Data is looped back in the ETHERC when full-duplex mode is selected. + #1 + + + + + RTM + Bit Rate + 2 + 2 + read-write + + + 0 + 10 Mbps + #0 + + + 1 + 100 Mbps + #1 + + + + + DM + Duplex Mode + 1 + 1 + read-write + + + 0 + Half-duplex mode + #0 + + + 1 + Full-duplex mode + #1 + + + + + PRM + Promiscuous Mode + 0 + 0 + read-write + + + 0 + Promiscuous mode is disabled. + #0 + + + 1 + Promiscuous mode is enabled. + #1 + + + + + + + RFLR + Receive Frame Maximum Length Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RFL + Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes. + 0 + 11 + read-write + + + + + ECSR + ETHERC Status Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BFR + Continuous Broadcast Frame Reception Flag + 5 + 5 + read-write + oneToClear + modify + + + 0 + Continuous reception of broadcast frames has not been detected. + #0 + + + 1 + Continuous reception of broadcast frames has been detected. + #1 + + + + + PSRTO + PAUSE Frame Retransmit Over Flag + 4 + 4 + read-write + oneToClear + modify + + + 0 + PAUSE frame retransmit count has not reached the upper limit. + #0 + + + 1 + PAUSE frame retransmit count has reached the upper limit. + #1 + + + + + LCHNG + LCHNG Link Signal Change Flag + 2 + 2 + read-write + oneToClear + modify + + + 0 + Change in the ETn_LINKSTA signal has not been detected. + #0 + + + 1 + Change in the ETn_LINKSTA signal has been detected (high to low, or low to high). + #1 + + + + + MPD + Magic Packet Detect Flag + 1 + 1 + read-write + oneToClear + modify + + + 0 + Magic Packet has not been detected. + #0 + + + 1 + Magic Packet has been detected. + #1 + + + + + ICD + False Carrier Detect Flag + 0 + 0 + read-write + oneToClear + modify + + + 0 + PHY-LSI has not detected a false carrier on the line. + #0 + + + 1 + PHY-LSI has detected a false carrier on the line. + #1 + + + + + + + ECSIPR + ETHERC Interrupt Enable Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BFSIPR + Continuous Broadcast Frame Reception Interrupt Enable + 5 + 5 + read-write + + + 0 + Notification of continuous broadcast frame reception interrupt is disabled. + #0 + + + 1 + Notification of continuous broadcast frame reception interrupt is enabled. + #1 + + + + + PSRTOIP + PAUSE Frame Retransmit Over Interrupt Enable + 4 + 4 + read-write + + + 0 + Notification of PAUSE frame retransmit over interrupt is disabled. + #0 + + + 1 + Notification of PAUSE frame retransmit over interrupt is enabled. + #1 + + + + + LCHNGIP + LINK Signal Change Interrupt Enable + 2 + 2 + read-write + + + 0 + Notification of ETn_LINKSTA signal change interrupt is disabled. + #0 + + + 1 + Notification of ETn_LINKSTA signal change interrupt is enabled. + #1 + + + + + MPDIP + Magic Packet Detect Interrupt Enable + 1 + 1 + read-write + + + 0 + Notification of the Magic Packet detect interrupt is disabled. + #0 + + + 1 + Notification of the Magic Packet detect interrupt is enabled. + #1 + + + + + ICDIP + False Carrier Detect Interrupt Enable + 0 + 0 + read-write + + + 0 + Notification of the false carrier detect interrupt is disabled. + #0 + + + 1 + Notification of the false carrier detect interrupt is enabled. + #1 + + + + + + + PIR + PHY Interface Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFF7 + + + MDI + MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0. + 3 + 3 + read-only + + + MDO + MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read). + 2 + 2 + read-write + + + MMD + MII/RMII Management Mode + 1 + 1 + read-write + + + 0 + Read + #0 + + + 1 + Write + #1 + + + + + MDC + MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII. + 0 + 0 + read-write + + + + + PSR + PHY Status Register + 0x28 + 32 + read-only + 0x00000000 + 0xFFFFFFFE + + + LMON + ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI. + 0 + 0 + read-only + + + + + RDMLR + Random Number Generation Counter Upper Limit Setting Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RMD + Random Number Generation Counter + 0 + 19 + read-write + + + 00000h + Normal operation + 0x00000 + + + others + Setting prohibited + true + + + + + + + IPGR + IPG Register + 0x50 + 32 + read-write + 0x00000014 + 0xFFFFFFFF + + + IPG + Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)" + 0 + 4 + read-write + + + 14h + 96 bit time (initial value) + 0x14 + + + others + (IPGx4+16) bit time + true + + + + + + + APR + Automatic PAUSE Frame Register + 0x54 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AP + Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. + 0 + 15 + read-write + + + + + MPR + Manual PAUSE Frame Register + 0x58 + 32 + write-only + 0x00000000 + 0xFFFF0000 + + + MP + Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined. + 0 + 15 + write-only + + + + + RFCF + Received PAUSE Frame Counter + 0x60 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RPAUSE + Received PAUSE Frame CountNumber of received PAUSE frames + 0 + 7 + read-only + + + + + TPAUSER + PAUSE Frame Retransmit Count Setting Register + 0x64 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TPAUSE + Automatic PAUSE Frame Retransmit Setting + 0 + 15 + read-write + + + 0x0000 + Number of retransmissions is unlimited + 0x0000 + + + others + Maximum number of retransmissions is (TPAUSE) + true + + + + + + + TPAUSECR + PAUSE Frame Retransmit Counter + 0x68 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + + BCFRR + Broadcast Frame Receive Count Setting Register + 0x6C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCF + Broadcast Frame Continuous Receive Count Setting + 0 + 15 + read-write + + + 0000h + Number of receptions is unlimited. + 0x0000 + + + others + Receive (BFC) frame. + true + + + + + + + MAHR + MAC Address Upper Bit Register + 0xC0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MAHR + MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address. + 0 + 31 + read-write + + + + + MALR + MAC Address Lower Bit Register + 0xC8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MALR + MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address. + 0 + 15 + read-write + + + + + TROCR + Transmit Retry Over Counter Register + 0xD0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TROCR + Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted. + 0 + 31 + read-write + clear + + + + + CDCR + Late Collision Detect Counter Register + 0xD4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + LCCR + Lost Carrier Counter Register + 0xD8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCCR + Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission. + 0 + 31 + read-write + clear + + + + + CNDCR + Carrier Not Detect Counter Register + 0xDC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CNDCR + Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission. + 0 + 31 + read-write + clear + + + + + CEFCR + CRC Error Frame Receive Counter Register + 0xE4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CEFCR + CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected. + 0 + 31 + read-write + clear + + + + + FRECR + Frame Receive Error Counter Register + 0xE8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRECR + Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred. + 0 + 31 + read-write + clear + + + + + TSFRCR + Too-Short Frame Receive Counter Register + 0xEC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TSFRCR + Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received. + 0 + 31 + read-write + clear + + + + + TLFRCR + Too-Long Frame Receive Counter Register + 0xF0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TLFRCR + Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received. + 0 + 31 + read-write + clear + + + + + RFCR + Received Alignment Error Frame Counter Register + 0xF4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RFCR + Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets). + 0 + 31 + read-write + clear + + + + + MAFCR + Multicast Address Frame Receive Counter Register + 0xF8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MAFCR + Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received. + 0 + 31 + read-write + clear + + + + + + + R_ETHERC_EDMAC + Ethernet DMA Controller + 0x40064000 - 0x00000A50 - 0x02 + 0x00000000 + 0x04 registers - 0x00000A54 - 0x008 + 0x00000008 + 0x04 registers - 0x00000A60 - 0x02 + 0x00000010 + 0x04 registers - 0x00000A64 - 0x008 + 0x00000018 + 0x04 registers - 0x00000A70 - 0x02 + 0x00000020 + 0x04 registers - 0x00000A74 - 0x008 + 0x00000028 + 0x04 registers - 0x00000A80 - 0x02 + 0x00000030 + 0x04 registers - 0x00000A84 - 0x008 + 0x00000038 + 0x04 registers - 0x00000A90 - 0x02 + 0x00000040 + 0x04 registers - 0x00000A94 - 0x008 + 0x00000048 + 0x04 registers - 0x00000AA0 - 0x02 + 0x00000050 + 0x04 registers - 0x00000AA4 - 0x008 + 0x00000058 + 0x04 registers - 0x00000AB0 - 0x02 + 0x00000064 + 0x010 registers - 0x00000AB4 + 0x00000078 0x008 registers - 0x00000AC0 - 0x02 - registers - - - 0x00000AC4 + 0x000000C8 0x008 registers - 0x00000AD0 - 0x02 - registers - - - 0x00000AD4 + 0x000000D4 0x008 registers + + + EDMR + EDMAC Mode Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DE + Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers. + 6 + 6 + read-write + + + 0 + Big endian mode + #0 + + + 1 + Little endian mode + #1 + + + + + DL + Transmit/Receive DescriptorLength + 4 + 5 + read-write + + + 00 + 16 bytes + #00 + + + 01 + 32 bytes + #01 + + + 10 + 64 bytes + #10 + + + 11 + 16 bytes + #11 + + + + + SWR + Software Reset + 0 + 0 + write-only + + + 0 + no effect. + #0 + + + 1 + the corresponding channels of the EDMAC and ETHERC are reset. Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset. + #1 + + + + + + + EDTRR + EDMAC Transmit Request Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TR + Transmit Request + 0 + 0 + write-only + + + 0 + no effect. + #0 + + + 1 + When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted. + #1 + + + + + + + EDRRR + EDMAC Receive Request Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RR + Receive Request + 0 + 0 + read-write + + + 0 + Receive function is disabled. + #0 + + + 1 + Receive descriptor is read, and the receive function is enabled. + #1 + + + + + + + TDLAR + Transmit Descriptor List Start Address Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDLAR + The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b + 0 + 31 + read-write + + + + + RDLAR + Receive Descriptor List Start Address Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RDLAR + The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b + 0 + 31 + read-write + + + + + EESR + ETHERC/EDMAC Status Register + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TWB + Write-Back Complete Flag + 30 + 30 + read-write + oneToClear + modify + + + 0 + Write-back has not been completed, or no transmission has been requested. + #0 + + + 1 + Write-back to the transmit descriptor has been completed. + #1 + + + + + TABT + Transmit Abort Detect Flag + 26 + 26 + read-write + oneToClear + modify + + + 0 + Frame transmission has not been aborted or no transmission has been requested. + #0 + + + 1 + Frame transmission has been aborted. + #1 + + + + + RABT + Receive Abort Detect Flag + 25 + 25 + read-write + oneToClear + modify + + + 0 + Frame reception has not been aborted or no reception has been requested. + #0 + + + 1 + Frame reception has been aborted. + #1 + + + + + RFCOF + Receive Frame Counter Overflow Flag + 24 + 24 + read-write + oneToClear + modify + + + 0 + Receive frame counter has not overflowed. + #0 + + + 1 + Receive frame counter has overflowed. + #1 + + + + + ADE + Address Error Flag + 23 + 23 + read-write + oneToClear + modify + + + 0 + Invalid memory address has not been detected (normal operation). + #0 + + + 1 + Invalid memory address has been detected. + #1 + + + + + ECI + ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared. + 22 + 22 + read-only + + + 0 + ETHERC status interrupt source has not been detected. + #0 + + + 1 + ETHERC status interrupt source has been detected. + #1 + + + + + TC + Frame Transfer Complete Flag + 21 + 21 + read-write + oneToClear + modify + + + 0 + Transfer have not been completed, or no transfer has been requested. + #0 + + + 1 + All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO. + #1 + + + + + TDE + Transmit Descriptor Empty Flag + 20 + 20 + read-write + oneToClear + modify + + + 0 + The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1. + #0 + + + 1 + The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0. + #1 + + + + + TFUF + Transmit FIFO Underflow Flag + 19 + 19 + read-write + oneToClear + modify + + + 0 + Underflow has not occurred. + #0 + + + 1 + Underflow has occurred. + #1 + + + + + FR + Frame Receive Flag + 18 + 18 + read-write + oneToClear + modify + + + 0 + Frame has not been received. + #0 + + + 1 + Frame has been received. Update of the receive descriptor is complete. + #1 + + + + + RDE + Receive Descriptor Empty Flag + 17 + 17 + read-write + oneToClear + modify + + + 0 + The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1. + #0 + + + 1 + The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0. + #1 + + + + + RFOF + Receive FIFO Overflow Flag + 16 + 16 + read-write + oneToClear + modify + + + 0 + Overflow has not occurred. + #0 + + + 1 + Overflow has occurred. + #1 + + + + + CND + Carrier Not Detect Flag + 11 + 11 + read-write + oneToClear + modify + + + 0 + A carrier has been detected when transmission starts. + #0 + + + 1 + A carrier has not been detected during preamble transmission. + #1 + + + + + DLC + Loss of Carrier Detect Flag + 10 + 10 + read-write + oneToClear + modify + + + 0 + Loss of carrier has not been detected. + #0 + + + 1 + Loss of carrier has been detected during frame transmission. + #1 + + + + + CD + Late Collision Detect Flag + 9 + 9 + read-write + oneToClear + modify + + + 0 + Late collision has not been detected. + #0 + + + 1 + Late collision has been detected during frame transmission. + #1 + + + + + TRO + Transmit Retry Over Flag + 8 + 8 + read-write + oneToClear + modify + + + 0 + Transmit retry-over condition has not been detected. + #0 + + + 1 + Transmit retry-over condition has been detected. + #1 + + + + + RMAF + Multicast Address Frame Receive Flag + 7 + 7 + read-write + oneToClear + modify + + + 0 + Multicast address frame has not been received. + #0 + + + 1 + Multicast address frame has been received. + #1 + + + + + RRF + Alignment Error Flag + 4 + 4 + read-write + oneToClear + modify + + + 0 + Alignment error has not been detected. + #0 + + + 1 + Alignment error has been detected. + #1 + + + + + RTLF + Frame-Too-Long Error Flag + 3 + 3 + read-write + oneToClear + modify + + + 0 + Frame-too-long error has not been detected. + #0 + + + 1 + Frame-too-long error has been detected. + #1 + + + + + RTSF + Frame-Too-Short Error Flag + 2 + 2 + read-write + oneToClear + modify + + + 0 + Frame-too-short error has not been detected. + #0 + + + 1 + Frame-too-short error has been detected. + #1 + + + + + PRE + PHY-LSI Receive Error Flag + 1 + 1 + read-write + oneToClear + modify + + + 0 + PHY-LSI receive error has not been detected. + #0 + + + 1 + PHY-LSI receive error has been detected. + #1 + + + + + CERF + CRC Error Flag + 0 + 0 + read-write + oneToClear + modify + + + 0 + CRC error has not been detected. + #0 + + + 1 + CRC error has been detected. + #1 + + + + + + + EESIPR + ETHERC/EDMAC Status Interrupt Enable Register + 0x30 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TWBIP + Write-Back Complete Interrupt Request Enable + 30 + 30 + read-write + + + 0 + Write-back complete interrupt request is disabled. + #0 + + + 1 + Write-back complete interrupt request is enabled. + #1 + + + + + TABTIP + Transmit Abort Detect Interrupt Request Enable + 26 + 26 + read-write + + + 0 + Transmit abort detect interrupt request is disabled. + #0 + + + 1 + Transmit abort detect interrupt request is enabled. + #1 + + + + + RABTIP + Receive Abort Detect Interrupt Request Enable + 25 + 25 + read-write + + + 0 + Receive abort detect interrupt request is disabled. + #0 + + + 1 + Receive abort detect interrupt request is enabled. + #1 + + + + + RFCOFIP + Receive Frame Counter Overflow Interrupt Request Enable + 24 + 24 + read-write + + + 0 + Receive frame counter overflow interrupt request is disabled. + #0 + + + 1 + Receive frame counter overflow interrupt request is enabled. + #1 + + + + + ADEIP + Address Error Interrupt Request Enable + 23 + 23 + read-write + + + 0 + Address error interrupt request is disabled. + #0 + + + 1 + Address error interrupt request is enabled. + #1 + + + + + ECIIP + ETHERC Status Register Source Interrupt Request Enable + 22 + 22 + read-write + + + 0 + ETHERC status interrupt request is disabled. + #0 + + + 1 + ETHERC status interrupt request is enabled. + #1 + + + + + TCIP + Frame Transfer Complete Interrupt Request Enable + 21 + 21 + read-write + + + 0 + Frame transmission complete interrupt request is disabled. + #0 + + + 1 + Frame transmission complete interrupt request is enabled. + #1 + + + + + TDEIP + Transmit Descriptor Empty Interrupt Request Enable + 20 + 20 + read-write + + + 0 + Transmit descriptor empty interrupt request is disabled. + #0 + + + 1 + Transmit descriptor empty interrupt request is enabled. + #1 + + + + + TFUFIP + Transmit FIFO Underflow Interrupt Request Enable + 19 + 19 + read-write + + + 0 + Underflow interrupt request is disabled. + #0 + + + 1 + Underflow interrupt request is enabled. + #1 + + + + + FRIP + Frame Receive Interrupt Request Enable + 18 + 18 + read-write + + + 0 + Frame reception interrupt request is disabled. + #0 + + + 1 + Frame reception interrupt request is enabled. + #1 + + + + + RDEIP + Receive Descriptor Empty Interrupt Request Enable + 17 + 17 + read-write + + + 0 + Receive descriptor empty interrupt request is disabled. + #0 + + + 1 + Receive descriptor empty interrupt request is enabled. + #1 + + + + + RFOFIP + Receive FIFO Overflow Interrupt Request Enable + 16 + 16 + read-write + + + 0 + Overflow interrupt request is disabled. + #0 + + + 1 + Overflow interrupt request is enabled. + #1 + + + + + CNDIP + Carrier Not Detect Interrupt Request Enable + 11 + 11 + read-write + + + 0 + Carrier not detect interrupt request is disabled. + #0 + + + 1 + Carrier not detect interrupt request is enabled. + #1 + + + + + DLCIP + Loss of Carrier Detect Interrupt Request Enable + 10 + 10 + read-write + + + 0 + Loss of carrier detect interrupt request is disabled. + #0 + + + 1 + Loss of carrier detect interrupt request is enabled. + #1 + + + + + CDIP + Late Collision Detect Interrupt Request Enable + 9 + 9 + read-write + + + 0 + Late collision detect interrupt request is disabled. + #0 + + + 1 + Late collision detect interrupt request is enabled. + #1 + + + + + TROIP + Transmit Retry Over Interrupt Request Enable + 8 + 8 + read-write + + + 0 + Transmit retry over interrupt request is disabled. + #0 + + + 1 + Transmit retry over interrupt request is enabled. + #1 + + + + + RMAFIP + Multicast Address Frame Receive Interrupt Request Enable + 7 + 7 + read-write + + + 0 + Multicast address frame receive interrupt request is disabled. + #0 + + + 1 + Multicast address frame receive interrupt request is enabled. + #1 + + + + + RRFIP + Alignment Error Interrupt Request Enable + 4 + 4 + read-write + + + 0 + Alignment error interrupt request is disabled. + #0 + + + 1 + Alignment error interrupt request is enabled. + #1 + + + + + RTLFIP + Frame-Too-Long Error Interrupt Request Enable + 3 + 3 + read-write + + + 0 + Frame-too-long error interrupt request is disabled. + #0 + + + 1 + Frame-too-long error interrupt request is enabled. + #1 + + + + + RTSFIP + Frame-Too-Short Error Interrupt Request Enable + 2 + 2 + read-write + + + 0 + Frame-too-short error interrupt request is disabled. + #0 + + + 1 + Frame-too-short error interrupt request is enabled. + #1 + + + + + PREIP + PHY-LSI Receive Error Interrupt Request Enable + 1 + 1 + read-write + + + 0 + PHY-LSI receive error interrupt request is disabled. + #0 + + + 1 + PHY-LSI receive error interrupt request is enabled. + #1 + + + + + CERFIP + CRC Error Interrupt Request Enable + 0 + 0 + read-write + + + 0 + CRC error interrupt request is disabled. + #0 + + + 1 + CRC error interrupt request is enabled. + #1 + + + + + + + TRSCER + ETHERC/EDMAC Transmit/Receive Status Copy Enable Register + 0x38 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RMAFCE + RMAF Flag Copy Enable + 7 + 7 + read-write + + + 0 + The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor. + #0 + + + 1 + The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor. + #1 + + + + + RRFCE + RRF Flag Copy Enable + 4 + 4 + read-write + + + 0 + The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor. + #0 + + + 1 + The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor. + #1 + + + + + + + RMFCR + Missed-Frame Counter Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MFC + Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception. + 0 + 15 + read-write + clear + + + + + TFTR + Transmit FIFO Threshold Register + 0x48 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TFT + Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4. Example: 00Dh: 52 bytes 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes + 0 + 10 + read-write + + + 0x000 + 0x200 + + + + + 0x000 + Store and forward mode + 0x000 + + + others + The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited) + true + + + + + + + FDR + Transmit FIFO Threshold Register + 0x50 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TFD + Receive FIFO Depth + 8 + 12 + read-write + + + 01111 + 4096 bytes + #01111 + + + others + Settings other than above are prohibited. + true + + + + + RFD + Transmit FIFO Depth + 0 + 4 + read-write + + + 00111 + 2048 bytes + #00111 + + + others + Settings other than above are prohibited. + true + + + + + + + RMCR + Receive Method Control Register + 0x58 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RNR + Receive Request Reset + 0 + 0 + read-write + + + 0 + EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received. + #0 + + + 1 + EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received. + #1 + + + + + + + TFUCR + Transmit FIFO Underflow Counter + 0x64 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + UNDER + Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh. + 0 + 15 + read-write + + + + + RFOCR + Receive FIFO Overflow Counter + 0x68 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + OVER + Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh. + 0 + 15 + read-write + + + + + IOSR + Independent Output Signal Setting Register + 0x6C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ELB + External Loopback Mode + 0 + 0 + read-write + + + 0 + The ETn_EXOUT pin outputs low. + #0 + + + 1 + The ETn_EXOUT pin outputs high. + #1 + + + + + + + FCFTR + Flow Control Start FIFO Threshold Setting Register + 0x70 + 32 + read-write + 0x00070007 + 0xFFFFFFFF + + + RFFO + Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.) + 16 + 18 + read-write + + + 000 + When 2 receive frames have been stored in the receive FIFO. + #000 + + + 001 + When 4 receive frames have been stored in the receive FIFO. + #001 + + + 010 + When 6 receive frames have been stored in the receive FIFO. + #010 + + + 011 + When 8 receive frames have been stored in the receive FIFO. + #011 + + + 100 + When 10 receive frames have been stored in the receive FIFO. + #100 + + + 101 + When 12 receive frames have been stored in the receive FIFO. + #101 + + + 110 + When 14 receive frames have been stored in the receive FIFO. + #110 + + + 111 + When 16 receive frames have been stored in the receive FIFO. + #111 + + + + + RFDO + Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.) + 0 + 2 + read-write + + + 000 + When 224 ( 256 - 32) bytes of data is stored in the receive FIFO. + #000 + + + 001 + When 480 ( 512 - 32) bytes of data is stored in the receive FIFO. + #001 + + + 010 + When 736 ( 768 - 32) bytes of data is stored in the receive FIFO. + #010 + + + 011 + When 992 (1024 - 32) bytes of data is stored in the receive FIFO. + #011 + + + 100 + When 1248 (1280 - 32) bytes of data is stored in the receive FIFO. + #100 + + + 101 + When 1504 (1536 - 32) bytes of data is stored in the receive FIFO. + #101 + + + 110 + When 1760 (1792 - 32) bytes of data is stored in the receive FIFO. + #110 + + + 111 + When 2016 (2048 - 32) bytes of data is stored in the receive FIFO. + #111 + + + + + + + RPADIR + Receive Data Padding Insert Register + 0x78 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PADS + Padding Size + 16 + 17 + read-write + + + 00 + No padding is inserted. + #00 + + + 01 + 1 byte is inserted. + #01 + + + 10 + 2 bytes are inserted. + #10 + + + 11 + 3 bytes are inserted. + #11 + + + + + PADR + Padding Slot + 0 + 5 + read-write + + + 00h + Padding is inserted at the head of received data. + 0x00 + + + others + Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data. + true + + + + + + + TRIMD + Transmit Interrupt Setting Register + 0x07C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TIM + Transmit Interrupt Mode + 4 + 4 + read-write + + + 0 + Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted. + #0 + + + 1 + Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed. + #1 + + + + + TIS + Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt. + 0 + 0 + read-write + + + 0 + Transmit Interrupt is disabled. + #0 + + + 1 + Transmit Interrupt is enabled. + #1 + + + + + + + RBWAR + Receive Buffer Write Address Register + 0xC8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RBWAR + Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception. + 0 + 31 + read-only + + + + + RDFAR + Receive Descriptor Fetch Address Register + 0xCC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RDFAR + Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception. + 0 + 31 + read-only + + + + + TBRAR + Transmit Buffer Read Address Register + 0x0D4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TBRAR + Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register. + 0 + 31 + read-only + + + + + TDFAR + Transmit Descriptor Fetch Address Register + 0xD8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + TDFAR + Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register. + 0 + 31 + read-only + + + + + + + R_ETHERC_EPTPC + Ethernet PTP Controller + 0x40065800 - 0x00000AE0 - 0x02 - registers - - - 0x00000AE4 + 0x00000000 0x008 registers - 0x00000AF0 - 0x02 + 0x00000010 + 0x010 registers - 0x00000AF4 + 0x00000040 0x008 registers - 0x00000B00 - 0x02 + 0x00000050 + 0x01C registers - 0x00000B04 - 0x008 + 0x00000080 + 0x04 registers - 0x00000B10 - 0x02 + 0x00000090 + 0x00C registers - 0x00000B14 - 0x008 + 0x000000A0 + 0x00C registers - 0x00000B20 - 0x02 + 0x000000C0 + 0x018 registers - 0x00000B24 - 0x008 + 0x000000E0 + 0x018 registers - 0x00000B30 - 0x02 + 0x00000100 + 0x014 registers - 0x00000B34 - 0x008 + 0x00000120 + 0x024 registers - 0x00000B40 - 0x02 + 0x00000160 + 0x018 registers - 0x00000B44 - 0x008 + 0x000001C0 + 0x018 registers + + + 2 + 0x8 + F[%s] + Frame Reception Filter Setting Registers + 0x160 + + 2 + 0x8 + 0-1 + MACRU + Frame Reception Filter MAC Address Setting Registers + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FMACRU + These bits hold the setting for the higher-order 24 bits of the destination MAC address for received multicast frames. + 0 + 23 + read-write + + + + + 2 + 0x8 + 0-1 + MACRL + Frame Reception Filter MAC Address Setting Registers + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FMACRL + These bits hold the setting for the lower-order 24 bits of the destination MAC address for received multicast frames. + 0 + 23 + read-write + + + + + + SYSR + SYNFP Status Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GENDN + Generation Stop Completion Detection Flag + 17 + 17 + read-write + oneToClear + modify + + + 0 + Stopping generation has not been completed. + #0 + + + 1 + Stopping generation has been completed. + #1 + + + + + RESDN + Response Stop Completion Detection Flag + 16 + 16 + read-write + oneToClear + modify + + + 0 + Stopping responses has not been completed. + #0 + + + 1 + Stopping responses has been completed. + #1 + + + + + INFABT + Control Information Abnormality Detection Flag + 14 + 14 + read-write + oneToClear + modify + + + 0 + No abnormality in control information + #0 + + + 1 + Abnormality in control information + #1 + + + + + RECLP + Loop Reception Detection Flag + 12 + 12 + read-write + oneToClear + modify + + + 0 + A received message has not returned through a loop. + #0 + + + 1 + A received message has returned through a loop. + #1 + + + + + DRQOVR + Delay_Req Reception FIFO Overflow Detection Flag + 6 + 6 + read-write + oneToClear + modify + + + 0 + The received Delay_Req has not caused the reception FIFO to overflow. + #0 + + + 1 + The received Delay_Req has caused the reception FIFO to overflow. + #1 + + + + + INTDEV + Receive logMessageInterval Value Out-of-Range Flag + 5 + 5 + read-write + oneToClear + modify + + + 0 + The received logMessageInterval value is within the range. + #0 + + + 1 + The received logMessageInterval value is out of the range. + #1 + + + + + DRPTO + Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag + 4 + 4 + read-write + oneToClear + modify + + + 0 + A Delay_Resp/Pdelay_Resp timeout has not occurred. + #0 + + + 1 + A Delay_Resp/Pdelay_Resp timeout has occurred. + #1 + + + + + MPDUD + meanPathDelay Value Update Flag + 2 + 2 + read-write + oneToClear + modify + + + 0 + The meanPathDelay value has not been updated. + #0 + + + 1 + The meanPathDelay value has been updated. + #1 + + + + + INTCHG + Receive logMessageInterval Value Change Detection Flag + 1 + 1 + read-write + oneToClear + modify + + + 0 + No change in the received logMessageInterval value. + #0 + + + 1 + A change in the received logMessageInterval value. + #1 + + + + + OFMUD + offsetFromMaster Value Update Flag + 0 + 0 + read-write + oneToClear + modify + + + 0 + The offsetFromMaster value has not been updated. + #0 + + + 1 + The offsetFromMaster value has been updated. + #1 + + + + + + + SYIPR + SYNFP Status Notification Permission Register + 0x004 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GENDN + SYSR.GENDN Status Notification Permission + 17 + 17 + read-write + + + 0 + Prohibits notification of the state of SYSR.GENDN. + #0 + + + 1 + Permits notification of the state of SYSR.GENDN. + #1 + + + + + RESDN + SYSR.RESDN Status Notification Permission + 16 + 16 + read-write + + + 0 + Prohibits notification of the state of SYSR.RESDN. + #0 + + + 1 + Permits notification of the state of SYSR.RESDN. + #1 + + + + + INFABT + SYSR.INFABT Status Notification Permission + 14 + 14 + read-write + + + 0 + Prohibits notification of the state of SYSR.INFABT. + #0 + + + 1 + Permits notification of the state of SYSR.INFABT. + #1 + + + + + RECLP + SYSR.RECLP Status Notification Permission + 12 + 12 + read-write + + + 0 + Prohibits notification of the state of SYSR.RECLP. + #0 + + + 1 + Permits notification of the state of SYSR.RECLP. + #1 + + + + + DRQOVR + SYSR.DRQOVR Status Notification Permission + 6 + 6 + read-write + + + 0 + Prohibits notification of the state of SYSR.DRQOVR. + #0 + + + 1 + Permits notification of the state of SYSR.DRQOVR. + #1 + + + + + INTDEV + SYSR.INTDEV Status Notification Permission + 5 + 5 + read-write + + + 0 + Prohibits notification of the state of SYSR.INTDEV. + #0 + + + 1 + Permits notification of the state of SYSR.INTDEV. + #1 + + + + + DRPTO + SYSR.DRPTO Status Notification Permission + 4 + 4 + read-write + + + 0 + Prohibits notification of the state of SYSR.DRPTO. + #0 + + + 1 + Permits notification of the state of SYSR.DRPTO. + #1 + + + + + MPDUD + SYSR.MPDUD Status Notification Permission + 2 + 2 + read-write + + + 0 + Prohibits notification of the state of SYSR.MPDUD. + #0 + + + 1 + Permits notification of the state of SYSR.MPDUD. + #1 + + + + + INTCHG + SYSR.INTCHG Status Notification Permission + 1 + 1 + read-write + + + 0 + Prohibits notification of the state of SYSR.INTCHG. + #0 + + + 1 + Permits notification of the state of SYSR.INTCHG. + #1 + + + + + OFMUD + SYSR.OFMUD Status Notification Permission + 0 + 0 + read-write + + + 0 + Prohibits notification of the state of SYSR.OFMUD. + #0 + + + 1 + Permits notification of the state of SYSR.OFMUD. + #1 + + + + + + + SYMACRU + SYNFP MAC Address Registers + 0x010 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYMACRU + These bits hold the setting for the higher-order 24 bits of the local MAC address. + 0 + 23 + read-write + + + + + SYMACRL + SYNFP MAC Address Registers + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYMACRL + These bits hold the setting for the lower-order 24 bits of the local MAC address. + 0 + 23 + read-write + + + + + SYLLCCTLR + SYNFP LLC-CTL Value Register + 0x018 + 32 + read-write + 0x00000003 + 0xFFFFFFFF + + + CTL + LLC-CTL FieldThese bits specify the value used for the control field in the LLC sublayer when generating IEEE802.3 frames. + 0 + 7 + read-write + + + + + SYIPADDRR + SYNFP Local IP Address Register + 0x01C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYIPADDRR + These bits hold the setting for the local IP address. + 0 + 31 + read-write + + + + + SYSPVRR + SYNFP Specification Version Setting Register + 0x040 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + TRSP + transportSpecific Field ValueThese bits are used to set the transportSpecific field value of the PTP v2 header.When a message is received, this value is compared with the transportSpecific field of the received frame.In generating messages, the value is used for the transportSpecific field of the frame for transmission.Set these bits to 0000b (IEEE 1588). + 4 + 7 + read-write + + + VER + versionPTP Field ValueThese bits are used to set the versionPTP field value of the PTP v2 header.When a message is received, this value is compared with the versionPTP field of the received frame.In generating messages, the value is used for the versionPTP field of the frame for transmission.Set these bits to 0010b (PTP v2). + 0 + 3 + read-write + + + + + SYDOMR + SYNFP Domain Number Setting Register + 0x044 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DNUM + domainNumber Field Value SettingThese bits are used to set the domainNumber field value of the PTP v2 header.When a message is received, this value is compared with the domainNumber field of the received frame as a condition for PTP reception processing.In generating messages, the value is used for the domainNumber field of the frame for transmission. + 0 + 7 + read-write + + + + + ANFR + Announce Message Flag Field Setting Register + 0x050 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRUE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRUE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRUE. + #1 + + + + + FLAG8 + alternateMasterFlag + 8 + 8 + read-write + + + 0 + alternateMasterFlag is set to FALSE. + #0 + + + 1 + alternateMasterFlag is set to TRUE. + #1 + + + + + FLAG5 + frequencyTraceableThis bit is used to set the logical value of the frequencyTraceable member of timePropertiesDS. + 5 + 5 + read-write + + + 0 + frequencyTraceable is set to FALSE. + #0 + + + 1 + frequencyTraceable is set to TRUE. + #1 + + + + + FLAG4 + timeTraceableThis bit is used to set the logical value of the timeTraceable member of timePropertiesDS. + 4 + 4 + read-write + + + 0 + timeTraceable is set to FALSE. + #0 + + + 1 + timeTraceable is set to TRUE. + #1 + + + + + FLAG3 + ptpTimescaleThis bit is used to set the logical value of the ptpTimescale member of timePropertiesDS. + 3 + 3 + read-write + + + 0 + ptpTimescale is set to FALSE. + #0 + + + 1 + ptpTimescale is set to TRUE. + #1 + + + + + FLAG2 + currentUtcOffsetValidThis bit is used to set the logical value of the currentUtcOffsetValid member of timePropertiesDS. + 2 + 2 + read-write + + + 0 + currentUtcOffsetValid is set to FALSE. + #0 + + + 1 + currentUtcOffsetValid is set to TRUE. + #1 + + + + + FLAG1 + leap59This bit is used to set the logical value of the leap59 member of timePropertiesDS. + 1 + 1 + read-write + + + 0 + leap59 is set to FALSE. + #0 + + + 1 + leap59 is set to TRUE. + #1 + + + + + FLAG0 + leap61This bit is used to set the logical value of the leap61 member of timePropertiesDS. + 0 + 0 + read-write + + + 0 + leap61 is set to FALSE. + #0 + + + 1 + leap61 is set to TRUE. + #1 + + + + + + + SYNFR + Sync Message Flag Field Setting Register + 0x054 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRUE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRUE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRUE. + #1 + + + + + FLAG9 + twoStepFlag + 9 + 9 + read-write + + + 0 + Set this bit to 0 (FALSE). + #0 + + + 1 + Setting prohibited + #1 + + + + + FLAG8 + alternateMasterFlag + 8 + 8 + read-write + + + 0 + alternateMasterFlag is set to FALSE. + #0 + + + 1 + alternateMasterFlag is set to TRUE. + #1 + + + + + + + DYRQFR + Delay_Req Message Flag Field Setting Register + 0x058 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRULE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRULE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRULE. + #1 + + + + + + + DYRPFR + Delay_Resp Message Flag Field Setting Register + 0x05C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FLAG14 + PTP profile Specific 2 + 14 + 14 + read-write + + + 0 + PTP profile Specific 2 is set to FALSE. + #0 + + + 1 + PTP profile Specific 2 is set to TRUE. + #1 + + + + + FLAG13 + PTP profile Specific 1 + 13 + 13 + read-write + + + 0 + PTP profile Specific 1 is set to FALSE. + #0 + + + 1 + PTP profile Specific 1 is set to TRUE. + #1 + + + + + FLAG10 + unicastFlag + 10 + 10 + read-write + + + 0 + unicastFlag is set to FALSE. + #0 + + + 1 + unicastFlag is set to TRUE. + #1 + + + + + FLAG9 + woStepFlag + 9 + 9 + read-write + + + 0 + Set this bit to 0 (FALSE). + #0 + + + 1 + Setting prohibited + #1 + + + + + FLAG8 + alternateMasterFlag + 8 + 8 + read-write + + + 0 + alternateMasterFlag is set to FALSE. + #0 + + + 1 + alternateMasterFlag is set to TRUE. + #1 + + + + + + + SYCIDRU + SYNFP Local Clock ID Registers + 0x060 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYCIDRU + These bits hold the setting for the higher-order 32 bits of the clock-ID of your port. + 0 + 31 + read-write + + + + + SYCIDRL + SYNFP Local Clock ID Registers + 0x064 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYCIDRL + These bits hold the setting for the lower-order 32 bits of the clock-ID of your port. + 0 + 31 + read-write + + + + + SYPNUMR + SYNFP Local Port Number Register + 0x068 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PNUM + Local Port Number SettingThese bits hold the setting for the port number of the local port. + 0 + 15 + read-write + + + + + SYRVLDR + SYNFP Register Value Load Directive Register + 0x080 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + ANUP + Announce Message Generation Information Update + 2 + 2 + write-only + + + 0 + no effect + #0 + + + 1 + Setting this bit to 1 leads to simultaneous reflection in the Announce message generation block of the values of the registers required for the generation of Announce messages. + #1 + + + + + STUP + State Update + 1 + 1 + write-only + + + 0 + no effect + #0 + + + 1 + Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers related to the reception and transmission of PTP messages. + #1 + + + + + BMUP + BMC Update + 0 + 0 + write-only + + + 0 + no effect + #0 + + + 1 + Setting this bit to 1 leads to simultaneous reflection in the SYNFP module of the values of the registers holding the MasterClock identifying information. + #1 + + + + + + + SYRFL1R + SYNFP Reception Filter Register 1 + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PDFUP2 + Pdelay_Resp_Follow_Up Message Processing + 30 + 30 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP does not process messages. + #1 + + + + + PDFUP1 + Pdelay_Resp_Follow_Up Message Processing + 29 + 29 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + PDFUP0 + Pdelay_Resp_Follow_Up Message Processing + 28 + 28 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + PDRP2 + Pdelay_Resp Message Processing + 26 + 26 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + PDRP1 + Pdelay_Resp Message Processing + 25 + 25 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + PDRP0 + Pdelay_Resp Message Processing + 24 + 24 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + PDRQ2 + Pdelay_Req Message Processing + 22 + 22 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + PDRQ1 + Pdelay_Req Message Processing + 21 + 21 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + PDRQ0 + Pdelay_Req Message Processing + 20 + 20 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + DRP2 + Delay_Resp Message Processing + 18 + 18 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + DRP1 + Delay_Resp Message Processing + 17 + 17 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + DRP0 + Delay_Resp Message Processing + 16 + 16 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + DRQ2 + Delay_Req Message Processing + 14 + 14 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + DRQ1 + Delay_Req Message Processing + 13 + 13 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + DRQ0 + Delay_Req Message Processing + 12 + 12 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + FUP2 + Follow_Up Message Processing + 10 + 10 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + FUP1 + Follow_Up Message Processing + 9 + 9 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + FUP0 + Follow_Up Message Processing + 8 + 8 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + SYNC2 + Sync Message Processing + 6 + 6 + read-write + + + 0 + The SYNFP does not process messages. + #0 + + + 1 + The SYNFP processes messages. + #1 + + + + + SYNC1 + Sync Message Processing + 5 + 5 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + SYNC0 + Sync Message Processing + 4 + 4 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + ANCE1 + Announce Message Processing + 1 + 1 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + ANCE0 + Announce Message Processing + 0 + 0 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + + + SYRFL2R + SYNFP Reception Filter Register 2 + 0x094 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ILL1 + Illegal Message Processing Setting + 29 + 29 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + ILL0 + Illegal Message Processing Setting + 28 + 28 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + SIG1 + Signaling Message Processing Setting + 5 + 5 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + SIG0 + Signaling Message Processing Setting + 4 + 4 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + MAN1 + Management Message Processing Setting + 1 + 1 + read-write + + + 0 + The PRC-TC does not relay messages between ports 0 and 1. + #0 + + + 1 + The PRC-TC relays messages between ports 0 and 1. + #1 + + + + + MAN0 + Management Message Processing Setting + 0 + 0 + read-write + + + 0 + Messages are not transferred to the PTPEDMAC. + #0 + + + 1 + Messages are transferred to the PTPEDMAC. + #1 + + + + + + + SYTRENR + SYNFP Transmission Enable Register + 0x098 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PDRQ + Pdelay_Req Message Transmission Enable + 12 + 12 + read-write + + + 0 + Pdelay_Req messages are not transmitted. + #0 + + + 1 + Pdelay_Req messages are transmitted. + #1 + + + + + DRQ + Delay_Req Message Transmission Enable + 8 + 8 + read-write + + + 0 + Delay_Req messages are not transmitted. + #0 + + + 1 + Delay_Req messages are transmitted. + #1 + + + + + SYNC + Sync Message Transmission Enable + 4 + 4 + read-write + + + 0 + Sync messages are not transmitted. + #0 + + + 1 + Sync messages are transmitted. + #1 + + + + + ANCE + Announce Message Transmission Enable + 0 + 0 + read-write + + + 0 + Announce messages are not transmitted. + #0 + + + 1 + Announce messages are transmitted. + #1 + + + + + + + MTCIDU + Master Clock ID Registers + 0x0A0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MTCIDU + These bits hold the setting for the higher-order 32 bits of the clock-ID of the master clock. + 0 + 31 + read-write + + + + + MTCIDL + Master Clock ID Registers + 0x0A4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MTCIDL + These bits hold the setting for the lower-order 32 bits of the clock-ID of the master clock. + 0 + 31 + read-write + + + + + MTPID + Master clock port number register + 0x0A8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PNUM + Master Clock Port Number SettingThese bits hold the setting for the port number of the master clock. + 0 + 15 + read-write + + + + + SYTLIR + SYNFP Transmission Interval Setting Register + 0x0C0 + 32 + read-write + 0x00000001 + 0xFFFFFFFF + + + DREQ + Delay_Req Transmission Interval Average Value/ Pdelay_Req Transmission Interval SettingThe bits set the average interval for the transmission of Delay_Req messages and the interval for the transmission of Pdelay_Req messages.The setting is also placed in the logMessageInterval field of Delay_Resp messages. + 16 + 23 + read-write + + + SYNC + Sync Message Transmission Interval SettingThese bits set the interval for the transmission of Sync messages. The setting is also placed in the logMessageInterval field of transmitted Sync messages. + 8 + 15 + read-write + + + ANCE + Announce Message Transmission Interval SettingThese bits set the interval for the transmission of Announce messages. + 0 + 7 + read-write + + + + + SYRLIR + SYNFP Received logMessageInterval Value Indication Register + 0x0C4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + DRESP + Delay_Resp Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Delay_Resp message. + 16 + 23 + read-only + + + SYNC + Sync Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Sync message. + 8 + 15 + read-only + + + ANCE + Announce Message logMessageInterval Field IndicationThese bits indicate the logMessageInterval field value of a received Announce message. + 0 + 7 + read-only + + + + + OFMRU + offsetFromMaster Value Registers + 0x0C8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + OFMRU + These bits indicate the higher-order 32 bits of the calculated offsetFromMaster value. + 0 + 31 + read-only + + + + + OFMRL + offsetFromMaster Value Registers + 0x0CC + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + OFMRL + These bits indicate the lower-order 32 bits of the calculated offsetFromMaster value. + 0 + 31 + read-only + + + + + MPDRU + meanPathDelay Value Registers + 0x0D0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MPDRU + These bits indicate the higher-order 32 bits of the calculated meanPathDelay value. + 0 + 31 + read-only + + + + + MPDRL + meanPathDelay Value Registers + 0x0D4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MPDRL + These bits indicate the lower-order 32 bits of the calculated meanPathDelay value. + 0 + 31 + read-only + + + + + GMPR + grandmasterPriority Field Setting Register + 0x0E0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMPR1 + grandmasterPriority1 Field Value SettingThese bits are used to set the value of the grandmasterPriority1 fields of Announce messages. + 16 + 23 + read-write + + + GMPR2 + grandmasterPriority2 Field Value SettingThese bits are used to set the value of the grandmasterPriority2 fields of Announce messages. + 0 + 7 + read-write + + + + + GMCQR + grandmasterClockQuality Field Setting Register + 0x0E4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMCQR + These bits are used to set the value of the grandmasterClockQuality fields of Announce messages. The correspondence between bits and the grandmasterClockQuality fields is as listed below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 to b0: offsetScaledLogVariance + 0 + 31 + read-write + + + + + GMIDRU + grandmasterIdentity Field Setting Registers + 0x0E8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMIDRU + These bits hold the setting for the higher-order 32 bits of the value of the grandmasterIdentity fields of Announce messages. + 0 + 31 + read-write + + + + + GMIDRL + grandmasterIdentity Field Setting Registers + 0x0EC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GMIDRL + These bits hold the setting for the lower-order 32 bits of the value of the grandmasterIdentity fields of Announce messages. + 0 + 31 + read-write + + + + + CUOTSR + currentUtcOffset/timeSource Field Setting Register + 0x0F0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CUTO + currentUtcOffset Field SettingThese bits set the value of the currentUtcOffset fields of Announce messages. + 16 + 31 + read-write + + + TSRC + timeSource Field SettingThese bits set the value of the timeSource fields of Announce messages. + 0 + 7 + read-write + + + + + SRR + stepsRemoved Field Setting Register + 0x0F4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SRMV + stepsRemoved Field Value SettingThese bits set the value of the stepsRemoved fields of Announce messages. + 0 + 15 + read-write + + + + + PPMACRU + PTP-primary Message Destination MAC Address Setting Registers + 0x100 + 32 + read-write + 0x00011B19 + 0xFFFFFFFF + + + PPMACRU + These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-primary messages. + 0 + 23 + read-write + + + + + PPMACRL + PTP-primary Message Destination MAC Address Setting Registers + 0x104 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PPMACRL + These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-primary messages. + 0 + 23 + read-write + + + + + PDMACRU + PTP-pdelay Message MAC Address Setting Registers + 0x108 + 32 + read-write + 0x000180C2 + 0xFFFFFFFF + + + PDMACRU + These bits hold the setting for the higher-order 24 bits of the destination MAC address for PTP-pdelay messages. + 0 + 23 + read-write + + + + + PDMACRL + PTP-pdelay Message MAC Address Setting Registers + 0x10C + 32 + read-write + 0x0000000E + 0xFFFFFFFF + + + PDMACRL + These bits hold the setting for the lower-order 24 bits of the destination MAC address for PTP-pdelay messages. + 0 + 23 + read-write + + + + + PETYPER + PTP Message EtherType Setting Register + 0x110 + 32 + read-write + 0x000088F7 + 0xFFFFFFFF + + + TYPE + PTP Message EtherType Value SettingThese bits hold the setting for the EtherType field value for frames in the Ethernet II format. + 0 + 15 + read-write + + + + + PPIPR + PTP-primary Message Destination IP Address Setting Register + 0x120 + 32 + read-write + 0xE0000181 + 0xFFFFFFFF + + + PPIPR + These bits hold the setting for the destination IP address for PTPprimary messages. + 0 + 31 + read-write + + + + + PDIPR + PTP-pdelay Message Destination IP Address Setting Register + 0x124 + 32 + read-write + 0xE000006B + 0xFFFFFFFF + + + PDIPR + These bits hold the setting for the destination IP address for PTPpdelay messages. + 0 + 31 + read-write + + + + + PETOSR + PTP Event Message TOS Setting Register + 0x128 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EVTO + PTP Event Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP event messages. + 0 + 7 + read-write + + + + + PGTOSR + PTP general Message TOS Setting Register + 0x12C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GETO + PTP general Message TOS Field Value SettingThese bits hold the setting for the value of the TOS field within the IPv4 headers of PTP general messages. + 0 + 7 + read-write + + + + + PPTTLR + PTP-primary Message TTL Setting Register + 0x130 + 32 + read-write + 0x00000080 + 0xFFFFFFFF + + + PRTL + PTP-primary Message TTL Field Value SettingThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-primary messages. + 0 + 7 + read-write + + + + + PDTTLR + PTP-pdelay Message TTL Setting Register + 0x134 + 32 + read-write + 0x00000001 + 0xFFFFFFFF + + + PDTL + PTP-pdelay Message TTL Field ValueThese bits hold the setting for the value of the TTL field within the IPv4 headers of PTP-pdelay messages. + 0 + 7 + read-write + + + + + PEUDPR + PTP Event Message UDP Destination Port Number Setting Register + 0x138 + 32 + read-write + 0x0000013F + 0xFFFFFFFF + + + EVUPT + PTP Event Message Destination Port Number SettingThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP event messages. + 0 + 15 + read-write + + + + + PGUDPR + PTP general Message UDP Destination Port Number Setting Register + 0x13C + 32 + read-write + 0x00000140 + 0xFFFFFFFF + + + GEUPT + PTP general Message Destination Port NumberThese bits hold the setting for the value of the destination port number field within the UDP headers of PTP general messages. + 0 + 15 + read-write + + + + + FFLTR + Frame Reception Filter Setting Register + 0x140 + 32 + read-write + 0x00010000 + 0xFFFFFFFF + + + EXTPRM + Extended Promiscuous ModeSetting + 16 + 16 + read-write + + + 0 + Normal operation (unicast frames addressed to the EPTPC are received, filtering of PTP frames is applied, multicast filtering is applied, and all broadcast frames are received). + #0 + + + 1 + Extended promiscuous mode (all frames are received) + #1 + + + + + ENB + Reception Filter EnableNOTE: The setting of these bits is only effective when EXTPRM=0. + 2 + 2 + read-write + + + 0 + Filtering is disabled (all multicast frames are received). + #0 + + + 1 + See PRT and SEL bit. + #1 + + + + + PRT + Frame Reception EnableNOTE: The setting of these bits is only effective when EXTPRM=0 and ENB=1. + 1 + 1 + read-write + + + 0 + Do not receive multicast frames. + #0 + + + 1 + See SEL bit. + #1 + + + + + SEL + Receive MAC Address SelectNOTE: The setting of these bits is only effective when EXTPRM=0, ENB=1and RPT=1. + 0 + 0 + read-write + + + 0 + Only receive multicast frames matching the MAC address setting in FMAC0R(U/L). + #0 + + + 1 + Only receive multicast frames matching the MAC address setting in FMAC1R(U/L). + #1 + + + + + + + DASYMRU + Asymmetric Delay Setting Registers + 0x1C0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DASYMRU + These bits hold the setting for the higher-order 16 bits of the asymmetric delay value. + 0 + 15 + read-write + + + + + DASYMRL + Asymmetric Delay Setting Registers + 0x1C4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DASYMRL + These bits hold the setting for the lower-order 32 bits of the asymmetric delay value. + 0 + 31 + read-write + + + + + TSLATR + Timestamp Latency Setting Register + 0x1C8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + INGP + Output Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the output ports. + 16 + 31 + read-write + + + EGP + Input Port Timestamp Latency SettingThese bits hold the setting for the time stamp latency (ns) for the input ports. + 0 + 15 + read-write + + + + + SYCONFR + SYNFP Operation Setting Register + 0x1CC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TCMOD + TC Mode Setting + 20 + 20 + read-write + + + 0 + E2E TC + #0 + + + 1 + P2P TC + #1 + + + + + FILDIS + Receive Message domainNumber Filter Disable + 16 + 16 + read-write + + + 0 + Filtering conditions for the reception of PTP messages include comparison with the domainNumber field. + #0 + + + 1 + Filtering conditions for the reception of PTP messages do not include comparison with the domainNumber field. + #1 + + + + + SBDIS + Sync Message Transmission Bandwidth Securing Disable + 12 + 12 + read-write + + + 0 + Securing of the bandwidth for the transmission of SYNC messages is enabled (transfer by the EDMAC is given lower priority). + #0 + + + 1 + Securing of the bandwidth for the transmission of SYNC messages is disabled (transfer by the EDMAC is given higher priority). + #1 + + + + + TCYC + PTP Message Transmission Interval SettingThese bits are used to set the time from the completion of one transmission to the start of the next in cycles of the transmission clock. A value n in these bits means that a transmission interval of n cycles will be secured.No interval is secured if the setting is 00h.We recommend the setting 28h (40 cycles). + 0 + 7 + read-write + + + + + SYFORMR + SYNFP Frame Format Setting Register + 0x1D0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FORM1 + Ethernet Frame Format Setting + 1 + 1 + read-write + + + 0 + Set this bit to 0 (Ethernet II frame format). + #0 + + + 1 + Setting prohibited + #1 + + + + + FORM0 + Ethernet/UDP Encapsulation + 0 + 0 + read-write + + + 0 + PTP directly over Ethernet + #0 + + + 1 + PTP over UDP/IPv4 + #1 + + + + + + + RSTOUTR + Response Message Reception Timeout Register + 0x1D4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RSTOUTR + Response Message Reception Timeout Time SettingA response message not being received within n x 1024 (ns), where n is the setting, is judged to represent a timeout. + 0 + 31 + read-write + + + + + + + R_ETHERC_EPTPC1 + 0x40065C00 + + + R_ETHERC_EPTPC_CFG + Ethernet PTP Configuration + 0x40064500 - 0x00000B50 - 0x02 + 0x00000000 + 0x00C registers + + + PTRSTR + EPTPC Reset Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESET + EPTPC Software Reset + 0 + 0 + read-write + + + 0 + Do not reset the EPTPC + #0 + + + 1 + Reset the EPTPC. Do not access the EPTPC-related registers other than this register while a software reset is being issued. + #1 + + + + + + + STCSELR + STCA Clock Select Register + 0x04 + 32 + read-write + 0x00000006 + 0xFFFFFFFF + + + SCLKSEL + STCA Clock Select + 8 + 10 + read-write + + + 000 + PCLKA clock divided by 1 to 6 + #000 + + + 010 + Input clock from the REF50CK0 pin + #010 + + + 011 + Input clock from the REF50CK1 pin + #011 + + + others + Settings other than above are prohibited. + true + + + + + SCLKDIV + PCLKA Clock Frequency Division + 0 + 2 + read-write + + + 001 + 1 + #001 + + + 010 + 1/2 + #010 + + + 011 + 1/3 + #011 + + + 100 + 1/4 + #100 + + + 101 + 1/5 + #101 + + + 110 + 1/6 + #110 + + + others + Settings other than above are prohibited. + true + + + + + + + BYPASS + Bypass 1588 module Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BYPASS1 + Bypass 1588 module for Ether 1ch + 16 + 16 + read-write + + + 0 + to use 1588 module for Ether 1ch + #0 + + + 1 + to bypass 1588 module for Ether 1ch + #1 + + + + + BYPASS0 + Bypass 1588 module for Ether 0ch + 0 + 0 + read-write + + + 0 + to use 1588 module for Ether 0ch + #0 + + + 1 + to bypass 1588 module for Ether 0ch + #1 + + + + + + + + + R_ETHERC_EPTPC_COMMON + Ethernet PTP Controller Common + 0x40065000 - 0x00000B54 + 0x00000000 0x008 registers - 0x00000B60 - 0x02 - registers - - - 0x00000B64 + 0x00000010 0x008 registers - 0x00000B70 - 0x02 - registers - - - 0x00000B74 + 0x00000040 0x008 registers - 0x00000B80 - 0x02 - registers - - - 0x00000B84 - 0x008 + 0x00000050 + 0x00C registers - 0x00000B90 - 0x02 + 0x00000060 + 0x010 registers - 0x00000B94 + 0x00000080 0x008 registers - 0x00000BA0 - 0x02 - registers - - - 0x00000BA4 - 0x008 + 0x00000090 + 0x010 registers - 0x00000BB0 - 0x02 + 0x000000B0 + 0x00C registers - 0x00000BB4 - 0x008 + 0x00000124 + 0x020 registers - 0x00000BC0 - 0x02 + 0x00000170 + 0x00C registers - 0x00000BC4 - 0x008 + 0x00000210 + 0x00C registers - 0x00000BD0 - 0x02 + 0x000002D0 + 0x00C registers - 0x00000BD4 - 0x008 + 0x00000300 + 0x060 registers - 0x00000BE0 - 0x02 + 0x0000037C + 0x04 registers - 0x00000BE4 + 0x00000400 0x008 registers - 0x00000BF0 - 0x02 + 0x00000410 + 0x014 registers - 0x00000BF4 + 0x00000430 0x008 registers - 3 - 0x400 - - - A - A - 0 - - - B - B - 1 - - - C - C - 2 - - - MMPU[%s] - Bus Master MPU Registers - 0x0000 + 6 + 0x10 + TM[%s] + Timer Setting Registers + 0x300 - CTL - Bus Master MPU Control Register - 0x000 - 16 + STTRU + Timer Start Time Setting Register + 0x00 + 32 read-write - 0x0000 - 0xFFFF + 0x00000000 + 0xFFFFFFFF - KEY - Write Keyword The data written to these bits are not stored. - 8 - 15 - write-only - - - 0xA5 - Writing to the OAD and ENABLE bit is valid, when the KEY bits are written 0xA5. - 0xA5 - - - others - Writing to the OAD and ENABLE bit is invalid. - true - - + TMSTTRU + These bits hold the setting for the higher-order 32 bits of the start time of the pulse output timer in nanoseconds. + 0 + 31 + read-write + + + + STTRL + Timer Start Time Setting Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - OAD - Operation after detection - 1 - 1 + TMSTTRL + These bits hold the setting for the lower-order 32 bits of the start time of the pulse output timer in nanoseconds. + 0 + 31 + read-write + + + + + CYCR + Timer Cycle Setting Registers + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TMCYCR + These bits set the cycle of the pulse output timer in nanoseconds. Set a value that is equivalent to at least four cycles of the STCA clock. + 0 + 29 read-write - - - 0 - Non-maskable interrupt. - #0 - - - 1 - Internal reset. - #1 - - + + + + PLSR + Timer Pulse Width Setting Register + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - ENABLE - Master Group enable + TMPLSR + These bits set the width at high level of the pulse signal from the timer in nanoseconds. Set a value that is equivalent to at least two cycles of the STCA clock. 0 - 0 + 28 read-write - - - 0 - Master Group is disabled. Permission of all regions. - #0 - - - 1 - Master Group is enabled. Protection of all regions. - #1 - - + + + 2 + 0x8 + PR[%s] + Local MAC Address Registers + 0x410 - PT - Protection of Register - 0x102 - 16 + MACRU + Channel Local MAC Address Register + 0x00 + 32 read-write - 0x0000 - 0xFFFF + 0x00000000 + 0xFFFFFFFF - KEY - Write Keyword The data written to these bits are not stored. - 8 - 15 - write-only - - - 0xA5 - Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. - 0xA5 - - - others - Writing to the PROTECT bit is invalid. - true - - + PRMACRU + These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0. + 0 + 23 + read-write + + + + MACRL + Channel Local MAC Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - PROTECT - Protection of region register + PRMACRL + These bits hold the setting for the higher-order 24 bits of the local MAC address for Ethernet port 0. 0 - 0 + 23 read-write - - - 0 - All Bus Master MPU register writing is possible. - #0 - - - 1 - All Bus Master MPU register writing is protected. Read is possible. - #1 - - - - 32 - 0x10 - REGION[%s] - Address Region registers - 0x0200 - - C - Access Control Register - 0x00 - 16 + + + MIESR + MINT Interrupt Source Status Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CYC5 + Pulse Output Timer 5 Rising Edge Detection Flag + 21 + 21 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 5 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 5 is detected. + #1 + + + + + CYC4 + Pulse Output Timer 4 Rising Edge Detection Flag + 20 + 20 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 4 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 4 is detected. + #1 + + + + + CYC3 + Pulse Output Timer 3 Rising Edge Detection Flag + 19 + 19 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 3 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 3 is detected. + #1 + + + + + CYC2 + Pulse Output Timer 2 Rising Edge Detection Flag + 18 + 18 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 2 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 2 is detected. + #1 + + + + + CYC1 + Pulse Output Timer 1 Rising Edge Detection Flag + 17 + 17 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 1 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 1 is detected. + #1 + + + + + CYC0 + Pulse Output Timer 0 Rising Edge Detection Flag + 16 + 16 + read-write + oneToClear + modify + + + 0 + A rising edge in the periodic pulse signal from pulse output timer 0 is not detected. + #0 + + + 1 + A rising edge in the periodic pulse signal from pulse output timer 0 is detected. + #1 + + + + + PRC + PRC-TC Status Flag + 3 + 3 + read-only + + + 0 + No change in the state of the PRC-TC module + #0 + + + 1 + A change in the state of the PRC-TC module + #1 + + + + + SY1 + SYNFP1 Status Flag + 2 + 2 + read-only + + + 0 + No change in the state of the SYNFP1 module + #0 + + + 1 + A change in the state of the SYNFP1 module + #1 + + + + + SY0 + SYNFP0 Status Flag + 1 + 1 + read-only + + + 0 + No change in the state of the SYNFP0 module + #0 + + + 1 + A change in the state of the SYNFP0 module + #1 + + + + + ST + STCA Status Flag + 0 + 0 + read-only + + + 0 + No change in the state of the STCA module + #0 + + + 1 + A change in the state of the STCA module + #1 + + + + + + + MIEIPR + MINT Interrupt Request Permission Register + 0x004 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CYC5 + Pulse Output Timer 5 Rising Edge Detection Interrupt Request Permission + 21 + 21 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 5. + #1 + + + + + CYC4 + Pulse Output Timer 4 Rising Edge Detection Interrupt Request Permission + 20 + 20 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 4. + #1 + + + + + CYC3 + Pulse Output Timer 3 Rising Edge Detection Interrupt Request Permission + 19 + 19 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 3. + #1 + + + + + CYC2 + Pulse Output Timer 2 Rising Edge Detection Interrupt Request Permission + 18 + 18 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 2. + #1 + + + + + CYC1 + Pulse Output Timer 1 Rising Edge Detection Interrupt Request Permission + 17 + 17 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 1. + #1 + + + + + CYC0 + Pulse Output Timer 0 Rising Edge Detection Interrupt Request Permission + 16 + 16 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0. + #0 + + + 1 + Permits the generation of MINT interrupt requests in response to detection of a rising edge of pulse output timer 0. + #1 + + + + + PRC + PRC-TC Status Interrupt Request Permission + 3 + 3 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the PRC-TC status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the PRCTC status flag. + #1 + + + + + SY1 + SYNFP1 Status Interrupt Request Permission + 2 + 2 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the SYNFP1 status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the SYNFP1 status flag. + #1 + + + + + SY0 + SYNFP0 Status Interrupt Request Permission + 1 + 1 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the SYNFP0 status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the SYNFP0 status flag. + #1 + + + + + ST + STCA Status Interrupt Request Permission + 0 + 0 + read-write + + + 0 + Prohibits the generation of MINT interrupt requests by the STCA status flag. + #0 + + + 1 + Permits the generation of MINT interrupt requests by the STCA status flag. + #1 + + + + + + + ELIPPR + ELC Output/ETHER_IPLS Interrupt Request Permission Register + 0x010 + 32 + read-write + 0x00003F3F + 0xFFFFFFFF + + + PLSN + Pulse Output Timer Falling Edge Detection IPLS Interrupt Request Permission + 24 + 24 + read-write + + + 0 + Prohibits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer. + #0 + + + 1 + Permits IPLS interrupt requests due to falling edges of signals from the selected pulse output timer. + #1 + + + + + PLSP + Pulse Output Timer Rising Edge Detection IPLS Interrupt Request Permission + 16 + 16 + read-write + + + 0 + Prohibits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer. + #0 + + + 1 + Permits IPLS interrupt requests due to rising edges of signals from the selected pulse output timer. + #1 + + + + + CYCN5 + Pulse Output Timer 5 Falling Edge Detection Event Output Enable + 13 + 13 + read-write + + + 0 + Falling edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals. + #1 + + + + + CYCN4 + Pulse Output Timer 4 Falling Edge Detection Event Output Enable + 12 + 12 + read-write + + + 0 + Falling edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals. + #1 + + + + + CYCN3 + Pulse Output Timer 3 Falling Edge Detection Event Output Enable + 11 + 11 + read-write + + + 0 + Falling edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals. + #1 + + + + + CYCN2 + Pulse Output Timer 2 Falling Edge Detection Event Output Enable + 10 + 10 + read-write + + + 0 + Falling edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals. + #1 + + + + + CYCN1 + Pulse Output Timer 1 Falling Edge Detection Event Output Enable + 9 + 9 + read-write + + + 0 + Falling edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals. + #1 + + + + + CYCN0 + Pulse Output Timer 0 Falling Edge Detection Event Output Enable + 8 + 8 + read-write + + + 0 + Falling edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals. + #0 + + + 1 + Falling edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals. + #1 + + + + + CYCP5 + Pulse Output Timer 5 Rising Edge Detection Event Output Enable + 5 + 5 + read-write + + + 0 + Rising edges of the signal from pulse output timer 5 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 5 are conveyed to the ELC as event signals. + #1 + + + + + CYCP4 + Pulse Output Timer 4 Rising Edge Detection Event Output Enable + 4 + 4 + read-write + + + 0 + Rising edges of the signal from pulse output timer 4 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 4 are conveyed to the ELC as event signals. + #1 + + + + + CYCP3 + Pulse Output Timer 3 Rising Edge Detection Event Output Enable + 3 + 3 + read-write + + + 0 + Rising edges of the signal from pulse output timer 3 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 3 are conveyed to the ELC as event signals. + #1 + + + + + CYCP2 + Pulse Output Timer 2 Rising Edge Detection Event Output Enable + 2 + 2 + read-write + + + 0 + Rising edges of the signal from pulse output timer 2 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 2 are conveyed to the ELC as event signals. + #1 + + + + + CYCP1 + Pulse Output Timer 1 Rising Edge Detection Event Output Enable + 1 + 1 + read-write + + + 0 + Rising edges of the signal from pulse output timer 1 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 1 are conveyed to the ELC as event signals. + #1 + + + + + CYCP0 + Pulse Output Timer 0 Rising Edge Detection Event Output Enable + 0 + 0 + read-write + + + 0 + Rising edges of the signal from pulse output timer 0 are not conveyed to the ELC as event signals. + #0 + + + 1 + Rising edges of the signal from pulse output timer 0 are conveyed to the ELC as event signals. + #1 + + + + + + + ELIPACR + ELC Output/IPLS Interrupt Permission Automatic Clearing Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PLSN + ELIPPR.PLSN Bit Automatic Clearing + 24 + 24 + read-write + + + 0 + Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #0 + + + 1 + Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #1 + + + + + PLSP + ELIPPR.PLSP Bit Automatic Clearing + 16 + 16 + read-write + + + 0 + Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #0 + + + 1 + Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. + #1 + + + + + CYCN5 + ELIPPR.CYCN5 Bit Automatic Clearing + 13 + 13 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. + #1 + + + + + CYCN4 + ELIPPR.CYCN4 Bit Automatic Clearing + 12 + 12 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. + #1 + + + + + CYCN3 + ELIPPR.CYCN3 Bit Automatic Clearing + 11 + 11 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. + #1 + + + + + CYCN2 + ELIPPR.CYCN2 Bit Automatic Clearing + 10 + 10 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. + #1 + + + + + CYCN1 + ELIPPR.CYCN1 Bit Automatic Clearing + 9 + 9 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. + #1 + + + + + CYCN0 + ELIPPR.CYCN0 Bit Automatic Clearing + 8 + 8 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. + #1 + + + + + CYCP5 + ELIPPR.CYCP5 Bit Automatic Clearing + 5 + 5 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. + #1 + + + + + CYCP4 + ELIPPR.CYCP4 Bit Automatic Clearing + 4 + 4 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. + #1 + + + + + CYCP3 + ELIPPR.CYCP3 Bit Automatic Clearing + 3 + 3 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. + #1 + + + + + CYCP2 + ELIPPR.CYCP2 Bit Automatic Clearing + 2 + 2 + read-write + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. + #1 + + + + + CYCP1 + ELIPPR.CYCP1 Bit Automatic Clearing + 1 + 1 read-write - 0x0000 - 0xFFFF - - - WP - Write protection - 2 - 2 - read-write - - - 0 - Write permission - #0 - - - 1 - Write protection - #1 - - - - - RP - Read protection - 1 - 1 - read-write - - - 0 - Read permission - #0 - - - 1 - Read protection - #1 - - - - - ENABLE - Region enable - 0 - 0 - read-write - - - 0 - Group m Region n unit is disabled - #0 - - - 1 - Group m Region n unit is enabled - #1 - - - - - - - S - Start Address Register - 0x04 - 32 + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. + #1 + + + + + CYCP0 + ELIPPR.CYCP0 Bit Automatic Clearing + 0 + 0 read-write - 0x00000000 - 0xFFFFFFFF - - - MMPUSmn - Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. - 0 - 31 - read-write - - - - - E - End Address Register - 0x08 - 32 + + + 0 + Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. + #0 + + + 1 + Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. + #1 + + + + + + + STSR + STCA Status Register + 0x040 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + W10D + Worst 10 Acquisition Completion Flag + 4 + 4 read-write - 0x00000003 - 0xFFFFFFFF - - - MMPUEmn - Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. - 0 - 31 - read-write - - - - - - - - - R_MPU_SMPU - Bus Slave MPU - 0x40000C00 - - 0x00000000 - 0x02 - registers - - - 0x00000010 - 0x02 - registers - - - 0x00000014 - 0x02 - registers - - - 0x00000018 - 0x02 - registers - - - 0x0000001C - 0x02 - registers - - - 0x00000020 - 0x02 - registers - - - 0x00000024 - 0x02 - registers - - - 0x00000028 - 0x02 - registers - - - 0x0000002C - 0x02 - registers - - - 0x00000030 - 0x02 - registers - - - 0x00000034 - 0x02 - registers - - - - 10 - 0x4 - - - MBIU - MBIU - 0 - - - FBIU - FBIU - 1 - - - R_SRAM - R_SRAM - 2 - - - SRAM1 - SRAM1 - 3 - - - P0BIU - P0BIU - 4 - - - P2BIU - P2BIU - 5 - - - P6BIU - P6BIU - 6 - - - B7BIU - B7BIU - 7 - - - EXBIU - EXBIU - 8 - - - EXBIU2 - EXBIU2 - 9 - - - SMPU[%s] - Access Control Structure for MBIU - 0x10 - - R - Access Control Register for MBIU - 0x00 - 16 - read-write - 0x2000 - 0xFFFF - - - WPSRAMHS - SRAMHS Write Protection - 15 - 15 - read-write - - - 0 - Memory protection for SRAMHS writes from master group A, B, and C disabled - #0 - - - 1 - Memory protection for SRAMHS writes from master group A, B, and C enabled. - #1 - - - - - RPSRAMHS - SRAMHS Read Protection - 14 - 14 - read-write - - - 0 - Memory protection for SRAMHS reads from master group A, B, and C disabled - #0 - - - 1 - Memory protection for SRAMHS reads from master group A, B, and C enabled. - #1 - - - - - WPFLI - Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.) - 13 - 13 - read-write - - - 0 - Setting prohibited - #0 - - - 1 - Memory protection for code flash memory writes from master group A, B, and C enabled. - #1 - - - - - RPFLI - Code Flash Memory Read Protection - 12 - 12 - read-write - - - 0 - Memory protection for code flash memory reads from master group A, B, and C disabled - #0 - - - 1 - Memory protection for code flash memory reads from master group A, B, and C enabled. - #1 - - - - - WPGRPC - Master Group C Write protection - 7 - 7 - read-write - - - 0 - Memory protection for master group C writes disabled - #0 - - - 1 - Memory protection for master group C writes enabled. - #1 - - - - - RPGRPC - Master Group C Read protection - 6 - 6 - read-write - - - 0 - Memory protection for master group C reads disabled - #0 - - - 1 - Memory protection for master group C reads enabled. - #1 - - - - - WPGRPB - Master Group B Write protection - 5 - 5 - read-write - - - 0 - Memory protection for master group B writes disabled - #0 - - - 1 - Memory protection for master group B writes enabled. - #1 - - - - - RPGRPB - Master Group B Read protection - 4 - 4 - read-write - - - 0 - Memory protection for master group B reads disabled - #0 - - - 1 - Memory protection for master group B reads enabled. - #1 - - - - - WPGRPA - Master Group A Write protection - 3 - 3 - read-write - - - 0 - Memory protection for master group A writes disabled - #0 - - - 1 - Memory protection for master group A writes enabled. - #1 - - - - - RPGRPA - Master Group A Read protection - 2 - 2 - read-write - - - 0 - Memory protection for master group A reads disabled - #0 - - - 1 - Memory protection for master group A reads enabled. - #1 - - - - - - + oneToClear + + + 0 + Ten worst values not acquired yet + #0 + + + 1 + Ten worst values acquired + #1 + + + + + SYNTOUT + Sync Message Reception Timeout Detection Flag + 3 + 3 + read-write + oneToClear + + + 0 + Sync message reception timeout not detected + #0 + + + 1 + Sync message reception timeout detected + #1 + + + + + SYNCOUT + Synchronization Loss Detection Flag + 1 + 1 + read-write + oneToClear + + + 0 + Loss of synchronization not detected + #0 + + + 1 + Loss of synchronization detected + #1 + + + + + SYNC + Synchronized State Detection Flag + 0 + 0 + read-write + oneToClear + + + 0 + Synchronization not detected + #0 + + + 1 + Synchronization detected + #1 + + + + + - SMPUCTL - Slave MPU Control Register - 0x00 - 16 + STIPR + STCA Status Notification Permission Register + 0x044 + 32 read-write - 0x0000 - 0xFFFF + 0x00000000 + 0xFFFFFFFF - KEY - Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. - 8 - 15 - write-only + W10D + W10D Status Notification Enable + 4 + 4 + read-write - 0xA5 - Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5. - 0xA5 + 0 + Disable notification of the STSR.W10D state + #0 - others - Writing to the PROTECT and OAD bit is invalid. - true + 1 + Enable notification of the STSR.W10D state + #1 - PROTECT - Protection of register + SYNTOUT + SYNTOUT Status Notification Enable + 3 + 3 + read-write + + + 0 + Disable notification of the STSR.SYNTOUT state + #0 + + + 1 + Enable notification of the STSR.SYNTOUT state + #1 + + + + + SYNCOUT + SYNCOUT Status Notification Enable 1 1 read-write 0 - All Bus Slave register writing is possible. + Disable notification of the STSR.SYNCOUT state #0 1 - All Bus Slave register writing is protected. Read is possible. + Enable notification of the STSR.SYNCOUT state #1 - OAD - Master Group enable + SYNC + SYNC Status Notification Enable 0 0 read-write 0 - Non-maskable interrupt. + Disable notification of the STSR.SYNC state #0 1 - Internal reset. + Enable notification of the STSR.SYNC state #1 - - - - R_MPU_SPMON - CPU Stack Pointer Monitor - 0x40000D00 - - 0x00000000 - 0x02 - registers - - - 0x00000004 - 0x00E - registers - - - 0x00000014 - 0x00C - registers - - - - 2 - 0x10 - - - M - M - 0 - - - P - P - 1 - - - SP[%s] - Stack Pointer Monitor - 0x0000 - - OAD - Stack Pointer Monitor Operation After Detection Register - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - - KEY - Write Keyword The data written to these bits are not stored. - 8 - 15 - write-only - - - 0xA5 - Writing to the OAD bit is valid, when the KEY bits are written 0xA5. - 0xA5 - - - others - Writing to the OAD bit is invalid. - true - - - - - OAD - Operation after detection - 0 - 0 - read-write - - - 0 - Non-maskable interrupt - #0 - - - 1 - Reset. - #1 - - - - - - - CTL - Stack Pointer Monitor Access Control Register - 0x04 - 16 - read-write - 0x0000 - 0xFEFF - - - ERROR - Stack Pointer Monitor Error Flag - 8 - 8 - read-write - - - 0 - Stack pointer has not overflowed or underflowed - #0 - - - 1 - Stack pointer has overflowed or underflowed - #1 - - - - - ENABLE - Stack Pointer Monitor Enable - 0 - 0 - read-write - - - 0 - Stack pointer monitor is disabled - #0 - - - 1 - Stack pointer monitor is enabled. - #1 - - - - - - - PT - Stack Pointer Monitor Protection Register - 0x06 - 16 - read-write - 0x0000 - 0xFFFF - - - KEY - Write Keyword The data written to these bits are not stored. - 8 - 15 - write-only - - - 0xA5 - Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. - 0xA5 - - - others - Writing to the PROTECT bit is invalid. - true - - - - - PROTECT - Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) - 0 - 0 - read-write - - - 0 - Stack Pointer Monitor register writing is possible. - #0 - - - 1 - Stack Pointer Monitor register writing is protected. - #1 - - - - - - - SA - Stack Pointer Monitor Start Address Register - 0x08 - 32 - read-write - 0x00000000 - 0x00000003 - - - MSPMPUSA - Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. - 0 - 31 - read-write - - - 0x1FF00000 - 0x200FFFFC - - - - - - - EA - Stack Pointer Monitor End Address Register - 0x0C - 32 - read-write - 0x00000003 - 0x00000003 - - - MSPMPUEA - Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. - 0 - 31 - read-write - - - 0x1FF00003 - 0x200FFFFF - - - - - - - - - - R_MSTP - System-Module Stop - 0x40047000 - - 0x00000000 - 0x00C - registers - - - MSTPCRB - Module Stop Control Register B - 0x00 + STCFR + STCA Clock Frequency Setting Register + 0x050 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + STCF + STCA Clock Frequency + 0 + 1 + read-write + + + 00 + 20MHz + #00 + + + 01 + 25MHz + #01 + + + 10 + 50MHz + #10 + + + 11 + 100 MHz + #11 + + + + + + + STMR + STCA Operating Mode Register + 0x054 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ALEN1 + Alarm Detection Enable 1 + 29 + 29 + read-write + + + 0 + The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt. + #0 + + + 1 + The STSR.SYNTOUT flag is not set to 1 on detection of the Sync message reception timeout interrupt. + #1 + + + + + ALEN0 + Alarm Detection Enable 0 + 28 + 28 + read-write + + + 0 + The STSR.SYNC or SYNCOUT flag is not set to 1 on detection of synchronization or loss of synchronization. + #0 + + + 1 + The STSR.SYNC or SYNCOUT flag is set to 1 on detection of synchronization or loss of synchronization. + #1 + + + + + DVTH + Synchronization Loss Detection Threshold Setting + 20 + 23 + read-write + + + 0x0 + None + 0x0 + + + others + (DVTH) time + true + + + + + SYTH + Synchronized State Detection Threshold Setting + 16 + 19 + read-write + + + 0x0 + None + 0x0 + + + others + (SYTH) time + true + + + + + W10S + Worst 10 Acquisition Control Select + 15 + 15 + read-write + + + 0 + Measurement is started by hardware and the value acquired in the PW10VR or MW10R register is used as the limit for filtering. + #0 + + + 1 + Measurement is started by the GETW10R.GW10 bit. Also, the value set in the PLIMITR or MLIMITR register is used as the limit for filtering. + #1 + + + + + CMOD + Time Synchronization Correction Mode + 13 + 13 + read-write + + + 0 + Mode 1 + #0 + + + 1 + Mode 2 + #1 + + + + + WINT + Worst 10 Acquisition Time + 0 + 7 + read-write + + + 0x00 + The worst 10 values are not acquired. + 0x00 + + + others + Sync message reception: (WINT) time + true + + + + + + + SYNTOR + Sync Message Reception Timeout Register + 0x058 32 read-write - 0xFFFFFFFF + 0x00000000 0xFFFFFFFF - MSTPB31 - Serial Communication Interface 0 Module Stop - 31 + SYNTOR + A Sync message not being received within 1024 x n (ns), where n is the setting, leads to a timeout for reception of Sync messages, leading to the STSR.SYNTOUT flag being set to 1. + 0 31 read-write + + + + + IPTSELR + IPLS Interrupt Request Timer Select Register + 0x060 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + IPTSEL5 + Pulse Output Timer 5 Select + 5 + 5 + read-write 0 - Cancel the module-stop state + Pulse output timer 5 is not selected as a source of IPLS interrupt requests. #0 1 - Enter the module-stop state + Pulse output timer 5 is selected as a source of IPLS interrupt requests. #1 - MSTPB30 - Serial Communication Interface 1 Module Stop - 30 - 30 + IPTSEL4 + Pulse Output Timer 4 Select + 4 + 4 read-write 0 - Cancel the module-stop state + Pulse output timer 4 is not selected as a source of IPLS interrupt requests. #0 1 - Enter the module-stop state + Pulse output timer 4 is selected as a source of IPLS interrupt requests. #1 - MSTPB29 - Serial Communication Interface 2 Module Stop - 29 - 29 + IPTSEL3 + Pulse Output Timer 3 Select + 3 + 3 read-write 0 - Cancel the module-stop state + Pulse output timer 3 is not selected as a source of IPLS interrupt requests. #0 1 - Enter the module-stop state + Pulse output timer 3 is selected as a source of IPLS interrupt requests. #1 - MSTPB28 - Serial Communication Interface 3 Module Stop - 28 - 28 + IPTSEL2 + Pulse Output Timer 2 Select + 2 + 2 read-write 0 - Cancel the module-stop state + Pulse output timer 2 is not selected as a source of IPLS interrupt requests. #0 1 - Enter the module-stop state + Pulse output timer 2 is selected as a source of IPLS interrupt requests. #1 - MSTPB27 - Serial Communication Interface 4 Module Stop - 27 - 27 + IPTSEL1 + Pulse Output Timer 1 Select + 1 + 1 read-write 0 - Cancel the module-stop state + Pulse output timer 1 is not selected as a source of IPLS interrupt requests. #0 1 - Enter the module-stop state + Pulse output timer 1 is selected as a source of IPLS interrupt requests. #1 - MSTPB26 - Serial Communication Interface 5 Module Stop - 26 - 26 + IPTSEL0 + Pulse Output Timer 0 Select + 0 + 0 read-write 0 - Cancel the module-stop state + Pulse output timer 0 is not selected as a source of IPLS interrupt requests. #0 1 - Enter the module-stop state + Pulse output timer 0 is selected as a source of IPLS interrupt requests. #1 + + + + MITSELR + MINT Interrupt Request Timer Select Register + 0x064 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPB25 - Serial Communication Interface 6 Module Stop - 25 - 25 + MINTEN5 + Pulse Output Timer 5 MINT Interrupt Output Enable + 5 + 5 read-write 0 - Cancel the module-stop state + Output of rising edges by pulse output timer 5 is not reflected by the MIESR.CYC5 flag as a MINT interrupt source. #0 1 - Enter the module-stop state + Output of rising edges by pulse output timer 5 is reflected by the MIESR.CYC5 flag as a MINT interrupt source. #1 - MSTPB24 - Serial Communication Interface 7 Module Stop - 24 - 24 + MINTEN4 + Pulse Output Timer 4 MINT Interrupt Output Enable + 4 + 4 read-write 0 - Cancel the module-stop state + Output of rising edges by pulse output timer 4 is not reflected by the MIESR.CYC4 flag as a MINT interrupt source. #0 1 - Enter the module-stop state + Output of rising edges by pulse output timer 4 is reflected by the MIESR.CYC4 flag as a MINT interrupt source. #1 - MSTPB23 - Serial Communication Interface 8 Module Stop - 23 - 23 + MINTEN3 + Pulse Output Timer 3 MINT Interrupt Output Enable + 3 + 3 read-write 0 - Cancel the module-stop state + Output of rising edges by pulse output timer 3 is not reflected by the MIESR.CYC3 flag as a MINT interrupt source. #0 1 - Enter the module-stop state + Output of rising edges by pulse output timer 3 is reflected by the MIESR.CYC3 flag as a MINT interrupt source. #1 - MSTPB22 - Serial Communication Interface 9 Module Stop - 22 - 22 + MINTEN2 + Pulse Output Timer 2 MINT Interrupt Output Enable + 2 + 2 read-write 0 - Cancel the module-stop state + Output of rising edges by pulse output timer 2 is not reflected by the MIESR.CYC2 flag as a MINT interrupt source. #0 1 - Enter the module-stop state + Output of rising edges by pulse output timer 2 is reflected by the MIESR.CYC2 flag as a MINT interrupt source. #1 - Reserved - These bits are read as 11. The write value should be 11. - 20 - 21 - read-write - - - MSTPB19 - Serial Peripheral Interface 0 Module Stop - 19 - 19 + MINTEN1 + Pulse Output Timer 1 MINT Interrupt Output Enable + 1 + 1 read-write 0 - Cancel the module-stop state + Output of rising edges by pulse output timer 1 is not reflected by the MIESR.CYC1 flag as a MINT interrupt source. #0 1 - Enter the module-stop state + Output of rising edges by pulse output timer 1 is reflected by the MIESR.CYC1 flag as a MINT interrupt source. #1 - MSTPB18 - Serial Peripheral Interface Module Stop - 18 - 18 + MINTEN0 + Pulse Output Timer 0 MINT Interrupt Output Enable + 0 + 0 read-write 0 - Cancel the module-stop state + Output of rising edges by pulse output timer 0 is not reflected by the MIESR.CYC0 flag as a MINT interrupt source. #0 1 - Enter the module-stop state + Output of rising edges by pulse output timer 0 is reflected by the MIESR.CYC0 flag as a MINT interrupt source. #1 + + + + ELTSELR + ELC Output Timer Select Register + 0x068 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - Reserved - These bits are read as 11. The write value should be 11. - 16 - 17 - read-write - - - MSTPB15 - ETHERC0 and EDMAC0 Module Stop - 15 - 15 + ELTDIS5 + Pulse Output Timer 5 Event Generation Disable + 5 + 5 read-write 0 - Cancel the module-stop state + Pulse output timer 5 is used for the generation of event signals for the ELC. #0 1 - Enter the module-stop state + Pulse output timer 5 is not used for the generation of event signals for the ELC. #1 - MSTPB14 - ETHERC1 and EDMAC1 Module Stop - 14 - 14 + ELTDIS4 + Pulse Output Timer 4 Event Generation Disable + 4 + 4 read-write 0 - Cancel the module-stop state + Pulse output timer 4 is used for the generation of event signals for the ELC. #0 1 - Enter the module-stop state + Pulse output timer 4 is not used for the generation of event signals for the ELC. #1 - MSTPB13 - EPTPC and PTPEDMAC Module Stop - 13 - 13 + ELTDIS3 + Pulse Output Timer 3 Event Generation Disable + 3 + 3 read-write 0 - Cancel the module-stop state + Pulse output timer 3 is used for the generation of event signals for the ELC. #0 1 - Enter the module-stop state + Pulse output timer 3 is not used for the generation of event signals for the ELC. #1 - MSTPB12 - Universal Serial Bus 2.0 HS Interface Module Stop - 12 - 12 + ELTDIS2 + Pulse Output Timer 2 Event Generation Disable + 2 + 2 read-write 0 - Cancel the module-stop state + Pulse output timer 2 is used for the generation of event signals for the ELC. #0 1 - Enter the module-stop state + Pulse output timer 2 is not used for the generation of event signals for the ELC. #1 - MSTPB11 - Universal Serial Bus 2.0 FS Interface Module Stop - 11 - 11 + ELTDIS1 + Pulse Output Timer 1 Event Generation Disable + 1 + 1 read-write 0 - Cancel the module-stop state + Pulse output timer 1 is used for the generation of event signals for the ELC. #0 1 - Enter the module-stop state + Pulse output timer 1 is not used for the generation of event signals for the ELC. #1 - Reserved - This bit is read as 1. The write value should be 1. - 10 - 10 - read-write - - - MSTPB9 - I2C Bus Interface 0 Module Stop - 9 - 9 + ELTDIS0 + Pulse Output Timer 0 Event Generation Disable + 0 + 0 read-write 0 - Cancel the module-stop state + Pulse output timer 0 is used for the generation of event signals for the ELC. #0 1 - Enter the module-stop state + Pulse output timer 0 is not used for the generation of event signals for the ELC. #1 + + + + STCHSELR + Time Synchronization Channel Select Register + 0x06C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPB8 - I2C Bus Interface 1 Module Stop - 8 - 8 + SYSEL + Timer Information Input SelectNOTE: Do not change the value of this bit while the SYNSTARTR.STR bit is 1. + 0 + 0 read-write 0 - Cancel the module-stop state + Time information from synchronization from the SYNFP0 module is used. #0 1 - Enter the module-stop state + Time information from synchronization from the SYNFP1 module is used. #1 + + + + SYNSTARTR + Slave Time Synchronization Start Register + 0x080 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPB7 - I2C Bus Interface 2 Module Stop - 7 - 7 + STR + Slave Time Synchronization Control + 0 + 0 read-write 0 - Cancel the module-stop state + Slave time synchronization is stopped. #0 1 - Enter the module-stop state + Slave time synchronization is started. #1 + + + + LCIVLDR + Local Time Counter Initial Value Load Directive Register + 0x084 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + - MSTPB6 - Queued Serial Peripheral Interface Module Stop - 6 - 6 - read-write + LOAD + Local Time Counter Initial Value Load Directive + 0 + 0 + write-only 0 - Cancel the module-stop state + The initial value is not loaded into the local time counter. #0 1 - Enter the module-stop state + The initial value is loaded into the local time counter. #1 + + + + SYNTDARU + Synchronization Loss Detection Threshold Registers + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDARU + These bits hold the setting for the higher-order 32 bits of the threshold for detection of loss of synchronization. + 0 + 31 + read-write + + + + + SYNTDARL + Synchronization Loss Detection Threshold Registers + 0x094 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDARL + These bits hold the setting for the lower-order 32 bits of the threshold for detection of loss of synchronization. + 0 + 31 + read-write + + + + + SYNTDBRU + Synchronization Detection Threshold Registers + 0x098 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDBRU + These bits hold the setting for the higher-order 32 bits of the threshold for detection of synchronization. + 0 + 31 + read-write + + + + + SYNTDBRL + Synchronization Detection Threshold Registers + 0x09C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYNTDBRL + These bits hold the setting for the lower-order 32 bits of the threshold for detection of synchronization. + 0 + 31 + read-write + + + + + LCIVRU + Local Time Counter Initial Value Registers + 0x0B0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCIVRU + These bits hold the setting for the higher-order 16 bits of the integer portion of the initial value for the local timer counter. + 0 + 15 + read-write + + + + + LCIVRM + Local Time Counter Initial Value Registers + 0x0B4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCIVRM + These bits hold the setting for the lower-order 32 bits of the integer portion of the initial value for the local timer counter. + 0 + 31 + read-write + + + + + LCIVRL + Local Time Counter Initial Value Registers + 0x0B8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LCIVRL + These bits hold the setting for the fractional portion of the initial value of the local timer counter in nanoseconds. + 0 + 31 + read-write + + + + + GETW10R + Worst 10 Acquisition Directive Register + 0x124 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPB5 - IrDA Module Stop - 5 - 5 + GW10 + Worst 10 Acquisition Directive + 0 + 0 read-write 0 - Cancel the module-stop state + The worst-10 values are not acquired. #0 1 - Enter the module-stop state + Starts acquisition of the worst-10 values. #1 + + + + PLIMITRU + Positive Gradient Limit Registers + 0x128 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - Reserved - These bits are read as 11. The write value should be 11. - 3 - 4 + PLIMITRU + These bits hold the setting for the higher-order 31 bits of the limit for the positive gradient. + 0 + 30 read-write + + + + PLIMITRM + Positive Gradient Limit Registers + 0x12C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPB2 - RCAN0 Module Stop - 2 - 2 + PLIMITRM + These bits hold the setting for the middle-order 32 bits of the limit for the positive gradient. + 0 + 31 read-write - - - 0 - Cancel the module-stop state - #0 - - - 1 - Enter the module-stop state - #1 - - + + + + PLIMITRL + Positive Gradient Limit Registers + 0x130 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPB1 - RCAN1 Module Stop - 1 - 1 + PLIMITRL + These bits hold the setting for the lower-order 32 bits of the limit for the positive gradient. + 0 + 31 read-write - - - 0 - Cancel the module-stop state - #0 - - - 1 - Enter the module-stop state - #1 - - + + + + MLIMITRU + Negative Gradient Limit Registers + 0x134 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - Reserved - This bit is read as 1. The write value should be 1. + MLIMITRU + These bits hold the setting for the higher-order 31 bits of the limit for the negative gradient. 0 - 0 + 30 read-write - MSTPCRC - Module Stop Control Register C - 0x04 + MLIMITRM + Negative Gradient Limit Registers + 0x138 32 read-write - 0xFFFFFFFF + 0x00000000 0xFFFFFFFF - MSTPC31 - AES Module Stop - 31 + MLIMITRM + These bits hold the setting for the middle-order 32 bits of the limit for the negative gradient. + 0 31 read-write - - - 0 - Cancel the module-stop state - #0 - - - 1 - Enter the module-stop state - #1 - - + + + + MLIMITRL + Negative Gradient Limit Registers + 0x13C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPC28 - Random Number Generator Module Stop - 28 - 28 + MLIMITRL + These bits hold the setting for the lower-order 32 bits of the limit for the negative gradient. + 0 + 31 read-write - - - 0 - Cancel the module-stop state - #0 - - - 1 - Enter the module-stop state. - #1 - - + + + + GETINFOR + Statistical Information Retention Control Register + 0x140 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPC14 - Event Link Controller Module Stop - 14 - 14 + INFO + Information Retention ControlNOTE: Once information fetching is directed, values of various statistical information read before completion of information fetching are not guaranteed. + 0 + 0 read-write 0 - Cancel the module-stop state + Has no effects.(write) / Information retention is completed.(read) #0 1 - Enter the module-stop state + Information is retained.(write) / Processing for information retention is in progress.(read) #1 + + + + LCCVRU + Local Time Counters + 0x170 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + - MSTPC13 - Data Operation Circuit Module Stop - 13 - 13 + LCCVRU + These bits are for reading the higher-order 16 bits of the integer portion of the local timer counter's value. + 0 + 15 + read-only + + + + + LCCVRM + Local Time Counters + 0x174 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + LCCVRM + These bits are for reading the lower-order 32 bits of the integer portion of the local timer counter's value. + 0 + 31 + read-only + + + + + LCCVRL + Local Time Counters + 0x178 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + LCCVRL + These bits are for reading the fractional portion of the local timer counter's value (in nanoseconds). + 0 + 31 + read-only + + + + + PW10VRU + Positive Gradient Worst 10 Value Registers + 0x210 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PW10VRU + These bits are for reading the higher-order 32 bits of the positive gradient value. + 0 + 31 + read-only + + + + + PW10VRM + Positive Gradient Worst 10 Value Registers + 0x214 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PW10VRM + These bits are for reading the middle-order 32 bits of the positive gradient value. + 0 + 31 + read-only + + + + + PW10VRL + Positive Gradient Worst 10 Value Registers + 0x218 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PW10VRL + These bits are for reading the lower-order 32 bits of the positive gradient value. + 0 + 31 + read-only + + + + + MW10RU + Negative Gradient Worst 10 Value Registers + 0x2D0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MW10RU + These bits are for reading the higher-order 32 bits of the negative gradient value. + 0 + 31 + read-only + + + + + MW10RM + Negative Gradient Worst 10 Value Registers + 0x2D4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MW10RM + These bits are for reading the middle-order 32 bits of the negative gradient value. + 0 + 31 + read-only + + + + + MW10RL + Negative Gradient Worst 10 Value Registers + 0x2D8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + MW10RL + These bits are for reading the lower-order 32 bits of the negative gradient value. + 0 + 31 + read-only + + + + + TMSTARTR + Timer Start Register + 0x37C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EN5 + Pulse Output Timer 5 Start + 5 + 5 read-write 0 - Cancel the module-stop state + Stops pulse output timer 5. #0 1 - Enter the module-stop state + Starts pulse output timer 5. #1 - MSTPC4 - Segment LCD Controller Module Stop + EN4 + Pulse Output Timer 4 Start 4 4 read-write 0 - Cancel the module-stop state + Stops pulse output timer 4. #0 1 - Enter the module-stop state + Starts pulse output timer 4. #1 - MSTPC3 - Capacitive Touch Sensing Unit Module Stop + EN3 + Pulse Output Timer 3 Start 3 3 read-write 0 - Cancel the module-stop state + Stops pulse output timer 3. #0 1 - Enter the module-stop state + Starts pulse output timer 3. #1 - MSTPC2 - Parallel Data Capture Module Stop + EN2 + Pulse Output Timer 2 Start 2 2 read-write 0 - Cancel the module-stop state + Stops pulse output timer 2. #0 1 - Enter the module-stop state + Starts pulse output timer 2. #1 - MSTPC1 - CRC Calculator Module Stop + EN1 + Pulse Output Timer 1 Start 1 1 read-write 0 - Cancel the module-stop state + Stops pulse output timer 1. #0 1 - Enter the module-stop state + Starts pulse output timer 1. #1 - MSTPC0 - CAC Module Stop + EN0 + Pulse Output Timer 0 Start 0 0 read-write 0 - Cancel the module-stop state + Stops pulse output timer 0. #0 1 - Enter the module-stop state + Starts pulse output timer 0. #1 @@ -48800,389 +34099,299 @@ FMS2,1,0: - MSTPCRD - Module Stop Control Register D - 0x08 + PRSR + PRC-TC Status Register + 0x400 32 read-write - 0xFFFFFFFF + 0x00000000 0xFFFFFFFF - MSTPD31 - Operational Amplifier Module Stop - 31 - 31 + URE1 + Relay Packet Underflow Detection Flag 1 + 29 + 29 read-write + oneToClear 0 - Cancel the module-stop state + No underflow in transfer of data from SYNFP0 to SYNFP1. #0 1 - Enter the module-stop state + An underflow has been detected in transfer of data from SYNFP0 to SYNFP1. #1 - MSTPD29 - Comparator-LP Module Stop - 29 - 29 + URE0 + Relay Packet Underflow Detection Flag 0 + 28 + 28 read-write + oneToClear 0 - Cancel the module-stop state + No underflow in transfer of data from SYNFP1 to SYNFP0. #0 1 - Enter the module-stop state + An underflow has been detected in transfer of data from SYNFP1 to SYNFP0. #1 - MSTPD28 - ACMPHS0 Module Stop - 28 - 28 + MACE + Originating MAC Address Mismatch Detection Flag + 8 + 8 read-write + oneToClear + modify 0 - Cancel the module-stop state + A MAC address mismatch has not been detected. #0 1 - Enter the module-stop state + A MAC address mismatch has been detected. #1 - MSTPD20 - 12-bit D/A Converter Module Stop - 20 - 20 + OVRE3 + Relay Packet Overflow Detection Flag 3 + 3 + 3 read-write + oneToClear + modify 0 - Cancel the module-stop state + No overflow in transfer of data from SYNFP0 to SYNFP1. #0 1 - Enter the module-stop state + An overflow has been detected in transfer of data from SYNFP0 to SYNFP1. #1 - MSTPD19 - 8-Bit D/A Converter Module Stop - 19 - 19 + OVRE2 + Relay Packet Overflow Detection Flag 2 + 2 + 2 read-write + oneToClear + modify 0 - Cancel the module-stop state + No overflow in transfer of data from SYNFP1 to SYNFP0. #0 1 - Enter the module-stop state + An overflow has been detected in transfer of data from SYNFP1 to SYNFP0. #1 - MSTPD17 - 24-bit Sigma-Delta A/DConverter Module Stop - 17 - 17 + OVRE1 + Relay Packet Overflow Detection Flag 1 + 1 + 1 read-write + oneToClear + modify 0 - Cancel the module-stop state + No overflow in transfer of data from SYNFP0 to PTPEDMAC. #0 1 - Enter the module-stop state + An overflow has been detected in transfer of data from SYNFP0 to PTPEDMAC. #1 - MSTPD16 - 16-Bit A/D Converter Module Stop - 16 - 16 + OVRE0 + Relay Packet Overflow Detection Flag 0 + 0 + 0 read-write + oneToClear + modify 0 - Cancel the module-stop state + No overflow in transfer of data from SYNFP1 to PTPEDMAC. #0 1 - Enter the module-stop state + An overflow has been detected in transfer of data from SYNFP1 to PTPEDMAC. #1 + + + + PRIPR + PRC-TC Status Notification Permission Register + 0x404 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - MSTPD14 - POEG Module Stop - 14 - 14 + URE1 + PRSR.URE1 Status Notification Permission + 29 + 29 read-write 0 - Cancel the module-stop state + Prohibits notification of the state of PRSR.URE1. #0 1 - Enter the module-stop state + Permits notification of the state of PRSR.URE1. #1 - MSTPD6 - GPT ch6 - ch1 Module Stop - 6 - 6 + URE0 + PRSR.URE0 Status Notification Permission + 28 + 28 read-write 0 - Cancel the module-stop state + Prohibits notification of the state of PRSR.URE0. #0 1 - Enter the module-stop state + Permits notification of the state of PRSR.URE0. #1 - MSTPD5 - GPT ch0 Module Stop - 5 - 5 + MACE + PRSR.MACE Status Notification Permission + 8 + 8 read-write 0 - Cancel the module-stop state + Prohibits notification of the state of PRSR.MACE #0 1 - Enter the module-stop state + Permits notification of the state of PRSR.MACE #1 - MSTPD3 - AGT0 Module StopNote: AGT0 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT0. + OVRE3 + PRSR.OVRE3 Status Notification Permission 3 3 read-write 0 - Cancel the module-stop state + Prohibits notification of the state of PRSR.OVRE3. #0 1 - Enter the module-stop state + Permits notification of the state of PRSR.OVRE3. #1 - MSTPD2 - AGT1 Module StopNote: AGT1 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT1. + OVRE2 + PRSR.OVRE2 Status Notification Permission 2 2 read-write 0 - Cancel the module-stop state + Prohibits notification of the state of PRSR.OVRE2. #0 1 - Enter the module-stop state + Permits notification of the state of PRSR.OVRE2. #1 - - - - - - R_OPAMP - Operational Amplifier - 0x40086000 - - 0x00000008 - 0x005 - registers - - - 0x0000000E - 0x00C - registers - - - 0x0000001F - 0x007 - registers - - - - 4 - 0x3 - AMP[%s] - Input and Output Selectors for Operational Amplifier %s - 0x0E - read-write - - OS - Output Select Register - 0 - 8 - read-write - 0x00 - 0xFF - - - - PS - Plus Input Select Register - 2 - 8 - read-write - 0x00 - 0xFF - - - - MS - Minus Input Select Register - 1 - 8 - read-write - 0x00 - 0xFF - - - - - 3 - 2 - AMPOT[%s] - Operational Amplifier n Offset Trimming Registers - 0x20 - read-write - - P - Operational Amplifier n Offset Trimming Pch Register - 0 - 8 - read-write - 0 - 0xD0 - - - TRMP - AMPn input offset trimming Pch side - 0 - 4 - read-write - - - - - N - Operational Amplifier n Offset Trimming Nch Register - 1 - 8 - - - TRMN - AMPn input offset trimming Nch side - 0 - 4 - - - - - - AMPMC - Operational amplifier mode control register - 0x08 - 8 - read-write - 0x00 - 0xFF - - AMPSP - Operation mode selection - 7 - 7 + OVRE1 + PRSR.OVRE1 Status Notification Permission + 1 + 1 read-write 0 - Low-power mode (low-speed). + Prohibits notification of the state of PRSR.OVRE1. #0 1 - High-speed mode. + Permits notification of the state of PRSR.OVRE1. #1 - 3 - 1 - AMPPC%s - Operational amplifier precharge control status + OVRE0 + PRSR.OVRE0 Status Notification Permission 0 0 read-write 0 - Precharging is stopped. + Prohibits notification of the state of PRSR.OVRE0. #0 1 - Precharging is enabled. + Permits notification of the state of PRSR.OVRE0. #1 @@ -49190,81 +34399,39 @@ FMS2,1,0: - AMPTRM - Operational amplifier trigger mode control register - 0x09 - 8 + TRNDISR + Packet Transmission Control Register + 0x420 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xFFFFFFFF - 4 - 2 - AMPTRM%s - Operational amplifier function activation/stop trigger control + TDIS + Packet Transmission Control 0 1 read-write 00 - Software trigger mode. + PTP packets are transmitted through both Ethernet port 0 and Ethernet port 1. #00 01 - An activation and A/D trigger mode. + PTP packets are only transmitted through Ethernet port 0. #01 10 - Setting prohibited. + PTP packets are only transmitted through Ethernet port 1. #10 11 - An activation and A/D trigger mode. - #11 - - - - - - - AMPTRS - Operational Amplifier Activation Trigger Select Register - 0x0A - 8 - read-write - 0x00 - 0xFF - - - AMPTRS - ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register. - 0 - 1 - read-write - - - 00 - Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3 - #00 - - - 01 - Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1 - #01 - - - 10 Setting prohibited - #10 - - - 11 - Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0 #11 @@ -49272,82 +34439,67 @@ FMS2,1,0: - AMPC - Operational amplifier control register - 0x0B - 8 + TRNMR + Relay Mode Register + 0x430 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xFFFFFFFF - IREFE - Operation control of operational amplifier reference current circuit - 7 - 7 + FWD1 + Channel 1 Relay Enable + 9 + 9 read-write 0 - Operational amplifier reference current circuit is stopped. + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 1 to port 0. #0 1 - Operation of operational amplifier reference current circuit is enabled. + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 1 to port 0. #1 - 4 - 1 - AMPE%s - Operation control of operational amplifier - 0 - 0 + FWD0 + Channel 0 Relay Enable + 8 + 8 read-write 0 - Operation amplifier is stopped. + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are not relayed from port 0 to port 1. #0 1 - Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. + Unicast, multicast (other than PTP packets), and broadcast messages from the other node are relayed from port 0 to port 1. #1 - - - - AMPMON - Operational amplifier monitor register - 0x0C - 8 - read-only - 0x00 - 0xFF - - 4 - 1 - AMPMON%s - Operational amplifier status + MOD + Cut-Through Mode 0 0 - read-only + read-write 0 - Operational amplifier is stopped. + Store-and-forward #0 1 - Operational amplifier is operating. + Cut-through #1 @@ -49355,363 +34507,386 @@ FMS2,1,0: - AMPCPC - Operational amplifier switch charge pump control register - 0x1A - 8 + TRNCTTDR + Cut-Through Transfer Start Threshold Register + 0x434 + 32 read-write - 0x00 - 0xFF + 0x00000060 + 0xFFFFFFFF - 3 - 1 - PUMP%sEN - charge pump for AMP%s enable/disable + THVAL + FIFO Read Start ThresholdThreshold for starting to read data from the relay FIFO in cut-through mode (specified as the number of bytes)NOTE1: A value cannot be set in the lower-order 2 bits. These bits are fixed to 0.NOTE2: A value of less than 96 bytes cannot be set. 0 - 0 + 10 read-write - - - 0 - charge pump for AMP is disabled. - #0 - - - 1 - charge pump for AMP is enabled. - #1 - - + + + + R_FACI_HP_CMD + Flash Application Command Interface Command-Issuing Area + 0x407E0000 + + 0x00000000 + 4 + registers + + - AMPUOTE - Operational Amplifier User Offset Trimming Enable Register - 0x1F + FACI_CMD16 + FACI Command Issuing Area (halfword access) + 0 + 16 + read-write + 0x0000 + 0xFFFF + + + FACI_CMD8 + FACI Command Issuing Area (halfword access) + FACI_CMD16 + 0 8 read-write 0x00 0xFF - - - 3 - 1 - AMP%sTE - AMP%sOT write enable - 0 - 0 - read-write - - - 0 - Not possible to write the AMPnOTP and AMPnOTN registers - #0 - - - 1 - Possible to write the AMPnOTP and AMPnOTN registers - #1 - - - - - R_PDC - Parallel Data Capture Unit - 0x40094000 + R_FACI_HP + Flash Application Command Interface + 0x407FE000 0x00000000 - 0x01C + 0x100 registers - PCCR0 - PDC Control Register 0 - 0x000 - 32 + FASTAT + Flash Access Status + 0x0010 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x00 + 0xFF - EDS - Endian Select - 14 - 14 - read-write - - - 0 - Little endian - #0 - - - 1 - Big endian - #1 - - - - - PCKDIV - PCKO Frequency Division Ratio Select - 11 - 13 - read-write - - - 000 - PCKO/2 - #000 - - - 001 - PCKO/4 - #001 - - - 010 - PCKO/6 - #010 - - - 011 - PCKO/8 - #011 - - - 100 - PCKO/10 - #100 - - - 101 - PCKO/12 - #101 - - - 110 - PCKO/14 - #110 - - - 111 - PCKO/16 - #111 - - - - - PCKOE - PCKO Output Enable - 10 - 10 + CFAE + Code Flash Access Error + 7 + 7 read-write + zeroToClear + modify 0 - PCKO output is disabled (fixed to the high level) + No code flash access error has occurred. #0 1 - PCKO output is enabled. + Code flash access error has occurred. #1 - HERIE - Horizontal Byte Number Setting Error Interrupt Enable - 9 - 9 + CMDLK + Command Lock + 4 + 4 + read-only + + + DFAE + Data Flash Access Error + 3 + 3 + read-write + zeroToClear + modify + + + ECRCT + 0 + 0 + read-only + + + + + FAEINT + Flash Access Error Interrupt Enable + 0x0014 + 8 + read-write + 0x99 + 0xFF + + + CFAEIE + Code Flash Access Error Interrupt Enable + 7 + 7 read-write 0 - Generation of horizontal byte number setting error interrupt requests is disabled. + Does not generate "intflerr" interrupt request when CFAE = "1". #0 1 - Generation of horizontal byte number setting error interrupt requests is enabled. + Generates "intflerr" interrupt request when CFAE = "1". #1 - VERIE - Vertical Line Number Setting Error Interrupt Enable - 8 - 8 + CMDLKIE + Command Lock Interrupt Enable + 4 + 4 read-write 0 - Generation of vertical line number setting error interrupt requests is disabled. + Does not generate "intflerr" interrupt request when CMDLK = "1". #0 1 - Generation of vertical line number setting error interrupt requests is enabled. + Generates "intflerr" interrupt request when CMDLK = "1". #1 - UDRIE - Underrun Interrupt Enable - 7 - 7 + DFAEIE + Data Flash Access Error Interrupt Enable + 3 + 3 read-write 0 - Generation of underrun interrupt requests is disabled. + Does not generate "intflerr" interrupt request when DFAE = "1". #0 1 - Generation of underrun interrupt requests is enabled. + Generates "intflerr" interrupt request when DFAE = "1". #1 - OVIE - Overrun Interrupt Enable - 6 - 6 + ECRCTIE + Error Correct Interrupt Enable + 0 + 0 read-write 0 - Generation of overrun interrupt requests is disabled. + Does not generate "intflerr" interrupt request when ECRCT = "1". #0 1 - Generation of overrun interrupt requests is enabled. + Generates "intflerr" interrupt request when ECRCT = "1". #1 + + + + FRDYIE + Flash Ready Interrupt Enable + 0x0018 + 8 + read-write + 0x00 + 0xFF + - FEIE - Frame End Interrupt Enable - 5 - 5 + FRDYIE + FRDY Interrupt Enable + 0 + 0 read-write 0 - Generation of frame end interrupt requests is disabled. + Does not generate "intflend" interrupt request when FRDY is changed from "0" to "1". #0 1 - Generation of frame end interrupt requests is enabled. + Generates "intflend" interrupt request when FRDY is changed from "0" to "1". #1 + + + + FSADDR + Flash Start Address + 0x0030 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - DFIE - Receive Data Ready Interrupt Enable - 4 - 4 + FSA + Start Address of Flash Sequencer Command Target Area + These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored. + 0 + 31 read-write - 0 - Generation of receive data ready interrupt requests is disabled. - #0 - - - 1 - Generation of receive data ready interrupt requests is enabled. - #1 + others + Specifies start address for each command processing. + true + + + + FEADDR + Flash End Address + 0x0034 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - PRST - PDC Reset - 3 - 3 + FEA + End Address of Flash Sequencer Command Target Area + Specifies end address of target area in "Blank Check" command. + These bits can be written when FRDY bit of FSTATR register is "1". Writing to these bits in FRDY = "0" is ignored. + 0 + 31 + read-write + + + + + FMEPROT + Flash P/E Mode Entry Protection Register + 0x0044 + 16 + read-write + 0x0001 + 0xFFFF + + + KEY + KEY Code + 8 + 15 write-only - 0 - PDC reset is not applied. - #0 + 0xD9 + Writing to the other bits in this register is enabled. + 0xD9 - 1 - PDC is reset. - #1 + others + Writing to the other bits in this register is disabled. + true - HPS - HSYNC Signal Polarity Select - 2 - 2 + CEPROT + Code Flash P/E Mode Entry Protection +Writing to this bit is only possible when the FRDY bit in the FSTATR register is 1. Writing to this bit while the FRDY bit = 0 is +ignored. +Writing to this bit is only possible when 16 bits are written and the value written to the KEY bits is D9h. +Written values are not retained by these bits (always read as 0x00). +Only secure access can write to this register. Both secure access and non-secure read access are allowed. Non-secure write +access is denied, but TrustZone access error is note generated. + + 0 + 0 read-write 0 - HSYNC signal is active high. + FENTRYC bit is not protected #0 1 - HSYNC signal is active low. + FENTRYC bit is protected. #1 + + + + FBPROT0 + Flash Block Protection Register + 0x0078 + 16 + read-write + 0x0000 + 0xFFFF + - VPS - VSYNC Signal Polarity Select - 1 - 1 - read-write + KEY + KEY Code + 8 + 15 + write-only - 0 - VSYNC signal is active high. - #0 + 0x78 + Writing to the other bits in this register is enabled. + 0x78 - 1 - VSYNC signal is active low. - #1 + others + Writing to the other bits in this register is disabled. + true - PCKE - Channel 0 GTCNT Count Clear + BPCN0 + Block Protection for Non-secure Cancel +This bit can be written when the FRDY bit in the FSTATR register is 1. Writing to this bit is ignored when the FRDY bit is 0. +Writing to this bit is only possible when 16 bits are written and the value written to the KEY[7:0] bits is 0x78. +Written values are not retained by these bits (always read as 0x00). + 0 0 read-write 0 - Operations for reception are stopped. + FENTRYC bit is not protected #0 1 - Operations for reception are ongoing. + FENTRYC bit is protected. #1 @@ -49719,29 +34894,52 @@ FMS2,1,0: - PCCR1 - PDC Control Register 1 - 0x004 - 32 + FBPROT1 + Flash Block Protection for Secure Register + 0x007C + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - PCE - PDC Operation Enable + KEY + KEY Code + 8 + 15 + write-only + + + 0xB1 + Writing to the other bits in this register is enabled. + 0xB1 + + + others + Writing to the other bits in this register is disabled. + true + + + + + BPCN1 + Block Protection for Secure Cancel +Writing to this bit is only possible when the FRDY bit in the FSTATR register is 1. Writing to this bit while FRDY bit = 0 is ignored. +Writing to this bit is only possible when 16 bits are written and the value written to the KEY[7:0] bits is 0xB1. +Written values are not retained by these bits (always read as 0x00). + 0 0 read-write 0 - Operations for reception are disabled. + FENTRYC bit is not protected #0 1 - Operations for reception are enabled. + FENTRYC bit is protected. #1 @@ -49749,331 +34947,252 @@ FMS2,1,0: - PCSR - PDC Status Register - 0x008 + FSTATR + Flash Status + 0x0080 32 - read-write - 0x00000002 + read-only + 0x00000000 0xFFFFFFFF - HERF - Horizontal Byte Number Setting Error Flag - 6 - 6 - read-write - zeroToClear - modify + ILGCOMERR + Illegal Command Error + 23 + 23 + read-only 0 - Horizontal byte number setting error has not been generated. + A status clear or forced stop command processing is complete #0 1 - Horizontal byte number setting error has been generated. + An error has occurred. #1 - VERF - Vertical Line Number Setting Error Flag - 5 - 5 - read-write - zeroToClear - modify + FESETERR + FENTRY Setting Error + 22 + 22 + read-only 0 - Vertical line number setting error has not been generated. + A status clear or forced stop command processing is complete #0 1 - Vertical line number setting error has been generated. + An error has occurred. #1 - UDRF - Underrun Flag - 4 - 4 + SECERR + Security Error + 21 + 21 read-write - zeroToClear - modify 0 - Underrun has not been generated. + A status clear or forced stop command processing is complete #0 1 - Underrun has been generated. + An error has occurred. #1 - OVRF - Overrun Flag - 3 - 3 - read-write - zeroToClear - modify + OTERR + Other Error + 20 + 20 + read-only 0 - FIFO overrun has not been generated. + A status clear or forced stop command processing is complete #0 1 - FIFO overrun has been generated. + An error has occurred. #1 - FEF - Frame End Flag - 2 - 2 - read-write - zeroToClear - modify + FRDY + Flash Ready + 15 + 15 + read-only 0 - Frame end has not been generated. + "Program", "DMA Program", "Erase", "Program" or "Erase" command suspension, "Forced Stop", "Blank Check", "Config Program", "Config Clear", "Lock Bit Program", "Lock Bit Read", or "OTP Program" is processing. #0 1 - Frame end has been generated. + None of the above is in progress. #1 - FEMPF - FIFO Empty Flag - 1 - 1 + ILGLERR + Illegal Command Error + 14 + 14 read-only 0 - FIFO is not empty. + Flash sequencer has not detected any illegal command or illegal flash memory access. #0 1 - FIFO is empty. + Flash sequencer has detected an illegal command or illegal flash memory access #1 - FBSY - Frame Busy Flag - 0 - 0 + ERSERR + Erasure Error + 13 + 13 read-only 0 - Operations for reception are stopped. + Erasure processing has been completed successfully #0 1 - Operations for reception are ongoing. + An error has occurred during erasure #1 - - - - PCMONR - PDC Pin Monitor Register - 0x00C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - HSYNC - HSYNC Signal Status Flag - 1 - 1 + PRGERR + Programming Error + 12 + 12 read-only 0 - HSYNC signal is at the low level. + Programming has been completed successfully #0 1 - HSYNC signal is at the high level. + An error has occurred during programming #1 - VSYNC - VSYNC Signal Status Flag - 0 - 0 + SUSRDY + Suspend Ready + 11 + 11 read-only 0 - VSYNC signal is at the low level. + Flash sequencer cannot accept "Program/Erase Suspend" command. #0 1 - VSYNC signal is at the high level. + Flash sequencer can accept "Program/Erase Suspend" command. #1 - - - - PCDR - PDC Receive Data Register - 0x010 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - PCDR - The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time. - 0 - 31 + DBFULL + Data Buffer Full + 10 + 10 read-only + + + 0 + Data Buffer is not full + #0 + + - - - - VCR - Vertical Capture Register - 0x014 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - VSZ - Vertical Capture Size Number of lines to be captured. - 16 - 27 - read-write - - - VST - Vertical Capture Start Line PositionNumber of the line where capture is to start. - 0 - 11 - read-write - - - - - HCR - Horizontal Capture Register - 0x018 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - HSZ - Horizontal Capture Size Number of bytes to capture horizontally. - 16 - 27 - read-write - - - HST - Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start. - 0 - 11 - read-write - - - - - - - R_PORT0 - I/O Ports - 0x40040000 - - 0x00000000 - 0x010 - registers - - - - PCNTR1 - Port Control Register 1 - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - PODR - Pmn Output Data - 16 - 31 - read-write + ERSSPD + Erasure-Suspended Status + 9 + 9 + read-only + + + 0 + Flash sequencer is in status other than the below mentioned. + #0 + + + 1 + Flash sequencer is in erasure suspension process or erasure-suspended status. + #1 + + + + + PRGSPD + Programming-Suspended Status + 8 + 8 + read-only 0 - Low output + Flash sequencer is in status other than the below mentioned. #0 1 - High output. + Flash sequencer is in programming suspension process or programming-suspended status. #1 - PDR - Pmn Direction - 0 - 15 - read-write + FLWEERR + Flash Write/Erase Protect Error Flag + 6 + 6 + read-only 0 - Input (functions as an input pin) + An error has not occurred #0 1 - Output (functions as an output pin). + An error has occurred. #1 @@ -50081,32 +35200,71 @@ FMS2,1,0: - PODR - Output data register - PCNTR1 - 0x00 + FENTRYR + Program/Erase Mode Entry + 0x0084 16 read-write 0x0000 0xFFFF - 16 - 1 - PODR%s - Pmn Output Data + KEY + KEY Code + 8 + 15 + write-only + + + 0xAA + Writing to the other bits in this register is enabled. + 0xAA + + + others + Writing to the other bits in this register is disabled. + true + + + + + FENTRYD + Data Flash P/E Mode Entry + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits. + 7 + 7 + read-write + + + 0 + Data flash is in "Read Mode" + #0 + + + 1 + Data flash is in "P/E Mode" + #1 + + + + + FENTRYC + Code Flash P/E Mode Entry + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'AA is written to KEY bits 0 0 read-write 0 - Low output + Code flash is in "Read Mode" #0 1 - High output. + Code flash is in "P/E Mode" #1 @@ -50114,32 +35272,50 @@ FMS2,1,0: - PDR - Data direction register - PCNTR1 - 0x02 + FSUINITR + Flash Sequencer Set-up Initialize + 0x008C 16 read-write 0x0000 0xFFFF - 16 - 1 - PDR%s - Pmn Direction + KEY + KEY Code + 8 + 15 + write-only + + + 0x2D + Writing to the other bits in this register is enabled. + 0x2D + + + others + Writing to the other bits in this register is disabled. + true + + + + + SUINIT + Set-up Initialization + This bit can be written when FRDY bit of FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'2D is written to KEY bits. 0 0 read-write 0 - Input (functions as an input pin) + Set-up registers keep its' value. #0 1 - Output (functions as an output pin). + Set-up registers are initialized. #1 @@ -50147,81 +35323,113 @@ FMS2,1,0: - PCNTR2 - Port Control Register 2 - 0x04 - 32 + FCMDR + Flash Sequencer Command + 0x00A0 + 16 read-only - 0x00000000 - 0xFFFF0000 + 0x0000 + 0xFFFF - EIDR - Pmn Event Input Data - 16 - 31 + CMDR + Command Register + 8 + 15 read-only - 0 - Low input - #0 - - - 1 - High input. - #1 + others + These bits store the latest command accepted by FACI. + true - PIDR - Pmn Input Data + PCMDR + Previous Command Register 0 - 15 + 7 read-only - 0 - Low input - #0 - - - 1 - High input. - #1 + others + These bits store previous command accepted by FACI. + true - EIDR - Event input data register - PCNTR2 - 0x04 + FPESTAT + Program/Erase Error Status + 0x00C0 16 read-only 0x0000 0xFFFF - 16 - 1 - EIDR%s - Pmn Event Input Data + PEERRST + P/E Error Status 0 - 0 + 7 read-only + + + 0x01 + A write attempt made to an area protected by the lock bits + 0x01 + + + 0x02 + A write error caused by other source than the above + 0x02 + + + 0x11 + An erase attempt made to an area protected by the lock bits + 0x11 + + + 0x12 + An erase error caused by other source than the above + 0x12 + + + others + Reserved + true + + + + + + + FBCCNT + Blank Check Control + 0x00D0 + 8 + read-write + 0x00 + 0xFF + + + BCDIR + Blank Check Direction + 0 + 0 + read-write 0 - Low input + Blank check is executed from smaller address to larger address. (Incremental mode) #0 1 - High input. + Blank check is executed from larger address to smaller address. (Decremental mode) #1 @@ -50229,32 +35437,29 @@ FMS2,1,0: - PIDR - Input data register - PCNTR2 - 0x06 - 16 + FBCSTAT + Blank Check Status + 0x00D4 + 8 read-only - 0x0000 - 0x0000 + 0x00 + 0xFF - 16 - 1 - PIDR%s - Pmn Input Data + BCST + Blank Check Status Bit 0 0 read-only 0 - Low input + The target area is erased (blank). #0 1 - High input. + The target area is filled with 0s and/or 1s. #1 @@ -50262,81 +35467,113 @@ FMS2,1,0: - PCNTR3 - Port Control Register 3 - 0x08 + FPSADDR + Programmed Area Start Address + 0x00D8 32 - write-only + read-only 0x00000000 0xFFFFFFFF - PORR - Pmn Output Reset - 16 + PSADR + Programmed Area Start Address + NOTE: Indicates address of the first programmed data which is found in "Blank Check" command execution. + 0 + 18 + read-only + + + + + FAWMON + Flash Access Window Monitor + 0x0DC + 32 + read-only + 0x00000000 + 0x00000000 + + + BTFLG + Flag of Start-Up area select for Boot Swap + 31 31 - write-only + read-only 0 - No affect to output + The start-up area is the alternate area (sector 1) #0 1 - Low output. + The start-up area is the default area (sector 0) #1 - POSR - Pmn Output Set - 0 + FAWE + End Sector Address for Access Window + NOTE: These bits indicate the end sector address for setting the access window that is located in the configuration area. + 16 + 26 + read-only + + + FSPR + Protection Flag of programming the Access Window, Boot Flag and Temporary Boot Swap Control and "Config Clear" command execution + 15 15 - write-only + read-only 0 - No affect to output + Protected state #0 1 - High output. + Non-protected state #1 + + FAWS + Start Sector Address for Access Window + NOTE: These bits indicate the start sector address for setting the access window that is located in the configuration area. + 0 + 10 + read-only + - PORR - Output set register - PCNTR3 - 0x08 + FCPSR + FCU Process Switch + 0x00E0 16 - write-only + read-write 0x0000 0xFFFF - 16 - 1 - PORR%s - Pmn Output Reset + ESUSPMD + Erasure-Suspended Mode 0 0 - write-only + read-write 0 - No affect to output + Suspension-priority mode #0 1 - Low output. + Erasure-priority mode #1 @@ -50344,81 +35581,231 @@ FMS2,1,0: - POSR - Output reset register - PCNTR3 - 0x0A + FPCKAR + Flash Sequencer Processing Clock Frequency Notification + 0x00E4 16 - write-only + read-write 0x0000 0xFFFF - 16 - 1 - POSR%s - Pmn Output Set + KEY + KEY Code + 8 + 15 + write-only + + + 0x1E + Writing to the other bits in this register is enabled. + 0x1E + + + others + Writing to the other bits in this register is disabled. + true + + + + + PCKA + Flash Sequencer Processing Clock Frequency + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'1E is written to KEY bits. 0 - 0 + 7 + read-write + + + others + Notifies operating frequency of clkf. + true + + + + + + + FSUACR + Flash Start-Up Area Control Register + 0x00E8 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + KEY Code + 8 + 15 write-only - 0 - No affect to output - #0 + 0x66 + Writing to the other bits in this register is enabled. + 0x66 - 1 - High output. - #1 + others + Writing to the other bits in this register is disabled. + true + + + + + SAS + Start Up Area Select + These bits can be written when FRDY bit in FSTATR register is "1". Writing to this bit in FRDY = "0" is ignored. + Writing to these bits is enabled only when this register is accessed in 16-bit size and H'66 is written to KEY bits. + 0 + 1 + read-write + + + 10 + The start-up area is temporarily switched to the default area (sector 0) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit. + #10 + + + 11 + The start-up area is temporarily switched to the alternate area (sector 1) regardless of the BTFLG bit. When a reset is generated after setting, the start-up area is selected according to the BTFLG bit. + #11 + + + others + The start-up area is selected according to the start-up area setting of the configuration area (BTFLG bit). + true + + + + R_FACI_LP + Flash Application Command Interface + 0x407EC000 + + 0x00000000 + 0x400 + registers + + + + DFLCTL + Flash P/E Mode Control Register + 0x090 + 8 + read-write + 0x00 + 0xFF + - PCNTR4 - Port Control Register 4 - 0x0C - 32 + FPMCR + Flash P/E Mode Control Register + 0x100 + 8 read-write - 0x00000000 - 0xFFFFFFFF + 0x08 + 0xFF - EORR - Pmn Event Output Reset - 16 - 31 + FMS2 + Flash Operating Mode Select 2. +Refer to the description of the FMS0 bit. + 7 + 7 + read-write + + + VLPE + Low-Voltage P/E Mode Enable + 6 + 6 + read-write + + + 0 + Low-voltage programming is disabled + #0 + + + 1 + Low-voltage programming is enabled + #1 + + + + + FMS1 + The bit to make data flash a programming mode +Refer to the description of the FMS0 bit. + 4 + 4 + read-write + + + RPDIS + Code Flash P/E Disable + 3 + 3 read-write 0 - No affect to output + The programming of the code flash is enabled #0 1 - Low output + The programming of the code flash is disabled #1 - EOSR - Pmn Event Output Set + FMS0 + Flash Operating Mode Select 0 +FMS2,1,0: + 000: Read mode + 011: Discharge mode 1 + 111: Discharge mode 2 + 101: Code Flash P/E mode + 010: Data flash P/E mode + Others: Setting prohibited. + 1 + 1 + read-write + + + + + FASR + Flash Area Select Register + 0x104 + 8 + read-write + 0x00 + 0xFF + + + EXS + Extra area select 0 - 15 + 0 read-write 0 - No affect to output + User area or data area #0 1 - High output. + Extra area #1 @@ -50426,1200 +35813,622 @@ FMS2,1,0: - EORR - Event output set register - PCNTR4 - 0x0C + FSARL + Flash Processing Start Address Register L + 0x108 16 read-write 0x0000 0xFFFF - 16 - 1 - EORR%s - Pmn Event Output Reset + FSAR15_0 + Start address 0 - 0 + 15 read-write - - - 0 - No affect to output - #0 - - - 1 - Low output - #1 - - - EOSR - Event output reset register - PCNTR4 - 0x0E + FSARH + Flash Processing Start Address Register H + 0x110 16 read-write 0x0000 0xFFFF - 16 - 1 - EOSR%s - Pmn Event Output Set + FSAR31_25 + Start address + 9 + 15 + read-write + + + FSAR20_16 + Start address 0 - 0 + 4 read-write - - - 0 - No affect to output - #0 - - - 1 - High output. - #1 - - - - - - R_PORT1 - 0x40040020 - - - R_PORT2 - 0x40040040 - - - R_PORT3 - 0x40040060 - - - R_PORT4 - 0x40040080 - - - R_PORT5 - 0x400400A0 - - - R_PORT6 - 0x400400C0 - - - R_PORT7 - 0x400400E0 - - - R_PORT8 - 0x40040100 - - - R_PORT9 - 0x40040120 - - - R_PORT10 - 0x40040140 - - - R_PORT11 - 0x40040160 - - - R_PFS - I/O Ports-PFS - 0x40040800 - - 0x00000000 - 0x040 - registers - - - - 12 - 0x40 - PORT[%s] - Port %s - - 16 - 4 - PIN[%s] - Pin Function Selects - 0 - - PmnPFS_BY - Pin Function Control Register - 0x003 - 8 - read-write - 0x00 - 0xFD - - - NCODR - N-Channel Open Drain Control - 6 - 6 - read-write - - - 0 - CMOS output - #0 - - - 1 - NMOS open-drain output - #1 - - - - - PIM - Port Input Mode Control - 5 - 5 - read-write - - - 0 - CMOS input - #0 - - - 1 - TTL input - #1 - - - - - PCR - Pull-up Control - 4 - 4 - read-write - - - 0 - Disables an input pull-up. - #0 - - - 1 - Enables an input pull-up. - #1 - - - - - PDR - Port Direction - 2 - 2 - read-write - - - 0 - Input (Functions as an input pin.) - #0 - - - 1 - Output (Functions as an output pin.) - #1 - - - - - PIDR - Port Input Data - 1 - 1 - read-only - - - 0 - Low input - #0 - - - 1 - High input - #1 - - - - - PODR - Port Output Data - 0 - 0 - read-write - - - 0 - Low output - #0 - - - 1 - High output - #1 - - - - - - - PmnPFS_HA - Pin Function Control Register - 0x002 - 16 - read-write - 0x0000 - 0xFFFD - - - ASEL - Analog Input enable - 15 - 15 - read-write - - - 0 - Used other than as analog pin - #0 - - - 1 - Used as analog pin - #1 - - - - - ISEL - IRQ input enable - 14 - 14 - read-write - - - 0 - Not used as IRQn input pin - #0 - - - 1 - Used as IRQn input pin - #1 - - - - - EOFR - Event on Falling/Rising - 12 - 13 - read-write - - - 00 - Do not care - #00 - - - 01 - Detect rising edge - #01 - - - 10 - Detect falling edge - #10 - - - 11 - Detect rising and falling edge - #11 - - - - - DSCR - Drive Strength Control Register - 10 - 11 - read-write - - - 00 - Normal drive output - #00 - - - 01 - Middle drive output - #01 - - - 10 - Middle drive with IIC - #10 - - - 11 - High-drive output - #11 - - - - - - - PmnPFS - Pin Function Control Register - 0x000 - 32 - read-write - 0x00000000 - 0xFFFFFFFD - - - PSEL - Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table - 24 - 28 - read-write - - - PMR - Port Mode Control - 16 - 16 - read-write - - - 0 - Uses the pin as a general I/O pin. - #0 - - - 1 - Uses the pin as an I/O port for peripheral functions. - #1 - - - - - - - - - - - R_PMISC - I/O Ports-MISC - 0x40040D00 - - 0x00000003 - 0x01 - registers - - - PFENET - Ethernet Control Register - 0x00 + FCR + Flash Control Register + 0x114 8 read-write 0x00 0xFF - Reserved - These bits are read as 00. The write value should be 00. - 6 + OPST + Processing Start + 7 7 read-write - - - PHYMODE1 - Ethernet Mode Setting ch1 - 5 - 5 - read-write 0 - RMII mode (ETHERC channel 1) + Processing stops. #0 1 - MII mode (ETHERC channel 1) + Processing starts. #1 - PHYMODE0 - Ethernet Mode Setting ch0 + STOP + Forced Processing Stop + 6 + 6 + read-write + + + DRC + Data Read Completion 4 4 read-write 0 - RMII mode (ETHERC channel 0) + Data is not read or next data is requested. #0 1 - MII mode (ETHERC channel 0) + Data reading is completed. #1 - Reserved - These bits are read as 0000. The write value should be 0000. + CMD + Software Command Setting 0 3 read-write + + + 0001 + Program + #0001 + + + 0011 + Blank check + #0011 + + + 0100 + Block erase + #0100 + + + 0101 + Consecutive read + #0101 + + + 0111 + Chip erase + #0111 + + + others + Setting prohibited + true + + - PWPR - Write-Protect Register - 3 - 8 + FEARL + Flash Processing End Address Register L + 0x118 + 16 read-write + 0x0000 + 0xFFFF - PFSWE - PmnPFS Register Write - 6 - 6 + FEAR15_0 + End address + 0 + 15 + read-write + + + + + FEARH + Flash Processing End Address Register H + 0x120 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FEAR31_25 + End address + 9 + 15 read-write - - - 0 - Writing to the PmnPFS register is disabled - #0 - - - 1 - Writing to the PmnPFS register is enabled. - #1 - - - B0WI - PFSWE Bit Write Disable - 7 - 7 - - - 0 - Writing to the PFSWE bit is enabled - #0 - - - 1 - Writing to the PFSWE bit is disabled. - true - - + FEAR20_16 + End address + 0 + 4 + read-write - - - - R_QSPI - Quad Serial Peripheral Interface - 0x64000000 - - 0x00000000 - 0x01C - registers - - - 0x00000020 - 0x00C - registers - - - 0x00000030 - 0x008 - registers - - - 0x00000804 - 0x04 - registers - - - SFMSMD - Transfer Mode Control Register - 0x000 + FRESETR + Flash Reset Register + 0x124 32 read-write 0x00000000 0xFFFFFFFF - SFMCCE - Read instruction code selection. - 15 - 15 + FRESET + Software Reset of the registers + 0 + 0 read-write 0 - Default instruction code set for each instruction + No effect #0 1 - Instruction code written in the SFMSIC register + The registers relates to the flash programming are reset. #1 + + + + FSTATR00 + Flash Status Register00 + 0x128 + 32 + read-only + 0x00000000 + 0xFFFFFFEF + - SFMOSW - Setup time adjustment for serial transmission - 11 - 11 - read-write + EILGLERR + Extra Area Illegal Command Error Flag + 5 + 5 + read-only 0 - Does not extend the low-level width of SCK at transmission time + No illegal command or illegal access to the extra area is detected. #0 1 - Extends the low-level width of SCK by 1*PCLKA at transmission time + An illegal command or illegal access to the extra area is detected. #1 - SFMOHW - Hold time adjustment for serial transmission - 10 - 10 - read-write + ILGLERR + Illegal Command Error Flag + 4 + 4 + read-only 0 - Does not extend the high-level width of SCK at transmission time + No illegal software command or illegal access is detected. #0 1 - Extends the high-level width of SCK by 1*PCLKA at transmission time + An illegal command or illegal access is detected. #1 - SFMOEX - Extension of the I/O buffer output enable signal for the serial interface - 9 - 9 - read-write + BCERR0 + Blank Check Error Flag0 + 3 + 3 + read-only 0 - Does not extend the output enable signal + Blank checking terminates normally. #0 1 - Extends the output enable signal by 1*QSPCLK + An error occurs during blank checking. #1 - SFMMD3 - SPI mode selection. An initial value is determined by input to CFGMD3. - 8 - 8 - read-write + PRGERR01 + Program Error Flag 01 + 2 + 2 + read-only 0 - SPI mode 0 + Programming by the FEXCR register terminates normally. #0 1 - SPI mode 3 + An error occurs during programming. #1 - SFMPAE - Selection of the function for stopping prefetch at locations other than on byte boundaries - 7 - 7 - read-write + PRGERR0 + Program Error Flag0 + 1 + 1 + read-only 0 - Disables prefetch stopping at locations other than on byte boundaries + Programming terminates normally. #0 1 - Enables prefetch stopping at locations other than on byte boundaries + An error occurs during programming. #1 - SFMPFE - Selection of the prefetch function - 6 - 6 - read-write + ERERR0 + Erase Error Flag0 + 0 + 0 + read-only 0 - Disables prefetch + Erasure terminates normally. #0 1 - Enables prefetch + An error occurs during erasure. #1 - - SFMSE - Selection of the prefetch function - 4 - 5 - read-write - - - 00 - Does not extend QSSL - #00 - - - 01 - Extends QSSL by 33*QSPCLK - #01 - - - 10 - Extends QSSL by 129*QSPCLK - #10 - - - 11 - Extends QSSL infinitely - #11 - - - - - SFMRM - Serial interface read mode selection - 0 - 2 - read-write - - - 000 - Standard Read - #000 - - - 001 - Fast Read - #001 - - - 010 - Fast Read Dual Output - #010 - - - 011 - Fast Read Dual I/O - #011 - - - 100 - Fast Read Quad Output - #100 - - - 101 - Fast Read Quad I/O - #101 - - - 110 - Setting prohibited - #110 - - - 111 - Setting prohibited - #111 - - - - SFMSSC - Chip Selection Control Register - 0x004 + FSTATR1 + Flash Status Register1 + 0x12C 32 - read-write - 0x00000037 - 0xFFFFFFFF + read-only + 0x00000000 + 0xFFFFFFFB - SFMSLD - QSSL signal output timing selection - 5 - 5 - read-write + EXRDY + End status signal of a Extra programming sequencer + 7 + 7 + read-only 0 - Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK + Other than below #0 1 - Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK + The software command of the FEXCR register is terminated. #1 - SFMSHD - QSSL signal release timing selection - 4 - 4 - read-write + FRDY + End status signal of a sequencer + 6 + 6 + read-only 0 - Releases QSSL 0.5*SCK after the last rising edge of QSPCLK + Other than below #0 1 - Releases QSSL 1.5*SCK after the last rising edge of QSPCLK + The software command of the FCR register is terminated. #1 - SFMSW - Selection of a minimum high-level width of the QSSL signal - 0 - 3 - read-write + DRRDY + Data read request + 1 + 1 + read-only - 0000 - 1 x QSPCLK - #0000 - - - 0001 - 2 x QSPCLK - #0001 - - - 0010 - 3 x QSPCLK - #0010 - - - 0011 - 4 x QSPCLK - #0011 - - - 0100 - 5 x QSPCLK - #0100 - - - 0101 - 6 x QSPCLK - #0101 - - - 0110 - 7 x QSPCLK - #0110 - - - 0111 - 8 x QSPCLK - #0111 - - - 1000 - 9 x QSPCLK - #1000 - - - 1001 - 10 x QSPCLK - #1001 - - - 1010 - 11 x QSPCLK - #1010 - - - 1011 - 12 x QSPCLK - #1011 - - - 1100 - 13 x QSPCLK - #1100 - - - 1101 - 14 x QSPCLK - #1101 - - - 1110 - 15 x QSPCLK - #1110 + 0 + Other than below + #0 - 1111 - 16 x QSPCLK - #1111 + 1 + The read processing of the consecutive read command at each address is terminated and read data is stored to the FRBH and FRBL registers. + #1 - SFMSKC - Clock Control Register - 0x008 + FWBL0 + Flash Write Buffer Register L0 + 0x130 32 read-write - 0x00000008 + 0x00000000 0xFFFFFFFF - SFMDTY - Selection of a duty ratio correction function for the SCK signal - 5 - 5 + WDATA + Program data of the program command + 0 + 15 read-write - - - 0 - Serial interface reference cycle selection (* Pay attention to the irregularity.) - #0 - - - 1 - Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number) - #1 - - + + + + FWBH0 + Flash Write Buffer Register H0 + 0x138 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - SFMDV - Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction. + WDATA + Program data of the program command 0 - 4 - read-write - - - 10000 - 18 x PCLKA - #10000 - - - 10001 - 20 x PCLKA - #10001 - - - 10010 - 22 x PCLKA - #10010 - - - 10011 - 24 x PCLKA - #10011 - - - 10100 - 26 x PCLKA - #10100 - - - 10101 - 28 x PCLKA - #10101 - - - 10110 - 30 x PCLKA - #10110 - - - 10111 - 32 x PCLKA - #10111 - - - 11000 - 34 x PCLKA - #11000 - - - 11001 - 36 x PCLKA - #11001 - - - 11010 - 38 x PCLKA - #11010 - - - 11011 - 40 x PCLKA - #11011 - - - 11100 - 42 x PCLKA - #11100 - - - 11101 - 44 x PCLKA - #11101 - - - 11110 - 46 x PCLKA - #11110 - - - 11111 - 48 x PCLKA - #11111 - - - others - ( SFMDV + 2 ) x PCLKA - true - - + 15 - SFMSST - Status Register - 0x00C + FSTATR01 + Flash Status Register01 + 0x13C 32 read-only - 0x00000080 + 0x00000000 0xFFFFFFFF - PFOFF - Prefetch function operation state - 7 - 7 - read-only + BCERR1 + Blank Check Error Flag1 + 3 + 3 0 - The prefetch function is operating. + Blank checking terminates normally. #0 1 - The prefetch function is not enabled or is not operating. + An error occurs during blank checking. #1 - PFFUL - Prefetch buffer state - 6 - 6 - read-only + PRGERR1 + Program Error Flag1 + 1 + 1 0 - The prefetch buffer has a free space. + Programming terminates normally. #0 1 - The prefetch buffer is full. + An error occurs during programming. #1 - PFCNT - Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.) + ERERR1 + Erase Error Flag1 0 - 4 - read-only + 0 - 00000 - Nodata has been prefetched. - #00000 + 0 + Erasure terminates normally. + #0 - others - Data of (PFCNT) bytes hs been prefetched. - true + 1 + An error occurs during erasure. + #1 - SFMCOM - Communication Port Register - 0x010 + FWBL1 + Flash Write Buffer Register L1 + 0x140 32 read-write 0x00000000 - 0xFFFFFF00 + 0xFFFFFFFF - SFMD - Port for direct communication with the SPI bus.Input/output to and from this port is converted to a SPIbus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode. + WDATA47_32 + Program data of the program command 0 - 7 + 15 read-write - SFMCMD - Communication Mode Control Register - 0x014 + FWBH1 + Flash Write Buffer Register H1 + 0x144 32 read-write 0x00000000 0xFFFFFFFF - DCOM - Selection of a mode of communication with the SPI bus + WDATA63_48 + Program data of the program command 0 - 0 - read-write - - - 0 - ROM access mode - #0 - - - 1 - Direct communication mode - #1 - - + 15 - SFMCST - Communication Status Register - 0x018 + FRBL1 + Flash Read Buffer Register L1 + 0x148 32 - read-write + read-only 0x00000000 0xFFFFFFFF - EROMR - Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored. - 7 - 7 + RDATA47_32 + Read data of the consecutive read command + 0 + 15 read-only - - - 0 - ROM access is not detected in direct communication mode - #0 - - - 1 - ROM access is detected in direct communication mode - #1 - - + + + + FRBH1 + Flash Read Buffer Register H1 + 0x14C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + - COMBSY - SPI bus cycle completion state in direct communication + RDATA63_48 + Read data of the consecutive read command + 0 + 15 + read-only + + + + + FPR + Protection Unlock Register + 0x180 + 32 + write-only + 0x00000000 + 0xFFFFFF00 + + + FPR + Protection Unlock Register + 0 + 7 + write-only + + + + + FPSR + Protection Unlock Status Register + 0x184 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PERR + Protect Error Flag 0 0 read-only 0 - There is no serial transfer being processed. + No error #0 1 - There is a serial transfer being processed. + An error occurs. #1 @@ -51627,2916 +36436,6945 @@ FMS2,1,0: - SFMSIC - Instruction Code Register - 0x020 + FRBL0 + Flash Read Buffer Register L0 + 0x188 32 - read-write + read-only 0x00000000 0xFFFFFFFF - SFMCIC - Serial ROM instruction code to substitute + RDATA + Read data of the consecutive read command + 0 + 15 + + + + + FRBH0 + Flash Read Buffer Register H0 + 0x190 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + RDATA + Read data of the consecutive read command + 0 + 15 + + + + + FSCMR + Flash Start-Up Setting Monitor Register + 0x1C0 + 32 + read-only + 0x00000000 + 0xFFFFBEFF + + + FSPR + Access Window Protection Flag + 14 + 14 + read-only + + + SASMF + Start-up Area Setting Monitor Flag + 8 + 8 + read-only + + + + + FAWSMR + Flash Access Window Start Address Monitor Register + 0x1C8 + 32 + read-only + 0x00000000 + 0xFFFFF000 + + + FAWS + Flash Access Window Start Address + 0 + 11 + read-only + + + + + FAWEMR + Flash Access Window End Address Monitor Register + 0x1D0 + 32 + read-only + 0x00000000 + 0xFFFFF000 + + + FAWE + Flash Access Window End Address 0 + 11 + read-only + + + + + FISR + Flash Initial Setting Register + 0x1D8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SAS + Temporary boot swap mode + 6 7 - read-write + + + 10 + The start-up area is switched to the default area temporarily. + #10 + + + 11 + The start-up area is switched to the alternate area temporarily. + #11 + + + others + The start-up area is selected according to the start-up area settings of the extra area. + true + + + + + PCKA + Peripheral Clock Notification + 0 + 5 - SFMSAC - Address Mode Control Register - 0x024 + FEXCR + Flash Extra Area Control Register + 0x1DC 32 read-write - 0x00000002 + 0x00000000 0xFFFFFFFF - SFM4BC - Selection of a default instruction code, when Serial Interface address width is selected 4 bytes. - 4 - 4 + OPST + Software Command Setting + 7 + 7 read-write 0 - Does not use 4 Byte address read Instruction code + Processing stops. #0 1 - Use 4 Byte address read Instruction code + Processing starts. #1 - SFMAS - Selection the number of address bits of the serial interface + CMD + Processing Start) 0 - 1 + 2 read-write - 00 - 1byte - #00 + 001 + Start-up area selection and security setting + #001 - 01 - 2bytes - #01 + 010 + Access window information program + #010 - 10 - 3bytes - #10 + 011 + OCDID1 program + #011 - 11 - 4 bytes - #11 + 100 + OCDID2 program + #100 + + + 101 + OCDID3 program + #101 + + + 110 + OCDID4 program + #110 + + + 111 + Extra area clear + #111 + + + others + Setting prohibited + true - SFMSDC - Dummy Cycle Control Register - 0x028 - 32 + FEAML + Flash Error Address Monitor Register L + 0x1E0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + FEAM + Flash Error Address Monitor Register + 0 + 15 + + + + + FEAMH + Flash Error Address Monitor Register H + 0x1E8 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + FEAM + Flash Error Address Monitor Register + 0 + 15 + + + + + FSTATR2 + Flash Status Register2 + 0x1F0 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + EILGLERR + Extra Area Illegal Command Error Flag + 5 + 5 + read-only + + + ILGLERR + Illegal Command Error Flag + 4 + 4 + read-only + + + BCERR + Blank Check Error Flag + 3 + 3 + read-only + + + PRGERR01 + Program Error Flag 01 + 2 + 2 + read-write + + + PRGERR1 + Program Error Flag + 1 + 1 + read-only + + + ERERR + Erase Error Flag + 0 + 0 + read-only + + + + + FENTRYR_MF4 + Flash P/E Mode Entry Register for MF4 + 0x3FB0 + 16 + read-write + 0x0000 + 0xFFFF + + + FENTRYR + Flash P/E Mode Entry Register + 0x3FB2 + 16 + read-write + 0x0000 + 0xFFFF + + + FLWAITR + Flash Wait Cycle Register + 0x3FC0 + 8 + read-write + 0x00 + 0xFF + + + PFBER + Prefetch Buffer Enable Register + 0x3FC8 + 8 + read-write + 0x00 + 0xFF + + + + + R_FCACHE + Flash Memory Cache + 0x4001C000 + + 0x00000100 + 0x02 + registers + + + 0x00000104 + 0x02 + registers + + + 0x0000011C + 0x01 + registers + + + + FCACHEE + Flash Cache Enable Register + 0x100 + 16 read-write - 0x0000FF00 - 0xFFFFFFFF + 0x0000 + 0xFFFF - SFMXD - Mode data for serial ROM. (Control XIP mode) - 8 - 15 + FCACHEEN + FCACHE Enable + 0 + 0 read-write 0 - XIP mode is prohibited + Disable FCACHE #0 1 - XIP mode is permitted + Enable FCACHE #1 + + + + FCACHEIV + Flash Cache Invalidate Register + 0x104 + 16 + read-write + 0x0000 + 0xFFFF + - SFMXEN - XIP mode permission - 7 - 7 + FCACHEIV + Flash Cache Invalidate Register + 0 + 0 read-write 0 - XIP mode is prohibited - #0 - - - 1 - XIP mode is permitted - #1 - - - - - SFMXST - XIP mode status - 6 - 6 - read-only - - - 0 - Normal (non-XIP) mode is operating + Do not invalidate reads, setting ignored on writes #0 1 - XIP mode is operating + Invalidate on reads and writes. #1 + + + + FLWT + Flash Wait Cycle Register + 0x11C + 8 + read-write + - SFMDN - Selection of the number of dummy cycles of Fast Read instructions + FLWT + Flash Wait Cycle 0 - 3 + 2 read-write - 0000 - Default dummy cycles of each instruction. - #0000 + 000 + 0 waits (ICLK <= 80 MHz) + #000 - others - ( SFMDN + 2 ) x SCK - true + 001 + 1 wait (80 MHz < ICLK <= 160 MHz) + #001 + + + 010 + 2 waits (160 MHz < ICLK <= 240 MHz). + #010 - SFMSPC - SPI Protocol Control Register - 0x030 - 32 + FSAR + Flash Security Attribution Register + 0x140 + 16 read-write - 0x00000010 - 0xFFFFFFFF + 0xffff + 0xffff - SFMSDE - Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected. - 4 - 4 + FLWTSA + FLWT Security Attribution + 0 + 0 read-write 0 - Does not allocate minimum switch time + Secure #0 1 - Allocate the minimum switch time equivalent to 1*QSPXLK + Non-Secure #1 - SFMSPI - Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately. - 0 - 1 - read-write - - - 00 - Extended SPI protocol - #00 - - - 01 - Dual SPI protocol - #01 - - - 10 - Quad SPI protocol - #10 - - - 11 - Setting prohibited. - #11 - - - - - - - SFMPMD - Port Control Register - 0x034 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SFMWPL - Specify level of WP pin - 2 - 2 + FCKMHZSA + FCKMHZ Security Attribution + 8 + 8 read-write 0 - Low level + Secure #0 1 - High level + Non-Secure #1 - - SFMCNT1 - External QSPI Address Register 1 - 0x804 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - QSPI_EXT - BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. - 26 - 31 - read-write - - - - R_RTC - Realtime Clock - 0x40044000 + R_GLCDC + Graphics LCD Controller + 0x400E0000 0x00000000 - 0x01 - registers - - - 0x00000002 - 0x01 - registers - - - 0x00000004 - 0x01 - registers - - - 0x00000006 - 0x01 - registers - - - 0x00000008 - 0x01 - registers - - - 0x0000000A - 0x01 - registers - - - 0x0000000C - 0x01 - registers - - - 0x0000000E - 0x003 - registers - - - 0x00000012 - 0x01 - registers - - - 0x00000014 - 0x01 - registers - - - 0x00000016 - 0x01 - registers - - - 0x00000018 - 0x01 - registers - - - 0x0000001A - 0x01 - registers - - - 0x0000001C - 0x003 - registers - - - 0x00000022 - 0x01 - registers - - - 0x00000024 - 0x01 - registers - - - 0x00000028 - 0x01 - registers - - - 0x0000002A - 0x005 - registers - - - 0x00000040 - 0x01 - registers - - - 0x00000042 - 0x01 - registers - - - 0x00000044 - 0x01 - registers - - - 0x00000052 - 0x01 - registers - - - 0x00000054 - 0x01 + 0x101C registers - 0x00000056 - 0x01 + 0x00001100 + 0x014 registers - 0x0000005A - 0x01 + 0x00001118 + 0x02C registers - 0x0000005C - 0x01 + 0x0000114C + 0x00C registers - 0x00000062 - 0x01 + 0x00001200 + 0x014 registers - 0x00000064 - 0x01 + 0x00001218 + 0x02C registers - 0x00000066 - 0x01 + 0x0000124C + 0x00C registers - 0x0000006A - 0x01 + 0x00001300 + 0x03C registers - 0x0000006C - 0x01 + 0x00001340 + 0x03C registers - 0x00000072 - 0x01 + 0x00001380 + 0x03C registers - 0x00000074 - 0x01 + 0x000013C0 + 0x018 registers - 0x00000076 - 0x01 + 0x000013E4 + 0x04 registers - 0x0000007A - 0x01 + 0x00001404 + 0x028 registers - 0x0000007C - 0x01 + 0x00001440 + 0x014 registers + + BG + Background Registers + 0x1000 + + EN + Background Plane Setting Operation Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SWRST + Entire module SW reset control + 16 + 16 + read-write + + + 1 + Releases the entire module from the SW reset state. + #1 + + + 0 + Places the entire module in the SW reset state. + #0 + + + + + VEN + Control of LCDC internal register value reflection to internal operations + 8 + 8 + read-write + oneToSet + modify + + + 1 + Enables + #1 + + + 0 + Disables(Cleared to 0 by an internal source) + #0 + + + + + EN + Background plane generation module operation enable + 0 + 0 + read-write + + + 1 + Enables operation. + #1 + + + 0 + Disables operation. + #0 + + + + + + + PERI + Background Plane Setting Free-Running Period Register + 0x04 + 32 + read-write + 0x00170017 + 0xFFFFFFFF + + + FV + Background plane vertical synchronization signal period on the basis of line. + 16 + 26 + read-write + + + 0x013 + 0x3FF + + + + + FV + FV lines.The valid range is 0x013 to 0x3FF. + true + + + + + FH + Background plane horizontal synchronization signal period on the basis of pixel clock (PXCLK). + 0 + 10 + read-write + + + 0x017 + 0x3FF + + + + + FH + FH lines. The valid range is 0x017 to 0x3FF. + true + + + + + + + SYNC + Background Plane Setting Synchronization Position Register + 0x08 + 32 + read-write + 0x00010001 + 0xFFFFFFFF + + + VP + Background plane vertical synchronization signal assertion position on the basis of line. + 16 + 19 + read-write + + + 0x0 + Setting prohibited + 0x0 + + + others + (VP)th line + true + + + + + HP + Background plane horizontal synchronization signal assertion position on the basis of pixel clock (PXCLK). + 0 + 3 + read-write + + + 0x0 + Setting prohibited + 0x0 + + + others + (HP)th line (pixels) + true + + + + + + + VSIZE + Background Plane Setting Full Image Vertical Size Register + 0x0C + 32 + read-write + 0x00070010 + 0xFFFFFFFF + + + VP + Background plane vertical valid pixel start position on the basis of line + 16 + 26 + read-write + + + 0x0003 + 0x3EF + + + + + VP + VP lines. The valid range is 0x003 to 0x3EF. + true + + + + + VW + Background plane vertical valid pixel width on the basis of line + 0 + 10 + read-write + + + 0x0010 + 0x03FC + + + + + VW + VW lines. The valid range is 0x010 to 0x3F0. + true + + + + + + + HSIZE + Background Plane Setting Full Image Horizontal Size Register + 0x10 + 32 + read-write + 0x00060010 + 0xFFFFFFFF + + + HP + Background plane horizontal valid pixel start position on the basis of pixel clock (PXCLK). + 16 + 26 + read-write + + + 0x006 + 0x3EE + + + + + HP + HP cycle(pixel). The valid range is 0x006 to 0x3EE. + true + + + + + HW + + Background plane horizontall valid pixel width on the basis of pixel clock (PXCLK) + Note: When serial RGB is selected as the output format for the output control block, add two to the horizontal enable signal width and set the resulting value to this field. + + 0 + 10 + read-write + + + 0x010 + 0x3F8 + + + + + HW + HW cycles. The valid range is 0x010 to 0x3F8. + true + + + + + + + BGC + Background Plane Setting Background Color Register + 0x14 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + R + + R value for background plane valid pixel area. + Unsigned; 8-bit integer. + + 16 + 23 + read-write + + + G + + G value for background plane valid pixel area + Unsigned; 8-bit integer + + 8 + 15 + read-write + + + B + + B value for background plane valid pixel area + Unsigned; 8-bit integer + + 0 + 7 + read-write + + + + + MON + Background Plane Setting Status Monitor Register + 0x18 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SWRST + Entire module SW reset state monitor. + 16 + 16 + read-only + + + 1 + The entire module is released from the SW reset state. + #1 + + + 0 + The entire module is in the SW reset state. + #0 + + + + + VEN + + Entire module internal operation reflection control signal monitor. + The signal state for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal. + + 8 + 8 + read-only + + + 1 + The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is asserted. + #1 + + + 0 + The signal for controlling reflection of the register values to the internal operations upon assertion of the vertical synchronization signal is negated. + #0 + + + + + EN + Background plane generation module operation state monitor. + 0 + 0 + read-only + + + 1 + Operation is in progress. + #1 + + + 0 + Operation is stopped. + #0 + + + + + + + + 2 + 0x100 + GR[%s] + Layer Registers + 0x1100 + + VEN + Graphics Register Update Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PVEN + + Control of graphics n module register value reflection to internal operations. + Reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). + + 0 + 0 + read-write + zeroToClear + modify + + + 1 + Enables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). + #1 + + + 0 + Disables reflection of the register values to the internal operation at the assertion of the vertical synchronization signal (VS). + #0 + + + + + + + FLMRD + Graphics Frame Buffer Read Control Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + RENB + Graphics data (frame buffer data) read enable. + 0 + 0 + read-write + + + 1 + Enables reading. + #1 + + + 0 + Disables reading. + #0 + + + + + + + FLM1 + Graphics Frame Buffer Control Register 1 + 0x08 + 32 + read-only + 0x00000003 + 0xFFFFFFFF + + + BSTMD + + Burst transfer control for graphics data (frame buffer data) + access + + 0 + 1 + read-only + + + 11 + 16-beat increment burst transfer (64-byte boundary) + #11 + + + others + Setting prohibited. + true + + + + + + + FLM2 + Graphics Frame Buffer Control Register 2 + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BASE + + Base address for accessing graphics data (frame buffer data) + Set the head address in the frame buffer where graphics data is to be stored. GRn_FLM2.BASE[5:0] should be fixed to 0 during 64-byte burst transfer. + + 0 + 31 + read-write + + + + + FLM3 + Graphics Frame Buffer Control Register 3 + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LNOFF + + Macro line offset address for accessing graphics data + (frame buffer data) + Signed; 16-bit integer + + 16 + 31 + read-write + + + + + FLM5 + Graphics Frame Buffer Control Register 5 + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + LNNUM + Number of lines per frame for accessing graphics data (frame buffer data). + 16 + 26 + read-write + + + 0x00F + 0x3FF + + + + + LNNUM + LNNUM lines. The valid range is 0x00F to 0x3FF. + true + + + + + DATANUM + Number of data transfer times per line for accessing graphics data (frame buffer data), where one transfer is defined as 16-beat burst access (64-byte boundary) + 0 + 15 + read-write + + + DATAUM + DATAUM+1 times. + true + + + + + + + FLM6 + Graphics Frame Buffer Control Register 6 + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FORMAT + Data format for accessing graphics data (frame buffer data). + 28 + 30 + read-write + + + 111 + CLUT11bit/pix) + #111 + + + 110 + CLUT4 (4 bits/pix) + #110 + + + 101 + CLUT8 (8 bits/pix) + #101 + + + 100 + ARGB8888 (32 bits/pix) + #100 + + + 011 + ARGB4444 (16 bits/pix) + #011 + + + 010 + ARGB1555 (16 bits/pix, 1 bit of A is LUT data) + #010 + + + 001 + RGB888 (32 bits/pix, 8 bits on the MSB side are invalid) + #001 + + + 000 + RGB565 (16 bits/pix) + #000 + + + others + Setting prohibited. + true + + + + + + + AB1 + Graphics Alpha Blending Control Register 1 + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ARCON + Rectangular area alpha blending control. + 12 + 12 + read-write + + + 1 + On + #1 + + + 0 + Off + #0 + + + + + ARCDISPON + Image area border display control for rectangular area alpha blending. + 8 + 8 + read-write + + + 1 + Display on + #1 + + + 0 + Display off + #0 + + + + + GRCDISPON + Graphics image area border display control. + 4 + 4 + read-write + + + 1 + Display on + #1 + + + 0 + Display off + #0 + + + + + DISPSEL + Graphics display plane control. + 0 + 1 + read-write + + + 11 + Blended display of lower-layer graphics (input image from the previous stage) and current graphics (graphics data read from the AHB bus) + #11 + + + 10 + Current graphics display + #10 + + + 01 + Lower-layer graphics display + #01 + + + 00 + Background color display (value set by the GRn_BASE register). + #00 + + + + + + + AB2 + Graphics Alpha Blending Control Register 2 + 0x24 + 32 + read-write + 0x00060010 + 0xFFFFFFFF + + + GRCVS + Vertical start position of graphics image area. + 16 + 26 + read-write + + + 0x002 + 0x3EE + + + + + GRCVS + GRCVS lines. The valid range is 0x002 to 0x3EE. + true + + + + + GRCVW + Vertical width of graphics image area. + 0 + 10 + read-write + + + 0x010 + 0x3FC + + + + + GRCVW + GRCVW lines. The valid range is 0x010 to 0x3F0. + true + + + + + + + AB3 + Graphics Alpha Blending Control Register 3 + 0x28 + 32 + read-write + 0x00050010 + 0xFFFFFFFF + + + GRCHS + Horizontal start position of graphics image area. + 16 + 26 + read-write + + + 0x005 + 0x3ED + + + + + GRCHS + GRCHS lines. The valid range is 0x005 to 0x3ED. + true + + + + + GRCHW + Horizontal width of graphics image area. + 0 + 10 + read-write + + + 0x010 + 0x3F0 + + + + + GRCHW + GRCHW pixels. The valid range is 0x010 to 0x3F0. + true + + + + + + + AB4 + Graphics Alpha Blending Control Register 4 + 0x2C + 32 + read-write + 0x00060010 + 0xFFFFFFFF + + + ARCVS + Vertical start position of rectangular area alpha blending image area + 16 + 26 + read-write + + + 0x002 + 0x3EE + + + + + ARCVS + ARCVS linels. The valid range is 0x002 to 0x3EE. + true + + + + + ARCVW + Vertical width of rectangular area alpha blending image area. + 0 + 10 + read-write + + + 0x001 + 0x3FC + + + + + ARCVW + ARCVW linels. The valid range is 0x001 to 0x3F0. + true + + + + + + + AB5 + Graphics Alpha Blending Control Register 5 + 0x30 + 32 + read-write + 0x00050010 + 0xFFFFFFFF + + + ARCHS + Horizontal start position of rectangular area alpha blending image area. + 16 + 26 + read-write + + + 0x005 + 0x3ED + + + + + ARCHS + ARCHS pixel. The valid range is 0x005 to 0x3ED. + true + + + + + ARCHW + Horizontal width of rectangular area alpha blending image area. + 0 + 10 + read-write + + + 0x001 + 0x3F8 + + + + + ARCHW + ARCHW pixels. The valid range is 0x001 to 0x3F0. + true + + + + + + + AB6 + Graphics Alpha Blending Control Register 6 + 0x34 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ARCCOEF + + Alpha coefficient for alpha blending in rectangular area (-255 to 255). + [8]: Sign (0: addition, 1: subtraction) + [7:0]: Variation (absolute value) + + 16 + 24 + read-write + + + ARCRATE + Frame rate for alpha blending in rectangular area. + 0 + 7 + read-write + + + ARCRATE + ARCRATE+1 frames + true + + + + + + + AB7 + Graphics Alpha Blending Control Register 7 + 0x38 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ARCDEF + Initial alpha value for alpha blending in rectangular area. + 16 + 23 + read-write + + + CKON + RGB-index chroma-key processing control. + 0 + 0 + read-write + + + 1 + Enables chroma-key processing + #1 + + + 0 + Disables chroma-key processing + #0 + + + + + + + AB8 + Graphics Alpha Blending Control Register 8 + 0x3C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKKG + + G signal for RGB-index chroma-key processing + Unsigned; 8 bits. + + 16 + 23 + read-write + + + CKKB + + B signal for RGB-index chroma-key processing + Unsigned; 8 bits. + + 8 + 15 + read-write + + + CKKR + + R signal for RGB-index chroma-key processing + Unsigned; 8 bits. + + 0 + 7 + read-write + + + + + AB9 + Graphics Alpha Blending Control Register 9 + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKA + A value after RGB-index chroma-key processing replacement. + 24 + 31 + read-write + + + CKG + + G value after RGB-index chroma-key processing replacement + Unsigned; 8 bits. + + 16 + 23 + read-write + + + CKB + + B value after RGB-index chroma-key processing replacement + Unsigned; 8 bits. + + 8 + 15 + read-write + + + CKR + + R value after RGB-index chroma-key processing replacement + Unsigned; 8 bits. + + 0 + 7 + read-write + + + + + BASE + Graphics Background Color Control Register + 0x4C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + G + + Background color G value + Unsigned; 8 bits + + 16 + 23 + read-write + + + B + + Background color B value + Unsigned; 8 bits + + 8 + 15 + read-write + + + R + + Background color R value + Unsigned; 8 bits + + 0 + 7 + read-write + + + + + CLUTINT + Graphics CLUT Table Interrupt Control Register + 0x50 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEL + CLUT table control + 16 + 16 + read-write + + + 1 + Uses CLUT1 plane for internal operations. + #1 + + + 0 + Uses CLUT0 plane for internal operations. + #0 + + + others + Setting prohibited + true + + + + + LINE + Number of detection lines + 0 + 10 + read-write + + + 0x000 + 0x400 + + + + + LINE + LINE+1 lines. The valid range is 0x000 to 0x400. + true + + + + + + + MON + Graphics Status Monitor Register + 0x54 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + UNDFLST + Status monitor for underflow + 16 + 16 + read-only + + + 1 + An underflow occurs in internal operations. + #1 + + + 0 + No underflow occurs in internal operations. + #0 + + + + + ARCST + Status monitor for alpha blending in rectangular area + 0 + 0 + read-only + + + 1 + Fade-in/fade-out is in progress. + #1 + + + 0 + Fade-in/fade-out is not in progress. + #0 + + + + + + 3 - 0x2 - RTCCR[%s] - Time Capture Control Register - 0x40 + 0x40 + GAM[%s] + Gamma Settings + 0x1300 + + LATCH + Gamma Register Update Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VEN + + Control of gamma correction x module register value reflection to internal operations. + The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + + 0 + 0 + read-write + zeroToClear + modify + + + 1 + Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #1 + + + 0 + Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #0 + + + + + + + GAM_SW + Gamma Correction Block Function Switch Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + GAMON + Gamma correction on/off control + 0 + 0 + read-write + + + 1 + Turns on gamma correction. + #1 + + + 0 + Turns off gamma correction. + #0 + + + + + + + 8 + 0x04 + LUT[%s] + Gamma Correction Block Table Setting Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 2 + 16 + HIGH,LOW + _%s + + Gain value of area 0. + Unsigned 11-bit fixed point. + + 0 + 10 + read-write + + + GAIN00 + GAIN00/1024 + true + + + + + + + 5 + 0x04 + AREA[%s] + Gamma Correction Block Area Setting Register + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 3 + 10 + HIGH,MID,LOW + _%s + + Start threshold of area 1 + Unsigned 10-bit integer + + 0 + 9 + read-write + + + + + + OUT + Output Control Registers + 0x13C0 + + VLATCH + Output Control Block Register Update Control Register + 0x0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VEN + + Control of output control module register value reflection to internal operations. + The register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + + 0 + 0 + read-write + zeroToClear + modify + + + 1 + Enables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #1 + + + 0 + Disables the register values to be reflected to the internal operations at the assertion of the vertical synchronization signal (VS). + #0 + + + + + + + SET + Output Control Block Output Interface Register + 0x4 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ENDIANON + Bit endian change control + 28 + 28 + read-write + + + 1 + Ascending order (big endian) + #1 + + + 0 + Descending order (little endian) + #0 + + + + + SWAPON + Pixel order control + 24 + 24 + read-write + + + 1 + In the order of BGR + #1 + + + 0 + In the order of RGB + #0 + + + + + FORMAT + Output format select + 12 + 13 + read-write + + + 11 + Serial RGB; select RGB888 as dither output format. + #11 + + + 10 + RGB565; select RGB565 as dither output format. + #10 + + + 01 + RGB666; select RGB666 as dither output format. + #01 + + + 00 + RGB888; select RGB888 as dither output format. + #00 + + + + + FRQSEL + Clock frequency division control + 8 + 9 + read-write + + + 11 + Setting prohibited + #11 + + + 10 + Quarter frequency (serial RGB) + #10 + + + 01 + Setting prohibited + #01 + + + 00 + No frequency division, parallel RGB + #00 + + + + + DIRSEL + Invalid data position control in serial RGB format + 4 + 4 + read-write + + + 1 + Invalid data is output prior to valid (RGB) data. + #1 + + + 0 + Invalid data is output following valid (RGB) data. + #0 + + + + + PHASE + Data delay in serial RGB format (based on OUTCLK) + 0 + 1 + read-write + + + 11 + 3 cycles + #11 + + + 10 + 2 cycles + #10 + + + 01 + 1 cycle + #01 + + + 00 + 0 cycle + #00 + + + + + + + BRIGHT1 + Output Control Block Brightness Correction Register 1 + 0x8 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRTG + + Brightness (DC) adjustment of G signal + Unsigned; 10 bits; +512 with offset; integer + + 0 + 9 + read-write + + + + + BRIGHT2 + Output Control Block Brightness Correction Register 2 + 0xC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRTB + + Brightness (DC) adjustment of B signal + Unsigned; 10 bits; +512 with offset; integer + + 16 + 25 + read-write + + + BRTR + + Brightness (DC) adjustment of R signal + Unsigned; 10 bits; +512 with offset; integer + + 0 + 9 + read-write + + + + + CONTRAST + Output Control Block Contrast Correction Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CONTG + + Contrast (GAIN) adjustment of G signal + Unsigned; 8 bits fixed point. + + 16 + 23 + read-write + + + CONTG + CONTG/128 + true + + + + + CONTB + + Contrast (GAIN) adjustment of B signal + Unsigned; 8 bits fixed point + + 8 + 15 + read-write + + + CONTB + CONTB/128 + true + + + + + CONTR + + Contrast (GAIN) adjustment of R signal + Unsigned; 8 bits fixed point + + 0 + 7 + read-write + + + CONTR + CONTR/128 + true + + + + + - RTCCR - Time Capture Control Register - 0 - 8 + PDTHA + Output Control Block Panel Dither Correction Register + 0x14 + 32 read-write - 0x00 - 0x00 + 0x00000000 + 0xFFFFFFFF - TCNF - Time Capture Noise Filter Control - 4 - 5 + SEL + Operation mode + 20 + 21 read-write + + 11 + Setting prohibited + #11 + + + 10 + 2x2 pattern dither + #10 + + + 01 + Round-off + #01 + 00 - The noise filter is off. + Truncate #00 + + + + FORM + Output format select + 16 + 17 + read-write + + + 11 + Setting prohibited + #11 + + + 10 + RGB565; select RGB565 as output interface format. + #10 + 01 - Setting prohibited + RGB666; select RGB666 as output interface format. #01 - 10 - The noise filter is on (count source). - #10 + 00 + RGB888; select RGB888 or serial RGB as output interface format. + #00 + + + + + PA + + Pattern value (A) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 12 + 13 + read-write + + + PB + + Pattern value (B) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 8 + 9 + read-write + + + PC + + Pattern value (C) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 4 + 5 + read-write + + + PD + + Pattern value (D) of 2 x 2 pattern dither + Unsigned 2-bit integer + + 0 + 1 + read-write + + + + + CLKPHASE + Output Control Block Output Phase Control Register + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + FRONTGAM + Correction control + 12 + 12 + read-write + + + 1 + Gamma correction is followed by brightness/contrast correction. + #1 + + + 0 + Brightness/contrast correction is followed by gamma correction. + #0 + + + + + LCDEDGE + LCD_DATA Output Phase Control + 8 + 8 + read-write + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + 1 + In synchronization with the falling edge of LCD_CLK + #1 + + + + + TCON0EDGE + LCD_TCON0 Output Phase Control + 6 + 6 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + TCON1EDGE + LCD_TCON1 Output Phase Control + 5 + 5 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + TCON2EDGE + LCD_TCON2 Output Phase Control + 4 + 4 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + TCON3EDGE + LCD_TCON3 Output Phase Control + 3 + 3 + read-write + + + 1 + In synchronization with the falling edge of LCD_CLK. + #1 + + + 0 + In synchronization with the rising edge of LCD_CLK. + #0 + + + + + + + + TCON + Timing Control Registers + 0x1400 + + TIM + TCON Reference Timing Setting Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HALF + + Vertical synchronization signal generation change timing + Sets the delay from the assertion of the internal horizontal synchronization signal in terms of pixels. + + 16 + 26 + read-write + + + 0x000 + 0x3FF + + + + + HALF + HALF pixels. The valid range is 0x000 to 0x3FF. + true + + + + + OFFSET + + Horizontal synchronization signal generation reference timing + Sets the offset from the assertion of the internal horizontal synchronization signal in terms of pixels. + + 0 + 10 + read-write + + + 0x000 + 0x3FF + + + + + OFFSET + OFFSET+1 pixels. The valid range is 0x000 to 0x3FF. + true + + + + + + + 2 + 0x8 + A,B + STV%s1 + TCON Vertical Timing Setting Register %s1 + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VS + STVx1 first change timing + 16 + 26 + read-write + + + 0x000 + 0x7FF + + + + + VS + VS pixels. The valid range is 0x000 to 0x3FF. + true + + + + + VW + + STVx1 second change timing + Sets the signal assertion width. + + 0 + 10 + read-write + + + 0x000 + 0x7FF + + + + + VW + VW pixels. The valid range is 0x000 to 0x3FF. + true + + + + + + + 2 + 0x8 + A,B + STV%s2 + TCON Vertical Timing Setting Register %s2 + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + INV + STVx signal polarity inversion control + 4 + 4 + read-write + + + 1 + Inverted + #1 + + + 0 + Not inverted + #0 + + + + + SEL + Output signal select control for VSOUT (controlled by TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 register) pin + 0 + 2 + read-write + + + 111 + DE + #111 + + + 110 + Setting prohibited + #110 + + + 101 + Setting prohibited + #101 + + + 100 + Setting prohibited + #100 + + + 011 + STHB + #011 + + + 010 + STHA + #010 + + + 001 + STVB + #001 + + + 000 + STVA + #000 + + + + + + + 2 + 0x8 + A,B + STH%s1 + TCON Horizontal Timing Setting Register STH%s1 + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HS + STHx1 first change timing + 16 + 26 + read-write + + + 0x000 + 0x3FF + + + + + HS + HS lines. The valid range is 0x000 to 0x3FF. + true + + + + + HW + + STHx1 second change timing. + Sets the signal assertion width. + + 0 + 10 + read-write + + + 0x000 + 0x3FF + + + + + HW + HW pixels. The valid range is 0x000 to 0x3FF. + true + + + + + + + 2 + 0x8 + A,B + STH%s2 + TCON Horizontal Timing Setting Register STH%s2 + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSSEL + STHx signal generation reference timing control. + 8 + 8 + read-write + + + 1 + Reference timing is the offset set with the TCON_TIM.OFFSET[10:0] (horizontal synchronization generation reference timing) field + #1 - 11 - The noise filter is on (count source by divided by 32). - #11 + 0 + Reference timing is the input horizontal synchronization signal (HSIN) + #0 - TCST - Time Capture Status - 2 - 2 - read-only + INV + STVx signal polarity inversion control. + 4 + 4 + read-write - - 0 - No event is detected. - #0 - 1 - An event is detected. + Inverted #1 + + 0 + Not inverted + #0 + - TCCT - Time Capture Control + SEL + Output signal select control for LCD_TCON2 (controlled by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 register) pin. 0 - 1 + 2 read-write - 00 - No event is detected. - #00 + 111 + DE + #111 - 01 - Rising edge is detected. - #01 + 110 + Setting prohibited + #110 - 10 - Falling edge is detected. - #10 + 101 + Setting prohibited + #101 - 11 - Both edges are detected. - #11 + 100 + Setting prohibited + #100 + + + 011 + STHB + #011 + + + 010 + STHA + #010 + + + 001 + STVB + #001 + + + 000 + STVA + #000 - - - 3 - 0x10 - CP[%s] - Capture registers - 0x50 - RSEC - Second Capture Register - 0x02 - 8 - read-only - 0x00 - 0x00 + DE + TCON Data Enable Polarity Setting Register + 0x28 + 32 + read-write + 0x00000000 + 0xFFFFFFFF - SEC10 - 10-Second Capture Capture value for the tens place of seconds - 4 - 6 - read-only - - - SEC1 - 1-Second Capture Capture value for the ones place of seconds + INV + DE signal polarity inversion control. 0 - 3 - read-only + 0 + read-write + + + 1 + Inverted + #1 + + + 0 + Not inverted + #0 + + + + + SYSCNT + GLCDC System Control Registers + 0x1440 - BCNT0 - BCNT0 Capture Register - RSEC - 0x02 - 8 - read-only - 0x00 - 0x00 + DTCTEN + System control block State Detection Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF - BCNT0CP - BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. - 0 - 7 - read-only + L2UNDFDTC + Graphics 2 underflow detection control + 2 + 2 + read-write + + + 1 + Enables detection. + #1 + + + 0 + Disables detection. + #0 + + - - - - RMIN - Minute Capture Register - 0x04 - 8 - read-only - 0x00 - 0x00 - - MIN10 - 10-Minute Capture Capture value for the tens place of minutes - 4 - 6 - read-only + L1UNDFDTC + Graphics 1 underflow detection control + 1 + 1 + read-write + + + 1 + Enables detection. + #1 + + + 0 + Disables detection. + #0 + + - MIN1 - 1-Minute Capture Capture value for the ones place of minutes + VPOSDTC + Specified line detection control 0 - 3 - read-only + 0 + read-write + + + 1 + Enables detection. + #1 + + + 0 + Disables detection. + #0 + + - BCNT1 - BCNT1 Capture Register - RMIN + INTEN + System control block Interrupt Request Enable Control Register 0x04 - 8 - read-only - 0x00 - 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF - BCNT1CP - BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. + L2UNDFINTEN + Interrupt request signal GLCDC_L2UNDF enable control. + 2 + 2 + read-write + + + 1 + Enables GLCDC_L2UNDF output + #1 + + + 0 + Disables GLCDC_L2UNDF output + #0 + + + + + L1UNDFINTEN + Interrupt request signal GLCDC_L1UNDF enable control. + 1 + 1 + read-write + + + 1 + Enables GLCDC_L1UNDF output + #1 + + + 0 + Disables GLCDC_L1UNDF output + #0 + + + + + VPOSINTEN + Interrupt request signal GLCDC_VPOS enable control. 0 - 7 - read-only + 0 + read-write + + + 1 + Enables GLCDC_VPOS output + #1 + + + 0 + Disables GLCDC_VPOS output + #0 + + - RHR - Hour Capture Register - 0x06 - 8 - read-only - 0x00 - 0x00 + STCLR + System control block Status Clear Register + 0x08 + 32 + read-write + 0x00000000 + 0xFFFFFFFF - PM - A.m./p.m. select for time counter setting. - 6 - 6 - read-only + L2UNDFCLR + Graphics 2 underflow detection flag clear field + 2 + 2 + read-write + + 1 + Clears the graphics 2 underflow detection flag. + #1 + 0 - a.m. + No operation #0 + + + + L1UNDFCLR + Graphics 1 underflow detection flag clear field + 1 + 1 + read-write + 1 - p.m. + Clears the graphics 1 underflow detection flag. #1 + + 0 + No operation + #0 + - HR10 - 10-Minute Capture Capture value for the tens place of minutes - 4 - 5 - read-only - - - HR1 - 1-Minute Capture Capture value for the ones place of minutes + VPOSCLR + Graphics 2 specified line detection flag clear field 0 - 3 - read-only + 0 + read-write + + + 1 + Clears the specified line detection flag. + #1 + + + 0 + No operation + #0 + + - BCNT2 - BCNT2 Capture Register - RHR - 0x06 - 8 + STMON + System control block Status Monitor Register + 0x0c + 32 read-only - 0x00 - 0x00 + 0x00000000 + 0xFFFFFFFF - BCNT2CP - BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. - 0 - 7 + L2UNDF + Graphics 2 underflow detection flag + 2 + 2 read-only + + + 1 + An underflow has been detected in graphics 2. + #1 + + + 0 + No underflow has been detected in graphics 2. + #0 + + - - - - RDAY - Date Capture Register - 0x0A - 8 - read-only - 0x00 - 0x00 - - DATE10 - 10-Day Capture Capture value for the tens place of minutes - 4 - 5 + L1UNDF + Graphics 1 underflow detection flag + 1 + 1 read-only + + + 1 + An underflow has been detected in graphics 1. + #1 + + + 0 + No underflow has been detected in graphics 1. + #0 + + - DATE1 - 1-Day Capture Capture value for the ones place of minutes + VPOS + Graphics 2 specified line detection flag 0 - 3 + 0 read-only + + + 1 + A specified line notification has been detected in graphics 2. + #1 + + + 0 + No specified line notification has been detected in graphics 2. + #0 + + - BCNT3 - BCNT3 Capture Register - RDAY - 0x0A - 8 - read-only - 0x00 - 0x00 + PANEL_CLK + System control block Version and Panel Clock Control Register + 0x10 + 32 + read-write + 0x01000000 + 0xFFFFFFFF - BCNT3CP - BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. - 0 - 7 + VER + + Version information + Version information of the GLCDC + + 16 + 31 read-only - - - - RMON - Month Capture Register - 0x0C - 8 - read-only - 0x00 - 0x00 - - MON10 - 10-Month Capture Capture value for the tens place of months - 4 - 4 - read-only + PIXSEL + + Pixel clock select control. + Must be set to the same value as OUT_SET.FRQSEL[1]. + + 12 + 12 + read-write + + + 0 + No frequency division, parallel RGB + #0 + + + 1 + Quarter frequency,serial RGB + #1 + + + + + CLKSEL + Panel clock supply source select + 8 + 8 + read-write + + + 0 + External clock select + #0 + + + 1 + PLL output select + #1 + + + + + CLKEN + + Panel clock output enable control + Note: Before changing the PIXSEL,CLKSEL or DCDR bit, this bit must be set to 0. + + 6 + 6 + read-write + + + 0 + Disable panel clock output + #0 + + + 1 + Enable panel clock output + #1 + + - MON1 - 1-Month Capture Capture value for the ones place of months + DCDR + + Clock division ratio setting control + Refer toTable 2.7.1 for details about setting value. + Note: Settings that are not listed in table 2.7.1 are prohibited. + 0 - 3 - read-only + 5 + read-write - R64CNT - 64-Hz Counter - 0x00 - 8 - read-only - 0x00 - 0x80 + 256 + 0x4 + GR1_CLUT0[%s] + Color Palette 0 Plane for Graphics 1 Plane + 0x0000 + 32 + read-write + 0x00000000 + 0x00000000 + + + A + Alpha Blending Value of Color Palette n Plane for Graphics m Plane + 24 + 31 + read-write + + + R + R Value of Color Palette n Plane for Graphics m Plane + 16 + 23 + read-write + + + G + G Value of Color Palette n Plane for Graphics m Plane + 8 + 15 + read-write + + + B + B Value of Color Palette n Plane for Graphics m Plane + 0 + 7 + read-write + + + + + GR1_CLUT1[%s] + Color Palette 1 Plane for Graphics 1 Plane + 0x0400 + + + + GR2_CLUT0[%s] + Color Palette 0 Plane for Graphics 2 Plane + 0x0800 + + + + GR2_CLUT1[%s] + Color Palette 1 Plane for Graphics 2 Plane + 0x0C00 + + + + + + R_GPT0 + General PWM Timer + 0x40078000 + + 0x00000000 + 0x0A4 + registers + + + + GTWP + General PWM Timer Write-Protection Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PRKEY + GTWP Key Code + 8 + 15 + write-only + + + 0xA5 + Written to these bits, the WP bits write is permitted. + 0xA5 + + + others + The WP bits write is not permitted. + true + + + + + WP + Register Write Disable + 0 + 0 + read-write + + + 0 + Write to the register is enabled + #0 + + + 1 + Write to the register is disabled + #1 + + + + + STRWP + GTSTR.CSTRT Bit Write Disable + 1 + 1 + read-write + + + 0 + Write to the bit is enabled + #0 + + + 1 + Write to the bit is disabled + #1 + + + + + STPWP + GTSTP.CSTOP Bit Write Disable + 2 + 2 + read-write + + + 0 + Write to the bit is enabled + #0 + + + 1 + Write to the bit is disabled + #1 + + + + + CLRWP + GTCLR.CCLR Bit Write Disable + 3 + 3 + read-write + + + 0 + Write to the bit is enabled + #0 + + + 1 + Write to the bit is disabled + #1 + + + + + CMNWP + Common Register Write Disabled + 4 + 4 + read-write + + + 0 + Write to the register is enabled + #0 + + + 1 + Write to the register is disabled + #1 + + + + + + + GTSTR + General PWM Timer Software Start Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 14 + 1 + CSTRT%s + Channel GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. + 0 + 0 + read-write + + + 0 + No effect (write) / counter stop (read) + #0 + + + 1 + GTCNT counter starts (write) / Counter running (read) + #1 + + + + + + + GTSTP + General PWM Timer Software Stop Register + 0x08 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + 14 + 1 + CSTOP%s + Channel GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. + 0 + 0 + read-write + + + 0 + No effect (write) / counter running (read) + #0 + + + 1 + GPT GTCNT counter stops (write) / Counter stop (read) + #1 + + + + + + + GTCLR + General PWM Timer Software Clear Register + 0x0C + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + 14 + 1 + CCLR%s + Channel GTCNT Count Clear + 0 + 0 + write-only + + + 0 + No effect + #0 + + + 1 + GPT GTCNT counter clears + #1 + + + + + + + GTSSR + General PWM Timer Start Source Select Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSTRT + Software Source Counter Start Enable + 31 + 31 + read-write + + + 0 + Counter start is disable by the GTSTR register + #0 + + + 1 + Counter start is enable by the GTSTR register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + SSELC%s + ELC_GPT Event Source Counter Start Enable + 16 + 16 + read-write + + + 0 + Counter start is disable at the ELC_GPT input + #0 + + + 1 + Counter start is enable at the ELC_GPT input + #1 + + + + + SSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable + 15 + 15 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + SSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable + 14 + 14 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + SSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable + 13 + 13 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + SSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable + 12 + 12 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + SSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable + 11 + 11 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + SSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable + 10 + 10 + read-write + + + 0 + Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + SSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable + 9 + 9 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + SSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable + 8 + 8 + read-write + + + 0 + Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + SSGTRG%sF + GTETRG Pin Falling Input Source Counter Start Enable + 1 + 1 + read-write + + + 0 + Counter start is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter start is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + SSGTRG%sR + GTETRG Pin Rising Input Source Counter Start Enable + 0 + 0 + read-write + + + 0 + Counter start is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter start is enable at the rising edge of GTETRG input + #1 + + + + + + + GTPSR + General PWM Timer Stop Source Select Register + 0x14 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CSTOP + Software Source Counter Stop Enable + 31 + 31 + read-write + + + 0 + Counter stop is disable by the GTSTP register + #0 + + + 1 + Counter stop is enable by the GTSTP register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + PSELC%s + ELC_GPTA Event Source Counter Stop Enable + 16 + 16 + read-write + + + 0 + Counter stop is disable at the ELC_GPTA input + #0 + + + 1 + Counter stop is enable at the ELC_GPTA input + #1 + + + + + PSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable + 15 + 15 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + PSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable + 14 + 14 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + PSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable + 13 + 13 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + PSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable + 12 + 12 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + PSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable + 11 + 11 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + PSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable + 10 + 10 + read-write + + + 0 + Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + PSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable + 9 + 9 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + PSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable + 8 + 8 + read-write + + + 0 + Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + PSGTRG%sF + GTETRG Pin Falling Input Source Counter Stop Enable + 1 + 1 + read-write + + + 0 + Counter stop is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter stop is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + PSGTRG%sR + GTETRG Pin Rising Input Source Counter Stop Enable + 0 + 0 + read-write + + + 0 + Counter stop is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter stop is enable at the rising edge of GTETRG input + #1 + + + + + + + GTCSR + General PWM Timer Clear Source Select Register + 0x18 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CCLR + Software Source Counter Clear Enable + 31 + 31 + read-write + + + 0 + Counter clear is disable by the GTCLR register + #0 + + + 1 + Counter clear is enable by the GTCLR register + #1 + + + + + 8 + 1 + A,B,C,D,E,F,G,H + CSELC%s + ELC_GPTA Event Source Counter Clear Enable + 16 + 16 + read-write + + + 0 + Counter clear is disable at the ELC_GPTA input + #0 + + + 1 + Counter clear is enable at the ELC_GPTA input + #1 + + + + + CSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable + 15 + 15 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + CSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable + 14 + 14 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + CSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable + 13 + 13 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + CSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable + 12 + 12 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + CSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable + 11 + 11 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + CSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable + 10 + 10 + read-write + + + 0 + Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + CSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable + 9 + 9 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + CSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable + 8 + 8 + read-write + + + 0 + Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + CSGTRG%sF + GTETRG Pin Falling Input Source Counter Clear Enable + 1 + 1 + read-write + + + 0 + Counter clear is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter clear is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + CSGTRG%sR + GTETRG Pin Rising Input Source Counter Clear Enable + 0 + 0 + read-write + + + 0 + Counter clear is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter clear is enable at the rising edge of GTETRG input + #1 + + + + + + + GTUPSR + General PWM Timer Up Count Source Select Register + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + USELC%s + ELC_GPT Event Source Counter Count Up Enable + 16 + 16 + read-write + + + 0 + Counter count up is disable at the ELC_GPT input + #0 + + + 1 + Counter count up is enable at the ELC_GPT input + #1 + + + + + USCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable + 15 + 15 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + USCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable + 14 + 14 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + USCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable + 13 + 13 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + USCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable + 12 + 12 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + USCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable + 11 + 11 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + USCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable + 10 + 10 + read-write + + + 0 + Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + USCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable + 9 + 9 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + USCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable + 8 + 8 + read-write + + + 0 + Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + USGTRG%sF + GTETRG Pin Falling Input Source Counter Count Up Enable + 1 + 1 + read-write + + + 0 + Counter count up is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter count up is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + USGTRG%sR + GTETRG Pin Rising Input Source Counter Count Up Enable + 0 + 0 + read-write + + + 0 + Counter count up is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter count up is enable at the rising edge of GTETRG input + #1 + + + + + + + GTDNSR + General PWM Timer Down Count Source Select Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + 8 + 1 + A,B,C,D,E,F,G,H + DSELC%s + ELC_GPT Event Source Counter Count Down Enable + 16 + 16 + read-write + + + 0 + Counter count down is disable at the ELC_GPT input + #0 + + + 1 + Counter count down is enable at the ELC_GPT input + #1 + + + + + DSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable + 15 + 15 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + DSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable + 14 + 14 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + DSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable + 13 + 13 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + + + + DSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable + 12 + 12 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + + + + DSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable + 11 + 11 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + DSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable + 10 + 10 + read-write + + + 0 + Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + DSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable + 9 + 9 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + DSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable + 8 + 8 + read-write + + + 0 + Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + DSGTRG%sF + GTETRG Pin Falling Input Source Counter Count Down Enable + 1 + 1 + read-write + + + 0 + Counter count down is disable at the falling edge of GTETRG input + #0 + + + 1 + Counter count down is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + DSGTRG%sR + GTETRG Pin Rising Input Source Counter Count Down Enable + 0 + 0 + read-write + + + 0 + Counter count down is disable at the rising edge of GTETRG input + #0 + + + 1 + Counter count down is enable at the rising edge of GTETRG input + #1 + + + + + + + GTICASR + General PWM Timer Input Capture Source Select Register A + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF - F1HZ - 1Hz - 6 - 6 - read-only + 8 + 1 + A,B,C,D,E,F,G,H + ASELC%s + ELC_GPT Event Source GTCCRA Input Capture Enable + 16 + 16 + read-write + + + 0 + GTCCRA input capture is disable at the ELC_GPT input + #0 + + + 1 + GTCCRA input capture is enable at the ELC_GPT input + #1 + + - F2HZ - 2Hz - 5 - 5 - read-only + ASCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable + 15 + 15 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + - F4HZ - 4Hz - 4 - 4 - read-only + ASCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable + 14 + 14 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + - F8HZ - 8Hz - 3 - 3 - read-only + ASCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable + 13 + 13 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + - F16HZ - 16Hz - 2 - 2 - read-only + ASCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable + 12 + 12 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + - F32HZ - 32Hz + ASCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable + 11 + 11 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + ASCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable + 10 + 10 + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + ASCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable + 9 + 9 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + ASCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable + 8 + 8 + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + + + + 4 + 2 + A,B,C,D + ASGTRG%sF + GTETRG Pin Falling Input Source GTCCRA Input Capture Enable 1 1 - read-only + read-write + + + 0 + GTCCRA input capture is disable at the falling edge of GTETRG input + #0 + + + 1 + GTCCRA input capture is enable at the falling edge of GTETRG input + #1 + + - F64HZ - 64Hz + 4 + 2 + A,B,C,D + ASGTRG%sR + GTETRG Pin Rising Input Source GTCCRA Input Capture Enable 0 0 - read-only + read-write + + + 0 + GTCCRA input capture is disable at the rising edge of GTETRG input + #0 + + + 1 + GTCCRA input capture is enable at the rising edge of GTETRG input + #1 + + - RSECCNT - Second Counter - 0x02 - 8 + GTICBSR + General PWM Timer Input Capture Source Select Register B + 0x28 + 32 read-write - 0x00 - 0x00 + 0x00000000 + 0xFFFFFFFF - SEC10 - 10-Second Count Counts from 0 to 5 for 60-second counting. - 4 - 6 + 8 + 1 + A,B,C,D,E,F,G,H + BSELC%s + ELC_GPT Event Source GTCCRB Input Capture Enable + 16 + 16 read-write + + + 0 + GTCCRB input capture is disable at the ELC_GPT input + #0 + + + 1 + GTCCRB input capture is enable at the ELC_GPT input + #1 + + - SEC1 - 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place. - 0 - 3 + BSCBFAH + GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable + 15 + 15 read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 + #1 + + - - - - BCNT0 - Binary Counter 0 - RSECCNT - 0x02 - 8 - read-write - 0x00 - 0x00 - - BCNT0 - The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0. - 0 - 7 + BSCBFAL + GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable + 14 + 14 read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 + #1 + + - - - - RMINCNT - Minute Counter - 0x04 - 8 - read-write - 0x00 - 0x00 - - MIN10 - 10-Minute Count Counts from 0 to 5 for 60-minute counting. - 4 - 6 + BSCBRAH + GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable + 13 + 13 read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 + #1 + + - MIN1 - 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. - 0 - 3 + BSCBRAL + GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable + 12 + 12 read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 + #1 + + - - - - BCNT1 - Binary Counter 1 - RMINCNT - 0x04 - 8 - read-write - 0x00 - 0x00 - - BCNT1 - The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8. - 0 - 7 + BSCAFBH + GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable + 11 + 11 read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 + #1 + + - - - - RHRCNT - Hour Counter - 0x06 - 8 - read-write - 0x00 - 0x00 - - PM - Time Counter Setting for a.m./p.m. - 6 - 6 + BSCAFBL + GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable + 10 + 10 read-write 0 - a.m. + GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 - p.m. + GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 - HR10 - 10-Hour Count Counts from 0 to 2 once per carry from the ones place. - 4 - 5 + BSCARBH + GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable + 9 + 9 + read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 + #1 + + + + + BSCARBL + GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable + 8 + 8 read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 + #1 + + - HR1 - 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place. + 4 + 2 + A,B,C,D + BSGTRG%sF + GTETRG Pin Falling Input Source GTCCRB Input Capture Enable + 1 + 1 + read-write + + + 0 + GTCCRB input capture is disable at the falling edge of GTETRG input + #0 + + + 1 + GTCCRB input capture is enable at the falling edge of GTETRG input + #1 + + + + + 4 + 2 + A,B,C,D + BSGTRG%sR + GTETRG Pin Rising Input Source GTCCRB Input Capture Enable 0 - 3 + 0 read-write + + + 0 + GTCCRB input capture is disable at the rising edge of GTETRG input + #0 + + + 1 + GTCCRB input capture is enable at the rising edge of GTETRG input + #1 + + - BCNT2 - Binary Counter 2 - RHRCNT - 0x06 - 8 + GTCR + General PWM Timer Control Register + 0x2C + 32 read-write - 0x00 - 0x00 + 0x00000000 + 0xFFFFFFFF - BCNT2 - The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16. - 0 - 7 + TPCS + Timer Prescaler Select + 23 + 26 read-write + + + 0000 + PCLK/1 + #0000 + + + 0001 + PCLK/2 + #0001 + + + 0010 + PCLK/4 + #0010 + + + 0011 + PCLK/8 + #0011 + + + 0100 + PCLK/16 + #0100 + + + 0101 + PCLK/32 + #0101 + + + 0110 + PCLK/64 + #0110 + + + 1000 + PCLK/256 + #1000 + + + 1010 + PCLK/1024 + #1010 + + + 1100 + GTETRGA + #1100 + + + 1101 + GTETRGB + #1101 + + + 1110 + GTETRGC + #1110 + + + 1111 + GTETRGD + #1111 + + + others + Setting prohibied + true + + - - - - RWKCNT - Day-of-Week Counter - 0x08 - 8 - read-write - 0x00 - 0x00 - - DAYW - Day-of-Week Counting - 0 - 2 + MD + Mode Select + 16 + 18 read-write 000 - Sunday + Saw-wave PWM mode (single buffer or double buffer possible) #000 001 - Monday + Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 - Tuesday + Setting prohibited #010 011 - Wednesday + Setting prohibited #011 100 - Thursday + Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 - Friday + Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 - Saturday + Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 - Setting Prohibited + Setting prohibited #111 - - - - BCNT3 - Binary Counter 3 - RWKCNT - 0x08 - 8 - read-write - 0x00 - 0x00 - - - BCNT3 - The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24. - 0 - 7 - read-write - - - - - RDAYCNT - Day Counter - 0x0A - 8 - read-write - 0x00 - 0xC0 - - - DATE10 - 10-Day Count Counts from 0 to 3 once per carry from the ones place. - 4 - 5 - read-write - - - DATE1 - 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. - 0 - 3 - read-write - - - - - RMONCNT - Month Counter - 0x0C - 8 - read-write - 0x00 - 0xE0 - - - MON10 - 10-Month Count Counts from 0 to 1 once per carry from the ones place. - 4 - 4 - read-write - - - MON1 - 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. - 0 - 3 - read-write - - - - - RYRCNT - Year Counter - 0x0E - 16 - read-write - 0x0000 - 0xFF00 - - - YR10 - 10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place. - 4 - 7 - read-write - - YR1 - 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place. + CST + Count Start 0 - 3 + 0 read-write + + + 0 + Count operation is stopped + #0 + + + 1 + Count operation is performed + #1 + + - RSECAR - Second Alarm Register - 0x10 - 8 + GTUDDTYC + General PWM Timer Count Direction and Duty Setting Register + 0x30 + 32 read-write - 0x00 - 0x00 + 0x00000001 + 0xFFFFFFFF - ENB - Compare enable - 7 - 7 + OBDTYR + GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + 27 + 27 read-write 0 - The register value is not compared with the RSECCNT counter value. + Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 - The register value is compared with the RSECCNT counter value. + Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 - SEC10 - 10-Seconds Value for the tens place of seconds - 4 - 6 + OBDTYF + Forcible GTIOCB Output Duty Setting + 26 + 26 read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + - SEC1 - 1-Second Value for the ones place of seconds - 0 - 3 - write-only - - - - - BCNT0AR - Binary Counter 0 Alarm Register - RSECAR - 0x10 - 8 - read-write - 0x00 - 0x00 - - - BCNT0AR - he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0. - 0 - 7 + OBDTY + GTIOCB Output Duty Setting + 24 + 25 read-write + + + 00 + GTIOCB pin duty is depend on compare match + #00 + + + 01 + GTIOCB pin duty is depend on compare match + #01 + + + 10 + GTIOCB pin duty 0 percent + #10 + + + 11 + GTIOCB pin duty 100 percent + #11 + + - - - - RMINAR - Minute Alarm Register - 0x12 - 8 - read-write - 0x00 - 0x00 - - ENB - Compare enable - 7 - 7 + OADTYR + GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting + 19 + 19 read-write 0 - The register value is not compared with the RMINCNT counter value. + Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 - The register value is compared with the RMINCNT counter value. + Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 - MIN10 - 10-Minute Count Value for the tens place of minutes - 4 - 6 - read-write - - - MIN1 - 1-Minute Count Value for the ones place of minutes - 0 - 3 + OADTYF + Forcible GTIOCA Output Duty Setting + 18 + 18 read-write + + + 0 + Not forcibly set + #0 + + + 1 + Forcibly set + #1 + + - - - - BCNT1AR - Binary Counter 1 Alarm Register - RMINAR - 0x12 - 8 - read-write - 0x00 - 0x00 - - BCNT1AR - he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8. - 0 - 7 + OADTY + GTIOCA Output Duty Setting + 16 + 17 read-write + + + 00 + GTIOCA pin duty is depend on compare match + #00 + + + 01 + GTIOCA pin duty is depend on compare match + #01 + + + 10 + GTIOCA pin duty 0 percent + #10 + + + 11 + GTIOCA pin duty 100 percent + #11 + + - - - - RHRAR - Hour Alarm Register - 0x14 - 8 - read-write - 0x00 - 0x00 - - ENB - Compare enable - 7 - 7 + UDF + Forcible Count Direction Setting + 1 + 1 read-write 0 - The register value is not compared with the RHRCNT counter value. + Not forcibly set #0 1 - The register value is compared with the RHRCNT counter value. + Forcibly set #1 - PM - Time Counter Setting for a.m./p.m. - 6 - 6 + UD + Count Direction Setting + 0 + 0 read-write 0 - a.m. + GTCNT counts down. #0 1 - p.m. + GTCNT counts up. #1 - - HR10 - 10-Hour Count Value for the tens place of hours - 4 - 5 - read-write - - - HR1 - 1-Hour Count Value for the ones place of hours - 0 - 3 - read-write - - BCNT2AR - Binary Counter 2 Alarm Register - RHRAR - 0x14 - 8 + GTIOR + General PWM Timer I/O Control Register + 0x34 + 32 read-write - 0x00 - 0x00 + 0x00000000 + 0xFFFFFFFF - BCNT2AR - The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16. - 0 - 7 + NFCSB + Noise Filter B Sampling Clock Select + 30 + 31 read-write + + + 00 + PCLK/1 + #00 + + + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 + + - - - - RWKAR - Day-of-Week Alarm Register - 0x16 - 8 - read-write - 0x00 - 0x00 - - ENB - Compare enable - 7 - 7 + NFBEN + Noise Filter B Enable + 29 + 29 read-write 0 - The register value is not compared with the RWKCNT counter value. + The noise filter for the GTIOCB pin is disabled. #0 1 - The register value is compared with the RWKCNT counter value. + The noise filter for the GTIOCB pin is enabled. #1 - DAYW - Day-of-Week Counting - 0 - 2 + OBDF + GTIOCB Pin Disable Value Setting + 25 + 26 read-write - 000 - Sunday - #000 - - - 001 - Monday - #001 - - - 010 - Tuesday - #010 - - - 011 - Wednesday - #011 - - - 100 - Thursday - #100 + 00 + Output disable is prohibited. + #00 - 101 - Friday - #101 + 01 + GTIOCB pin is set to Hi-Z when output disable is performed. + #01 - 110 - Saturday - #110 + 10 + GTIOCB pin is set to 0 when output disable is performed. + #10 - 111 - Setting Prohibited - #111 + 11 + GTIOCB pin is set to 1 when output disable is performed. + #11 - - - - BCNT3AR - Binary Counter 3 Alarm Register - RWKAR - 0x16 - 8 - read-write - 0x00 - 0x00 - - - BCNT3AR - The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24. - 0 - 7 - read-write - - - - - RDAYAR - Date Alarm Register - 0x18 - 8 - read-write - 0x00 - 0x00 - - ENB - Compare enable - 7 - 7 + OBE + GTIOCB Pin Output Enable + 24 + 24 read-write 0 - The register value is not compared with the RDAYCNT counter value. + Output is disabled #0 1 - The register value is compared with the RDAYCNT counter value. + Output is enabled #1 - DATE10 - 10 Days Value for the tens place of days - 4 - 5 - read-write - - - DATE1 - 1 Day Value for the ones place of days - 0 - 3 - read-write - - - - - BCNT0AER - Binary Counter 0 Alarm Enable Register - RDAYAR - 0x18 - 8 - read-write - 0x00 - 0x00 - - - ENB - The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0. - 0 - 7 - read-write - - - - - RMONAR - Month Alarm Register - 0x1A - 8 - read-write - 0x00 - 0x00 - - - ENB - Compare enable - 7 - 7 + OBHLD + GTIOCB Pin Output Setting at the Start/Stop Count + 23 + 23 read-write 0 - The register value is not compared with the RMONCNT counter value. + The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 - The register value is compared with the RMONCNT counter value. + The GTIOCB pin output level is retained at start/stop of counting. #1 - MON10 - 10 Months Value for the tens place of months - 4 - 4 - read-write - - - MON1 - 1 Month Value for the ones place of months - 0 - 3 - read-write - - - - - BCNT1AER - Binary Counter 1 Alarm Enable Register - RMONAR - 0x1A - 8 - read-write - 0x00 - 0x00 - - - ENB - The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8. - 0 - 7 - read-write - - - - - RYRAR - Year Alarm Register - 0x1C - 16 - read-write - 0x0000 - 0xFF00 - - - YR10 - 10 Years Value for the tens place of years - 4 - 7 - read-write - - - YR1 - 1 Year Value for the ones place of years - 0 - 3 - read-write - - - - - BCNT2AER - Binary Counter 2 Alarm Enable Register - RYRAR - 0x1C - 16 - read-write - 0x0000 - 0xFF00 - - - ENB - The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16. - 0 - 7 - read-write - - - - - RYRAREN - Year Alarm Enable Register - 0x1E - 8 - read-write - 0x00 - 0x00 - - - ENB - Compare enable - 7 - 7 + OBDFLT + GTIOCB Pin Output Value Setting at the Count Stop + 22 + 22 read-write 0 - The register value is not compared with the RYRCNT counter value. + The GTIOCB pin outputs low when counting is stopped. #0 1 - The register value is compared with the RYRCNT counter value. + The GTIOCB pin outputs high when counting is stopped. #1 - - - - BCNT3AER - Binary Counter 3 Alarm Enable Register - RYRAREN - 0x1E - 8 - read-write - 0x00 - 0x00 - - - ENB - The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. - 0 - 7 - read-write - - - - - RCR1 - RTC Control Register 1 - 0x22 - 8 - read-write - 0x00 - 0x0A - - PES - Periodic Interrupt Select - 4 - 7 + GTIOB + GTIOCB Pin Function Select + 16 + 20 read-write - 0110 - A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1). - #0110 + 00000 + Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. + #00000 - 0111 - A periodic interrupt is generated every 1/128 second. - #0111 + 00001 + Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. + #00001 - 1000 - A periodic interrupt is generated every 1/64 second. - #1000 + 00010 + Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. + #00010 - 1001 - A periodic interrupt is generated every 1/32 second. - #1001 + 00011 + Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. + #00011 - 1010 - A periodic interrupt is generated every 1/16 second. - #1010 + 00100 + Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. + #00100 - 1011 - A periodic interrupt is generated every 1/8 second. - #1011 + 00101 + Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. + #00101 - 1100 - A periodic interrupt is generated every 1/4 second. - #1100 + 00110 + Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. + #00110 - 1101 - A periodic interrupt is generated every 1/2 second. - #1101 + 00111 + Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. + #00111 - 1110 - A periodic interrupt is generated every 1 second. - #1110 + 01000 + Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. + #01000 - 1111 - A periodic interrupt is generated every 2 seconds. - #1111 + 01001 + Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. + #01001 - others - No periodic interrupts are generated. - true + 01010 + Initial output is Low. High output at cycle end. High output at GTCCRB compare match. + #01010 + + + 01011 + Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. + #01011 + + + 01100 + Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. + #01100 + + + 01101 + Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. + #01101 + + + 01110 + Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. + #01110 + + + 01111 + Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. + #01111 + + + 10000 + Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. + #10000 + + + 10001 + Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. + #10001 + + + 10010 + Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. + #10010 + + + 10011 + Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. + #10011 + + + 10100 + Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. + #10100 + + + 10101 + Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. + #10101 + + + 10110 + Initial output is High. Low output at cycle end. High output at GTCCRB compare match. + #10110 + + + 10111 + Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. + #10111 + + + 11000 + Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. + #11000 + + + 11001 + Initial output is High. High output at cycle end. Low output at GTCCRB compare match. + #11001 + + + 11010 + Initial output is High. High output at cycle end. High output at GTCCRB compare match. + #11010 + + + 11011 + Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. + #11011 + + + 11100 + Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. + #11100 + + + 11101 + Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. + #11101 + + + 11110 + Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. + #11110 + + + 11111 + Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. + #11111 - RTCOS - RTCOUT Output Select - 3 - 3 + NFCSA + Noise Filter A Sampling Clock Select + 14 + 15 read-write - 0 - RTCOUT outputs 1 Hz. - #0 + 00 + PCLK/1 + #00 - 1 - RTCOUT outputs 64 Hz. - #1 + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 - PIE - Periodic Interrupt Enable - 2 - 2 + NFAEN + Noise Filter A Enable + 13 + 13 read-write 0 - A periodic interrupt request is disabled. + The noise filter for the GTIOCA pin is disabled. #0 1 - A periodic interrupt request is enabled. + The noise filter for the GTIOCA pin is enabled. #1 - CIE - Carry Interrupt Enable - 1 - 1 + OADF + GTIOCA Pin Disable Value Setting + 9 + 10 read-write - 0 - A carry interrupt request is disabled. - #0 + 00 + Output disable is prohibited. + #00 - 1 - A carry interrupt request is enabled. - #1 + 01 + GTIOCA pin is set to Hi-Z when output disable is performed. + #01 + + + 10 + GTIOCA pin is set to 0 when output disable is performed. + #10 + + + 11 + GTIOCA pin is set to 1 when output disable is performed. + #11 - AIE - Alarm Interrupt Enable - 0 - 0 + OAE + GTIOCA Pin Output Enable + 8 + 8 read-write 0 - An alarm interrupt request is disabled. + Output is disabled #0 1 - An alarm interrupt request is enabled. + Output is enabled #1 - - - - RCR2 - RTC Control Register 2 - 0x24 - 8 - read-write - 0x00 - 0x0E - - CNTMD - Count Mode Select + OAHLD + GTIOCA Pin Output Setting at the Start/Stop Count 7 7 read-write 0 - The calendar count mode. + The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 - The binary count mode. + The GTIOCA pin output level is retained at start/stop of counting. #1 - HR24 - Hours Mode + OADFLT + GTIOCA Pin Output Value Setting at the Count Stop 6 6 read-write 0 - The RTC operates in 12-hour mode. + The GTIOCA pin outputs low when counting is stopped. #0 1 - The RTC operates in 24-hour mode. + The GTIOCA pin outputs high when counting is stopped. #1 - AADJP - Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.) - 5 - 5 + GTIOA + GTIOCA Pin Function Select + 0 + 4 read-write - 0 - The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute. - #0 + 00000 + Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. + #00000 - 1 - The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds. - #1 + 00001 + Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. + #00001 - - - - AADJE - Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.) - 4 - 4 - read-write - - 0 - Automatic adjustment is disabled. - #0 + 00010 + Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. + #00010 - 1 - Automatic adjustment is enabled. - #1 + 00011 + Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. + #00011 - - - - RTCOE - RTCOUT Output Enable - 3 - 3 - read-write - - 0 - RTCOUT output disabled. - #0 + 00100 + Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. + #00100 - 1 - RTCOUT output enabled. - #1 + 00101 + Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. + #00101 - - - - ADJ30 - 30-Second Adjustment - 2 - 2 - read-write - - 0 - Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read) - #0 + 00110 + Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. + #00110 - 1 - 30-second adjustment is executed.(write) / During 30-second adjustment.(read) - #1 + 00111 + Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. + #00111 - - - - RESET - RTC Software Reset - 1 - 1 - read-write - - 0 - Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read) - #0 + 01000 + Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. + #01000 - 1 - The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read) - #1 + 01001 + Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. + #01001 - - - - START - Start - 0 - 0 - read-write - - 0 - Prescaler and time counter are stopped. - #0 + 01010 + Initial output is Low. High output at cycle end. High output at GTCCRA compare match. + #01010 - 1 - Prescaler and time counter operate normally. - #1 + 01011 + Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. + #01011 - - - - - - RCR4 - RTC Control Register 4 - 0x28 - 8 - read-write - 0x00 - 0xFE - - - RCKSEL - Count Source Select - 0 - 0 - read-write - - 0 - Sub-clock oscillator is selected. - #0 + 01100 + Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. + #01100 - 1 - LOCO clock oscillator is selected. - #1 + 01101 + Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. + #01101 - - - - ROPSEL - RTC Operation Mode Select - 7 - 7 - read-write - - 0 - Normal operation mode is selected. - #0 + 01110 + Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. + #01110 - 1 - Low-consumption clock mode is selected. - #1 + 01111 + Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. + #01111 - - - - - - RFRH - Frequency Register H - 0x2A - 16 - read-write - 0x0000 - 0xFFFE - - - RFC16 - Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle. - 0 - 0 - read-write - - - - - RFRL - Frequency Register L - 0x2C - 16 - read-write - 0x0000 - 0x0000 - - - RFC - Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle. - 0 - 15 - read-write - - - - - RADJ - Time Error Adjustment Register - 0x2E - 8 - read-write - 0x00 - 0x00 - - - PMADJ - Plus-Minus - 6 - 7 - read-write - - 00 - Adjustment is not performed. - #00 + 10000 + Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. + #10000 - 01 - Adjustment is performed by the addition to the prescaler. - #01 + 10001 + Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. + #10001 - 10 - Adjustment is performed by the subtraction from the prescaler. - #10 + 10010 + Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. + #10010 - 11 - Setting prohibited - #11 + 10011 + Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. + #10011 + + + 10100 + Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. + #10100 + + + 10101 + Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. + #10101 + + + 10110 + Initial output is High. Low output at cycle end. High output at GTCCRA compare match. + #10110 + + + 10111 + Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. + #10111 + + + 11000 + Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. + #11000 + + + 11001 + Initial output is High. High output at cycle end. Low output at GTCCRA compare match. + #11001 + + + 11010 + Initial output is High. High output at cycle end. High output at GTCCRA compare match. + #11010 + + + 11011 + Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. + #11011 + + + 11100 + Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. + #11100 + + + 11101 + Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. + #11101 + + + 11110 + Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. + #11110 + + + 11111 + Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. + #11111 - - ADJ - Adjustment Value These bits specify the adjustment value from the prescaler. - 0 - 5 - read-write - - - - - R_SCI0 - Serial Communications Interface - 0x40070000 - - 0x00000000 - 0x01D - registers - - - SMR - Serial Mode Register (SCMR.SMIF = 0) - 0x00 - 8 + GTINTAD + General PWM Timer Interrupt Output Setting Register + 0x38 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xFFFFFFFF - CM - Communication Mode - 7 - 7 + GRPABL + Same Time Output Level Low Disable Request Enable + 30 + 30 read-write 0 - Asynchronous mode or simple I2C mode + Same time output level low disable request is disabled. #0 1 - Clock synchronous mode + Same time output level low disable request is enabled. #1 - CHR - Character Length(Valid only in asynchronous mode) - 6 - 6 + GRPABH + Same Time Output Level High Disable Request Enable + 29 + 29 read-write 0 - Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) + Same time output level high disable request is disabled. #0 1 - Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) + Same time output level high disable request is enabled. #1 - PE - Parity Enable(Valid only in asynchronous mode) - 5 - 5 + GRPDTE + Dead Time Error Output Disable Request Enable + 28 + 28 read-write 0 - Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) + Disable dead time error output disable request #0 1 - The parity bit is added (transmitting) / The parity bit is checked (receiving) + Enable dead time error output disable request #1 - PM - Parity Mode (Valid only when the PE bit is 1) - 4 - 4 + GRP + Output Disable Source Select + 24 + 25 read-write - 0 - Selects even parity - #0 + 00 + Group A output disable request + #00 - 1 - Selects odd parity - #1 + 01 + Group B output disable request + #01 + + + 10 + Group C output disable request + #10 + + + 11 + Group D output disable request + #11 + + + others + Setting prohibited + true - STOP - Stop Bit Length(Valid only in asynchronous mode) - 3 - 3 + GTINTPC + Period Count Function Finish Interrupt Enable + 31 + 31 read-write 0 - 1 stop bit + Interrupt request is disabled #0 1 - 2 stop bits + Interrupt request is enabled #1 + + + + GTST + General PWM Timer Status Register + 0x3C + 32 + read-write + 0x00008000 + 0xFFFFFFFF + - MP - Multi-Processor Mode(Valid only in asynchronous mode) - 2 - 2 - read-write + OABLF + Same Time Output Level Low Disable Request Enable + 30 + 30 + read-only 0 - Multi-processor communications function is disabled + GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 - Multi-processor communications function is enabled + GTIOCA pin and GTIOCB pin output 0 at the same time. #1 - CKS - Clock Select - 0 - 1 - read-write + OABHF + Same Time Output Level High Disable Request Enable + 29 + 29 + read-only - 00 - PCLK clock - #00 - - - 01 - PCLK/4 clock - #01 - - - 10 - PCLK/16 clock - #10 + 0 + GTIOCA pin and GTIOCB pin don't output 1 at the same time. + #0 - 11 - PCLK/64 clock - #11 + 1 + GTIOCA pin and GTIOCB pin output 1 at the same time. + #1 - - - - SMR_SMCI - Serial mode register (SCMR.SMIF = 1) - SMR - 0x00 - 8 - read-write - 0x00 - 0xFF - - GM - GSM Mode - 7 - 7 - read-write + DTEF + Dead Time Error Flag + 28 + 28 + read-only 0 - Normal mode operation + No dead time error has occurred. #0 1 - GSM mode operation + A dead time error has occurred. #1 - BLK - Block Transfer Mode - 6 - 6 - read-write + ODF + Output Disable Flag + 24 + 24 + read-only 0 - Normal mode operation + No output disable request is generated. #0 1 - Block transfer mode operation + An output disable request is generated. #1 - PE - Parity Enable(Valid only in asynchronous mode) - 5 - 5 + ADTRBDF + GTADTRB Compare Match(Down-Counting) A/D Convertor Start Request Flag + 19 + 19 read-write 0 - Setting Prohibited + No compare match of GTADTRB at down-counting is generated. #0 1 - Set this bit to 1 in smart card interface mode. + A compare match of GTADTRB at down-counting is generated. #1 - PM - Parity Mode (Valid only when the PE bit is 1) - 4 - 4 + ADTRBUF + GTADTRB Compare Match(Up-Counting) A/D Convertor Start Request Flag + 18 + 18 read-write 0 - Selects even parity + No compare match of GTADTRB at up-counting is generated. #0 1 - Selects odd parity + A compare match of GTADTRB at up-counting is generated. #1 - BCP - Base Clock Pulse(Valid only in asynchronous mode) - 2 - 3 + ADTRADF + GTADTRA Compare Match(Down-Counting) A/D Convertor Start Request Flag + 17 + 17 read-write - 00 - 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) - #00 - - - 01 - 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) - #01 - - - 10 - 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) - #10 + 0 + No compare match of GTADTRA at down-counting is generated. + #0 - 11 - 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) - #11 + 1 + A compare match of GTADTRA at down-counting is generated. + #1 - CKS - Clock Select - 0 - 1 + ADTRAUF + GTADTRA Compare Match (Up-Counting) A/D Converter Start Request Interrupt Enable + 16 + 16 read-write - 00 - PCLK clock - #00 + 0 + No compare match of GTADTRA at up-counting is generated. + #0 - 01 - PCLK/4 clock - #01 + 1 + A compare match of GTADTRA at up-counting is generated. + #1 + + + + TUCF + Count Direction Flag + 15 + 15 + read-only + - 10 - PCLK/16 clock - #10 + 0 + The GTCNT counter counts downward. + #0 - 11 - PCLK/64 clock - #11 + 1 + The GTCNT counter counts upward. + #1 - - - - BRR - Bit Rate Register - 0x01 - 8 - read-write - 0xFF - 0xFF - - BRR - BRR is an 8-bit register that adjusts the bit rate. - 0 - 7 - read-write + ITCNT + GTCIV/GTCIU Interrupt Skipping Count Counter(Counter for counting the number of times a timer interrupt has been skipped.) + 8 + 10 + read-only - - - - SCR - Serial Control Register (SCMR.SMIF = 0) - 0x02 - 8 - read-write - 0x00 - 0xFF - - TIE - Transmit Interrupt Enable + TCFPU + Underflow Flag 7 7 read-write 0 - SCI_TXI interrupt request is disabled + No underflow (trough) has occurred. #0 1 - SCI_TXI interrupt request is enabled + An underflow (trough) has occurred. #1 - RIE - Receive Interrupt Enable + TCFPO + Overflow Flag 6 6 read-write 0 - SCI_RXI and SCI_ERI interrupt requests are disabled + No overflow (crest) has occurred. #0 1 - SCI_RXI and SCI_ERI interrupt requests are enabled + An overflow (crest) has occurred. #1 - TE - Transmit Enable + TCFF + Input Compare Match Flag F 5 5 read-write 0 - Serial transmission is disabled + No compare match of GTCCRF is generated. #0 1 - Serial transmission is enabled + A compare match of GTCCRF is generated. #1 - RE - Receive Enable + TCFE + Input Compare Match Flag E 4 4 read-write 0 - Serial reception is disabled + No compare match of GTCCRE is generated. #0 1 - Serial reception is enabled + A compare match of GTCCRE is generated. #1 - MPIE - Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) + TCFD + Input Compare Match Flag D 3 3 read-write 0 - Normal reception + No compare match of GTCCRD is generated. #0 1 - When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. + A compare match of GTCCRD is generated. #1 - TEIE - Transmit End Interrupt Enable + TCFC + Input Compare Match Flag C 2 2 read-write 0 - SCI_TEI interrupt request is disabled + No compare match of GTCCRC is generated. #0 1 - SCI_TEI interrupt request is enabled + A compare match of GTCCRC is generated. #1 - CKE - Clock Enable - 0 + TCFB + Input Capture/Compare Match Flag B + 1 1 read-write - 00 - The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) - #00 - - - 01 - The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) - #01 + 0 + No input capture/compare match of GTCCRB is generated. + #0 - others - The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) - true + 1 + An input capture/compare match of GTCCRB is generated. + #1 - - - - SCR_SMCI - Serial Control Register (SCMR.SMIF =1) - SCR - 0x02 - 8 - read-write - 0x00 - 0xFF - - TIE - Transmit Interrupt Enable - 7 - 7 + TCFA + Input Capture/Compare Match Flag A + 0 + 0 read-write 0 - A SCI_TXI interrupt request is disabled + No input capture/compare match of GTCCRA is generated. #0 1 - A SCI_TXI interrupt request is enabled + An input capture/compare match of GTCCRA is generated. #1 - RIE - Receive Interrupt Enable - 6 - 6 + PCF + Period Count Function Finish Flag + 31 + 31 read-write 0 - SCI_RXI and SCI_ERI interrupt requests are disabled + No period count function finish has occurred #0 1 - SCI_RXI and SCI_ERI interrupt requests are enabled + A period count function finish has occurred #1 + + + + GTBER + General PWM Timer Buffer Enable Register + 0x40 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - TE - Transmit Enable - 5 - 5 + ADTDB + GTADTRB Double Buffer Operation + 30 + 30 read-write 0 - Serial transmission is disabled + Single buffer operation (GTADTBRB --> GTADTRB) #0 1 - Serial transmission is enabled + Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB) #1 - RE - Receive Enable - 4 - 4 + ADTTB + GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. + 28 + 29 + read-write + + + 00 + No transfer + #00 + + + 01 + Transfer at crest + #01 + + + 10 + Transfer at trough + #10 + + + 11 + Transfer at both crest and trough + #11 + + + + + ADTDA + GTADTRA Double Buffer Operation + 26 + 26 read-write 0 - Serial reception is disabled + Single buffer operation (GTADTBRA --> GTADTRA) #0 1 - Serial reception is enabled + Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA) #1 - MPIE - Multi-Processor Interrupt Enable - 3 - 3 - read-write - - - TEIE - Transmit End Interrupt Enable - 2 - 2 - read-write - - - CKE - Clock Enable - 0 - 1 + ADTTA + GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed. + 24 + 25 read-write 00 - Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) + No transfer #00 01 - Clock Output + Transfer at crest #01 10 - Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) + Transfer at trough #10 11 - Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) + Transfer at both crest and trough #11 - - - - TDR - Transmit Data Register - 0x03 - 8 - read-write - 0xFF - 0xFF - - - TDR - TDR is an 8-bit register that stores transmit data. - 0 - 7 - read-write - - - - - SSR - Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) - 0x04 - 8 - read-write - 0x84 - 0xFF - - TDRE - Transmit Data Empty Flag - 7 - 7 - read-write - zeroToClear - modify + CCRSWT + GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. + 22 + 22 + write-only 0 - Transmit data is in TDR register + no effect #0 1 - No transmit data is in TDR register + Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 - RDRF - Receive Data Full Flag - 6 - 6 + PR + GTPR Buffer Operation + 20 + 21 + read-write + + + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTPBR --> GTPR) + #01 + + + others + Setting prohibited + true + + + + + CCRB + GTCCRB Buffer Operation + 18 + 19 read-write - zeroToClear - modify - 0 - No received data is in RDR register - #0 + 00 + Buffer operation is not performed + #00 + + + 01 + Single buffer operation (GTCCRB <--> GTCCRE) + #01 + + + 10 + Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) + #10 - 1 - Received data is in RDR register - #1 + 11 + Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) + #11 - ORER - Overrun Error Flag - 5 - 5 + CCRA + GTCCRA Buffer Operation + 16 + 17 read-write - zeroToClear - modify - 0 - No overrun error occurred - #0 + 00 + Buffer operation is not performed + #00 - 1 - An overrun error has occurred - #1 + 01 + Single buffer operation (GTCCRA <--> GTCCRC) + #01 - - - - FER - Framing Error Flag - 4 - 4 - read-write - zeroToClear - modify - - 0 - No framing error occurred - #0 + 10 + Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) + #10 - 1 - A framing error has occurred - #1 + 11 + Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) + #11 - PER - Parity Error Flag + BD3 + BD[3]: GTDV Buffer Operation DisableBD[2] 3 3 read-write - zeroToClear - modify 0 - No parity error occurred + Enable buffer operation #0 1 - A parity error has occurred + Disable buffer operation #1 - TEND - Transmit End Flag + BD2 + BD[2]: GTADTR Buffer Operation DisableBD 2 2 - read-only + read-write 0 - A character is being transmitted. + Enable buffer operation #0 1 - Character transfer has been completed. + Disable buffer operation #1 - MPB - Multi-Processor + BD1 + BD[1]: GTPR Buffer Operation Disable 1 1 - read-only + read-write 0 - Data transmission cycles + Buffer operation is enabled #0 1 - ID transmission cycles + Buffer operation is disabled #1 - MPBT - Multi-Processor Bit Transfer + BD0 + BD[0]: GTCCR Buffer Operation Disable 0 0 read-write 0 - Data transmission cycles + Buffer operation is enabled #0 1 - ID transmission cycles + Buffer operation is disabled #1 @@ -54544,158 +43382,240 @@ FMS2,1,0: - SSR_FIFO - Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) - SSR - 0x04 - 8 + GTITC + General PWM Timer Interrupt and A/D Converter Start Request Skipping Setting Register + 0x44 + 32 read-write - 0x80 - 0xFD + 0x00000000 + 0xFFFFFFFF - TDFE - Transmit FIFO data empty flag - 7 - 7 + ADTBL + GTADTRB A/D Converter Start Request Link + 14 + 14 read-write - zeroToClear - modify 0 - The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 - RDF - Receive FIFO data full flag - 6 - 6 + ADTAL + GTADTRA A/D Converter Start Request Link + 12 + 12 read-write - zeroToClear - modify 0 - The quantity of receive data written in FRDR falls below the specified receive triggering number. + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. + Link with GPTn_OVF/GPTn_UDF interrupt skipping function #1 - ORER - Overrun Error Flag + IVTT + GPT_OVF/GPT_UDF Interrupt Skipping Count Select + 8 + 10 + read-write + + + 000 + No skipping + #000 + + + 001 + Skipping count of 1 + #001 + + + 010 + Skipping count of 2 + #010 + + + 011 + Skipping count of 3 + #011 + + + 100 + Skipping count of 4 + #100 + + + 101 + Skipping count of 5 + #101 + + + 110 + Skipping count of 6 + #110 + + + 111 + Skipping count of 7. + #111 + + + + + IVTC + GPT_OVF/GPT_UDF Interrupt Skipping Function Select + 6 + 7 + read-write + + + 00 + Do not perform skipping + #00 + + + 01 + Count and skip both overflow and underflow for saw waves and crest for triangle waves + #01 + + + 10 + Count and skip both overflow and underflow for saw waves and trough for triangle waves + #10 + + + 11 + Count and skip both overflow and underflow for saw waves and both crest and trough for triangle waves. + #11 + + + + + ITLF + GTCCRF Compare Match Interrupt Link 5 5 read-write - zeroToClear - modify 0 - No overrun error occurred + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - An overrun error has occurred + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 - FER - Framing Error Flag + ITLE + GTCCRE Compare Match Interrupt Link 4 4 read-write - zeroToClear - modify 0 - No framing error occurred. + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - A framing error has occurred. + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 - PER - Parity Error Flag + ITLD + GTCCRD Compare Match Interrupt Link 3 3 read-write - zeroToClear - modify 0 - No parity error occurred. + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - A parity error has occurred. + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 - TEND - Transmit End Flag + ITLC + GTCCRC Compare Match Interrupt Link 2 2 read-write - zeroToClear - modify 0 - A character is being transmitted or standing by for transmission. + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - Character transfer has been completed. + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 - DR - Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected) + ITLB + GTCCRB Compare Match/Input Capture Interrupt Link + 1 + 1 + read-write + + + 0 + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function + #0 + + + 1 + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. + #1 + + + + + ITLA + GTCCRA Compare Match/Input Capture Interrupt Link 0 0 read-write - zeroToClear - modify 0 - Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) + Do not link with GPTn_OVF/GPTn_UDF interrupt skipping function #0 1 - Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. + Link with GPTn_OVF/GPTn_UDF interrupt skipping function. #1 @@ -54703,273 +43623,460 @@ FMS2,1,0: - SSR_SMCI - Serial Status Register(SCMR.SMIF = 1) - SSR - 0x04 - 8 + GTCNT + General PWM Timer Counter + 0x48 + 32 read-write - 0x84 - 0xFF + 0x00000000 + 0xFFFFFFFF - TDRE - Transmit Data Empty Flag - 7 - 7 + GTCNT + Counter + 0 + 31 + read-write + + + + + 6 + 4 + + + A + A + 0 + + + B + B + 1 + + + C + C + 2 + + + E + E + 3 + + + D + D + 4 + + + F + F + 5 + + + GTCCR[%s] + General PWM Timer Compare Capture Register + 0x4C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTCCR + Compare Capture Register A + 0 + 31 + read-write + + + + + GTPR + General PWM Timer Cycle Setting Register + 0x64 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPR + Cycle Setting Register + 0 + 31 + read-write + + + + + GTPBR + General PWM Timer Cycle Setting Buffer Register + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPBR + Cycle Setting Buffer Register + 0 + 31 + read-write + + + + + GTPDBR + General PWM Timer Cycle Setting Double-Buffer Register + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTPDBR + Cycle Setting Double-Buffer Register + 0 + 31 + read-write + + + + + GTADTRA + A/D Converter Start Request Timing Register A + 0x70 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTRA + A/D Converter Start Request Timing Register A + 0 + 31 + read-write + + + + + GTADTRB + A/D Converter Start Request Timing Register B + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTRB + A/D Converter Start Request Timing Register B + 0 + 31 + read-write + + + + + GTADTBRA + A/D Converter Start Request Timing Buffer Register A + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTBRA + A/D Converter Start Request Timing Buffer Register A + 0 + 31 + read-write + + + + + GTADTBRB + A/D Converter Start Request Timing Buffer Register B + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTBRB + A/D Converter Start Request Timing Buffer Register B + 0 + 31 + read-write + + + + + GTADTDBRA + A/D Converter Start Request Timing Double-Buffer Register A + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTDBRA + A/D Converter Start Request Timing Double-Buffer Register A + 0 + 31 + read-write + + + + + GTADTDBRB + A/D Converter Start Request Timing Double-Buffer Register B + 0x84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + GTADTDBRB + A/D Converter Start Request Timing Double-Buffer Register B + 0 + 31 read-write - zeroToClear - modify - - - 0 - Transmit data is in TDR register - #0 - - - 1 - No transmit data is in TDR register - #1 - - + + + + GTDTCR + General PWM Timer Dead Time Control Register + 0x88 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - RDRF - Receive Data Full Flag - 6 - 6 + TDFER + GTDVD Setting + 8 + 8 read-write - zeroToClear - modify 0 - No received data is in RDR register + Set GTDVU and GTDVD separately #0 1 - Received data is in RDR register + Automatically set the value written to GTDVU to GTDVD #1 - ORER - Overrun Error Flag + TDBDE + GTDVD Buffer Operation Enable 5 5 read-write - zeroToClear - modify 0 - No overrun error occurred + Disable GTDVD buffer operation #0 1 - An overrun error has occurred + Enable GTDVD buffer operation #1 - ERS - Error Signal Status Flag + TDBUE + GTDVU Buffer Operation Enable 4 4 read-write - zeroToClear - modify 0 - Low error signal not responded + Disable GTDVU buffer operation #0 1 - Low error signal responded + Enable GTDVU buffer operation #1 - PER - Parity Error Flag - 3 - 3 + TDE + Negative-Phase Waveform Setting + 0 + 0 read-write - zeroToClear - modify - - - 0 - No parity error occurred - #0 - - - 1 - A parity error has occurred - #1 - - - - - TEND - Transmit End Flag - 2 - 2 - read-only 0 - A character is being transmitted. + GTCCRB is set without using GTDVU and GTDVD. #0 1 - Character transfer has been completed. + GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 + + + + GTDVU + General PWM Timer Dead Time Value Register U + 0x8C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + - MPB - Multi-ProcessorThis bit should be 0 in smart card interface mode. - 1 - 1 - read-only - - - MPBT - Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. + GTDVU + Dead Time Value Register U 0 - 0 + 31 read-write - RDR - Receive Data Register - 0x05 - 8 - read-only - 0x00 - 0xFF + GTDVD + General PWM Timer Dead Time Value Register D + 0x90 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF - RDR - RDR is an 8-bit register that stores receive data. + GTDVD + Dead Time Value Register D 0 - 7 - read-only + 31 + read-write - SCMR - Smart Card Mode Register - 0x06 - 8 + GTDBU + General PWM Timer Dead Time Buffer Register U + 0x94 + 32 read-write - 0xF2 - 0xFF + 0xFFFFFFFF + 0xFFFFFFFF - BCP2 - Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits - 7 - 7 + GTDVU + Dead Time Buffer Register U + 0 + 31 read-write - - - 0 - S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) - #0 - - - 1 - S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) - #1 - - + + + + GTDBD + General PWM Timer Dead Time Buffer Register D + 0x98 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + - CHR1 - Character Length 1(Only valid in asynchronous mode) - 4 - 4 + GTDBD + Dead Time Buffer Register D + 0 + 31 read-write - - - 0 - Transmit/receive in 9-bit data length - #0 - - - 1 - Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) - #1 - - + + + + GTSOS + General PWM Timer Output Protection Function Status Register + 0x9C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + - SDIR - Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. - 3 - 3 - read-write + SOS + Output Protection Function Status + 0 + 1 + read-only - 0 - Transfer with LSB first - #0 + 00 + Normal operation + #00 - 1 - Transfer with MSB first - #1 + 01 + Protected state (GTCCRA = 0 is set during transfer at trough or crest) + #01 - - - - SINV - Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. - 2 - 2 - read-write - - 0 - TDR contents are transmitted as they are. Receive data is stored as it is in RDR. - #0 + 10 + Protected state (GTCCRA >= GTPR is set during transfer at trough) + #10 - 1 - TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. - #1 + 11 + Protected state (GTCCRA >= GTPR is set during transfer at crest) + #11 + + + + GTSOTR + General PWM Timer Output Protection Function Temporary Release Register + 0xA0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - SMIF - Smart Card Interface Mode Select + SOTR + Output Protection Function Temporary Release 0 0 read-write 0 - Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) + Do not release protected state #0 1 - Smart card interface mode + Release protected state #1 @@ -54977,174 +44084,336 @@ FMS2,1,0: - SEMR - Serial Extended Mode Register - 0x07 - 8 + GTICLF + General PWM Timer Inter Channel Logical Operation Function Setting Register + 0xB8 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - RXDESEL - Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) - 7 - 7 + ICLFA + GTIOCnA Output Logical Operation Function Select + 0 + 2 read-write - 0 - The low level on the RXDn pin is detected as the start bit. - #0 + 000 + A (no delay) + #000 - 1 - A falling edge on the RXDn pin is detected as the start bit. - #1 + 001 + NOT A (no delay) + #001 + + + 010 + C (1PCLKGPT delay) + #010 + + + 011 + NOT C (1PCLKGPT delay) + #011 + + + 100 + A AND C (1PCLKGPT delay) + #100 + + + 101 + A OR C (1PCLKGPT delay) + #101 + + + 110 + A EXOR C (1PCLKGPT delay) + #110 + + + 111 + A NOR C (1PCLKGPT delay) + #111 - BGDM - Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). - 6 - 6 + ICLFSELC + Inter Channel Signal C Select + 4 + 9 read-write - 0 - Baud rate generator outputs the clock with normal frequency. - #0 + 0x00 + GTIOC0A + 0x00 - 1 - Baud rate generator outputs the clock with doubled frequency. - #1 + 0x01 + GTIOC0B + 0x01 + + + 0x02 + GTIOC1A + 0x02 + + + 0x03 + GTIOC1B + 0x03 + + + 0x04 + GTIOC2A + 0x04 + + + 0x05 + GTIOC2B + 0x05 + + + 0x06 + GTIOC3A + 0x06 + + + 0x07 + GTIOC3B + 0x07 + + + 0x08 + GTIOC4A + 0x08 + + + 0x09 + GTIOC4B + 0x09 + + + 0x0A + GTIOC5A + 0x0a + + + 0x0B + GTIOC5B + 0x0b + + + 0x0C + GTIOC6A + 0x0c + + + 0x0D + GTIOC6B + 0x0d + + + 0x0E + GTIOC7A + 0x0e + + + 0x0F + GTIOC7B + 0x0f + + + 0x10 + GTIOC8A + 0x10 + + + 0x11 + GTIOC8B + 0x11 + + + 0x12 + GTIOC9A + 0x12 + + + 0x13 + GTIOC9B + 0x13 + + + Others + Setting prohibited + true - NFEN - Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. - 5 - 5 + ICLFB + GTIOCnB Output Logical Operation Function Select + 16 + 18 read-write - 0 - Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. - #0 + 000 + B (no delay) + #000 - 1 - Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. - #1 + 001 + NOT B (no delay) + #001 + + + 010 + D (1PCLKGPT delay) + #010 + + + 011 + NOT D (1PCLKGPT delay) + #011 + + + 100 + B AND D (1PCLKGPT delay) + #100 + + + 101 + B OR D (1PCLKGPTn delay) + #101 + + + 110 + B EXOR D (1PCLKGPT delay) + #110 + + + 111 + B NOR D (1PCLKGPT delay) + #111 - ABCS - Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) - 4 - 4 + ICLFSELD + Inter Channel Signal D Select + 20 + 25 read-write - 0 - Selects 16 base clock cycles for 1-bit period. - #0 + 0x00 + GTIOC0A + 0x00 - 1 - Selects 8 base clock cycles for 1-bit period. - #1 + 0x01 + GTIOC0B + 0x01 + + + 0x02 + GTIOC1A + 0x02 + + + 0x03 + GTIOC1B + 0x03 + + + 0x04 + GTIOC2A + 0x04 + + + 0x05 + GTIOC2B + 0x05 + + + 0x06 + GTIOC3A + 0x06 + + + 0x07 + GTIOC3B + 0x07 + + + 0x08 + GTIOC4A + 0x08 + + + 0x09 + GTIOC4B + 0x09 + + + 0x0A + GTIOC5A + 0x0a - - - - ABCSE - Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) - 3 - 3 - read-write - - 0 - Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. - #0 + 0x0B + GTIOC5B + 0x0b - 1 - Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. - #1 + 0x0C + GTIOC6A + 0x0c - - - - BRME - Bit Rate Modulation Enable - 2 - 2 - read-write - - 0 - Bit rate modulation function is disabled. - #0 + 0x0D + GTIOC6B + 0x0d - 1 - Bit rate modulation function is enabled. - #1 + 0x0E + GTIOC7A + 0x0e - - - - - - SNFR - Noise Filter Setting Register - 0x08 - 8 - read-write - 0x00 - 0xFF - - - NFCS - Noise Filter Clock Select - 0 - 2 - read-write - - 000 - The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) - #000 + 0x0F + GTIOC7B + 0x0f - 001 - The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) - #001 + 0x10 + GTIOC8A + 0x10 - 010 - The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) - #010 + 0x11 + GTIOC8B + 0x11 - 011 - The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) - #011 + 0x12 + GTIOC9A + 0x12 - 100 - The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) - #100 + 0x13 + GTIOC9B + 0x13 - others - Settings prohibited. + Others + Setting prohibited true @@ -55152,293 +44421,256 @@ FMS2,1,0: - SIMR1 - I2C Mode Register 1 - 0x09 - 8 + GTPC + General PWM Timer Period Count Register + 0xBC + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - IICDL - SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. - 3 - 7 + PCEN + Period Count Function Enable + 0 + 0 read-write - 00000 - No output delay - #00000 + 0 + Period count function is disabled + #0 - others - (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. - true + 1 + Period count function is enabled + #1 - IICM - Simple I2C Mode Select - 0 - 0 + ASTP + Automatic Stop Function Enable + 8 + 8 read-write 0 - Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) + Automatic stop function is disabled #0 1 - Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) + Automatic stop function is enabled #1 + + PCNT + Period Counter + 16 + 27 + read-write + - SIMR2 - I2C Mode Register 2 - 0x0A - 8 + GTSECSR + General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register + 0xD0 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - IICACKT - ACK Transmission Data - 5 - 5 + SECSEL0 + Channel 0 Operation Enable Bit Simultaneous Control Channel Select + 0 + 0 read-write 0 - ACK transmission + Disable simultaneous control #0 1 - NACK transmission and reception of ACK/NACK + Enable simultaneous control #1 - IICCSC - Clock Synchronization + SECSEL1 + Channel 1 Operation Enable Bit Simultaneous Control Channel Select 1 1 read-write 0 - No synchronization with the clock signal + Disable simultaneous control #0 1 - Synchronization with the clock signal + Enable simultaneous control #1 - IICINTM - I2C Interrupt Mode Select - 0 - 0 + SECSEL2 + Channel 2 Operation Enable Bit Simultaneous Control Channel Select + 2 + 2 read-write 0 - Use ACK/NACK interrupts. + Disable simultaneous control #0 1 - Use reception and transmission interrupts + Enable simultaneous control #1 - - - - SIMR3 - I2C Mode Register 3 - 0x0B - 8 - read-write - 0x00 - 0xFF - - IICSCLS - SCL Output Select - 6 - 7 + SECSEL3 + Channel 3 Operation Enable Bit Simultaneous Control Channel Select + 3 + 3 read-write - 00 - Serial clock output - #00 - - - 01 - Generate a start, restart, or stop condition. - #01 - - - 10 - Output the low level on the SSCLn pin. - #10 + 0 + Disable simultaneous control + #0 - 11 - Place the SSCLn pin in the high-impedance state. - #11 + 1 + Enable simultaneous control + #1 - IICSDAS - SDA Output Select + SECSEL4 + Channel 4 Operation Enable Bit Simultaneous Control Channel Select 4 - 5 + 4 read-write - 00 - Serial data output - #00 - - - 01 - Generate a start, restart, or stop condition. - #01 - - - 10 - Output the low level on the SSDAn pin. - #10 + 0 + Disable simultaneous control + #0 - 11 - Place the SSDAn pin in the high-impedance state. - #11 + 1 + Enable simultaneous control + #1 - IICSTIF - Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) - 3 - 3 + SECSEL5 + Channel 5 Operation Enable Bit Simultaneous Control Channel Select + 5 + 5 read-write - zeroToClear - modify 0 - There are no requests for generating conditions or a condition is being generated. + Disable simultaneous control #0 1 - A start, restart, or stop condition is completely generated. + Enable simultaneous control #1 - IICSTPREQ - Stop Condition Generation - 2 - 2 + SECSEL6 + Channel 6 Operation Enable Bit Simultaneous Control Channel Select + 6 + 6 read-write 0 - A stop condition is not generated. + Disable simultaneous control #0 1 - A stop condition is generated. + Enable simultaneous control #1 - IICRSTAREQ - Restart Condition Generation - 1 - 1 + SECSEL7 + Channel 7 Operation Enable Bit Simultaneous Control Channel Select + 7 + 7 read-write 0 - A restart condition is not generated. + Disable simultaneous control #0 1 - A restart condition is generated. + Enable simultaneous control #1 - IICSTAREQ - Start Condition Generation - 0 - 0 + SECSEL8 + Channel 8 Operation Enable Bit Simultaneous Control Channel Select + 8 + 8 read-write 0 - A start condition is not generated. + Disable simultaneous control #0 1 - A start condition is generated. + Enable simultaneous control #1 - - - - SISR - I2C Status Register - 0x0C - 8 - read-only - 0x00 - 0xCB - - IICACKR - ACK Reception Data Flag - 0 - 0 - read-only + SECSEL9 + Channel 9 Operation Enable Bit Simultaneous Control Channel Select + 9 + 9 + read-write 0 - ACK received + Disable simultaneous control #0 1 - NACK received + Enable simultaneous control #1 @@ -55446,971 +44678,970 @@ FMS2,1,0: - SPMR - SPI Mode Register - 0x0D - 8 + GTSECR + General PWM Timer Operation Enable Bit Simultaneous Control Register + 0xD4 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - CKPH - Clock Phase Select - 7 - 7 + SBDCE + GTCCR Register Buffer Operation Simultaneous Enable + 0 + 0 read-write 0 - Clock is not delayed. + Disable simultaneous enabling GTCCR buffer operations #0 1 - Clock is delayed. + Enable GTCCR register buffer operations simultaneously #1 - CKPOL - Clock Polarity Select - 6 - 6 + SBDPE + GTPR Register Buffer Operation Simultaneous Enable + 1 + 1 read-write 0 - Clock polarity is not inverted. + Disable simultaneous enabling GTPR buffer operations #0 1 - Clock polarity is inverted + Enable GTPR register buffer operations simultaneously #1 - MFF - Mode Fault Flag - 4 - 4 + SBDCD + GTCCR Register Buffer Operation Simultaneous Disable + 8 + 8 read-write - zeroToClear - modify 0 - No mode fault error + Disable simultaneous disabling GTCCR buffer operations #0 1 - Mode fault error + Disable GTCCR register buffer operations simultaneously #1 - MSS - Master Slave Select - 2 - 2 + SBDPD + GTPR Register Buffer Operation Simultaneous Disable + 9 + 9 read-write 0 - Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). + Disable simultaneous disabling GTPR buffer operations #0 1 - Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). + Disable GTPR register buffer operations simultaneously #1 - CTSE - CTS Enable - 1 - 1 + SPCE + Period Count Function Simultaneous Enable + 16 + 16 read-write 0 - CTS function is disabled (RTS output function is enabled). + Disable simultaneous enabling period count function #0 1 - CTS function is enabled. + Enable period count function simultaneously #1 - SSE - SSn Pin Function Enable - 0 - 0 + SPCD + Period Count Function Simultaneous Disable + 24 + 24 read-write 0 - SSn pin function is disabled. + Disable simultaneous disabling period count function #0 1 - SSn pin function is enabled. + Disable period count function simultaneously #1 + + + + R_GPT1 + 0x40078100 + + + R_GPT2 + 0x40078200 + + + R_GPT3 + 0x40078300 + + + R_GPT4 + 0x40078400 + + + R_GPT5 + 0x40078500 + + + R_GPT6 + 0x40078600 + + + R_GPT7 + 0x40078700 + + + R_GPT8 + 0x40078800 + + + R_GPT9 + 0x40078900 + + + R_GPT10 + 0x40078A00 + + + R_GPT11 + 0x40078B00 + + + R_GPT12 + 0x40078C00 + + + R_GPT13 + 0x40078D00 + + + R_GPT_ODC + PWM Delay Generation Circuit + 0x4007B000 + + 0x00000000 + 0x004 + registers + + + 0x00000018 + 0x020 + registers + + + + 4 + 4 + GTDLYR[%s] + PWM DELAY RISING + 0x18 + + A + GTIOCA Output Delay Register + 0 + 16 + read-write + 0x0000 + 0xFFFF + + + DLY + GTIOCnA Output Rising Edge Delay Setting + 0 + 4 + read-write + + + 00000 + No delay on rising edges + #00000 + + + others + Delay of DLY/32 times the PCLKD period is applied. + true + + + + + + + B + GTIOCB Output Delay Register + 2 + 16 + read-write + 0x0000 + 0xFFFF + + + DLY + GTIOCnA Output Rising Edge Delay Setting + 0 + 4 + read-write + + + 00000 + No delay on rising edges + #00000 + + + others + Delay of DLY/32 times the PCLKD period is applied. + true + + + + + + + + GTDLYF[%s] + PWM DELAY FALLING + 0x28 + - TDRHL - Transmit 9-bit Data Register - 0x0E + GTDLYCR1 + PWM Output Delay Control Register1 + 0x00 16 read-write - 0xFFFF - 0xFFFF - - - TDRHL - TDRHL is a 16-bit register that stores transmit data. - 0 - 15 - write-only - - - - - FTDRHL - Transmit FIFO Data Register HL - TDRHL - 0x0E - 16 - write-only - 0xFFFF + 0x0000 0xFFFF - MPBT - Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) - 9 - 9 - write-only + DLLMOD + DLL Mode Select + 8 + 8 + read-write 0 - Data transmission cycles + 5 bit-mode #0 1 - ID transmission cycles + 4 bit-mode #1 - TDAT - Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) - 0 - 8 - write-only - - - - - FTDRH - Transmit FIFO Data Register H - TDRHL - 0x0E - 8 - write-only - 0xFF - 0xFF - - - MPBT - Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) + DLYRST + PWM Delay Generation Circuit Reset 1 1 - write-only + read-write 0 - Data transmission cycles + Normal operation #0 1 - ID transmission cycles + Reset #1 - TDATH - Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + DLLEN + DLL Operation Enable 0 0 - write-only - - - - - FTDRL - Transmit FIFO Data Register L - TDRHL - 0x0F - 8 - write-only - 0xFF - 0xFF - - - TDATL - Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) - 0 - 7 - write-only - - - - - RDRHL - Receive 9-bit Data Register - 0x10 - 16 - read-only - 0x0000 - 0xFFFF - - - RDRHL - RDRHL is an 16-bit register that stores receive data. - 0 - 15 - read-only + read-write + + + 0 + DLL operation is disabled + #0 + + + 1 + DLL operation is enabled + #1 + + - FRDRHL - Receive FIFO Data Register HL - RDRHL - 0x10 + GTDLYCR2 + PWM Output Delay Control Register2 + 0x02 16 - read-only + read-write 0x0000 0xFFFF - RDF - Receive FIFO data full flag(It is same as SSR.RDF) - 14 - 14 - read-only + 1 + 1 + DLYDENB%s + PWM Delay Generation Circuit Disenable for GTIOCB + 12 + 12 + read-write 0 - The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. + Delay generation circuit of GTIOCB is based on DLYEN1. #0 1 - The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. + Delay generation circuit of GTIOCB is disabled. #1 - ORER - Overrun error flag(It is same as SSR.ORER) - 13 - 13 - read-only + 1 + 1 + DLYEN%s + PWM Delay Generation Circuit enable + 8 + 8 + read-write 0 - No overrun error occurred. + Delay generation circuit of channel is enabled #0 1 - An overrun error has occurred. + Delay generation circuit of channel is disabled. #1 - FER - Framing error flag - 12 - 12 - read-only + 4 + 1 + DLYBS%s + PWM Delay Generation Circuit bypass + 0 + 0 + read-write 0 - No framing error occurred at the first data of FRDRH and FRDRL. + Delay generation circuit of channel is bypassed. #0 1 - A framing error has occurred at the first data of FRDRH and FRDRL. + Delay generation circuit of channel is not bypassed. #1 + + + + + + R_GPT_OPS + Output Phase Switching for GPT + 0x40078FF0 + + 0x00000000 + 0x04 + registers + + + + OPSCR + Output Phase Switching Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - PER - Parity error flag - 11 - 11 - read-only + NFCS + External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. + 30 + 31 + read-write - 0 - No parity error occurred at the first data of FRDRH and FRDRL. - #0 + 00 + PCLK/1 + #00 - 1 - A parity error has occurred at the first data of FRDRH and FRDRL. - #1 + 01 + PCLK/4 + #01 + + + 10 + PCLK/16 + #10 + + + 11 + PCLK/64 + #11 - DR - Receive data ready flag(It is same as SSR.DR) - 10 - 10 - read-only + NFEN + External Input Noise Filter Enable + 29 + 29 + read-write 0 - Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. + Do not use a noise filter to the external input. #0 1 - Next receive data has not been received for a period after normal completed receiving. + Use a noise filter to the external input. #1 - MPB - Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) - 9 - 9 - read-only + GODF + Group output disable function + 26 + 26 + read-write 0 - Data transmission cycles + This bit function is ignored. #0 1 - ID transmission cycles + Group disable will clear OPSCR.EN Bit. #1 - RDAT - Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) - 0 - 8 - read-only - - - - - FRDRH - Receive FIFO Data Register H - RDRHL - 0x10 - 8 - read-only - 0x00 - 0xFF - - - RDF - Receive FIFO data full flag(It is same as SSR.RDF) - 6 - 6 - read-only + GRP + Output disabled source selection + 24 + 25 + read-write - 0 - The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. - #0 + 00 + Select Group A output disable source + #00 - 1 - The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. - #1 + 01 + Select Group B output disable source + #01 + + + 10 + Select Group C output disable source + #10 + + + 11 + Select Group D output disable source + #11 - ORER - Overrun error flag(It is same as SSR.ORER) - 5 - 5 - read-only + ALIGN + Input phase alignment + 21 + 21 + read-write 0 - No overrun error occurred + Input phase is aligned to PCLK. #0 1 - An overrun error has occurred + Input phase is aligned PWM. #1 - FER - Framing error flag - 4 - 4 - read-only + RV + Output phase rotation direction reversal + 20 + 20 + read-write 0 - No framing error occurred at the first data of FRDRH and FRDRL + U/V/W-Phase output #0 1 - A framing error has occurred at the first data of FRDRH and FRDRL + Output to reverse the V / W-phase #1 - PER - Parity error flag - 3 - 3 - read-only + INV + Invert-Phase Output Control + 19 + 19 + read-write 0 - No parity error occurred at the first data of FRDRH and FRDRL + Positive Logic (Active High)output #0 1 - A parity error has occurred at the first data of FRDRH and FRDRL + Negative Logic (Active Low)output #1 - DR - Receive data ready flag(It is same as SSR.DR) - 2 - 2 - read-only + N + Negative-Phase Output (N) Control + 18 + 18 + read-write 0 - Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. + Level signal output #0 1 - Next receive data has not been received for a period after normal completed receiving. + PWM signal output (PWM of GPT0) #1 - MPB - Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) - 1 - 1 - read-only + P + Positive-Phase Output (P) Control + 17 + 17 + read-write 0 - Data transmission cycles + Level signal output #0 1 - ID transmission cycles + PWM signal output (PWM of GPT0) #1 - RDATH - Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) - 0 - 0 - read-only - - - - - FRDRL - Receive FIFO Data Register L - RDRHL - 0x11 - 8 - read-only - 0x00 - 0xFF - - - RDATL - Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. - 0 - 7 - read-only - - - - - MDDR - Modulation Duty Register - 0x12 - 8 - read-write - 0xFF - 0xFF - - - MDDR - MDDR corrects the bit rate adjusted by the BRR register. - 0 - 7 - read-write - - - - - DCCR - Data Compare Match Control Register - 0x13 - 8 - read-write - 0x40 - 0xFF - - - DCME - Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) - 7 - 7 + FB + External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. + 16 + 16 read-write 0 - Address match function is disabled. + Select the external input. #0 1 - Address match function is enabled + Select the soft setting(OPSCR.UF, VF, WF). #1 - IDSEL - ID frame select(Valid only in asynchronous mode(including multi-processor) - 6 - 6 + EN + Enable-Phase Output Control + 8 + 8 read-write 0 - Always compare data regardless of the value of the MPB bit. + Not Output(Hi-Z external terminals). #0 1 - Compare data when the MPB bit is 1 (ID frame) only. + Output #1 - DFER - Data Compare Match Framing Error Flag + W + Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 6 + 6 + read-only + + + V + Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) + 5 + 5 + read-only + + + U + Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 4 4 + read-only + + + WF + Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 2 + 2 + read-write + + + VF + Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 1 + 1 + read-write + + + UF + Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. + 0 + 0 + read-write + + + + + + + R_GPT_POEG0 + Port Output Enable for GPT + 0x40042000 + + 0x00000000 + 0x04 + registers + + + + POEGG + POEG Group Setting Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NFCS + Noise Filter Clock Select + 30 + 31 read-write - zeroToClear - modify - 0 - No framing error occurred - #0 + 00 + Sampling GTETRG pin input level for three times in every PCLKB. + #00 + + + 01 + Sampling GTETRG pin input level for three times in every PCLKB /8. + #01 + + + 10 + Sampling GTETRG pin input level for three times in every PCLKB /32. + #10 - 1 - A framing error has occurred - #1 + 11 + Sampling GTETRG pin input level for three times in every PCLKB /128. + #11 - DPER - Data Compare Match Parity Error Flag - 3 - 3 + NFEN + Noise Filter Enable + 29 + 29 read-write - zeroToClear - modify 0 - No parity error occurred + Filtering noise disabled #0 1 - A parity error has occurred + Filtering noise enabled #1 - DCMF - Data Compare Match Flag - 0 - 0 + INV + GTETRG Input Reverse + 28 + 28 read-write - zeroToClear - modify 0 - No matched + GTETRG Input #0 1 - Matched + GTETRG Input Reversed. #1 - - - - FCR - FIFO Control Register - 0x14 - 16 - read-write - 0xF800 - 0xFFFF - - RSTRG - RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) - 12 - 15 - read-write + ST + GTETRG Input Status Flag + 16 + 16 + read-only - 0000 - Trigger number 0 - #0000 + 0 + GTETRG input after filtering is 0. + #0 - others - Triger number n (n= 0-15) - true + 1 + GTETRG input after filtering is 1. + #1 - RTRG - Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 6 + 1 + CDRE%s + Comparator Disable Request Enable. Note: Can be modified only once after a reset. 8 - 11 - read-write - - - 0000 - Trigger number 0 - #0000 - - - others - Triger number n (n= 0-15) - true - - - - - TTRG - Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) - 4 - 7 - read-write - - - 0000 - Trigger number 0 - #0000 - - - others - Triger number n (n= 0-15) - true - - - - - DRES - Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) - 3 - 3 + 8 read-write 0 - reception data full interrupt (RXI) + A disable request of comparator 0 disabled. #0 1 - receive error interrupt (ERI) + A disable request of comparator 0 enabled. #1 - TFRST - Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) - 2 - 2 + OSTPE + Oscillation Stop Detection EnableNote: Can be modified only once after a reset. + 6 + 6 read-write 0 - The number of data stored in FTDRH and FTDRL register are NOT made 0 + A output-disable request from the oscillation stop detection disabled. #0 1 - The number of data stored in FTDRH and FTDRL register are made 0 + A output-disable request from the oscillation stop detection enabled. #1 - RFRST - Receive FIFO Data Register Reset(Valid only in FCR.FM=1) - 1 - 1 + IOCE + Enable for GPT Output-Disable RequestNote: Can be modified only once after a reset. + 5 + 5 read-write 0 - The number of data stored in FRDRH and FRDRL register are NOT made 0 + Disable output-disable requests from GPT disable request #0 1 - The number of data stored in FRDRH and FRDRL register are made 0 + Enable output-disable requests from GPT disable request #1 - FM - FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) - 0 - 0 + PIDE + Port Input Detection EnableNote: Can be modified only once after a reset. + 4 + 4 read-write 0 - Non-FIFO mode(Selects o TDR/RDR for communication) + A output-disable request from the GTETRG pins disabled. #0 1 - FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication) + A output-disable request from the GTETRG pins enabled. #1 - - - - FDR - FIFO Data Count Register - 0x16 - 16 - read-only - 0x0000 - 0xFFFF - - - T - Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) - 8 - 12 - read-only - - - R - Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) - 0 - 4 - read-only - - - - - LSR - Line Status Register - 0x18 - 16 - read-only - 0x0000 - 0xFFFF - - - PNUM - Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). - 8 - 12 - read-only - - - FNUM - Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). - 2 - 6 - read-only - - ORER - Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) - 0 - 0 - read-only + SSF + Software Stop Flag + 3 + 3 + read-write 0 - No overrun error occurred + A output-disable request from software has not been generated. #0 1 - An overrun error has occurred + A output-disable request from software has been generated. #1 - - - - CDR - Compare Match Data Register - 0x1A - 16 - read-write - 0x0000 - 0xFFFF - - - CMPD - Compare Match DataCompare data pattern for address match wake-up function - 0 - 8 - read-write - - - - - SPTR - Serial Port Register - 0x1C - 8 - read-write - 0x03 - 0xFF - - SPB2IO - Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) + OSTPF + Oscillation Stop Detection Flag 2 2 read-write + zeroToClear + modify 0 - The value of SPB2DT bit is not output in TXD pin. + A output-disable request from the oscillation stop detection has not been generated. #0 1 - The value of SPB2DT bit is output in TXD pin. + A output-disable request from the oscillation stop detection has been generated. #1 - SPB2DT - Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) + IOCF + Real Time Overcurrent Detection Flag 1 1 read-write + zeroToClear + modify 0 - Low level is output on TXD pin + A output-disable request from GPT disable request or comparator interrupt has not been generated. #0 1 - High level is output on TXD pin + A output-disable request from GPT disable request or comparator interrupt has been generated. #1 - RXDMON - Serial input data monitor bit(The state of the RXD terminal is shown.) + PIDF + Port Input Detection Flag 0 0 - read-only + read-write + zeroToClear + modify 0 - RXD pin is low. + A output-disable request from the GTETRG pin has not been generated. #0 1 - RXD pin is high. + A output-disable request from the GTETRG pin has been generated. #1 @@ -56419,812 +45650,702 @@ FMS2,1,0: - - R_SCI1 - 0x40070020 - - - R_SCI2 - 0x40070040 - - - R_SCI3 - 0x40070060 - - - R_SCI4 - 0x40070080 - - - R_SCI5 - 0x400700A0 - - - R_SCI6 - 0x400700C0 - - - R_SCI7 - 0x400700E0 + + R_GPT_POEG1 + 0x40042100 - - R_SCI8 - 0x40070100 + + R_GPT_POEG2 + 0x40042200 - - R_SCI9 - 0x40070120 + + R_GPT_POEG3 + 0x40042300 - R_SDADC0 - - 0x4009C000 + R_ICU + Interrupt Controller Unit + 0x40006000 0x00000000 - 0x02 + 0x010 registers - 0x00000004 + 0x00000100 0x01 registers - 0x00000008 - 0x019 + 0x00000120 + 0x02 registers - 0x00000024 - 0x008 + 0x00000130 + 0x02 registers - 0x00000030 - 0x01 + 0x00000140 + 0x02 registers - 0x00000034 - 0x01 + 0x000001A0 + 0x04 registers - 0x0000003C - 0x01 + 0x00000200 + 0x02 + registers + + + 0x00000280 + 0x020 + registers + + + 0x00000300 + 0x180 registers - STC1 - Startup Control Register 1 - 0x0 - 16 + 16 + 0x1 + IRQCR[%s] + IRQ Control Register %s + 0x000 + 8 read-write - 0XFFFF + 0x00 + 0xFF - VSBIAS - Reference voltage select - 8 - 11 + FLTEN + IRQ Digital Filter Enable + 7 + 7 read-write - 0000 - 0.8V - #0000 - - - 0001 - 1.0V - #0001 - - - 0010 - 1.2V - #0010 - - - 0011 - 1.4V - #0011 + 0 + Digital filter disabled. + #0 - 0100 - 1.6V - #0100 + 1 + Digital filter enabled. + #1 + + + + FCLKSEL + IRQ Digital Filter Sampling Clock Select + 4 + 5 + read-write + - 0101 - 1.8V - #0101 + 00 + PCLKB + #00 - 0110 - 2.0V - #0110 + 01 + PCLKB/8 + #01 - 0111 - 2.2V - #0111 + 10 + PCLKB/32 + #10 - 1111 - 2.4V(only available when VREFSEL=0) - #1111 + 11 + PCLKB/64 + #11 - CLKDIV - SDADC24 Reference Clock Division + IRQMD + IRQ Detection Sense Select 0 - 3 + 1 read-write - 0000 - No Division - #0000 - - - 0001 - SDADCCLK/2 - #0001 - - - 0010 - SDADCCLK/3 - #0010 - - - 0011 - SDADCCLK/4 - #0011 + 00 + Falling edge + #00 - 0100 - SDADCCLK/5 - #0100 + 01 + Rising edge + #01 - 0101 - SDADCCLK/6 - #0101 + 10 + Rising and falling edges + #10 - 0110 - SDADCCLK/8 - #0110 + 11 + Low level + #11 + + + + + + NMISR + Non-Maskable Interrupt Status Register + 0x140 + 16 + read-only + 0x0000 + 0xFFFF + + + SPEST + CPU Stack pointer monitor Interrupt Status Flag + 12 + 12 + read-only + - 0111 - SDADCCLK/12 - #0111 + 0 + Interrupt not requested + #0 - 1000 - SDADCCLK/16 - #1000 + 1 + Interrupt requested. + #1 - SDADLPM - A/D conversion operation model select - 7 - 7 - read-write + BUSMST + MPU Bus Master Error Interrupt Status Flag + 11 + 11 + read-only 0 - Normal A/D conversion mode, SDADC Reference Clock: 4 MHz, Oversampingly clock: 1MHz + Interrupt not requested #0 + + 1 + Interrupt requested. + #1 + - VREFSEL - VREF mode select - 15 - 15 - read-write + BUSSST + MPU Bus Slave Error Interrupt Status Flag + 10 + 10 + read-only 0 - Internal VREF Mode + Interrupt not requested #0 + + 1 + Interrupt requested. + #1 + - - - - STC2 - Startup Control Register 2 - 0x04 - 8 - read-write - 0x00 - 0xFF - - BGRPON - BGR part power control - 0 - 0 + RECCST + RAM ECC Error Interrupt Status Flag + 9 + 9 + read-only 0 - Turn off power to ADBGR, SBIAS, VREFI, and ADREG + Interrupt not requested #0 1 - Turn onpower to ADBGR, SBIAS, VREFI, and ADREG + Interrupt requested. #1 - ADFPWDS - ADC reference supply part - 2 - 2 + RPEST + RAM Parity Error Interrupt Status Flag + 8 + 8 + read-only 0 - Power of ADREG controlled by BGRPON register + Interrupt not requested #0 1 - Power of ADREG is off regardless of BGRPON setting + Interrupt requested. #1 - ADCPON - ADREG forced power-down - 1 - 1 + NMIST + NMI Status Flag + 7 + 7 + read-only 0 - Turn off power to VBIAS, PGA and sigma-delta A/D converter + Interrupt not requested #0 1 - Turn on power to VBIAS, PGA and sigma-delta A/D converter + Interrupt requested. #1 - - - - 5 - 4 - PGAC[%s] - Input Multiplexer %s Setting Register - 0x08 - 32 - read-write - 0x00010040 - 0xFFFFFFFF - - PGAASN - Selection of the mode for specifying the number of A/D conversions in ADSCAN - 31 - 31 - read-write + OSTST + Oscillation Stop Detection Interrupt Status Flag + 6 + 6 + read-only 0 - Specify 1 to 8,032 times by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits + Interrupt not requested for main oscillation stop #0 1 - Specify 1 to 255 times linearly by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits + Interrupt requested for main oscillation stop. #1 - PGACVE - Calibration enable - 30 - 30 - read-write + VBATTST + VBATT monitor Interrupt Status Flag + 4 + 4 + read-only 0 - Do not calculate the calibration correction factor + Interrupt not requested #0 1 - Calculate the calibration correction factor + Interrupt requested. #1 - PGAREV - Single-End Input A/D Converted Data Inversion Select - 28 - 28 - read-write + LVD2ST + Voltage-Monitoring 2 Interrupt Status Flag + 3 + 3 + read-only 0 - Do not invert the conversion result data + Interrupt not requested #0 1 - Invert the conversion result data + Interrupt requested. #1 - PGAAVE - Selection of averaging processing - 26 - 27 - read-write + LVD1ST + Voltage-Monitoring 1 Interrupt Status Flag + 2 + 2 + read-only - 00 - Do not average the A/D conversion results - #00 - - - 01 - Do not average the A/D conversion results - #01 - - - 10 - Average the A/D conversion results and generates SDADC_ADI each time an A/D conversion occurs - #10 + 0 + Interrupt not requested + #0 - 11 - Perform averaging, and generate SDADC_ADI at each time of average value output (A/D conversion is performed N times). - #11 + 1 + Interrupt requested. + #1 - PGAAVN - Selection of the number of data to be averaged - 24 - 25 - read-write + WDTST + WDT Underflow/Refresh Error Status Flag + 1 + 1 + read-only - 00 - 8 - #00 + 0 + Interrupt not requested + #0 - 01 - 16 - #01 + 1 + Interrupt requested. + #1 + + + + IWDTST + IWDT Underflow/Refresh Error Status Flag + 0 + 0 + read-only + - 10 - 32 - #10 + 0 + Interrupt not requested + #0 - 11 - 64 - #11 + 1 + Interrupt requested. + #1 - PGACTN - Coefficient (n) selection of the A/D conversion count (N) in AUTOSCAN - 21 - 23 - read-write + TZFST + 13 + 13 + read-only - 000 - 0 - #000 + 0 + TRUST Zone Filter Error interrupt is not requested. + #0 - 001 - 1 - #001 + 1 + TRUST Zone Filter Error interrupt is requested. + #1 + + + + CPEST + 15 + 15 + read-only + - 010 - 2 - #010 + 0 + Cache RAM Parity Error interrupt is not requested. + #0 - 011 - 3 - #011 + 1 + Cache RAM Parity Error interrupt is requested. + #1 + + + + + + NMIER + Non-Maskable Interrupt Enable Register + 0x120 + 16 + read-write + 0x0000 + 0xFFFF + + + SPEEN + CPU Stack pointer monitor Interrupt Enable + 12 + 12 + read-write + - 100 - 4 - #100 + 0 + Disabled + #0 - 101 - 5 - #101 + 1 + Enabled. + #1 + + + + BUSMEN + MPU Bus Master Error Interrupt Enable + 11 + 11 + read-write + - 110 - 6 - #110 + 0 + Disabled + #0 - 111 - 7 - #111 + 1 + Enabled. + #1 - PGACTM - Coefficient (m) selection of the A/D conversion count (N) in AUTOSCAN - 16 - 20 - read-write - - - PGASEL - Analog Channel Input Mode Select - 15 - 15 + BUSSEN + MPU Bus Slave Error Interrupt Enable + 10 + 10 read-write 0 - Differential input mode + Disabled #0 1 - Single-end input mode + Enabled. #1 - PGAPOL - Polarity select - 14 - 14 + RECCEN + RAM ECC Error Interrupt Enable + 9 + 9 read-write 0 - Positive-side single-end input + Disabled #0 1 - Negative-side single-end input + Enabled. #1 - PGAOFS - Offset voltage select + RPEEN + RAM Parity Error Interrupt Enable 8 - 12 - read-write - - - PGAOSR - Oversampling ratio select - 5 - 7 + 8 read-write - 000 - 64 - #000 - - - 001 - 128 - #001 + 0 + Disabled + #0 - 010 - 256 - #010 + 1 + Enabled. + #1 + + + + NMIEN + NMI Pin Interrupt Enable + 7 + 7 + read-write + - 011 - 512 - #011 + 0 + Disabled + #0 - 100 - 1024 - #100 + 1 + Enabled. + #1 + + + + OSTEN + Oscillation Stop Detection Interrupt Enable + 6 + 6 + read-write + - 101 - 2048 - #101 + 0 + Disabled + #0 - others - Settings are prohibited. - true + 1 + Enabled. + #1 - PGAGC - Gain selection of a programmable gain instrumentation amplifier ( Gset1, Gset2, Gtotal ) - 0 + VBATTEN + VBATT monitor Interrupt Enable + 4 4 read-write - - 00000 - (1, 1, 1) - #00000 - - - 00100 - (2, 1, 2) - #00100 - - - 01000 - (3, 1, 3) - #01000 - - - 01100 - (4, 1, 4) - #01100 - - - 10000 - (8, 1, 8) - #10000 - - - 00001 - (1, 2, 2) - #00001 - - - 00101 - (2, 2, 4) - #00101 - - - 01001 - (3, 2, 6) - #01001 - - - 01101 - (4, 2, 8) - #01101 - - - 10001 - (8, 2, 16) - #10001 - - - 00010 - (1, 4, 4) - #00010 - - - 00110 - (2, 4, 8) - #00110 - - - 01010 - (3, 4, 12) - #01010 - - - 01110 - (4, 4, 16) - #01110 - - - 10010 - (8, 4, 32) - #10010 - - - 00011 - (1, 8, 8) - #00011 - - - 00111 - (2, 8, 16) - #00111 - - - 01011 - (3, 8, 24) - #01011 - - - 01111 - (4, 8, 32). - #01111 + + 0 + Disabled + #0 - others - Settings are prohibited. - true + 1 + Enabled. + #1 - - - - ADC1 - Sigma-Delta A/D Converter Control Register 1 - 0x1C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - PGASLFT - PGA offset self-diagnosis enable - 20 - 20 + LVD2EN + Voltage-Monitoring 2 Interrupt Enable + 3 + 3 read-write 0 - Disable PGA offset self-diagnosis + Disabled #0 1 - Enable PGA offset self-diagnosis + Enabled. #1 - PGADISC - Disconnection Detection Assist Setting - 17 - 17 + LVD1EN + Voltage-Monitoring 1 Interrupt Enable + 2 + 2 read-write 0 - Discharge + Disabled #0 1 - Pre-charge + Enabled. #1 - PGADISA - Control of disconnection detection - 16 - 16 + WDTEN + WDT Underflow/Refresh Error Interrupt Enable + 1 + 1 read-write 0 - Normal operation + Disabled #0 1 - State of disconnection detection + Enabled. #1 - SDADBMP - A/D conversion control of the signal from input multiplexer - 8 - 12 - read-write - - - SDADTMD - Selection of A/D conversion trigger signal - 4 - 4 + IWDTEN + IWDT Underflow/Refresh Error Interrupt Enable + 0 + 0 read-write 0 - Software trigger (conversion is started by a write to SFR) + Disabled #0 1 - Hardware trigger (conversion is started in synchronization with the event signal selected by ELC_SDADC24). + Enabled. #1 - SDADSCM - Selection of autoscan mode - 0 - 0 + TZFEN + 13 + 13 read-write 0 - Continuous scan mode + Disabled #0 1 - Single scan mode + Enabled #1 - - - - ADC2 - Sigma-Delta A/D Converter Control Register 2 - 0x20 - 8 - read-write - 0x00 - 0xFF - - SDADST - Control of A/D conversion - 0 - 0 + CPEEN + 15 + 15 read-write 0 - Stop A/D conversion + Disabled #0 1 - Start A/D conversion + Enabled #1 @@ -57232,1173 +46353,815 @@ FMS2,1,0: - ADCR - Sigma-delta A/D Converter Conversion Result Register - 0x24 - 32 + NMICLR + Non-Maskable Interrupt Status Clear Register + 0x130 + 16 read-write - 0x00000000 - 0xFFFFFFFF + 0x0000 + 0xFFFF - SDADCRC - Channel number for an A/D conversion result - 25 - 27 - read-only + SPECLR + CPU Stack Pointer Monitor Interrupt Clear + 12 + 12 + write-only - 000 - Reset value (Conversion result is invalid) - #000 - - - 001 - Input multiplexer 0 (ANSD0P / ANSD0N) - #001 - - - 010 - Input multiplexer 1 (ANSD1P / ANSD1N) - #010 - - - 011 - Input multiplexer 2 (ANSD2P / ANSD2N) - #011 - - - 100 - Input multiplexer 3 (ANSD3P / ANSD3N) - #100 + 0 + No effect. + #0 - 101 - Input multiplexer 4 (AMP0O / AMP1O) - #101 + 1 + Clear the NMISR.SPEST flag. + #1 - SDADCRS - Status of an A/D conversion result - 24 - 24 - read-only + BUSMCLR + Bus Master Error Clear + 11 + 11 + write-only 0 - Normal status (within the range) + No effect. #0 1 - Overflow occurred + Clear the NMISR.BUSMST flag. #1 - SDADCRD - The 24-bit A/D conversion result - 0 - 23 - read-only - - - - - ADAR - Sigma-delta A/D Converter Average Value Register - 0x28 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SDADMVC - Channel number for an A/D conversion result - 25 - 27 - read-only + BUSSCLR + Bus Slave Error Clear + 10 + 10 + write-only - 000 - Reset value (Conversion result is invalid) - #000 + 0 + No effect. + #0 - 001 - Input multiplexer 0 (ANSD0P / ANSD0N) - #001 + 1 + Clear the NMISR.BUSSST flag. + #1 + + + + RECCCLR + SRAM ECC Error Clear + 9 + 9 + write-only + - 010 - Input multiplexer 1 (ANSD1P / ANSD1N) - #010 + 0 + No effect. + #0 - 011 - Input multiplexer 2 (ANSD2P / ANSD2N) - #011 + 1 + Clear the NMISR.RECCST flag. + #1 + + + + RPECLR + SRAM Parity Error Clear + 8 + 8 + write-only + - 100 - Input multiplexer 3 (ANSD3P / ANSD3N) - #100 + 0 + No effect. + #0 - 101 - Input multiplexer 4 (AMP0O / AMP1O). - #101 + 1 + Clear the NMISR.RPEST flag. + #1 - SDADMVS - Status of an A/D conversion result - 24 - 24 - read-only + NMICLR + NMI Clear + 7 + 7 + write-only 0 - Normal status (within the range) + No effect. #0 1 - Overflow occurred + Clear the NMISR.NMIST flag. #1 - SDADMVD - The 24-bit A/D average value - 0 - 23 - read-only - - - - - CLBC - Calibration Control Register - 0x30 - 8 - 0x00 - 0xFF - - - CLBMD - These bits are read as 0. The write value should be 0. - 0 - 1 - read-write + OSTCLR + OST Clear + 6 + 6 + write-only - 00 - Internal calibration mode - #00 + 0 + No effect. + #0 - 01 - External offset calibration mode - #01 + 1 + Clear the NMISR.OSTST flag. + #1 + + + + VBATTCLR + VBATT Clear + 4 + 4 + write-only + - 10 - External gain calibration mode - #10 + 0 + No effect. + #0 - 11 - Settings are prohibited - #11 + 1 + Clear the NMISR.VBATTST flag. + #1 - - - - CLBSTR - Calibration Start Control Register - 0x34 - 8 - read-write - 0x00 - 0xFF - - CLBST - Calibration start control - 0 - 0 - read-write + LVD2CLR + LVD2 Clear + 3 + 3 + write-only 0 - Disable writing + No effect. #0 1 - Start calibration + Clear the NMISR.LVD2ST flag. #1 - - - - CLBSSR - Calibration Status Register - 0x3C - 8 - read-only - 0x00 - - CLBSS - Calibration status - 0 - 0 - read-only + LVD1CLR + LVD1 Clear + 2 + 2 + write-only 0 - Calibration is not running + No effect. #0 1 - Calibration is running + Clear the NMISR.LVD1ST flag. #1 - - - - - - R_SDHI0 - SD/MMC Host Interface - 0x40062000 - - 0x00000000 - 0x04 - registers - - - 0x00000008 - 0x04C - registers - - - 0x00000058 - 0x00C - registers - - - 0x00000068 - 0x00C - registers - - - 0x000001B0 - 0x04 - registers - - - 0x000001C0 - 0x04 - registers - - - 0x000001CC - 0x04 - registers - - - 0x000001E0 - 0x04 - registers - - - - SD_CMD - Command Type Register - 0x000 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - CMD12AT - Multiple Block Transfer Mode (enabled at multiple block transfer) - 14 - 15 - read-write + WDTCLR + WDT Clear + 1 + 1 + write-only - 00 - CMD12 is automatically issued at multiple block transfer. - #00 + 0 + No effect. + #0 - 01 - CMD12 is not automatically issued at multiple block transfer. - #01 + 1 + Clear the NMISR.WDTST flag. + #1 + + + + IWDTCLR + IWDT Clear + 0 + 0 + write-only + - 10 - Setting prohibited - #10 + 0 + No effect. + #0 - 11 - Setting prohibited - #11 + 1 + Clear the NMISR.IWDTST flag. + #1 - TRSTP - Single/Multiple Block Transfer (enabled when the command with data is handled) + TZFCLR 13 13 read-write 0 - Single block transfer + No effect #0 1 - Multiple block transfer + Clear the NMISR.TZFCLR flag #1 - CMDRW - Write/Read Mode (enabled when the command with data is handled) - 12 - 12 + CPECLR + 15 + 15 read-write 0 - Write (SD/MMC host interface -> SD card/MMC) + No effect #0 1 - Read (SD/MMC host interface <- SD card/MMC) + Clear the NMISR.CPECLR flag #1 + + + + NMICR + NMI Pin Interrupt Control Register + 0x100 + 8 + read-write + 0x00 + 0xFF + - CMDTP - Data Mode (Command Type) - 11 - 11 + NFLTEN + NMI Digital Filter Enable + 7 + 7 read-write 0 - Command does not include data transfer (bc, bcr, or ac) + Digital filter is disabled. #0 1 - Command includes data transfer (adtc) + Digital filter is enabled. #1 - RSPTP - Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type. - 8 - 10 - read-write - - - 000 - Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. - #000 - - - 011 - Expansion mode and no response - #011 - - - 100 - Expansion mode and R1, R5, R6, or R7 response - #100 - - - 101 - Expansion mode and R1b response - #101 - - - 110 - Expansion mode and R2 response - #110 - - - 111 - Expansion mode and R3 or R4 response - #111 - - - others - Settings prohibited. - true - - - - - ACMD - Command Type Select - 6 - 7 + NFCLKSEL + NMI Digital Filter Sampling Clock Select + 4 + 5 read-write 00 - CMD + PCLKB #00 01 - ACMD + PCLKB/8 #01 - others - Setting prohibited - true + 10 + PCLKB/32 + #10 + + + 11 + PCLKB/64 + #11 - CMDIDX - Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 - 0 - 5 - read-write - - - - - SD_ARG - SD Command Argument Register - 0x008 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SD_ARG - Argument RegisterSet command format[39:8] (argument) - 0 - 31 - read-write - - - - - SD_ARG1 - SD Command Argument Register 1 - 0x00C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SD_ARG1 - Argument Register 1Set command format[39:24] (argument) + NMIMD + NMI Detection Set 0 - 15 - read-write - - - - - SD_STOP - Data Stop Register - 0x010 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SEC - Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. - 8 - 8 + 0 read-write 0 - Disables SD_SECCNT setting value. + Falling edge #0 1 - Enables SD_SECCNT setting value. + Rising edge #1 - - STP - Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set. - 0 - 0 - read-write - - SD_SECCNT - Block Count Register - 0x014 + 96 + 0x4 + IELSR[%s] + ICU Event Link Setting Register %s + 0x300 32 read-write 0x00000000 0xFFFFFFFF - SD_SECCNT - Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. - 0 - 31 + DTCE + DTC Activation Enable + 24 + 24 read-write - - - - - SD_RSP10 - SD Card Response Register 10 - 0x018 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP10 - Store the response from the SD card/MMC - 0 - 31 - read-only - - - - - SD_RSP1 - SD Card Response Register 1 - 0x01C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP1 - Store the response from the SD card/MMC - 0 - 15 - read-only - - - - - SD_RSP32 - SD Card Response Register 32 - 0x020 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP32 - Store the response from the SD card/MMC - 0 - 31 - read-only - - - - - SD_RSP3 - SD Card Response Register 3 - 0x024 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP3 - Store the response from the SD card/MMC - 0 - 15 - read-only - - - - - SD_RSP54 - SD Card Response Register 54 - 0x028 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP54 - Store the response from the SD card/MMC - 0 - 31 - read-only - - - - - SD_RSP5 - SD Card Response Register 5 - 0x02C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP5 - Store the response from the SD card/MMC - 0 - 15 - read-only - - - - - SD_RSP76 - SD Card Response Register 76 - 0x030 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP76 - Store the response from the SD card/MMC - 0 - 23 - read-only - - - - - SD_RSP7 - SD Card Response Register 7 - 0x034 - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - - SD_RSP7 - Store the response from the SD card/MMC - 0 - 7 - read-only - - - - - SD_INFO1 - SD Card Interrupt Flag Register 1 - 0x038 - 32 - read-write - 0x00000000 - 0xFFFFFB5F - - - SDD3MON - Inticates the SDnDAT3 State - 10 - 10 - read-only 0 - SDnDAT3 is set to 0. + DTC activation is disabled #0 1 - SDnDAT3 is set to 1. + DTC activation is enabled #1 - SDD3IN - SDnDAT3 Card Insertion - 9 - 9 + IR + Interrupt Status Flag + 16 + 16 read-write - zeroToClear - modify 0 - SD card insertion not detected + No interrupt request is generated #0 1 - SD card insertion detected + An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 - SDD3RM - SDnDAT3 Card Removal - 8 + IELS + ICU Event selection to NVICSet the number for the event signal to be linked . + 0 8 read-write - zeroToClear - modify - 0 - SD card removal not detected - #0 + 0x000 + Nothing is selected + 0x000 - 1 - SD card removal detected - #1 + others + See Event Table + true + + + + 8 + 0x4 + DELSR[%s] + DMAC Event Link Setting Register + 0x280 + 32 + read-write + 0x0000 + 0xFFFF + - SDWPMON - Indicates the SDnWP state - 7 - 7 - read-only + IR + Interrupt Status Flag for DMAC NOTE: Writing 1 to the IR flag is prohibited. + 16 + 16 + read-write - 0 - SDnWP is set to 1. + 0x0 + No interrupt request is generated. #0 - 1 - SDnWP is set to 0. + 0x1 + An interrupt request is generated. #1 - SDCDMON - Indicates the SDnCD state - 5 - 5 - read-only + DELS + Event selection to DMAC Start request + 0 + 8 + read-write - 0 - Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.) - #0 + 0x000 + Nothing is selected. + 0x000 - 1 - Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.) - #1 + others + See Event Table + true + + + + SELSR0 + Snooze Event Link Setting Register + 0x200 + 16 + read-write + 0x0000 + 0xFFFF + - SDCDIN - SDnCD Card Insertion - 4 - 4 + SELS + SYS Event Link Select + 0 + 8 read-write - zeroToClear - modify - 0 - Card insertion not detected - #0 - - - 1 - Card insertion detected - #1 + 0x000 + Nothing is selected + 0x000 + + + + WUPEN + Wake Up Interrupt Enable Register + 0x1A0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - SDCDRM - SDnCD Card Removal - 3 - 3 + IIC0WUPEN + IIC0 address match interrupt S/W standby returns enable + 31 + 31 read-write - zeroToClear - modify 0 - Card removal not detected + S/W standby returns by IIC0 address match interrupt is disabled #0 1 - Card removal detected + S/W standby returns by IIC0 address match interrupt is enabled #1 - ACEND - Access End - 2 - 2 + AGT1CBWUPEN + AGT1 compare match B interrupt S/W standby returns enable + 30 + 30 read-write - zeroToClear - modify 0 - Access end is not detected + S/W standby returns by AGT1 compare match B interrupt is disabled #0 1 - Access end is detected + S/W standby returns by AGT1 compare match B interrupt is enabled #1 - RSPEND - Response End Detection - 0 - 0 + AGT1CAWUPEN + AGT1 compare match A interrupt S/W standby returns enable + 29 + 29 read-write 0 - Response end is not detected + S/W standby returns by AGT1 compare match A interrupt is disabled #0 1 - Response end is detected + S/W standby returns by AGT1 compare match A interrupt is enabled #1 - - - - SD_INFO2 - SD Card Interrupt Flag Register 2 - 0x03C - 32 - read-write - 0x00002000 - 0xFFFFFF7F - - ILA - Illegal Access Error - 15 - 15 + AGT1UDWUPEN + AGT1 underflow interrupt S/W standby returns enable + 28 + 28 read-write - zeroToClear - modify 0 - Illegal access error not detected + S/W standby returns by AGT1 underflow interrupt is disabled #0 1 - Illegal access error detected + S/W standby returns by AGT1 underflow interrupt is enabled #1 - CBSY - Command Type Register Busy - 14 - 14 - read-only + USBFSWUPEN + USBFS interrupt S/W standby returns enable + 27 + 27 + read-write 0 - A command sequence is being executed. + S/W standby returns by USBFS interrupt is disabled #0 1 - A command sequence has been completed. + S/W standby returns by USBFS interrupt is enabled #1 - SD_CLK_CTRLEN - When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence. - 13 - 13 - read-only + USBHSWUPEN + USBHS interrupt S/W standby returns enable bit + 26 + 26 + read-write 0 - The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible. + S/W standby returns by USBHS interrupt is disabled #0 1 - The SD/MMC bus (CMD, DAT) is not busy. + S/W standby returns by USBHS interrupt is enabled #1 - BWE - SD_BUF Write Enable - 9 - 9 + RTCPRDWUPEN + RCT period interrupt S/W standby returns enable + 25 + 25 read-write - zeroToClear - modify - - 1 - Data can be written in SD_BUF0. - #1 - 0 - Data cannot be written in SD_BUF0. + S/W standby returns by RTC period interrupt is disabled #0 + + 1 + S/W standby returns by RTC period interrupt is enabled + #1 + - BRE - SD_BUF Read Enable - 8 - 8 + RTCALMWUPEN + RTC alarm interrupt S/W standby returns enable + 24 + 24 read-write - zeroToClear - modify - - 1 - Data can be read from SD_BUF0. - #1 - 0 - Data cannot be read from SD_BUF0. + S/W standby returns by RTC alarm interrupt is disabled #0 - - - - SDD0MON - SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL. - 7 - 7 - read-only - 1 - SDDAT0 is set to 1. + S/W standby returns by RTC alarm interrupt is enabled #1 + + + + ACMPLP0WUPEN + ACMPLP0 interrupt S/W standby returns enable + 23 + 23 + read-write + 0 - SDDAT0 is set to 0. + S/W standby returns by ACMPLP0 interrupt is disabled #0 + + 1 + S/W standby returns by ACMPLP0 interrupt is enabled + #1 + - RSPTO - Response Timeout - 6 - 6 + ACMPHS0WUPEN + ACMPHS0 interrupt S/W standby returns enable bit + 22 + 22 read-write - zeroToClear - modify 0 - Response timeout not detected + S/W standby returns by ACMPHS0 interrupt is disabled #0 1 - Response timeout detected + S/W standby returns by ACMPHS0 interrupt is enabled #1 - ILR - SD_BUF Illegal Read Access - 5 - 5 + VBATTWUPEN + VBATT monitor interrupt S/W standby returns enable + 20 + 20 read-write - zeroToClear - modify 0 - Illegal read access to the SD_BUF register not detected + S/W standby returns by VBATT monitor interrupt is disabled #0 1 - Illegal read access to the SD_BUF register detected + S/W standby returns by VBATT monitor interrupt is enabled #1 - ILW - SD_BUF Illegal Write Access - 4 - 4 + LVD2WUPEN + LVD2 interrupt S/W standby returns enable + 19 + 19 read-write - zeroToClear - modify 0 - Illegal write access to the SD_BUF register not detected + S/W standby returns by LVD2 interrupt is disabled #0 1 - Illegal write access to the SD_BUF register detected + S/W standby returns by LVD2 interrupt is enabled #1 - DTO - Data Timeout - 3 - 3 + LVD1WUPEN + LVD1 interrupt S/W standby returns enable + 18 + 18 read-write - zeroToClear - modify 0 - Data timeout not detected + S/W standby returns by LVD1 interrupt is disabled #0 1 - Data timeout detected + S/W standby returns by LVD1 interrupt is enabled #1 - ENDE - END Error - 2 - 2 + KEYWUPEN + Key interrupt S/W standby returns enable + 17 + 17 read-write - zeroToClear - modify 0 - End bit error not detected + S/W standby returns by KEY interrupt is disabled #0 1 - End bit error detected + S/W standby returns by KEY interrupt is enabled #1 - CRCE - CRC Error - 1 - 1 + IWDTWUPEN + IWDT interrupt S/W standby returns enable + 16 + 16 read-write - zeroToClear - modify 0 - CRC error not detected + S/W standby returns by IWDT interrupt is disabled #0 1 - CRC error detected + S/W standby returns by IWDT interrupt is enabled #1 - CMDE - Command Error + 16 + 0x01 + IRQWUPEN%s + IRQ interrupt S/W standby returns enable 0 0 read-write - zeroToClear - modify 0 - Command error not detected + S/W standby returns by IRQ interrupt is disabled #0 1 - Command error detected + S/W standby returns by IRQ interrupt is enabled #1 @@ -58406,325 +47169,442 @@ FMS2,1,0: - SD_INFO1_MASK - SD_INFO1 Interrupt Mask Register - 0x040 + WUPEN1 + Wake Up interrupt enable register 1 + 0x1A4 32 read-write - 0x0000031D - 0xFFFFFFFF + 0x00000000 + 0xffffffff - SDD3INM - SDnDAT3 Card Insertion Interrupt Request Mask - 9 - 9 + AGT3UDWUPEN + AGT3 underflow interrupt S/W standby returns enable bit + 0 + 0 read-write 0 - SD card insertion interrupt request by the SDnDAT3 is not masked + S/W standby returns by AGT3 underflow interrupt is disabled #0 1 - SD card insertion interrupt request by the SDnDAT3 is masked + S/W standby returns by AGT3 underflow interrupt is enabled #1 - SDD3RMM - SDnDAT3 Card Removal Interrupt Request Mask - 8 - 8 + AGT3CAWUPEN + AGT3 compare match A interrupt S/W standby returns enable bit + 1 + 1 read-write 0 - SD card removal interrupt request by the SDnDAT3 is not masked + S/W standby returns by AGT3 compare match A interrupt is disabled #0 1 - SD card removal interrupt request by the SDnDAT3 is masked + S/W standby returns by AGT3 compare match A interrupt is enabled #1 - SDCDINM - SDnCD card Insertion Interrupt Request Mask - 4 - 4 + AGT3CBWUPEN + AGT3 compare match B interrupt S/W standby returns enable bit + 2 + 2 read-write 0 - Card insertion interrupt request by the SDnCD is not masked + S/W standby returns by AGT3 compare match B interrupt is disabled #0 1 - Card insertion interrupt request by the SDnCD is masked + S/W standby returns by AGT3 compare match B interrupt is enabled #1 + + + + + + R_IIC0 + I2C Bus Interface + 0x40053000 + + 0x00000000 + 0x014 + registers + + + 0x00000016 + 0x002 + registers + + + + 3 + 0x2 + SAR[%s] + Slave Address Registers + 0x0A + 16 + + L + Slave Address Register L + 0x0 + 8 + read-write + 0x00 + 0xFF + + + SVA + A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } + 0 + 7 + read-write + + + + + U + Slave Address Register U + 0x01 + 8 + read-write + 0x00 + 0xFF + + + SVA9 + 10-Bit Address(bit9) + 2 + 2 + read-write + + + SVA8 + 10-Bit Address(bit8) + 1 + 1 + read-write + + + FS + 7-Bit/10-Bit Address Format Selection + 0 + 0 + read-write + + + 0 + The 7-bit address format is selected. + #0 + + + 1 + The 10-bit address format is selected. + #1 + + + + + + + + ICCR1 + I2C Bus Control Register 1 + 0x00 + 8 + read-write + 0x1F + 0xFF + - SDCDRMM - SDnCD card Removal Interrupt Request Mask - 3 - 3 + ICE + I2C Bus Interface Enable + 7 + 7 read-write 0 - Card removal interrupt request by the by the SDnCD is not masked + Disable (SCLn and SDAn pins in inactive state) #0 1 - Card removal interrupt request by the by the SDnCD is masked + Enable (SCLn and SDAn pins in active state) #1 - ACENDM - Access End Interrupt Request Mask - 2 - 2 + IICRST + I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). + 6 + 6 read-write 0 - Access end interrupt request is not masked + Releases the RIIC reset or internal reset. #0 1 - Access end interrupt request is masked + Initiates the RIIC reset or internal reset. #1 - RSPENDM - Response End Interrupt Request Mask - 0 - 0 + CLO + Extra SCL Clock Cycle Output + 5 + 5 read-write 0 - Response end interrupt request is not masked + Does not output an extra SCL clock cycle. #0 1 - Response end interrupt request is masked + Outputs an extra SCL clock cycle. #1 - - - - SD_INFO2_MASK - SD_INFO2 Interrupt Mask Register - 0x044 - 32 - read-write - 0x00008B7F - 0xFFFFFFFF - - ILAM - Illegal Access Error Interrupt Request Mask - 15 - 15 + SOWP + SCLO/SDAO Write Protect + 4 + 4 read-write 0 - Illegal access error interrupt request not masked + Bits SCLO and SDAO can be written #0 1 - Illegal access error interrupt request masked + Bits SCLO and SDAO are protected. #1 - BWEM - BWE Interrupt Request Mask - 9 - 9 + SCLO + SCL Output Control/Monitor + 3 + 3 read-write 0 - Write enable interrupt request for the SD_BUF register not masked + (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 - Write enable interrupt request for the SD_BUF register masked + (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 - BREM - BRE Interrupt Request Mask - 8 - 8 + SDAO + SDA Output Control/Monitor + 2 + 2 read-write 0 - Read enable interrupt request for the SD buffer not masked + (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 - Read enable interrupt request for the SD buffer masked + (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 - RSPTOM - Response Timeout Interrupt Request Mask - 6 - 6 - read-write + SCLI + SCL Line Monitor + 1 + 1 + read-only 0 - Response timeout interrupt request not masked + SCLn line is low. #0 1 - Response timeout interrupt request masked + SCLn line is high. #1 - ILRM - SD_BUF Register Illegal Read Interrupt Request Mask - 5 - 5 - read-write + SDAI + SDA Line Monitor + 0 + 0 + read-only 0 - Illegal read detection interrupt request for the SD_BUF register not masked + SDAn line is low. #0 1 - Illegal read detection interrupt request for the SD_BUF register masked + SDAn line is high. + #1 + + + + + + + ICCR2 + I2C Bus Control Register 2 + 0x01 + 8 + read-write + 0x00 + 0xFF + + + BBSY + Bus Busy Detection Flag + 7 + 7 + read-only + + + 0 + The I2C bus is released (bus free state). + #0 + + + 1 + The I2C bus is occupied (bus busy state). #1 - ILWM - SD_BUF Register Illegal Write Interrupt Request Mask - 4 - 4 + MST + Master/Slave Mode + 6 + 6 read-write 0 - Illegal write detection interrupt request for the SD_BUF register not masked + Slave mode #0 1 - Illegal write detection interrupt request for the SD_BUF register masked + Master mode #1 - DTOM - Data Timeout Interrupt Request Mask - 3 - 3 + TRS + Transmit/Receive Mode + 5 + 5 read-write 0 - Data timeout interrupt request not masked + Receive mode #0 1 - Data timeout interrupt request masked + Transmit mode #1 - ENDEM - End Bit Error Interrupt Request Mask - 2 - 2 + SP + Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. + 3 + 3 read-write 0 - End bit detection error interrupt request not masked + Does not request to issue a stop condition. #0 1 - End bit detection error interrupt request masked + Requests to issue a stop condition. #1 - CRCEM - CRC Error Interrupt Request Mask - 1 - 1 + RS + Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. + 2 + 2 read-write 0 - CRC error interrupt request not masked + Does not request to issue a restart condition. #0 1 - CRC error interrupt request masked + Requests to issue a restart condition. #1 - CMDEM - Command Error Interrupt Request Mask - 0 - 0 + ST + Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). + 1 + 1 read-write 0 - Command error interrupt request not masked + Does not request to issue a start condition. #0 1 - Command error interrupt request masked + Requests to issue a start condition. #1 @@ -58732,571 +47612,599 @@ FMS2,1,0: - SD_CLK_CTRL - SD Clock Control Register - 0x048 - 32 + ICMR1 + I2C Bus Mode Register 1 + 0x02 + 8 read-write - 0x00000020 - 0xFFFFFFFF + 0x08 + 0xFF - CLKCTRLEN - SD/MMC Clock Output Automatic Control Enable - 9 - 9 + MTWP + MST/TRS Write Protect + 7 + 7 read-write 0 - Automatic control for SD/MMC Clock output is disabled. + Disables writing to the MST and TRS bits in ICCR2. #0 1 - Automatic control for SD/MMC Clock output is enabled. + Enables writing to the MST and TRS bits in ICCR2. #1 - CLKEN - SD/MMC Clock Output Control Enable - 8 - 8 + CKS + Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) + 4 + 6 read-write + + + 000 + PCLKB/1 clock + #000 + + + 001 + PCLKB/2 clock + #001 + + + 010 + PCLKB/4 clock + #010 + + + 011 + PCLKB/8 clock + #011 + + + 100 + PCLKB/16 clock + #100 + + + 101 + PCLKB/32 clock + #101 + + + 110 + PCLKB/64 clock + #110 + + + 111 + PCLKB/128 clock + #111 + + + + + BCWP + BC Write Protect(This bit is read as 1.) + 3 + 3 + write-only 0 - SD/MMC Clock output is disabled. The SDCLK signal is fixed 0. + Enables a value to be written in the BC[2:0] bits. #0 1 - SD/MMC Clock output is enabled. + Disables a value to be written in the BC[2:0] bits. #1 - CLKSEL - SDHI Clock Frequency Select + BC + Bit Counter 0 - 7 + 2 read-write - 0x00 - PCLKA divided by 2 - 0x00 - - - 0x01 - PCLKA divided by 4 - 0x01 - - - 0x02 - PCLKA divided by 8 - 0x02 + 000 + 9 bits + #000 - 0x04 - PCLKA divided by 16 - 0x04 + 001 + 2 bits + #001 - 0x08 - PCLKA divided by 32 - 0x08 + 010 + 3 bits + #010 - 0x10 - PCLKA divided by 64 - 0x10 + 011 + 4 bits + #011 - 0x20 - PCLKA divided by 128 - 0x20 + 100 + 5 bits + #100 - 0x40 - PCLKA divided by 256 - 0x40 + 101 + 6 bits + #101 - 0x80 - PCLKA divided by 512 - 0x80 + 110 + 7 bits + #110 - others - Settings prohibited. - true + 111 + 8 bits + #111 - SD_SIZE - Transfer Data Length Register - 0x04C - 32 - read-write - 0x00000200 - 0xFFFFFFFF - - - LEN - Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0. - 0 - 9 - read-write - - - - - SD_OPTION - SD Card Access Control Option Register - 0x050 - 32 + ICMR2 + I2C Bus Mode Register 2 + 0x03 + 8 read-write - 0x000040EE - 0xFFFFFFFF + 0x06 + 0xFF - WIDTH - Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0. - 15 - 15 + DLCS + SDA Output Delay Clock Source Select + 7 + 7 read-write 0 - 4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1) + The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 - 1-bit width (WIDTH8=0 or 1 ) + The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 - WIDTH8 - Bus Widthsee b15, WIDTH bit - 13 - 13 - read-write - - - TOUTMASK - Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence. - 8 - 8 + SDDL + SDA Output Delay Counter + 4 + 6 read-write - 0 - Activate Timeout - #0 + 000 + No output delay + #000 - 1 - Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set) - #1 + 001 + 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) + #001 - - - - TOP - Timeout Counter - 4 - 7 - read-write - - 1111 - Setting prohibited - #1111 + 010 + 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) + #010 - others - SDHI clock x 2^(TOP+13) - true + 011 + 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) + #011 + + + 100 + 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) + #100 + + + 101 + 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) + #101 + + + 110 + 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) + #110 + + + 111 + 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) + #111 - CTOP - Card Detect Time Counter - 0 - 3 + TMOH + Timeout H Count Control + 2 + 2 read-write - 1111 - Setting prohibited - #1111 + 0 + Count is disabled while the SCLn line is at a high level. + #0 - others - IMCLK x 2^(CTOP+10) - true + 1 + Count is enabled while the SCLn line is at a high level. + #1 - - - - SD_ERR_STS1 - SD Error Status Register 1 - 0x058 - 32 - read-only - 0x00002000 - 0xFFFFFFFF - - - CRCTK - CRC Status TokenStore the CRC status token value (normal value is 010b) - 12 - 14 - read-only - - CRCTKE - CRC Status Token Error - 11 - 11 - read-only + TMOL + Timeout L Count Control + 1 + 1 + read-write 0 - An error has not occured in the CRC status. + Count is disabled while the SCLn line is at a low level. #0 1 - An error has occured in the CRC status. + Count is enabled while the SCLn line is at a low level. #1 - RDCRCE - Read Data CRC Error - 10 - 10 - read-only + TMOS + Timeout Detection Time Select + 0 + 0 + read-write 0 - CRC error has detected in read data + Long mode is selected. #0 1 - CRC error has not detected in read data + Short mode is selected. #1 + + + + ICMR3 + I2C Bus Mode Register 3 + 0x04 + 8 + read-write + 0x00 + 0xFF + - RSPCRCE1 - Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0. - 9 - 9 - read-only + SMBS + SMBus/I2C Bus Selection + 7 + 7 + read-write 0 - CRC error has not occured. + The I2C bus is selected. #0 1 - CRC error has occured in the response to a command issued within a command sequence. + The SMBus is selected. #1 - RSPCRCE0 - Response CRC Error 0NOTE: other than a response to a command issued within a command sequence - 8 - 8 - read-only + WAIT + WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. + 6 + 6 + read-write 0 - A CRC error has not occur in a response + No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 - A CRC error has occured in a response + WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 - CRCLENE - CRC Status Token Length Error + RDRFS + RDRF Flag Set Timing Selection 5 5 - read-only + read-write 0 - An error has not occured in the CRC status length. + The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 - An error has occured in the CRC status length (and the end bit has not been detected) + The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 - RDLENE - Read Data Length Error + ACKWP + ACKBT Write Protect 4 4 - read-only + read-write 0 - An error has occurred not in the read data length. + Modification of the ACKBT bit is disabled. #0 1 - An error has occured in the read data length (and the end bit has not been detected among the valid bits). + Modification of the ACKBT bit is enabled. #1 - RSPLENE1 - Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0. + ACKBT + Transmit Acknowledge 3 3 - read-only + read-write 0 - An error has not occurred in the response length to a command issued within a command sequence. + A 0 is sent as the acknowledge bit (ACK transmission). #0 1 - An error has occured in the response length to a command issued within a command sequence. + A 1 is sent as the acknowledge bit (NACK transmission). #1 - RSPLENE0 - Response Length Error 0NOTE: other than a response to a command issued within a command sequence + ACKBR + Receive Acknowledge 2 2 read-only 0 - An error has not occured in the response length + A 0 is received as the acknowledge bit (ACK reception). #0 1 - An error has occured in the response length + A 1 is received as the acknowledge bit (NACK reception). #1 - CMDE1 - Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0. - 1 + NF + Noise Filter Stage Selection + 0 1 - read-only + read-write - 0 - An error has not occurs in the command index of the response to a command issued within a command sequence. - #0 + 00 + Noise of up to one fIIC cycle is filtered out (single-stage filter). + #00 - 1 - An error has occured in the command index of the response to a command issued within a command sequence. - #1 + 01 + Noise of up to two fIIC cycles is filtered out (2-stage filter). + #01 + + + 10 + Noise of up to three fIIC cycles is filtered out (3-stage filter). + #10 + + + 11 + Noise of up to four fIIC cycles is filtered out (4-stage filter) + #11 + + + + ICFER + I2C Bus Function Enable Register + 0x05 + 8 + read-write + 0x72 + 0xFF + - CMDE0 - Command Error 0NOTE: other than a response to a command issued within a command sequence - 0 - 0 - read-only + FMPE + Fast-mode Plus Enable + 7 + 7 + read-write 0 - An error has not occured in the command index of a response. + No Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #0 1 - An error has occured in the command index of a response. + An Fm+ slope control circuit is used for the SCLn pin and SDAn pin. #1 - - - - SD_ERR_STS2 - SD Error Status Register 2 - 0x05C - 32 - read-only - 0x00000000 - 0xFFFFFFFF - - CRCBSYTO - CRC Status Token Busy Timeout + SCLE + SCL Synchronous Circuit Enable 6 6 - read-only + read-write 0 - Not timeout + No SCL synchronous circuit is used. #0 1 - The busy state continues for longer than N-cycle after the CRC status + An SCL synchronous circuit is used. #1 - CRCTO - CRC Status Token Timeout + NFE + Digital Noise Filter Circuit Enable 5 5 - read-only + read-write 0 - Not timeout + No digital noise filter circuit is used. #0 1 - The CRC status is not received though a longer time than N-cycle has elapsed after data writing. + A digital noise filter circuit is used. #1 - RDTO - Read Data Timeout + NACKE + NACK Reception Transfer Suspension Enable 4 4 - read-only + read-write 0 - Not timeout + Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 - The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state. + Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 - BSYTO1 - Busy Timeout 1 + SALE + Slave Arbitration-Lost Detection Enable 3 3 - read-only + read-write 0 - Not timeout. + Slave arbitration-lost detection is disabled. #0 1 - The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0. + Slave arbitration-lost detection is enabled. #1 - BSYTO0 - Busy Timeout 0 + NALE + NACK Transmission Arbitration-Lost Detection Enable 2 2 - read-only + read-write 0 - Not timeout. + NACK transmission arbitration-lost detection is disabled. #0 1 - The busy state for longer than N-cycle continues after R1b response. + NACK transmission arbitration-lost detection is enabled. #1 - RSPTO1 - Response Timeout 1 + MALE + Master Arbitration-Lost Detection Enable 1 1 - read-only + read-write 0 - Not timeout. + Master arbitration-lost detection is disabled. #0 1 - The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0. + Master arbitration-lost detection is enabled. #1 - RSPTO0 - Response Timeout 0 + TMOE + Timeout Function Enable 0 0 - read-only + read-write 0 - Not timeout. + The timeout function is disabled. #0 1 - The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. + The timeout function is enabled. #1 @@ -59304,130 +48212,124 @@ FMS2,1,0: - SD_BUF0 - SD Buffer Register - 0x060 - 32 + ICSER + I2C Bus Status Enable Register + 0x06 + 8 read-write - 0x00000000 - 0x00000000 + 0x09 + 0xFF - SD_BUF - SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data. - 0 - 31 + HOAE + Host Address Enable + 7 + 7 read-write + + + 0 + Host address detection is disabled. + #0 + + + 1 + Host address detection is enabled. + #1 + + - - - - SDIO_MODE - SDIO Mode Control Register - 0x068 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - C52PUB - SDIO None AbortNOTE: See manual - 9 - 9 + DIDE + Device-ID Address Detection Enable + 5 + 5 read-write + + + 0 + Device-ID address detection is disabled. + #0 + + + 1 + Device-ID address detection is enabled. + #1 + + - IOABT - SDIO AbortNOTE: See manual - 8 - 8 + GCAE + General Call Address Enable + 3 + 3 read-write + + + 0 + General call address detection is disabled. + #0 + + + 1 + General call address detection is enabled. + #1 + + - RWREQ - Read Wait Request + SAR2E + Slave Address Register 2 Enable 2 2 read-write 0 - Allow SD/MMC to exit read wait state + Slave address in SARL2 and SARU2 is disabled. #0 1 - Request for SD/MMC to enter read wait state. + Slave address in SARL2 and SARU2 is enabled #1 - INTEN - SDIO Mode - 0 - 0 + SAR1E + Slave Address Register 1 Enable + 1 + 1 read-write - - 1 - Enables the SD host interface to receive SDIO interrupt from the SDIO card - #1 - 0 - Disables the SD host interface to receive SDIO interrupt from the SDIO card + Slave address in SARL1 and SARU1 is disabled. #0 + + 1 + Slave address in SARL1 and SARU1 is enabled. + #1 + - - - - SDIO_INFO1 - SDIO Interrupt Flag Register 1 - 0x06C - 32 - read-write - 0x00000000 - 0xFFFFFFF9 - - - EXWT - EXWT Status FlagNOTE: See manual - 15 - 15 - read-write - zeroToClear - modify - - - EXPUB52 - EXPUB52 Status FlagNOTE: See manual - 14 - 14 - read-write - zeroToClear - modify - - IOIRQ - SDIO Interrupt Status + SAR0E + Slave Address Register 0 Enable 0 0 read-write - zeroToClear - modify 0 - SDIO interrupt not accepted + Slave address in SARL0 and SARU0 is disabled. #0 1 - SDIO interrupt accepted + Slave address in SARL0 and SARU0 is enabled. #1 @@ -59435,486 +48337,472 @@ FMS2,1,0: - SDIO_INFO1_MASK - SDIO_INFO1 Interrupt Mask Register - 0x070 - 32 + ICIER + I2C Bus Interrupt Enable Register + 0x07 + 8 read-write - 0x0000C007 - 0xFFFFFFFF + 0x00 + 0xFF - EXWTM - EXWT Interrupt Request Mask Control - 15 - 15 + TIE + Transmit Data Empty Interrupt Request Enable + 7 + 7 read-write 0 - EXWT interrupt request not masked + Transmit data empty interrupt request (IIC_TXI) is disabled. #0 1 - EXWT interrupt request masked + Transmit data empty interrupt request (IIC_TXI) is enabled. #1 - EXPUB52M - EXPUB52 Interrupt Request Mask Control - 14 - 14 + TEIE + Transmit End Interrupt Request Enable + 6 + 6 read-write 0 - EXPUB52 interrupt request not masked + Transmit end interrupt request (IIC_TEI) is disabled. #0 1 - EXPUB52 interrupt request masked + Transmit end interrupt request (IIC_TEI) is enabled. #1 - IOIRQM - IOIRQ Interrupt Mask Control - 0 - 0 + RIE + Receive Data Full Interrupt Request Enable + 5 + 5 read-write 0 - IOIRQ interrupt not masked + Receive data full interrupt request (IIC_RXI) is disabled. #0 1 - IOIRQ interrupt masked + Receive data full interrupt request (IIC_RXI) is enabled. #1 - - - - SD_DMAEN - DMA Mode Enable Register - 0x1B0 - 32 - read-write - 0x00001010 - 0xFFFFFFFF - - DMAEN - SD_BUF Read/Write DMA Transfer - 1 - 1 + NAKIE + NACK Reception Interrupt Request Enable + 4 + 4 read-write 0 - The SD_BUF read/write DMA transfer is disabled. + NACK reception interrupt request (NAKI) is disabled. #0 1 - The SD_BUF read/write DMA transfer is enabled. + NACK reception interrupt request (NAKI) is enabled. #1 - - - - SOFT_RST - Software Reset Register - 0x1C0 - 32 - read-write - 0x00000007 - 0xFFFFFFFF - - SDRST - Software Reset of SD I/F Unit - 0 - 0 + SPIE + Stop Condition Detection Interrupt Request Enable + 3 + 3 read-write 0 - Reset + Stop condition detection interrupt request (SPI) is disabled. #0 1 - Reset released + Stop condition detection interrupt request (SPI) is enabled. #1 - - - - SDIF_MODE - SD Interface Mode Setting Register - 0x1CC - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - NOCHKCR - CRC Check Mask (for MMC test commands) - 8 - 8 + STIE + Start Condition Detection Interrupt Request Enable + 2 + 2 read-write 0 - CRC check is valid + Start condition detection interrupt request (STI) is disabled. #0 1 - CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write) + Start condition detection interrupt request (STI) is enabled. #1 - - - - EXT_SWAP - Swap Control Register - 0x1E0 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - BRSWP - SD_BUF0 Swap Read - 7 - 7 + ALIE + Arbitration-Lost Interrupt Request Enable + 1 + 1 read-write 0 - The current data are read without swapping. + Arbitration-lost interrupt request (ALI) is disabled. #0 1 - Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds. + Arbitration-lost interrupt request (ALI) is enabled. #1 - BWSWP - SD_BUF0 Swap Write - 6 - 6 + TMOIE + Timeout Interrupt Request Enable + 0 + 0 read-write 0 - The current data are written without swapping. + Timeout interrupt request (TMOI) is disabled. #0 1 - Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds. + Timeout interrupt request (TMOI) is enabled. #1 - - - - R_SDHI1 - 0x40062400 - - - R_SLCDC - Segment LCD Controller/Driver - 0x40082000 - - 0x00 - 4 - registers - - - 0x100 - 38 - registers - - - LCDM0 - LCD Mode Register 0 - 0x000 + ICSR1 + I2C Bus Status Register 1 + 0x08 8 read-write 0x00 0xFF - MDSET - LCD drive voltage generator selection - 6 + HOA + Host Address Detection Flag + 7 7 read-write + zeroToClear + modify - 00 - External resistance division method - #00 - - - 01 - Internal voltage boosting method - #01 - - - 10 - Capacitor split method - #10 + 0 + Host address is not detected. + #0 - 11 - Setting prohibited - #11 + 1 + Host address is detected. + #1 - LWAVE - LCD display waveform selection + DID + Device-ID Address Detection Flag 5 5 read-write 0 - Waveform A + Device-ID command is not detected. #0 1 - Waveform B + Device-ID command is detected. #1 - LDTY - Time Slice of LCD Display Select - 2 - 4 + GCA + General Call Address Detection Flag + 3 + 3 read-write - 000 - Static - #000 - - - 001 - 2-time slice - #001 - - - 010 - 3-time slice - #010 + 0 + General call address is not detected. + #0 - 011 - 4-time slice - #011 + 1 + General call address is detected. + #1 + + + + AAS2 + Slave Address 2 Detection Flag + 2 + 2 + read-write + zeroToClear + modify + - 101 - 8-time slice - #101 + 0 + Slave address 2 is not detected. + #0 - others - Setting prohibited - true + 1 + Slave address 2 is detected + #1 - LBAS - LCD Display Bias Method Select - 0 + AAS1 + Slave Address 1 Detection Flag + 1 1 read-write + zeroToClear + modify - 00 - 1/2 bias method - #00 + 0 + Slave address 1 is not detected. + #0 - 01 - 1/3 bias method - #01 + 1 + Slave address 1 is detected. + #1 + + + + AAS0 + Slave Address 0 Detection Flag + 0 + 0 + read-write + zeroToClear + modify + - 10 - 1/4 bias method - #10 + 0 + Slave address 0 is not detected. + #0 - 11 - Setting prohibited - #11 + 1 + Slave address 0 is detected. + #1 - LCDM1 - LCD Mode Register 1 - 0x001 + ICSR2 + I2C Bus Status Register 2 + 0x09 8 read-write 0x00 0xFF - LCDON - LCD Display Enable/Disable + TDRE + Transmit Data Empty Flag 7 7 - read-write + read-only 0 - Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1) + ICDRT contains transmit data. #0 1 - Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1) + ICDRT contains no transmit data. #1 - SCOC - LCD Display Enable/Disable + TEND + Transmit End Flag 6 6 read-write + zeroToClear + modify 0 - Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1) + Data is being transmitted. #0 1 - Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1) + Data has been transmitted. #1 - VLCON - Voltage boost circuit or capacitor split circuit operation enable/disable + RDRF + Receive Data Full Flag 5 5 read-write + zeroToClear + modify 0 - Stops voltage boost circuit or capacitor split circuit operation + ICDRR contains no receive data. #0 1 - Enables voltage boost circuit or capacitor split circuit operation + ICDRR contains receive data. #1 - BLON - Display data area control + NACKF + NACK Detection Flag 4 4 read-write + zeroToClear + modify 0 - Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1) + NACK is not detected. #0 1 - Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC)) + NACK is detected. #1 - LCDSEL - Display data area control + STOP + Stop Condition Detection Flag 3 3 read-write + zeroToClear + modify 0 - Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) + Stop condition is not detected. #0 1 - Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) + Stop condition is detected. #1 - Reserved - These bits are read as 00. The write value should be 00. - 1 + START + Start Condition Detection Flag + 2 2 read-write + zeroToClear + modify + + + 0 + Start condition is not detected. + #0 + + + 1 + Start condition is detected. + #1 + + + + + AL + Arbitration-Lost Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Arbitration is not lost. + #0 + + + 1 + Arbitration is lost. + #1 + + - LCDVLM - Voltage Boosting Pin Initial Value Switching Control + TMOF + Timeout Detection Flag 0 0 read-write + zeroToClear + modify 0 - Set when VDD >= 2.7 V + Timeout is not detected. #0 1 - Set when VDD <= 4.2 V + Timeout is detected. #1 @@ -59922,771 +48810,631 @@ FMS2,1,0: - LCDC0 - LCD Clock Control Register 0 - 0x002 + ICBRL + I2C Bus Bit Rate Low-Level Register + 0x10 8 read-write - 0x00 + 0xFF 0xFF - LCDC - LCD clock (LCDCL) + BRL + Bit Rate Low-Level Period(Low-level period of SCL clock) 0 - 5 + 4 read-write - - - 000001 - (Sub clock)/22 or (LOCO clock)/22 - #000001 - - - 000010 - (Sub clock)/23 or (LOCO clock)/23 - #000010 - - - 000011 - (Sub clock)/24 or (LOCO clock)/24 - #000011 - - - 000100 - (Sub clock)/25 or (LOCO clock)/25 - #000100 - - - 000101 - (Sub clock)/26 or (LOCO clock)/26 - #000101 - - - 000110 - (Sub clock)/27 or (LOCO clock)/27 - #000110 - - - 000111 - (Sub clock)/28 or (LOCO clock)/28 - #000111 - - - 001000 - (Sub clock)/29 or (LOCO clock)/29 - #001000 - - - 001001 - (Sub clock)/210 or (LOCO clock)/210 - #001001 - - - 010001 - (Main clock)/28 or (HOCO clock)/28 - #010001 - - - 010010 - (Main clock)/29 or (HOCO clock)/29 - #010010 - - - 010011 - (Main clock)/210 or (HOCO clock)/210 - #010011 - - - 010100 - (Main clock)/211 or (HOCO clock)/211 - #010100 - - - 010101 - (Main clock)/212 or (HOCO clock)/212 - #010101 - - - 010110 - (Main clock)/213 or (HOCO clock)/213 - #010110 - - - 010111 - (Main clock)/214 or (HOCO clock)/214 - #010111 - - - 011000 - (Main clock)/215 or (HOCO clock)/215 - #011000 - - - 011001 - (Main clock)/216 or (HOCO clock)/216 - #011001 - - - 011010 - (Main clock)/217 or (HOCO clock)/217 - #011010 - - - 011011 - (Main clock)/218 or (HOCO clock)/218 - #011011 - - - 101011 - (Main clock)/219 or (HOCO clock)/219 - #101011 - - - others - Other than above Setting prohibited - true - - - VLCD - LCD Boost Level Control Register - 0x003 + ICBRH + I2C Bus Bit Rate High-Level Register + 0x11 8 read-write - 0x04 + 0xFF 0xFF - VLCD - Reference Voltage(Contrast Adjustment) Select + BRH + Bit Rate High-Level Period(High-level period of SCL clock) 0 4 read-write - - - 00100 - Reference voltageselection(contrast adjustment): 1.00 V (default) VL4 voltage: 3.00 V(1/3 bias method)/4.00 V(1/4 bias method) - #00100 - - - 00101 - Reference voltageselection(contrast adjustment): 1.05 V VL4 voltage: 3.15 V(1/3 bias method)/4.20 V(1/4 bias method) - #00101 - - - 00110 - Reference voltageselection(contrast adjustment): 1.10 V VL4 voltage: 3.30 V(1/3 bias method)/4.40 V(1/4 bias method) - #00110 - - - 00111 - Reference voltageselection(contrast adjustment): 1.15 V VL4 voltage: 3.45 V(1/3 bias method)/4.60 V(1/4 bias method) - #00111 - - - 01000 - Reference voltageselection(contrast adjustment): 1.20 V VL4 voltage: 3.60 V(1/3 bias method)/4.80 V(1/4 bias method) - #01000 - - - 01001 - Reference voltageselection(contrast adjustment): 1.25 V VL4 voltage: 3.75 V(1/3 bias method)/5.00 V(1/4 bias method) - #01001 - - - 01010 - Reference voltageselection(contrast adjustment): 1.30 V VL4 voltage: 3.90 V(1/3 bias method)/5.20 V(1/4 bias method) - #01010 - - - 01011 - Reference voltageselection(contrast adjustment): 1.35 V VL4 voltage: 4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #01011 - - - 01100 - Reference voltageselection(contrast adjustment): 1.40 V VL4 voltage: 4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #01100 - - - 01101 - Reference voltageselection(contrast adjustment): 1.45 V VL4 voltage: 4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #01101 - - - 01110 - Reference voltageselection(contrast adjustment): 1.50 V VL4 voltage: 4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #01110 - - - 01111 - Reference voltageselection(contrast adjustment): 1.55 V VL4 voltage: 4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #01111 - - - 10000 - Reference voltageselection(contrast adjustment): 1.60 V VL4 voltage: 4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #10000 - - - 10001 - Reference voltageselection(contrast adjustment): 1.65 V VL4 voltage: 4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #10001 - - - 10010 - Reference voltageselection(contrast adjustment): 1.70 V VL4 voltage: 5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #10010 - - - 10011 - Reference voltageselection(contrast adjustment): 1.75 V VL4 voltage: 5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method) - #10011 - - - others - Setting prohibited - true - - - 64 - 0x1 - SEG[%s] - LCD Display Data Array - 0x100 + ICDRT + I2C Bus Transmit Data Register + 0x12 8 read-write - 0x00 + 0xFF 0xFF - A - A-Pattern Area + ICDRT + 8-bit read-write register that stores transmit data. 0 - 3 + 7 read-write + + + + ICDRR + I2C Bus Receive Data Register + 0x13 + 8 + read-only + 0x00 + 0xFF + - B - B-Pattern Area - 4 + ICDRR + 8-bit register that stores the received data + 0 7 - read-write + read-only - - - - R_SPI0 - Serial Peripheral Interface - 0x40072000 - - 0x00000000 - 0x008 - registers - - - 0x0000000A - 0x008 - registers - - - SPCR - SPI Control Register - 0x00 + ICWUR + I2C Bus Wake Up Unit Register + 0x16 8 read-write - 0x00 + 0x10 0xFF - SPRIE - SPI Receive Buffer Full Interrupt Enable + WUE + Wakeup Function Enable 7 7 read-write 0 - Disables the generation of SPI receive buffer full interrupt requests + Wakeup function disabled #0 1 - Enables the generation of SPI receive buffer full interrupt requests + Wakeup function enabled. #1 - SPE - SPI Function Enable + WUIE + Wakeup Interrupt Request Enable 6 6 read-write 0 - Disables the SPI function + Wakeup Interrupt Request (IIC0_WUI) disabled #0 1 - Enables the SPI function + Wakeup Interrupt Request (IIC0_WUI) enabled. #1 - SPTIE - Transmit Buffer Empty Interrupt Enable + WUF + Wakeup Event Occurrence Flag 5 5 read-write 0 - Disables the generation of transmit buffer empty interrupt requests + Slave address does not match during wakeup function #0 1 - Enables the generation of transmit buffer empty interrupt requests + Slave address matches during wakeup function. #1 - SPEIE - SPI Error Interrupt Enable + WUACK + ACK bit for Wakeup Mode 4 4 read-write 0 - Disables the generation of SPI error interrupt requests - #0 - - - 1 - Enables the generation of SPI error interrupt requests - #1 - - - - - MSTR - SPI Master/Slave Mode Select - 3 - 3 - read-write - - - 0 - Slave mode - #0 - - - 1 - Master mode - #1 - - - - - MODFEN - Mode Fault Error Detection Enable - 2 - 2 - read-write - - - 0 - Disables the detection of mode fault error - #0 - - - 1 - Enables the detection of mode fault error - #1 - - - - - TXMD - Communications Operating Mode Select - 1 - 1 - read-write - - - 0 - Full-duplex synchronous serial communications - #0 - - - 1 - Serial communications consisting of only transmit operations - #1 - - - - - SPMS - SPI Mode Select - 0 - 0 - read-write - - - 0 - SPI operation (4-wire method) + State of synchronous operation #0 1 - Clock synchronous operation (3-wire method) + State of asynchronous operation #1 - - - - - - SSLP - SPI Slave Select Polarity Register - 0x01 - 8 - read-write - 0x00 - 0xFF - - - SSL3P - SSL3 Signal Polarity Setting - 3 - 3 + + + + WUAFA + Wakeup Analog Filter Additional Selection + 0 + 0 read-write 0 - SSL3 signal is active low + Do not add the wakeup analog filter #0 1 - SSL3 signal is active high + Add the wakeup analog filter. #1 + + + + ICWUR2 + I2C Bus Wake up Unit Register 2 + 0x17 + 8 + read-write + 0xFD + 0xFF + - SSL2P - SSL2 Signal Polarity Setting + WUSYF + Wake-up Function Synchronous Operation Status Flag 2 2 - read-write + read-only 0 - SSL2 signal is active low + IIC asynchronous circuit enable condition #0 1 - SSL2 signal is active high + IIC synchronous circuit enable condition. #1 - SSL1P - SSL1 Signal Polarity Setting + WUASYF + Wake-up Function Asynchronous Operation Status Flag 1 1 - read-write + read-only 0 - SSL1 signal is active low + IIC synchronous circuit enable condition #0 1 - SSL1 signal is active high + IIC asynchronous circuit enable condition. #1 - SSL0P - SSL0 Signal Polarity Setting + WUSEN + Wake-up Function Synchronous Enable 0 0 - read-write + read-only 0 - SSL0 signal is active low + IIC asynchronous circuit enable #0 1 - SSL0 signal is active high + IIC synchronous circuit enable #1 + + + + R_IIC1 + 0x40053100 + + + R_IIC2 + 0x40053200 + + + R_IRDA + IrDA Interface + 0x40070F00 + + 0x00000000 + 0x01 + registers + + - SPPCR - SPI Pin Control Register - 0x02 + IRCR + IrDA Control Register + 0x00 8 read-write 0x00 0xFF - MOIFE - MOSI Idle Value Fixing Enable - 5 - 5 + IRE + IrDA Enable + 7 + 7 read-write 0 - MOSI output value equals final data from previous transfer + Serial I/O pins are used for normal serial communication. #0 1 - MOSI output value equals the value set in the MOIFV bit + Serial I/O pins are used for IrDA data communication. #1 - MOIFV - MOSI Idle Fixed Value - 4 - 4 + IRTXINV + IRTXD Polarity Switching + 3 + 3 read-write 0 - The level output on the MOSIn pin during MOSI idling corresponds to low. + Data to be transmitted is output to IRTXD as is. #0 1 - The level output on the MOSIn pin during MOSI idling corresponds to high. + Data to be transmitted is output to IRTXD after the polarity is inverted. #1 - SPLP2 - SPI Loopback 2 - 1 - 1 + IRRXINV + IRRXD Polarity Switching + 2 + 2 read-write 0 - Normal mode + IRRXD input is used as received data as is. #0 1 - Loopback mode (data is not inverted for transmission) + IRRXD input is used as received data after the polarity is inverted. #1 + + + + + + R_IWDT + Independent Watchdog Timer + 0x40044400 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x02 + registers + + + + IWDTRR + IWDT Refresh Register + 0x00 + 8 + read-write + 0xFF + 0xFF + - SPLP - SPI Loopback + IWDTRR + The counter is refreshed by writing 0x00 and then writing 0xFF to this register. 0 - 0 + 7 read-write - - - 0 - Normal mode - #0 - - - 1 - Loopback mode (data is inverted for transmission) - #1 - - - SPSR - SPI Status Register - 0x03 - 8 + IWDTSR + IWDT Status Register + 0x04 + 16 read-write - 0x20 - 0xFF + 0x0000 + 0xFFFF - SPRF - SPI Receive Buffer Full Flag - 7 - 7 + REFEF + Refresh Error Flag + 15 + 15 read-write zeroToClear modify 0 - No valid data in SPDR + Refresh error not occurred #0 1 - Valid data found in SPDR + Refresh error occurred #1 - SPTEF - SPI Transmit Buffer Empty Flag - 5 - 5 + UNDFF + Underflow Flag + 14 + 14 read-write zeroToClear modify 0 - Data found in the transmit buffer + Underflow not occurred #0 1 - No data in the transmit buffer + Underflow occurred #1 - UDRF - Underrun Error Flag(When MODF is 0, This bit is invalid.) - 4 - 4 + CNTVAL + Counter ValueValue counted by the counter + 0 + 13 + read-only + + + + + + + R_JPEG + JPEG Codec + 0x400E6000 + + 0x00000000 + 0x002 + registers + + + 0x00000003 + 0x00F + registers + + + 0x00000040 + 0x014 + registers + + + 0x00000058 + 0x01C + registers + + + 0x0000008C + 0x008 + registers + + + 0x00000100 + 0x11C + registers + + + 0x00000220 + 0x0B2 + registers + + + 0x00000300 + 0x01C + registers + + + 0x00000320 + 0x0B2 + registers + + + + JCMOD + JPEG Code Mode Register + 0x000 + 8 + read-write + 0x00 + 0xFF + + + DSP + Compression/Decompression Set Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-downmodes. + 3 + 3 read-write - zeroToClear - modify 0 - A mode fault error occurs (MODF=1) + Compression process #0 1 - An underrun error occurs (MODF=1) + Decompression process #1 - PERF - Parity Error Flag - 3 - 3 + REDU + Pixel FormatNOTE: Read-only in Decompression. + 0 + 2 read-write - zeroToClear - modify + + + 001 + YCbCr422(Compression) / YCbCr422(Decompression) + #001 + + + 000 + Setting prohibited(Compression) / YCbCr444(Decompression) + #000 + + + 110 + Setting prohibited(Compression) / YCbCr411/[Decompression] + #110 + + + 010 + Setting prohibited(Compression) / YCbCr420/[Decompression] + #010 + + + others + Setting prohibited(Compression) / Error (this module cannot process normally.)(Decompression]) + true + + + + + + + JCCMD + JPEG Code Command Register + 0x001 + 8 + write-only + 0x00 + 0x00 + + + BRST + Bus Reset. NOTE: When this module is in operation, the bus reset command should not be issued. + 7 + 7 + write-only 0 - No parity error occurs + No effect. #0 1 - A parity error occurs + Resets the JCDTCU, JCDTCM, JCDTCD, JCDERR and JCRST registers. #1 - MODF - Mode Fault Error Flag + JEND + Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1 2 2 - read-write - zeroToClear - modify + write-only 0 - Neither mode fault error nor underrun error occurs + No effect. #0 1 - A mode fault error or an underrun error occurs. + Clear all bits in JINTE0. #1 - IDLNF - SPI Idle Flag + JRST + JPEG Core Process Stop Clear CommandTo clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1. 1 1 - read-only + write-only 0 - SPI is in the idle state + No effect. #0 1 - SPI is in the transfer state + Clear the process-stopped state caused by requests to read the image size and pixel format(enabled by the INT3 bit in JINTE0). #1 - OVRF - Overrun Error Flag + JSRT + JPEG Core Process Start CommandTo start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation. 0 0 - read-write - zeroToClear - modify + write-only 0 - No overrun error occurs + No effect. #0 1 - An overrun error occurs + Start JPEG core processing #1 @@ -60694,497 +49442,471 @@ FMS2,1,0: - SPDR - SPI Data Register - 0x04 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - SPDR_HA - SPI Data Register ( halfword access ) - SPDR - 0x04 - 16 - read-write - 0x0000 - 0xFFFF - - - SPDR_BY - SPI Data Register ( byte access ) - SPDR - 0x04 - 8 - read-write - 0x00 - 0xFF - - - SPSCR - SPI Sequence Control Register - 0x08 + JCQTN + JPEG Code Quantization Table Number Register + 0x003 8 read-write 0x00 0xFF - Reserved - These bits are read as 00000. The write value should be 00000. - 3 - 7 - read-write - - - SPSLN - RSPI Sequence Length Specification -The order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. - 0 - 2 + QT3 + Quantization table number for the third color component NOTE: Read-only in Decompression. + 4 + 5 read-write - 000 - Length 1 SPDMDx x = 0->0->... - #000 + 00 + Use quantization table No.0 (JCQTBL0) as the third color component. + #00 - 001 - Length 2 SPDMDx x = 0->1->0->... - #001 + 01 + Use quantization table No.1 (JCQTBL1) as the third color component. + #01 - 010 - Length 3 SPDMDx x = 0->1->2->0->... - #010 + 10 + Use quantization table No.2 (JCQTBL2) as the third color component. + #10 - 011 - Length 4 SPDMDx x = 0->1->2->3->0->... - #011 + 11 + Use quantization table No.3 (JCQTBL3) as the third color component. + #11 + + + + QT2 + Quantization table number for the second color component NOTE: Read-only in Decompression. + 2 + 3 + read-write + - 100 - Length 5 SPDMDx x = 0->1->2->3->4->0->... - #100 + 00 + Use quantization table No.0 (JCQTBL0) as the second color component. + #00 - 101 - Length 6 SPDMDx x = 0->1->2->3->4->5->0->... - #101 + 01 + Use quantization table No.1 (JCQTBL1) as the second color component. + #01 - 110 - Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... - #110 + 10 + Use quantization table No.2 (JCQTBL2) as the second color component. + #10 - 111 - Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... - #111 + 11 + Use quantization table No.3 (JCQTBL3) as the second color component. + #11 - - - - SPBR - SPI Bit Rate Register - 0x0A - 8 - read-write - 0xFF - 0xFF - - SPR - SPBR sets the bit rate in master mode. + QT1 + Quantization table number for the first color componentNOTE: Read-only in Decompression. 0 - 7 + 1 read-write + + + 00 + Use quantization table No.0 (JCQTBL0) as the first color component. + #00 + + + 01 + Use quantization table No.1 (JCQTBL1) as the first color component. + #01 + + + 10 + Use quantization table No.2 (JCQTBL2) as the first color component. + #10 + + + 11 + Use quantization table No.3 (JCQTBL3) as the first color component. + #11 + + - SPDCR - SPI Data Control Register - 0x0B + JCHTN + JPEG Code Huffman Table Number Register + 0x004 8 read-write 0x00 0xFF - SPBYT - SPI Byte Access Specification - 6 - 6 + HTA3 + Huffman table number (AC) for the third color componentNOTE: Read-only in Decompression. + 5 + 5 read-write 0 - SPDR is accessed in halfword or word (SPLW is valid) + AC Huffman table 0(HTD3=0)/Setting prohibited(HTD3=1) #0 1 - SPDR is accessed in byte (SPLW is invalid). + AC Huffman table 1(HTD3=1)/Setting prohibited(HTD3=0) #1 - SPLW - SPI Word Access/Halfword Access Specification - 5 - 5 + HTD3 + Huffman table number (DC) for the third color component NOTE: Read-only in Decompression. + 4 + 4 read-write 0 - Set SPDR_HA to valid for halfword access + DC Huffman table 0(HTA3=0)/Setting prohibited(HTA3=1) #0 1 - Set SPDR to valid for word access. + DC Huffman table 1(HTA3=1)/Setting prohibited(HTA3=0) #1 - SPRDTD - SPI Receive/Transmit Data Selection - 4 - 4 + HTA2 + Huffman table number (AC) for the second color componentNOTE: Read-only in Decompression. + 3 + 3 read-write 0 - SPDR values are read from the receive buffer + AC Huffman table 0(HTD2=0)/Setting prohibited(HTD2=1) #0 1 - SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) + AC Huffman table 1(HTD2=1)/Setting prohibited(HTD2=0) #1 - SPFC - Number of Frames Specification - 0 + HTD2 + Huffman table number (DC) for the second color component NOTE: Read-only in Decompression. + 2 + 2 + read-write + + + 0 + DC Huffman table 0(HTA2=0)/Setting prohibited(HTA2=1) + #0 + + + 1 + DC Huffman table 1(HTA2=1)/Setting prohibited(HTA2=0) + #1 + + + + + HTA1 + Huffman table number (AC) for the first color componentNOTE: Read-only in Decompression. + 1 1 read-write - 00 - 1 frame - #00 + 0 + AC Huffman table 0(HTD1=0)/Setting prohibited(HTD1=1) + #0 - 01 - 2 frames - #01 + 1 + AC Huffman table 1(HTD1=1)/Setting prohibited(HTD1=0) + #1 + + + + HTD1 + Huffman table number (DC) for the first color component NOTE: Read-only in Decompression. + 0 + 0 + read-write + - 10 - 3 frames - #10 + 0 + DC Huffman table 0(HTA1=0)/Setting prohibited(HTA1=1) + #0 - 11 - 4 frames. - #11 + 1 + DC Huffman table 1(HTA1=1)/Setting prohibited(HTA1=0) + #1 - SPCKD - SPI Clock Delay Register - 0x0C + JCDRIU + JPEG Code DRI Upper Register + 0x005 8 read-write 0x00 0xFF - SCKDL - RSPCK Delay Setting + DRIU + Upper Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. 0 - 2 + 7 read-write - - - 000 - 1 RSPCK - #000 - - - 001 - 2 RSPCK - #001 - - - 010 - 3 RSPCK - #010 - - - 011 - 4 RSPCK - #011 - - - 100 - 5 RSPCK - #100 - - - 101 - 6 RSPCK - #101 - - - 110 - 7 RSPCK - #110 - - - 111 - 8 RSPCK - #111 - - - SSLND - SPI Slave Select Negation Delay Register - 0x0D + JCDRID + JPEG Code DRI Lower Register + 0x006 8 read-write 0x00 0xFF - SLNDL - SSL Negation Delay Setting + DRID + Lower Bytes of MCUs Preceding RST MarkerWhen both upper and lower bytes are set to 00h, neither a DRI nor an RST marker is placed.NOTE: Read-only in Decompression. 0 - 2 + 7 read-write - - - 000 - 1 RSPCK - #000 - - - 001 - 2 RSPCK - #001 - - - 010 - 3 RSPCK - #010 - - - 011 - 4 RSPCK - #011 - - - 100 - 5 RSPCK - #100 - - - 101 - 6 RSPCK - #101 - - - 110 - 7 RSPCK - #110 - - - 111 - 8 RSPCK - #111 - - - SPND - SPI Next-Access Delay Register - 0x0E + JCVSZU + JPEG Code Vertical Size Upper Register + 0x007 8 read-write 0x00 0xFF - SPNDL - SPI Next-Access Delay Setting + VSZU + Upper Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. 0 - 2 + 7 read-write - - - 000 - 1 RSPCK + 2 PCLK - #000 - - - 001 - 2 RSPCK + 2 PCLK - #001 - - - 010 - 3 RSPCK + 2 PCLK - #010 - - - 011 - 4 RSPCK + 2 PCLK - #011 - - - 100 - 5 RSPCK + 2 PCLK - #100 - - - 101 - 6 RSPCK + 2 PCLK - #101 - - - 110 - 7 RSPCK + 2 PCLK - #110 - - - 111 - 8 RSPCK + 2 PCLK - #111 - - - SPCR2 - SPI Control Register 2 - 0x0F + JCVSZD + JPEG Code Vertical Size Lower Register + 0x008 8 read-write 0x00 0xFF - SCKASE - RSPCK Auto-Stop Function Enable - 4 - 4 + VSZD + Lower Bytes of Vertical Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 read-write - - - 0 - Disables the RSPCK auto-stop function - #0 - - - 1 - Enables the RSPCK auto-stop function - #1 - - + + + + JCHSZU + JPEG Code Horizontal Size Upper Register + 0x009 + 8 + read-write + 0x00 + 0xFF + - PTE - Parity Self-Testing - 3 - 3 + HSZU + Upper Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCHSZD + JPEG Coded Horizontal Size Lower Register + 0x00A + 8 + read-write + 0x00 + 0xFF + + + HSZD + Lower Bytes of Horizontal Image SizeIn decompression process, a downloaded value from the JPEG coded data is set. NOTE: Read-only in Decompression. + 0 + 7 + read-write + + + + + JCDTCU + JPEG Code Data Count Upper Register + 0x00B + 8 + read-only + 0x00 + 0xFF + + + DCU + Upper bytes of the counted amount of data to be compressed The values of this register are reset before compression starts.NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JCDTCM + JPEG Code Data Count Middle Register + 0x00C + 8 + read-only + 0x00 + 0xFF + + + DCM + Middle bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts. NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JCDTCD + JPEG Code Data Count Lower Register + 0x00D + 8 + read-only + 0x00 + 0xFF + + + DCD + Lower bytes of the counted amount of data to be compressedThe values of this register are reset before compression starts.NOTE: Read-only in Decompression. + 0 + 7 + read-only + + + + + JINTE0 + JPEG Interrupt Enable Register 0 + 0x00E + 8 + read-write + 0x00 + 0xFF + + + INT7 + This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression.When this bit is not set to enable interrupt generation, an error code is not returned. + 7 + 7 read-write 0 - Disables the self-diagnosis function of the parity circuit + Disabled #0 1 - Enables the self-diagnosis function of the parity circuit + Enabled #1 - SPIIE - SPI Idle Interrupt Enable - 2 - 2 + INT6 + This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + 6 + 6 read-write 0 - Disables the generation of idle interrupt requests + Disabled #0 1 - Enables the generation of idle interrupt requests + Enabled #1 - SPOE - Parity Mode - 1 - 1 + INT5 + This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. + 5 + 5 read-write 0 - Selects even parity for use in transmission and reception + Disabled #0 1 - Selects odd parity for use in transmission and reception + Enabled #1 - SPPE - Parity Enable - 0 - 0 + INT3 + This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. + 3 + 3 read-write 0 - Does not add the parity bit to transmit data and does not check the parity bit of receive data + Disabled #0 1 - Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) + Enabled #1 @@ -61192,159 +49914,134 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - 8 - 0x02 - SPCMD[%s] - SPI Command Register %s - 0x10 - 16 + JINTS0 + JPEG Interrupt Status Register 0 + 0x00F + 8 read-write - 0x070D - 0xFFFF + 0x00 + 0xFF - SCKDEN - RSPCK Delay Setting Enable - 15 - 15 + INS6 + This bit is set to 1 when this module completes compression process normally. + 6 + 6 read-write - - - 0 - An RSPCK delay of 1 RSPCK - #0 - - - 1 - An RSPCK delay is equal to the setting of the SPI clock delay register (SPCKD) - #1 - - + zeroToClear + modify - SLNDEN - SSL Negation Delay Setting Enable - 14 - 14 + INS5 + This bit is set to 1 when a compressed data error occurs. + 5 + 5 read-write - - - 0 - An SSL negation delay of 1 RSPCK - #0 - - - 1 - An SSL negation delay is equal to the setting of the SPI slave select negation delay register (SSLND) - #1 - - + zeroToClear + modify + + + INS3 + This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. + 3 + 3 + read-write + zeroToClear + modify + + + + JCDERR + JPEG Code Decode Error Register + 0x010 + 8 + read-write + 0x0A + 0xFF + - SPNDEN - SPI Next-Access Delay Enable - 13 - 13 + ERR + Error Code (See tables )Identify the type of the error which has occurred in the compressed data analysis for decompression. + 0 + 3 read-write - 0 - A next-access delay of 1 RSPCK + 2 PCLK - #0 + 0000 + Normal(Decompression error codes)/Normal(Segment error codes) + #0000 - 1 - A next-access delay is equal to the setting of the SPI next-access delay register (SPND) - #1 + 0001 + SOI not detected(Decompression error codes) + #0001 - - - - LSBF - SPI LSB First - 12 - 12 - read-write - - 0 - MSB first - #0 + 0010 + SOF1 to SOFF detected(Decompression error codes) + #0010 - 1 - LSB first - #1 + 0011 + Unprovided pixel format detected(Decompression error codes) + #0011 - - - - SPB - SPI Data Length Setting - 8 - 11 - read-write - 0100 - 8 bits + SOF accuracy error(Decompression error codes) #0100 0101 - 8 bits + DQT accuracy error(Decompression error codes) #0101 0110 - 8 bits + Component error 1(Decompression error codes) #0110 0111 - 8 bits + Component error 2(Decompression error codes) #0111 1000 - 9 bits + SOF0, DQT, and DHT not detected when SOS detected(Decompression error codes) #1000 1001 - 10 bits + SOS not detected(Decompression error codes) #1001 1010 - 11 bits + EOI not detected (default)(Decompression error codes) #1010 1011 - 12 bits + Restart interval data number error detected(Decompression error codes)/Restart interval data number error(Segment error codes) #1011 1100 - 13 bits + Image size error detected(Decompression error codes)/Image size error(Segment error codes) #1100 1101 - 14 bits + Last MCU data number error detected(Decompression error codes)/Last MCU data number error(Segment error codes) #1101 1110 - 15 bits + Block data number error detected(Decompression error codes)/Block data number error(Segment error codes) #1110 - - 1111 - 16 bits - #1111 - others Setting prohibited @@ -61352,1329 +50049,1277 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang + + + + JCRST + JPEG Code Reset Register + 0x011 + 8 + read-only + 0x00 + 0xFF + - SSLKP - SSL Signal Level Keeping - 7 - 7 - read-write + RST + Operating State + 0 + 0 + read-only 0 - Negates all SSL signals upon completion of transfer + State other than below #0 1 - Keeps the SSL signal level from the end of transfer until the beginning of the next access + Suspended state caused by interrupt sources of JINTE0 #1 + + + + JIFECNT + JPEG Interface Compression Control Register + 0x040 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - SSLA - SSL Signal Assertion Setting - 4 - 6 + JOUTSWAP + Byte/Halfword/Word Swap Output coded data in compression is swapped. + 8 + 10 read-write 000 - SSL0 + (1) (2) (3) (4) (5) (6) (7) (8) #000 001 - SSL1 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] #001 010 - SSL2 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] #010 011 - SSL3 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] #011 - others - Setting prohibited - true - - - - - BRDV - Bit Rate Division Setting - 2 - 3 - read-write - - - 00 - These bits select the base bit rate - #00 + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 - 01 - These bits select the base bit rate divided by 2 - #01 + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 - 10 - These bits select the base bit rate divided by 4 - #10 + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 - 11 - These bits select the base bit rate divided by 8 - #11 + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Word - byte swap] + #111 - CPOL - RSPCK Polarity Setting - 1 - 1 + DINRINI + Address Initialization when Resuming Input of Image Data Lines This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. + 6 + 6 read-write 0 - RSPCK is low when idle + The transfer address is not initialized when the input of image data lines is restarted #0 1 - RSPCK is high when idle + The transfer address is initialized when the input of image data lines is restarted #1 - CPHA - RSPCK Phase Setting - 0 - 0 + DINRCMD + Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. + 5 + 5 + write-only + + + DINLC + Count Mode Setting for Stopping Input Image Data Lines + 4 + 4 read-write 0 - Data sampling on odd edge, data variation on even edge + Count mode for stopping the input of image data lines is off #0 1 - Data variation on odd edge, data sampling on even edge + Count mode for stopping the input of image data lines is on #1 - - - - SPDCR2 - SPI Data Control Register 2 - 0x20 - 8 - read-write - 0x00 - 0xFF - - BYSW - Byte Swap Operating Mode Select + DINSWAP + Byte/Halfword Swap 0 - 0 + 2 read-write - 0 - Byte Swap Operating Mode disabled - #0 + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 - 1 - Byte Swap Operating Mode enabled - #1 + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 - - - - - - - - R_SPI1 - 0x40072100 - - - R_SRAM - SRAM - 0x40002000 - - 0x00000000 - 0x01 - registers - - - 0x00000004 - 0x01 - registers - - - 0x00000008 - 0x01 - registers - - - 0x000000C0 - 0x005 - registers - - - 0x000000D0 - 0x01 - registers - - - 0x000000D4 - 0x01 - registers - - - 0x000000D8 - 0x01 - registers - - - - PARIOAD - SRAM Parity Error Operation After Detection Register - 0x00 - 8 - read-write - 0x00 - 0xFF - - - OAD - Operation after Detection - 0 - 0 - read-write - - 1 - Reset - #1 + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 - 0 - Non maskable interrupt. - #0 + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 - - - - - - SRAMPRCR - SRAM Protection Register - 0x04 - 8 - read-write - 0x00 - 0xFF - - - KW - Write Key Code - 1 - 7 - write-only - - 1111000 - Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b. - #1111000 + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 - others - Writing to the RAMPRCR bit is invalid. - true + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 - - - - SRAMPRCR - Register Write Control - 0 - 0 - read-write - - 0 - Disable writes to protected registers - #0 + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 - 1 - Enable writes to protected registers. - #1 + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 - SRAMWTSC - RAM Wait State Control Register - 0x08 - 8 + JIFESA + JPEG Interface Compression Source Address Register + 0x044 + 32 read-write - 0x0E - 0xFF + 0x00000000 + 0xFFFFFFFF - SRAMHSWTEN - SRAMHS Wait Enable - 4 - 4 - read-write - - - 0 - Not add wait state in read access cycle to SRAMHS - #0 - - - 1 - Add wait state in read access cycle to SRAMHS - #1 - - - - - SRAM1WTEN - SRAM1 Wait Enable - 3 - 3 + ESA + Input Image Data Source Address (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 read-write - - - 0 - Not add wait state in read access cycle to SRAM1 - #0 - - - 1 - Add wait state in read access cycle to SRAM1 - #1 - - + + + + JIFESOFST + JPEG Interface Compression Line Offset Register + 0x048 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - SRAM0WTEN - SRAM0 Wait Enable - 2 - 2 + ESMW + Input Image Data Lines Offset(in 8-byte units)The lower three bits should be set to 0. + 0 + 14 read-write - - - 0 - Not add wait state in read access cycle to SRAM0 - #0 - - - 1 - Add wait state in read access cycle to SRAM0 - #1 - - + + + + JIFEDA + JPEG Interface Compression Destination Address Register + 0x04C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - ECCRAMRDWTEN - ECCRAM Read wait enable - 1 - 1 + EDA + Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. + 0 + 31 read-write - - - 0 - Not add wait state in read access cycle to SRAM0 (ECC area) - #0 - - - 1 - Add wait state in read access cycle to SRAM0 (ECC area) - #1 - - + + + + JIFESLC + JPEG Interface Compression Source Line Count Register + 0x050 + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + - ECCRAMWRWTEN - ECCRAM Write Wait Enable - 0 - 0 - read-write - - - 0 - Not add wait state in write access cycle to SRAM0 (ECC area) - #0 - - - 1 - Add wait state in write access cycle to SRAM0 (ECC area) - #1 - - + LINES + Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. + 0 + 15 + read-write - ECCMODE - ECC Operating Mode Control Register - 0xC0 - 8 + JIFDCNT + JPEG Interface Decompression Control Register + 0x058 + 32 read-write - 0x00 - 0xFF + 0x01000000 + 0xFFFFFFFF - ECCMOD - ECC Operating Mode Select - 0 - 1 + VINTER + Vertical SubsamplingSubsamples vertical output image data. + 28 + 29 read-write 00 - Disable ECC function + No subsampling #00 01 - Setting prohibited + Subsamples output data into 1/2. #01 10 - Enable ECC function without error checking + Subsamples output data into 1/4. #10 11 - Enable ECC function with error checking + Subsamples output data into 1/8. #11 - - - - ECC2STS - ECC 2-Bit Error Status Register - 0xC1 - 8 - read-write - 0x00 - 0xFF - - ECC2ERR - ECC 2-Bit Error Status - 0 - 0 + HINTER + Horizontal Subsampling Subsamples horizontal output image data. + 26 + 27 read-write - zeroToClear - modify - 0 - No 2-bit ECC error occurred - #0 + 00 + No subsampling + #00 - 1 - 2-bit ECC error occurred. - #1 + 01 + Subsamples output data into 1/2. + #01 + + + 10 + Subsamples output data into 1/4. + #10 + + + 11 + Subsamples output data into 1/8. + #11 - - - - ECC1STSEN - ECC 1-Bit Error Information Update Enable Register - 0xC2 - 8 - read-write - 0x00 - 0xFF - - E1STSEN - ECC 1-Bit Error Information Update Enable - 0 - 0 + OPF + Specifies output image data pixel format. + 24 + 25 read-write - 0 - Disables updating of the 1-bit ECC error information. - #0 + 01 + ARGB8888 + #01 - 1 - Enables updating of the 1-bit ECC error information. - #1 + 10 + RGB565 + #10 + + + others + Setting prohibited + true - - - - ECC1STS - ECC 1-Bit Error Status Register - 0xC3 - 8 - read-write - 0x00 - 0xFF - - ECC1ERR - ECC 1-Bit Error Status - 0 - 0 + JINRINI + Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. + 14 + 14 read-write - zeroToClear - modify 0 - No 1-bit ECC error occurred + The transfer address is not initialized when the input of coded data is restarted. #0 1 - 1-bit ECC error occurred + The transfer address is initialized when the input of coded data is restarted. #1 - - - - ECCPRCR - ECC Protection Register - 0xC4 - 8 - read-write - 0x00 - 0xFF - - KW - Write Key Code - 1 - 7 + JINRCMD + Input Coded Data Resume CommandThis bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0. + 13 + 13 write-only - - - 1111000 - Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b. - #1111000 - - - others - Writing to the ECCRAMPRCR bit is invalid. - true - - - ECCPRCR - Register Write Control - 0 - 0 + JINC + Count Mode Setting for Stopping Input Coded Data + 12 + 12 read-write 0 - Disable writes to the protected registers + Count mode for stopping the input of coded data is off. #0 1 - Enable writes to the protected registers + Count mode for stopping the input of coded data is on #1 - - - - ECCPRCR2 - ECC Protection Register 2 - 0xD0 - 8 - read-write - 0x00 - 0xFF - - KW2 - Write Key Code - 1 - 7 - write-only + JINSWAP + Byte/Word/Longword Swap Input coded data in decompression is swapped. + 8 + 10 + read-write - 1111000 - These bits enable or disable writes to the ECCPRCR2 bit.. - #1111000 + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 - others - Writing to the ECCRAMPRCR2 bit is invalid. - true + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word -Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 - ECCPRCR2 - Register Write Control - 0 - 0 + DOUTRINI + Address Initialization when Resuming Output of Image Data Lines This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the data-line resume command bit. + 6 + 6 read-write 0 - Disable writes to the protected registers + The transfer address is not initialized when the output of lines of image data is restarted. #0 1 - Enable writes to the protected registers. + The transfer address is initialized when the output of lines of image data is restarted #1 - - - - ECCETST - ECC Test Control Register - 0xD4 - 8 - read-write - 0x00 - 0xFF - - TSTBYP - ECC Bypass Select - 0 - 0 + DOUTRCMD + Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. + 5 + 5 + write-only + + + DOUTLC + Count Mode for Stopping Output Image Data Lines + 4 + 4 read-write 0 - ECC bypass disabled. + Count mode for stopping the output of image data lines is off. #0 1 - ECC bypass enabled. + Count mode for stopping the output of image data lines is on #1 - - - - ECCOAD - SRAM ECC Error Operation After Detection Register - 0xD8 - 8 - read-write - 0x00 - 0xFF - - OAD - Operation after Detection + DOUTSWAP + Byte/Word Swap Output image data in decompression is swapped. 0 - 0 + 2 read-write - 0 - Non-maskable interrupt - #0 + 000 + (1) (2) (3) (4) (5) (6) (7) (8) + #000 - 1 - Reset - #1 + 001 + (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] + #001 + + + 010 + (3) (4) (1) (2) (7) (8) (5) (6) [Halfword swap] + #010 + + + 011 + (4) (3) (2) (1) (8) (7) (6) (5) [Halfword - byte swap] + #011 + + + 100 + (5) (6) (7) (8) (1) (2) (3) (4) [Word swap] + #100 + + + 101 + (6) (5) (8) (7) (2) (1) (4) (3) [Word - byte swap] + #101 + + + 110 + (7) (8) (5) (6) (3) (4) (1) (2) [Word - Halfword swap] + #110 + + + 111 + (8) (7) (6) (5) (4) (3) (2) (1) [Word - Halfword - byte swap] + #111 - - - - R_SRC - Sampling Rate Converter - 0x40048000 - - 0x00000000 - 0x56C0 - registers - - - 0x00005FF0 - 0x010 - registers - - - 5552 - 0x4 - SRCFCTR[%s] - Filter Coefficient Table [%s] - 0x00 + JIFDSA + JPEG Interface Decompression Source Address Register + 0x05C 32 read-write 0x00000000 - 0xFFC00000 + 0xFFFFFFFF - SRCFCOE - Stores a filter coefficient value. + DSA + Input Coded Data Source AddressInput Coded Data Source Address (in 8-byte units) The lower three bits should be set to 0. 0 - 21 + 31 read-write - SRCID - Input Data Register - 0x5FF0 + JIFDDOFST + JPEG Interface Decompression Line Offset Register + 0x060 32 - write-only + read-write 0x00000000 0xFFFFFFFF - SRCID - SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0. + DDMW + Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. 0 - 31 - write-only + 14 + read-write - SRCOD - Output Data Register - 0x5FF4 + JIFDDA + JPEG Interface Decompression Destination Address Register + 0x064 32 - read-only + read-write 0x00000000 0xFFFFFFFF - SRCOD - SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again. + DDA + Output Image Data Destination Address (in 8-byte units) The lower three bits should be set to 0. 0 31 - read-only + read-write - SRCIDCTRL - Input Data Control Register - 0x5FF8 - 16 + JIFDSDC + JPEG Interface Decompression Source Data Count Register + 0x068 + 32 read-write - 0x0000 - 0xFFFF + 0xFFF8FFF8 + 0xFFFFFFFF - IED - Input Data Endian - 9 - 9 + JDATAS + Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. + 0 + 15 read-write - - - 0 - Endian formats 1 are the same between the CPU and input data. - #0 - - - 1 - Endian formats 1 are different between the CPU and input data. - #1 - - + + + + JIFDDLC + JPEG Interface Decompression Destination Line Count Register + 0x06C + 32 + read-write + 0xFFF8FFF8 + 0xFFFFFFFF + - IEN - Input FIFO Empty Interrupt Enable - 8 - 8 + LINES + Number of Input Image Lines to Be ReadThe lower three bits should be set to 0. These bits are read as0.Number of input image data lines to be read, in 8-line units. + 0 + 15 read-write - - - 0 - Input FIFO empty interrupt is disabled. - #0 - - - 1 - Input FIFO empty interrupt is enabled. - #1 - - + + + + JIFDADT + JPEG Interface Decompression alpha Set Register + 0x070 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - IFTRG - Input FIFO Data Triggering Number + ALPHA + Setting of the alpha value for output in ARGB8888 format. 0 - 1 + 7 read-write - - - 00 - 0 - #00 - - - 01 - 2 - #01 - - - 10 - 4 - #10 - - - 11 - 6 - #11 - - - - SRCCTRL - Control Register - 0x5FFC - 16 + + JINTE1 + JPEG Interrupt Enable Register 1 + 0x08C + 32 read-write - 0x0000 - 0xFFFF + 0x00000000 + 0xFFFFFFFF - FICRAE - Filter Coefficient Table Access Enable - 15 - 15 + CBTEN + Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. + 6 + 6 read-write 0 - Reading/writing to filter coefficient table RAM is disabled. + Disables an interrupt request. #0 1 - Reading/writing to filter coefficient table RAM is enabled. + Enables an interrupt request. #1 - CEEN - Conversion End Interrupt Enable - 13 - 13 + DINLEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1. + 5 + 5 read-write 0 - Disables conversion end interrupt requests. + Disables an interrupt request. #0 1 - Enables conversion end interrupt requests. + Enables an interrupt request. #1 - SRCEN - Module Enable - 12 - 12 + DBTEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1. + 2 + 2 read-write 0 - Disables this module operation. + Disables an interrupt request. #0 1 - Enables this module operation. + Enables an interrupt request. #1 - UDEN - Output Data FIFO Underflow Interrupt Enable - 11 - 11 + JINEN + Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1. + 1 + 1 read-write 0 - Disables output data FIFO underflow interrupt requests. + Disables an interrupt request. #0 1 - Enables output data FIFO underflow interrupt requests. + Enables an interrupt request. #1 - OVEN - Output Data FIFO Overwrite Interrupt Enable - 10 - 10 + DOUTLEN + Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1 + 0 + 0 read-write 0 - Output data FIFO overwrite interrupt is disabled. + Disables an interrupt request. #0 1 - Output data FIFO overwrite interrupt is enabled. + Enables an interrupt request. #1 + + + + JINTS1 + JPEG Interrupt Status Register 1 + 0x090 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CBTF + This bit is set to 1 when the last output coded data is written in compression. + 6 + 6 + read-write + modify + - FL - Internal Work Memory Flush - 9 - 9 + DINLF + This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression. This bit is valid only when the DINLC bit in JIFECNT is set to 1. + 5 + 5 + read-write + modify + + + DBTF + This bit is set to 1 when the last output image data is written in decompression. + 2 + 2 + read-write + modify + + + JINF + This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression. This bit is valid only when the JINC bit in JIFDCNT is set to 1. + 1 + 1 + read-write + modify + + + DOUTLF + In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. + 0 + 0 + read-write + modify + + + + + 64 + 0x1 + JCQTBL0[%s] + Quantization Table 0 + 0x0100 + 8 + write-only + 0x00 + 0x00 + + + JCQTBL1[%s] + Quantization Table 1 + 0x0140 + + + JCQTBL2[%s] + Quantization Table 2 + 0x0180 + + + JCQTBL3[%s] + Quantization Table 3 + 0x01C0 + + + 28 + 0x1 + JCHTBD0[%s] + DC Huffman Table 0 + 0x0200 + 8 + read-write + 0x00 + 0x00 + + + JCHTBD1[%s] + DC Huffman Table 1 + 0x0300 + + + 178 + 0x1 + JCHTBA0[%s] + AC Huffman Table 0 + 0x0220 + 8 + read-write + 0x00 + 0x00 + + + JCHTBA1[%s] + DC Huffman Table 1 + 0x0320 + + + + + R_KINT + Key Interrupt Function + 0x40080000 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + + KRCTL + KEY Return Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + KRMD + Usage of Key Interrupt Flags(KR0 to KR7) + 7 + 7 read-write 0 - no effect + Do not use key interrupt flags #0 1 - starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing). + Use key interrupt flags. #1 - CL - Internal Work Memory Clear - 8 - 8 + KREG + Detection Edge Selection (KRF0 to KRF7) + 0 + 0 read-write 0 - no effect + Falling edge #0 1 - Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator. + Rising edge #1 + + + + KRF + KEY Return Flag Register + 0x04 + 8 + read-write + 0x00 + 0xFF + zeroToClear + modify + - IFS - Input Sampling Rate - 4 + KRF7 + Key interrupt flag 7 + 7 7 read-write + zeroToClear + modify - 0000 - 8.0 kHz - #0000 - - - 0001 - 11.025 kHz - #0001 - - - 0010 - 12.0 kHz - #0010 - - - 0011 - Setting prohibited - #0011 - - - 0100 - 16.0 kHz - #0100 - - - 0101 - 22.05 kHz - #0101 - - - 0110 - 24.0 kHz - #0110 - - - 0111 - Setting prohibited - #0111 - - - 1000 - 32.0 kHz - #1000 - - - 1001 - 44.1 kHz - #1001 - - - 1010 - 48.0 kHz - #1010 + 0 + No interrupt detected + #0 - others - Settings prohibited. - true + 1 + Interrupt detected. + #1 - OFS - Output Sampling Rate - 0 - 2 + KRF6 + Key interrupt flag 6 + 6 + 6 read-write + zeroToClear + modify - 000 - 44.1 kHz - #000 - - - 001 - 48.0 kHz - #001 - - - 010 - 32.0 kHz - #010 - - - 011 - Setting prohibited - #011 + 0 + No interrupt detected + #0 - 100 - 8.0 kHz ( Valid only when IFS[3:0] =1001b ) - #100 + 1 + Interrupt detected. + #1 + + + + KRF5 + Key interrupt flag 5 + 5 + 5 + read-write + zeroToClear + modify + - 101 - 16.0 kHz ( Valid only when IFS[3:0] =1001b ) - #101 + 0 + No interrupt detected + #0 - others - Settings other than above are prohibited. - true + 1 + Interrupt detected. + #1 - - - - SRCODCTRL - Output Data Control Register - 0x5FFA - 16 - read-write - 0x0000 - 0xFFFF - - OCH - Output Data Channel Exchange - 10 - 10 + KRF4 + Key interrupt flag 4 + 4 + 4 read-write + zeroToClear + modify 0 - Does not exchange the channels (the same order as data input) + No interrupt detected #0 1 - Exchanges the channels (the opposite order from data input) + Interrupt detected. #1 - OED - Output Data Endian - 9 - 9 + KRF3 + Key interrupt flag 3 + 3 + 3 read-write + zeroToClear + modify 0 - Endian formats are the same between the chip and input data. + No interrupt detected #0 1 - Endian formats are different between the chip and input data. + Interrupt detected. #1 - OEN - Output Data FIFO Full Interrupt Enable - 8 - 8 + KRF2 + Key interrupt flag 2 + 2 + 2 read-write + zeroToClear + modify 0 - Output data FIFO full interrupt is disabled. + No interrupt detected #0 1 - Output data FIFO full interrupt is enabled. + Interrupt detected. #1 - OFTRG - Output FIFO Data Trigger Number - 0 + KRF1 + Key interrupt flag 1 + 1 1 read-write + zeroToClear + modify - 00 - 1 - #00 + 0 + No interrupt detected + #0 - 01 - 4 - #01 + 1 + Interrupt detected. + #1 + + + + KRF0 + Key interrupt flag 0 + 0 + 0 + read-write + zeroToClear + modify + - 10 - 8 - #10 + 0 + No interrupt detected + #0 - 11 - 12 - #11 + 1 + Interrupt detected. + #1 - SRCSTAT - Status Register - 0x5FFE - 16 + KRM + KEY Return Mode Register + 0x08 + 8 read-write - 0x0002 - 0xFFFF + 0x00 + 0xFF - OFDN - Output FIFO Data CountIndicates the number of data units in the output FIFO. - 11 - 15 + KRM7 + Key interrupt mode control 7 + 7 + 7 read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + - IFDN - Input FIFO Data CountIndicates the number of data units in the input FIFO. - 7 - 10 + KRM6 + Key interrupt mode control 6 + 6 + 6 read-write + + + 0 + Does not detect key interrupt signal + #0 + + + 1 + Detect key interrupt signal. + #1 + + - CEF - Conversion End Flag + KRM5 + Key interrupt mode control 5 5 5 read-write - zeroToClear - modify 0 - All of the output data has not been read out. + Does not detect key interrupt signal #0 1 - All of the output data has been read out. + Detect key interrupt signal. #1 - FLF - Flush Processing Status Flag + KRM4 + Key interrupt mode control 4 4 4 - read-only + read-write 0 - Flash processing is completed. + Does not detect key interrupt signal #0 1 - Flash processing is in progress. + Detect key interrupt signal. #1 - UDF - Output FIFO Underflow Interrupt Request Flag + KRM3 + Key interrupt mode control 3 3 3 read-write - zeroToClear - modify 0 - Output data FIFO has not been read out. + Does not detect key interrupt signal #0 1 - Output data FIFO has been read out. + Detect key interrupt signal. #1 - OVF - Output Data FIFO Overwrite Interrupt Request Flag + KRM2 + Key interrupt mode control 2 2 2 read-write - zeroToClear - modify 0 - Next data conversion processing is not completed. + Does not detect key interrupt signal #0 1 - Next data conversion processing is completed. + Detect key interrupt signal. #1 - IINT - Input Data FIFO Empty Interrupt Request Flag + KRM1 + Key interrupt mode control 1 1 1 read-write - zeroToClear - modify 0 - Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number. + Does not detect key interrupt signal #0 1 - Number of data units in the input FIFO has become equal to or smaller than the specified triggering number. + Detect key interrupt signal. #1 - OINT - Output Data FIFO Full Interrupt Request Flag + KRM0 + Key interrupt mode control 0 0 0 read-write - zeroToClear - modify 0 - Number of data units in the output FIFO has not become equal to or greater than the specified triggering number. + Does not detect key interrupt signal #0 1 - Number of data units in the output FIFO has become equal to or greater than the specified triggering number. + Detect key interrupt signal. #1 @@ -62684,1151 +51329,20253 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - R_SSI0 - Serial Sound Interface Enhanced (SSIE) - 0x4004E000 - - 0x00 - 8 - registers - - - 0x10 - 24 - registers - - - - SSICR - Control Register - 0x00 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - CKS - Oversampling Clock Select - 30 - 30 - read-write - - - 0 - AUDIO_CLK input - #0 - - - 1 - Setting prohibited - #1 - - - - - TUIEN - Transmit Underflow Interrupt Enable - 29 - 29 - read-write - - - 0 - Disables an underflow interrupt. - #0 - - - 1 - Enables an underflow interrupt. - #1 - - - - - TOIEN - Transmit Overflow Interrupt Enable - 28 - 28 - read-write - - - 0 - Disables an overflow interrupt. - #0 - - - 1 - Enables an overflow interrupt. - #1 - - - - - RUIEN - Receive Underflow Interrupt Enable - 27 - 27 - read-write - - - 0 - Disables an underflow interrupt. - #0 - - - 1 - Enables an underflow interrupt. - #1 - - - - - ROIEN - Receive Overflow Interrupt Enable - 26 - 26 - read-write - - - 0 - Disables an overflow interrupt. - #0 - - - 1 - Enables an overflow interrupt. - #1 - - - - - IIEN - Idle Mode Interrupt Enable - 25 - 25 - read-write - - - 0 - Disables an idle mode interrupt. - #0 - - - 1 - Enables an idle mode interrupt. - #1 - - - - - FRM - Channels - 22 - 23 - read-write - - - 00 - One channel - #00 - - - others - Settings other than above are prohibited. - true - - - - - DWL - Data Word Length - 19 - 21 - read-write - - - 000 - 8 bits - #000 - - - 001 - 16 bits - #001 - - - 010 - 18 bits - #010 - - - 011 - 20 bits - #011 - - - 100 - 22 bits - #100 - - - 101 - 24 bits - #101 - - - others - Settings other than above are prohibited. - true - - - - - SWL - System Word LengthSet the system word length to the bit clock frequency/2 fs. - 16 - 18 - read-write - - - 000 - 8 bits (serial bit clock frequency = 16fs ) - #000 - - - 001 - 16 bits (serial bit clock frequency = 32fs ) - #001 - - - 010 - 24 bits (serial bit clock frequency = 48fs ) - #010 - - - 011 - 32 bits (serial bit clock frequency = 64fs ) - #011 - - - others - Settings other than above are prohibited. - true - - - - - MST - Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited. - 14 - 14 - read-write - - - 0 - Serial word select is input, slave mode. - #0 - - - 1 - Serial word select is output, master mode. - #1 - - - - - BCKP - Serial Bit Clock Polarity - 13 - 13 - read-write - - - 0 - SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge). - #0 - - - 1 - SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge). - #1 - - - - - LRCKP - Serial WS Polarity - 12 - 12 - read-write - - - 0 - SSIWS is low for 1st channel, high for 2nd channel. - #0 - - - 1 - SSIWS is high for 1st channel, low for 2nd channel. - #1 - - - - - SPDP - Serial Padding Polarity - 11 - 11 - read-write - - - 0 - Padding bits are low. - #0 - - - 1 - Padding bits are high. - #1 - - - - - SDTA - Serial Data Alignment - 10 - 10 - read-write - - - 0 - Transmitting and receiving in the order of serial data and padding bits - #0 - - - 1 - Transmitting and receiving in the order of padding bits and serial data - #1 - - - - - PDTA - Parallel Data Alignment - 9 - 9 - read-write - - - 0 - The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits) - #0 - - - 1 - The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits) - #1 - - - - - DEL - Serial Data Delay - 8 - 8 - read-write - - - 0 - 1 clock cycle delay between SSIWS and SSIDATA - #0 - - - 1 - No delay between SSIWS and SSIDATA - #1 - - - - - CKDV - Serial Oversampling Clock Division Ratio - 4 - 7 - read-write - - - 0x0 - CLK - 0x0 - - - 0x1 - CLK/2 - 0x1 - - - 0x2 - CLK/4 - 0x2 - - - 0x3 - CLK/8 - 0x3 - - - 0x4 - CLK/16 - 0x4 - - - 0x5 - CLK/32 - 0x5 - - - 0x6 - CLK/64 - 0x6 - - - 0x7 - CLK/128 - 0x7 - - - 0x8 - CLK/6 - 0x8 - - - 0x9 - CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) - 0x9 - - - 0xA - CLK/24 - 0xA - - - 0xB - CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) - 0xB - - - 0xC - CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) - 0xC - - - others - Settings other than above are prohibited. - true - - - - - MUEN - Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing. - 3 - 3 - read-write - - - 0 - This module is not muted. - #0 - - - 1 - This module is muted. - #1 - - - - - TEN - Transmit Enable - 1 - 1 - read-write - - - 0 - Disables the transmit operation. - #0 - - - 1 - Enables the transmit operation. - #1 - - - - - REN - Receive Enable - 0 - 0 - read-write - - - 0 - Disables the receive operation. - #0 - - - 1 - Enables the receive operation. - #1 - - - - + R_MMF + Memory Mirror Function + 0x40001000 + + 0x00000000 + 0x008 + registers + + + + MMSFR + MemMirror Special Function Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + KEY + MMSFR Key Code + 24 + 31 + write-only + + + 0xDB + Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB. + 0xDB + + + others + Writing to the MEMMIRADDR bits are invalid. + true + + + + + MEMMIRADDR + Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0. + 7 + 22 + read-write + + + + + MMEN + MemMirror Enable Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + KEY + MMEN Key Code + 24 + 31 + write-only + + + 0xDB + Writing to the EN bit is valid, when the KEY bits are written 0xDB. + 0xDB + + + others + Writing to the EN bit is invalid. + true + + + + + EN + Memory Mirror Function Enable + 0 + 0 + read-write + + + 1 + Memory Mirror Function is enabled. + #1 + + + 0 + Memory Mirror Function is disabled. + #0 + + + + + + + + + R_MPU_MMPU + Bus Master MPU + 0x40000000 + + 0x00000000 + 0x02 + registers + + + 0x00000102 + 0x02 + registers + + + 0x00000200 + 0x02 + registers + + + 0x00000204 + 0x008 + registers + + + 0x00000210 + 0x02 + registers + + + 0x00000214 + 0x008 + registers + + + 0x00000220 + 0x02 + registers + + + 0x00000224 + 0x008 + registers + + + 0x00000230 + 0x02 + registers + + + 0x00000234 + 0x008 + registers + + + 0x00000240 + 0x02 + registers + + + 0x00000244 + 0x008 + registers + + + 0x00000250 + 0x02 + registers + + + 0x00000254 + 0x008 + registers + + + 0x00000260 + 0x02 + registers + + + 0x00000264 + 0x008 + registers + + + 0x00000270 + 0x02 + registers + + + 0x00000274 + 0x008 + registers + + + 0x00000280 + 0x02 + registers + + + 0x00000284 + 0x008 + registers + + + 0x00000290 + 0x02 + registers + + + 0x00000294 + 0x008 + registers + + + 0x000002A0 + 0x02 + registers + + + 0x000002A4 + 0x008 + registers + + + 0x000002B0 + 0x02 + registers + + + 0x000002B4 + 0x008 + registers + + + 0x000002C0 + 0x02 + registers + + + 0x000002C4 + 0x008 + registers + + + 0x000002D0 + 0x02 + registers + + + 0x000002D4 + 0x008 + registers + + + 0x000002E0 + 0x02 + registers + + + 0x000002E4 + 0x008 + registers + + + 0x000002F0 + 0x02 + registers + + + 0x000002F4 + 0x008 + registers + + + 0x00000300 + 0x02 + registers + + + 0x00000304 + 0x008 + registers + + + 0x00000310 + 0x02 + registers + + + 0x00000314 + 0x008 + registers + + + 0x00000320 + 0x02 + registers + + + 0x00000324 + 0x008 + registers + + + 0x00000330 + 0x02 + registers + + + 0x00000334 + 0x008 + registers + + + 0x00000340 + 0x02 + registers + + + 0x00000344 + 0x008 + registers + + + 0x00000350 + 0x02 + registers + + + 0x00000354 + 0x008 + registers + + + 0x00000360 + 0x02 + registers + + + 0x00000364 + 0x008 + registers + + + 0x00000370 + 0x02 + registers + + + 0x00000374 + 0x008 + registers + + + 0x00000380 + 0x02 + registers + + + 0x00000384 + 0x008 + registers + + + 0x00000390 + 0x02 + registers + + + 0x00000394 + 0x008 + registers + + + 0x000003A0 + 0x02 + registers + + + 0x000003A4 + 0x008 + registers + + + 0x000003B0 + 0x02 + registers + + + 0x000003B4 + 0x008 + registers + + + 0x000003C0 + 0x02 + registers + + + 0x000003C4 + 0x008 + registers + + + 0x000003D0 + 0x02 + registers + + + 0x000003D4 + 0x008 + registers + + + 0x000003E0 + 0x02 + registers + + + 0x000003E4 + 0x008 + registers + + + 0x000003F0 + 0x02 + registers + + + 0x000003F4 + 0x008 + registers + + + 0x00000400 + 0x02 + registers + + + 0x00000502 + 0x02 + registers + + + 0x00000600 + 0x02 + registers + + + 0x00000604 + 0x008 + registers + + + 0x00000610 + 0x02 + registers + + + 0x00000614 + 0x008 + registers + + + 0x00000620 + 0x02 + registers + + + 0x00000624 + 0x008 + registers + + + 0x00000630 + 0x02 + registers + + + 0x00000634 + 0x008 + registers + + + 0x00000640 + 0x02 + registers + + + 0x00000644 + 0x008 + registers + + + 0x00000650 + 0x02 + registers + + + 0x00000654 + 0x008 + registers + + + 0x00000660 + 0x02 + registers + + + 0x00000664 + 0x008 + registers + + + 0x00000670 + 0x02 + registers + + + 0x00000674 + 0x008 + registers + + + 0x00000680 + 0x02 + registers + + + 0x00000684 + 0x008 + registers + + + 0x00000690 + 0x02 + registers + + + 0x00000694 + 0x008 + registers + + + 0x000006A0 + 0x02 + registers + + + 0x000006A4 + 0x008 + registers + + + 0x000006B0 + 0x02 + registers + + + 0x000006B4 + 0x008 + registers + + + 0x000006C0 + 0x02 + registers + + + 0x000006C4 + 0x008 + registers + + + 0x000006D0 + 0x02 + registers + + + 0x000006D4 + 0x008 + registers + + + 0x000006E0 + 0x02 + registers + + + 0x000006E4 + 0x008 + registers + + + 0x000006F0 + 0x02 + registers + + + 0x000006F4 + 0x008 + registers + + + 0x00000700 + 0x02 + registers + + + 0x00000704 + 0x008 + registers + + + 0x00000710 + 0x02 + registers + + + 0x00000714 + 0x008 + registers + + + 0x00000720 + 0x02 + registers + + + 0x00000724 + 0x008 + registers + + + 0x00000730 + 0x02 + registers + + + 0x00000734 + 0x008 + registers + + + 0x00000740 + 0x02 + registers + + + 0x00000744 + 0x008 + registers + + + 0x00000750 + 0x02 + registers + + + 0x00000754 + 0x008 + registers + + + 0x00000760 + 0x02 + registers + + + 0x00000764 + 0x008 + registers + + + 0x00000770 + 0x02 + registers + + + 0x00000774 + 0x008 + registers + + + 0x00000780 + 0x02 + registers + + + 0x00000784 + 0x008 + registers + + + 0x00000790 + 0x02 + registers + + + 0x00000794 + 0x008 + registers + + + 0x000007A0 + 0x02 + registers + + + 0x000007A4 + 0x008 + registers + + + 0x000007B0 + 0x02 + registers + + + 0x000007B4 + 0x008 + registers + + + 0x000007C0 + 0x02 + registers + + + 0x000007C4 + 0x008 + registers + + + 0x000007D0 + 0x02 + registers + + + 0x000007D4 + 0x008 + registers + + + 0x000007E0 + 0x02 + registers + + + 0x000007E4 + 0x008 + registers + + + 0x000007F0 + 0x02 + registers + + + 0x000007F4 + 0x008 + registers + + + 0x00000800 + 0x02 + registers + + + 0x00000902 + 0x02 + registers + + + 0x00000A00 + 0x02 + registers + + + 0x00000A04 + 0x008 + registers + + + 0x00000A10 + 0x02 + registers + + + 0x00000A14 + 0x008 + registers + + + 0x00000A20 + 0x02 + registers + + + 0x00000A24 + 0x008 + registers + + + 0x00000A30 + 0x02 + registers + + + 0x00000A34 + 0x008 + registers + + + 0x00000A40 + 0x02 + registers + + + 0x00000A44 + 0x008 + registers + + + 0x00000A50 + 0x02 + registers + + + 0x00000A54 + 0x008 + registers + + + 0x00000A60 + 0x02 + registers + + + 0x00000A64 + 0x008 + registers + + + 0x00000A70 + 0x02 + registers + + + 0x00000A74 + 0x008 + registers + + + 0x00000A80 + 0x02 + registers + + + 0x00000A84 + 0x008 + registers + + + 0x00000A90 + 0x02 + registers + + + 0x00000A94 + 0x008 + registers + + + 0x00000AA0 + 0x02 + registers + + + 0x00000AA4 + 0x008 + registers + + + 0x00000AB0 + 0x02 + registers + + + 0x00000AB4 + 0x008 + registers + + + 0x00000AC0 + 0x02 + registers + + + 0x00000AC4 + 0x008 + registers + + + 0x00000AD0 + 0x02 + registers + + + 0x00000AD4 + 0x008 + registers + + + 0x00000AE0 + 0x02 + registers + + + 0x00000AE4 + 0x008 + registers + + + 0x00000AF0 + 0x02 + registers + + + 0x00000AF4 + 0x008 + registers + + + 0x00000B00 + 0x02 + registers + + + 0x00000B04 + 0x008 + registers + + + 0x00000B10 + 0x02 + registers + + + 0x00000B14 + 0x008 + registers + + + 0x00000B20 + 0x02 + registers + + + 0x00000B24 + 0x008 + registers + + + 0x00000B30 + 0x02 + registers + + + 0x00000B34 + 0x008 + registers + + + 0x00000B40 + 0x02 + registers + + + 0x00000B44 + 0x008 + registers + + + 0x00000B50 + 0x02 + registers + + + 0x00000B54 + 0x008 + registers + + + 0x00000B60 + 0x02 + registers + + + 0x00000B64 + 0x008 + registers + + + 0x00000B70 + 0x02 + registers + + + 0x00000B74 + 0x008 + registers + + + 0x00000B80 + 0x02 + registers + + + 0x00000B84 + 0x008 + registers + + + 0x00000B90 + 0x02 + registers + + + 0x00000B94 + 0x008 + registers + + + 0x00000BA0 + 0x02 + registers + + + 0x00000BA4 + 0x008 + registers + + + 0x00000BB0 + 0x02 + registers + + + 0x00000BB4 + 0x008 + registers + + + 0x00000BC0 + 0x02 + registers + + + 0x00000BC4 + 0x008 + registers + + + 0x00000BD0 + 0x02 + registers + + + 0x00000BD4 + 0x008 + registers + + + 0x00000BE0 + 0x02 + registers + + + 0x00000BE4 + 0x008 + registers + + + 0x00000BF0 + 0x02 + registers + + + 0x00000BF4 + 0x008 + registers + + + + 3 + 0x400 + + + A + A + 0 + + + B + B + 1 + + + C + C + 2 + + + MMPU[%s] + Bus Master MPU Registers + 0x0000 + + CTL + Bus Master MPU Control Register + 0x000 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the OAD and ENABLE bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the OAD and ENABLE bit is invalid. + true + + + + + OAD + Operation after detection + 1 + 1 + read-write + + + 0 + Non-maskable interrupt. + #0 + + + 1 + Internal reset. + #1 + + + + + ENABLE + Master Group enable + 0 + 0 + read-write + + + 0 + Master Group is disabled. Permission of all regions. + #0 + + + 1 + Master Group is enabled. Protection of all regions. + #1 + + + + + + + PT + Protection of Register + 0x102 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the PROTECT bit is invalid. + true + + + + + PROTECT + Protection of region register + 0 + 0 + read-write + + + 0 + All Bus Master MPU register writing is possible. + #0 + + + 1 + All Bus Master MPU register writing is protected. Read is possible. + #1 + + + + + + + 32 + 0x10 + REGION[%s] + Address Region registers + 0x0200 + + C + Access Control Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + WP + Write protection + 2 + 2 + read-write + + + 0 + Write permission + #0 + + + 1 + Write protection + #1 + + + + + RP + Read protection + 1 + 1 + read-write + + + 0 + Read permission + #0 + + + 1 + Read protection + #1 + + + + + ENABLE + Region enable + 0 + 0 + read-write + + + 0 + Group m Region n unit is disabled + #0 + + + 1 + Group m Region n unit is enabled + #1 + + + + - SSISR - Status Register - 0x04 - 32 + S + Start Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + MMPUSmn + Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. + 0 + 31 + read-write + + + + + E + End Address Register + 0x08 + 32 + read-write + 0x00000003 + 0xFFFFFFFF + + + MMPUEmn + Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. + 0 + 31 + read-write + + + + + + + + + R_MPU_SMPU + Bus Slave MPU + 0x40000C00 + + 0x00000000 + 0x02 + registers + + + 0x00000010 + 0x02 + registers + + + 0x00000014 + 0x02 + registers + + + 0x00000018 + 0x02 + registers + + + 0x0000001C + 0x02 + registers + + + 0x00000020 + 0x02 + registers + + + 0x00000024 + 0x02 + registers + + + 0x00000028 + 0x02 + registers + + + 0x0000002C + 0x02 + registers + + + 0x00000030 + 0x02 + registers + + + 0x00000034 + 0x02 + registers + + + + 10 + 0x4 + + + MBIU + MBIU + 0 + + + FBIU + FBIU + 1 + + + R_SRAM + R_SRAM + 2 + + + SRAM1 + SRAM1 + 3 + + + P0BIU + P0BIU + 4 + + + P2BIU + P2BIU + 5 + + + P6BIU + P6BIU + 6 + + + B7BIU + B7BIU + 7 + + + EXBIU + EXBIU + 8 + + + EXBIU2 + EXBIU2 + 9 + + + SMPU[%s] + Access Control Structure for MBIU + 0x10 + + R + Access Control Register for MBIU + 0x00 + 16 + read-write + 0x2000 + 0xFFFF + + + WPSRAMHS + SRAMHS Write Protection + 15 + 15 + read-write + + + 0 + Memory protection for SRAMHS writes from master group A, B, and C disabled + #0 + + + 1 + Memory protection for SRAMHS writes from master group A, B, and C enabled. + #1 + + + + + RPSRAMHS + SRAMHS Read Protection + 14 + 14 + read-write + + + 0 + Memory protection for SRAMHS reads from master group A, B, and C disabled + #0 + + + 1 + Memory protection for SRAMHS reads from master group A, B, and C enabled. + #1 + + + + + WPFLI + Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.) + 13 + 13 + read-write + + + 0 + Setting prohibited + #0 + + + 1 + Memory protection for code flash memory writes from master group A, B, and C enabled. + #1 + + + + + RPFLI + Code Flash Memory Read Protection + 12 + 12 + read-write + + + 0 + Memory protection for code flash memory reads from master group A, B, and C disabled + #0 + + + 1 + Memory protection for code flash memory reads from master group A, B, and C enabled. + #1 + + + + + WPGRPC + Master Group C Write protection + 7 + 7 + read-write + + + 0 + Memory protection for master group C writes disabled + #0 + + + 1 + Memory protection for master group C writes enabled. + #1 + + + + + RPGRPC + Master Group C Read protection + 6 + 6 + read-write + + + 0 + Memory protection for master group C reads disabled + #0 + + + 1 + Memory protection for master group C reads enabled. + #1 + + + + + WPGRPB + Master Group B Write protection + 5 + 5 + read-write + + + 0 + Memory protection for master group B writes disabled + #0 + + + 1 + Memory protection for master group B writes enabled. + #1 + + + + + RPGRPB + Master Group B Read protection + 4 + 4 + read-write + + + 0 + Memory protection for master group B reads disabled + #0 + + + 1 + Memory protection for master group B reads enabled. + #1 + + + + + WPGRPA + Master Group A Write protection + 3 + 3 read-write - 0x02000013 - 0x3E00007F - - - TUIRQ - Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 29 - 29 - read-write - zeroToClear - modify - - - 0 - No transmit underflow has occurred. - #0 - - - 1 - A transmit underflow has occurred. - #1 - - - - - TOIRQ - Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 28 - 28 - read-write - zeroToClear - modify - - - 0 - No transmit overflow has occurred. - #0 - - - 1 - A transmit overflow has occurred. - #1 - - - - - RUIRQ - Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 27 - 27 - read-write - zeroToClear - modify - - - 0 - No receive underflow has occurred. - #0 - - - 1 - A receive underflow has occurred. - #1 - - - - - ROIRQ - Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 26 - 26 - read-write - zeroToClear - modify - - - 0 - No receive overflow has occurred. - #0 - - - 1 - A receive overflow has occurred. - #1 - - - - - IIRQ - Idle Mode Interrupt Status Flag - 25 - 25 - read-only - - - 0 - This module is not in idle state. - #0 - - - 1 - This module is in idle state. - #1 - - - - - TCHNO - Transmit Channel Number - 5 - 6 - read-only - - - TSWNO - Transmit Serial Word Number - 4 - 4 - read-only - - - RCHNO - Receive Channel Number.These bits are read as 00b. - 2 - 3 - read-only - - - RSWNO - Receive Serial Word Number - 1 - 1 - read-only - - - IDST - Idle Mode Status Flag - 0 - 0 - read-only - - - 0 - Serial bus is operating. - #0 - - - 1 - The current communication is stopped. - #1 - - - - - - - SSIFCR - FIFO Control Register - 0x10 - 32 + + + 0 + Memory protection for master group A writes disabled + #0 + + + 1 + Memory protection for master group A writes enabled. + #1 + + + + + RPGRPA + Master Group A Read protection + 2 + 2 read-write - 0x00000000 - 0xFFFFFFFF - - - AUCKE - Oversampling Clock Enable - 31 - 31 - read-write - - - 0 - The oversampling clock is disabled. - #0 - - - 1 - The oversampling clock is enabled. - #1 - - - - - SSIRST - SSI soft ware reset - 16 - 16 - read-write - - - 0 - Clears the SSI software reset. - #0 - - - 1 - initiates the SSI software reset. - #1 - - - - - TTRG - Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set. - 6 - 7 - read-write - - - 00 - 7 (1) - #00 - - - 01 - 6 (2) - #01 - - - 10 - 4 (4) - #10 - - - 11 - 2 (6) - #11 - - - - - RTRG - Receive Data Trigger Number - 4 - 5 - read-write - - - 00 - 1 - #00 - - - 01 - 2 - #01 - - - 10 - 4 - #10 - - - 11 - 6 - #11 - - - - - TIE - Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit. - 3 - 3 - read-write - - - 0 - Transmit data empty interrupt (TXI) request is disabled - #0 - - - 1 - Transmit data empty interrupt (TXI) request is enabled - #1 - - - - - RIE - Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit. - 2 - 2 - read-write - - - 0 - Receive data full interrupt (RXI) request is disabled - #0 - - - 1 - Receive data full interrupt (RXI) request is enabled - #1 - - - - - TFRST - Transmit FIFO Data Register Reset - 1 - 1 - read-write - - - 0 - Clears the transmit data FIFO reset. - #0 - - - 1 - Initiates the transmit data FIFO reset. - #1 - - - - - RFRST - Receive FIFO Data Register Reset - 0 - 0 - read-write - - - 0 - Clears the receive data FIFO reset. - #0 - - - 1 - Initiates the receive data FIFO reset. - #1 - - - - - - - SSIFSR - FIFO Status Register - 0x14 - 32 + + + 0 + Memory protection for master group A reads disabled + #0 + + + 1 + Memory protection for master group A reads enabled. + #1 + + + + + + + + SMPUCTL + Slave MPU Control Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. + 8 + 15 + write-only + + + 0xA5 + Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the PROTECT and OAD bit is invalid. + true + + + + + PROTECT + Protection of register + 1 + 1 + read-write + + + 0 + All Bus Slave register writing is possible. + #0 + + + 1 + All Bus Slave register writing is protected. Read is possible. + #1 + + + + + OAD + Master Group enable + 0 + 0 + read-write + + + 0 + Non-maskable interrupt. + #0 + + + 1 + Internal reset. + #1 + + + + + + + + + R_MPU_SPMON + CPU Stack Pointer Monitor + 0x40000D00 + + 0x00000000 + 0x02 + registers + + + 0x00000004 + 0x00E + registers + + + 0x00000014 + 0x00C + registers + + + + 2 + 0x10 + + + M + M + 0 + + + P + P + 1 + + + SP[%s] + Stack Pointer Monitor + 0x0000 + + OAD + Stack Pointer Monitor Operation After Detection Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the OAD bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the OAD bit is invalid. + true + + + + + OAD + Operation after detection + 0 + 0 + read-write + + + 0 + Non-maskable interrupt + #0 + + + 1 + Reset. + #1 + + + + + + + CTL + Stack Pointer Monitor Access Control Register + 0x04 + 16 + read-write + 0x0000 + 0xFEFF + + + ERROR + Stack Pointer Monitor Error Flag + 8 + 8 + read-write + + + 0 + Stack pointer has not overflowed or underflowed + #0 + + + 1 + Stack pointer has overflowed or underflowed + #1 + + + + + ENABLE + Stack Pointer Monitor Enable + 0 + 0 + read-write + + + 0 + Stack pointer monitor is disabled + #0 + + + 1 + Stack pointer monitor is enabled. + #1 + + + + + + + PT + Stack Pointer Monitor Protection Register + 0x06 + 16 + read-write + 0x0000 + 0xFFFF + + + KEY + Write Keyword The data written to these bits are not stored. + 8 + 15 + write-only + + + 0xA5 + Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. + 0xA5 + + + others + Writing to the PROTECT bit is invalid. + true + + + + + PROTECT + Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) + 0 + 0 + read-write + + + 0 + Stack Pointer Monitor register writing is possible. + #0 + + + 1 + Stack Pointer Monitor register writing is protected. + #1 + + + + + + + SA + Stack Pointer Monitor Start Address Register + 0x08 + 32 + read-write + 0x00000000 + 0x00000003 + + + MSPMPUSA + Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. + 0 + 31 + read-write + + + 0x1FF00000 + 0x200FFFFC + + + + + + + EA + Stack Pointer Monitor End Address Register + 0x0C + 32 + read-write + 0x00000003 + 0x00000003 + + + MSPMPUEA + Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. + 0 + 31 + read-write + + + 0x1FF00003 + 0x200FFFFF + + + + + + + + + + R_MSTP + System-Module Stop + 0x40047000 + + 0x00000000 + 0x00C + registers + + + + MSTPCRB + Module Stop Control Register B + 0x00 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MSTPB31 + Serial Communication Interface 0 Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB30 + Serial Communication Interface 1 Module Stop + 30 + 30 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB29 + Serial Communication Interface 2 Module Stop + 29 + 29 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB28 + Serial Communication Interface 3 Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB27 + Serial Communication Interface 4 Module Stop + 27 + 27 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB26 + Serial Communication Interface 5 Module Stop + 26 + 26 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB25 + Serial Communication Interface 6 Module Stop + 25 + 25 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB24 + Serial Communication Interface 7 Module Stop + 24 + 24 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB23 + Serial Communication Interface 8 Module Stop + 23 + 23 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB22 + Serial Communication Interface 9 Module Stop + 22 + 22 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + These bits are read as 11. The write value should be 11. + 20 + 21 + read-write + + + MSTPB19 + Serial Peripheral Interface 0 Module Stop + 19 + 19 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB18 + Serial Peripheral Interface Module Stop + 18 + 18 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + These bits are read as 11. The write value should be 11. + 16 + 17 + read-write + + + MSTPB15 + ETHERC0 and EDMAC0 Module Stop + 15 + 15 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB14 + ETHERC1 and EDMAC1 Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB13 + EPTPC and PTPEDMAC Module Stop + 13 + 13 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB12 + Universal Serial Bus 2.0 HS Interface Module Stop + 12 + 12 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB11 + Universal Serial Bus 2.0 FS Interface Module Stop + 11 + 11 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + This bit is read as 1. The write value should be 1. + 10 + 10 + read-write + + + MSTPB9 + I2C Bus Interface 0 Module Stop + 9 + 9 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB8 + I2C Bus Interface 1 Module Stop + 8 + 8 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB7 + I2C Bus Interface 2 Module Stop + 7 + 7 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB6 + Queued Serial Peripheral Interface Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB5 + IrDA Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + These bits are read as 11. The write value should be 11. + 3 + 4 + read-write + + + MSTPB2 + RCAN0 Module Stop + 2 + 2 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPB1 + RCAN1 Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + Reserved + This bit is read as 1. The write value should be 1. + 0 + 0 + read-write + + + + + MSTPCRC + Module Stop Control Register C + 0x04 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MSTPC31 + AES Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC28 + Random Number Generator Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state. + #1 + + + + + MSTPC14 + Event Link Controller Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC13 + Data Operation Circuit Module Stop + 13 + 13 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC12 + Secure Digital Host IF/ Multi Media Card 0 Module Stop + 12 + 12 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC11 + Secure Digital Host IF/ Multi Media Card 1 Module Stop + 11 + 11 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC9 + Sampling Rate Converter Module Stop + 9 + 9 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC8 + Synchronous Serial Interface 0 Module Stop + 8 + 8 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC7 + Synchronous Serial Interface 1 Module Stop + 7 + 7 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC6 + 2DG engine Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC5 + JPEG codec engine Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC4 + Segment LCD Controller Module Stop + 4 + 4 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC3 + Capacitive Touch Sensing Unit Module Stop + 3 + 3 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC2 + Parallel Data Capture Module Stop + 2 + 2 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC1 + CRC Calculator Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPC0 + CAC Module Stop + 0 + 0 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + MSTPCRD + Module Stop Control Register D + 0x08 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MSTPD31 + Operational Amplifier Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD29 + Comparator-LP Module Stop + 29 + 29 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD28 + ACMPHS0 Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD27 + ACMPHS1 Module Stop + 27 + 27 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD26 + ACMPHS2 Module Stop + 26 + 26 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD25 + ACMPHS3 Module Stop + 25 + 25 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD24 + ACMPHS4 Module Stop + 24 + 24 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD23 + ACMPHS5 Module Stop + 23 + 23 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD22 + Temperature Sensor Module Stop + 22 + 22 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD20 + 12-bit D/A Converter Module Stop + 20 + 20 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD19 + 8-Bit D/A Converter Module Stop + 19 + 19 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD17 + 24-bit Sigma-Delta A/DConverter Module Stop + 17 + 17 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD16 + 16-Bit A/D Converter Module Stop + 16 + 16 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD15 + 12-Bit A/D Converter 1 Module Stop + 15 + 15 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD14 + POEG Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD13 + Port Output Enable for GPT 1 Module Stop + 13 + 13 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD12 + Port Output Enable for GPT 2 Module Stop + 12 + 12 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD11 + Port Output Enable for GPT 3 Module Stop + 11 + 11 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD6 + GPT Higher Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD5 + GPT Lower Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD3 + AGT0 Module StopNote: AGT0 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT0. + 3 + 3 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD2 + AGT1 Module StopNote: AGT1 is in the module stop state when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In case the count source is sub-clock or LOCO, this bit should be set to 1 except when accessing the registers of AGT1. + 2 + 2 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD1 + Low Power Asynchronous General Purpose Timer 2 Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPD0 + Low Power Asynchronous General Purpose Timer 3 Module Stop + 0 + 0 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + MSTPCRE + Module Stop Control Register E + 0x0C + 32 + read-write + 0xffffffff + 0xffffffff + + + MSTPE14 + Low Power Asynchronous General Purpose Timer 5 Module Stop + 14 + 14 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE15 + Low Power Asynchronous General Purpose Timer 4 Module Stop + 15 + 15 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE22 + GPT9 Module Stop + 22 + 22 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE23 + GPT8 Module Stop + 23 + 23 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE24 + GPT7 Module Stop + 24 + 24 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE25 + GPT6 Module Stop + 25 + 25 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE26 + GPT5 Module Stop + 26 + 26 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE27 + GPT4 Module Stop + 27 + 27 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE28 + GPT3 Module Stop + 28 + 28 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE29 + GPT2 Module Stop + 29 + 29 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE30 + GPT1 Module Stop + 30 + 30 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPE31 + GPT0 Module Stop + 31 + 31 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + + + R_OPAMP + Operational Amplifier + 0x40086000 + + 0x00000008 + 0x005 + registers + + + 0x0000000E + 0x00C + registers + + + 0x0000001F + 0x007 + registers + + + + 4 + 0x3 + AMP[%s] + Input and Output Selectors for Operational Amplifier %s + 0x0E + read-write + + OS + Output Select Register + 0 + 8 + read-write + 0x00 + 0xFF + + + + PS + Plus Input Select Register + 2 + 8 + read-write + 0x00 + 0xFF + + + + MS + Minus Input Select Register + 1 + 8 + read-write + 0x00 + 0xFF + + + + + 3 + 2 + AMPOT[%s] + Operational Amplifier n Offset Trimming Registers + 0x20 + read-write + + P + Operational Amplifier n Offset Trimming Pch Register + 0 + 8 + read-write + 0 + 0xD0 + + + TRMP + AMPn input offset trimming Pch side + 0 + 4 read-write - 0x00010000 - 0xFFFFFFFF - - - TDC - Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR) - 24 - 29 - read-only - - - TDE - Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs. - 16 - 16 - read-write - zeroToClear - modify - - - 0 - Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number. - #0 - - - 1 - Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number. - #1 - - - - - RDC - Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR) - 8 - 13 - read-only - - - RDF - Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read. - 0 - 0 - read-write - zeroToClear - modify - - - 0 - Number of received data bytes in SSIFRDR is less than the set receive trigger number. - #0 - - - 1 - Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number. - #1 - - - - - + + + + + N + Operational Amplifier n Offset Trimming Nch Register + 1 + 8 + + + TRMN + AMPn input offset trimming Nch side + 0 + 4 + + + + + + AMPMC + Operational amplifier mode control register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + AMPSP + Operation mode selection + 7 + 7 + read-write + + + 0 + Low-power mode (low-speed). + #0 + + + 1 + High-speed mode. + #1 + + + + + 3 + 1 + AMPPC%s + Operational amplifier precharge control status + 0 + 0 + read-write + + + 0 + Precharging is stopped. + #0 + + + 1 + Precharging is enabled. + #1 + + + + + + + AMPTRM + Operational amplifier trigger mode control register + 0x09 + 8 + read-write + 0x00 + 0xFF + + + 4 + 2 + AMPTRM%s + Operational amplifier function activation/stop trigger control + 0 + 1 + read-write + + + 00 + Software trigger mode. + #00 + + + 01 + An activation and A/D trigger mode. + #01 + + + 10 + Setting prohibited. + #10 + + + 11 + An activation and A/D trigger mode. + #11 + + + + + + + AMPTRS + Operational Amplifier Activation Trigger Select Register + 0x0A + 8 + read-write + 0x00 + 0xFF + + + AMPTRS + ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register. + 0 + 1 + read-write + + + 00 + Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3 + #00 + + + 01 + Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1 + #01 + + + 10 + Setting prohibited + #10 + + + 11 + Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0 + #11 + + + + + + + AMPC + Operational amplifier control register + 0x0B + 8 + read-write + 0x00 + 0xFF + + + IREFE + Operation control of operational amplifier reference current circuit + 7 + 7 + read-write + + + 0 + Operational amplifier reference current circuit is stopped. + #0 + + + 1 + Operation of operational amplifier reference current circuit is enabled. + #1 + + + + + 4 + 1 + AMPE%s + Operation control of operational amplifier + 0 + 0 + read-write + + + 0 + Operation amplifier is stopped. + #0 + + + 1 + Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. + #1 + + + + + + + AMPMON + Operational amplifier monitor register + 0x0C + 8 + read-only + 0x00 + 0xFF + + + 4 + 1 + AMPMON%s + Operational amplifier status + 0 + 0 + read-only + + + 0 + Operational amplifier is stopped. + #0 + + + 1 + Operational amplifier is operating. + #1 + + + + + + + AMPCPC + Operational amplifier switch charge pump control register + 0x1A + 8 + read-write + 0x00 + 0xFF + + + 3 + 1 + PUMP%sEN + charge pump for AMP%s enable/disable + 0 + 0 + read-write + + + 0 + charge pump for AMP is disabled. + #0 + + + 1 + charge pump for AMP is enabled. + #1 + + + + + + + AMPUOTE + Operational Amplifier User Offset Trimming Enable Register + 0x1F + 8 + read-write + 0x00 + 0xFF + + + 3 + 1 + AMP%sTE + AMP%sOT write enable + 0 + 0 + read-write + + + 0 + Not possible to write the AMPnOTP and AMPnOTN registers + #0 + + + 1 + Possible to write the AMPnOTP and AMPnOTN registers + #1 + + + + + + + + + R_PDC + Parallel Data Capture Unit + 0x40094000 + + 0x00000000 + 0x01C + registers + + + + PCCR0 + PDC Control Register 0 + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EDS + Endian Select + 14 + 14 + read-write + + + 0 + Little endian + #0 + + + 1 + Big endian + #1 + + + + + PCKDIV + PCKO Frequency Division Ratio Select + 11 + 13 + read-write + + + 000 + PCKO/2 + #000 + + + 001 + PCKO/4 + #001 + + + 010 + PCKO/6 + #010 + + + 011 + PCKO/8 + #011 + + + 100 + PCKO/10 + #100 + + + 101 + PCKO/12 + #101 + + + 110 + PCKO/14 + #110 + + + 111 + PCKO/16 + #111 + + + + + PCKOE + PCKO Output Enable + 10 + 10 + read-write + + + 0 + PCKO output is disabled (fixed to the high level) + #0 + + + 1 + PCKO output is enabled. + #1 + + + + + HERIE + Horizontal Byte Number Setting Error Interrupt Enable + 9 + 9 + read-write + + + 0 + Generation of horizontal byte number setting error interrupt requests is disabled. + #0 + + + 1 + Generation of horizontal byte number setting error interrupt requests is enabled. + #1 + + + + + VERIE + Vertical Line Number Setting Error Interrupt Enable + 8 + 8 + read-write + + + 0 + Generation of vertical line number setting error interrupt requests is disabled. + #0 + + + 1 + Generation of vertical line number setting error interrupt requests is enabled. + #1 + + + + + UDRIE + Underrun Interrupt Enable + 7 + 7 + read-write + + + 0 + Generation of underrun interrupt requests is disabled. + #0 + + + 1 + Generation of underrun interrupt requests is enabled. + #1 + + + + + OVIE + Overrun Interrupt Enable + 6 + 6 + read-write + + + 0 + Generation of overrun interrupt requests is disabled. + #0 + + + 1 + Generation of overrun interrupt requests is enabled. + #1 + + + + + FEIE + Frame End Interrupt Enable + 5 + 5 + read-write + + + 0 + Generation of frame end interrupt requests is disabled. + #0 + + + 1 + Generation of frame end interrupt requests is enabled. + #1 + + + + + DFIE + Receive Data Ready Interrupt Enable + 4 + 4 + read-write + + + 0 + Generation of receive data ready interrupt requests is disabled. + #0 + + + 1 + Generation of receive data ready interrupt requests is enabled. + #1 + + + + + PRST + PDC Reset + 3 + 3 + write-only + + + 0 + PDC reset is not applied. + #0 + + + 1 + PDC is reset. + #1 + + + + + HPS + HSYNC Signal Polarity Select + 2 + 2 + read-write + + + 0 + HSYNC signal is active high. + #0 + + + 1 + HSYNC signal is active low. + #1 + + + + + VPS + VSYNC Signal Polarity Select + 1 + 1 + read-write + + + 0 + VSYNC signal is active high. + #0 + + + 1 + VSYNC signal is active low. + #1 + + + + + PCKE + Channel 0 GTCNT Count Clear + 0 + 0 + read-write + + + 0 + Operations for reception are stopped. + #0 + + + 1 + Operations for reception are ongoing. + #1 + + + + + + + PCCR1 + PDC Control Register 1 + 0x004 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PCE + PDC Operation Enable + 0 + 0 + read-write + + + 0 + Operations for reception are disabled. + #0 + + + 1 + Operations for reception are enabled. + #1 + + + + + + + PCSR + PDC Status Register + 0x008 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + HERF + Horizontal Byte Number Setting Error Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + Horizontal byte number setting error has not been generated. + #0 + + + 1 + Horizontal byte number setting error has been generated. + #1 + + + + + VERF + Vertical Line Number Setting Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + Vertical line number setting error has not been generated. + #0 + + + 1 + Vertical line number setting error has been generated. + #1 + + + + + UDRF + Underrun Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Underrun has not been generated. + #0 + + + 1 + Underrun has been generated. + #1 + + + + + OVRF + Overrun Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + FIFO overrun has not been generated. + #0 + + + 1 + FIFO overrun has been generated. + #1 + + + + + FEF + Frame End Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Frame end has not been generated. + #0 + + + 1 + Frame end has been generated. + #1 + + + + + FEMPF + FIFO Empty Flag + 1 + 1 + read-only + + + 0 + FIFO is not empty. + #0 + + + 1 + FIFO is empty. + #1 + + + + + FBSY + Frame Busy Flag + 0 + 0 + read-only + + + 0 + Operations for reception are stopped. + #0 + + + 1 + Operations for reception are ongoing. + #1 + + + + + + + PCMONR + PDC Pin Monitor Register + 0x00C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + HSYNC + HSYNC Signal Status Flag + 1 + 1 + read-only + + + 0 + HSYNC signal is at the low level. + #0 + + + 1 + HSYNC signal is at the high level. + #1 + + + + + VSYNC + VSYNC Signal Status Flag + 0 + 0 + read-only + + + 0 + VSYNC signal is at the low level. + #0 + + + 1 + VSYNC signal is at the high level. + #1 + + + + + + + PCDR + PDC Receive Data Register + 0x010 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + PCDR + The PDC includes a 32-bit-wide, 22-stage FIFO for the storage of captured data. The PCDR register is a 4-byte space to which the FIFO is mapped, and four bytes of data are read from the PCDR register at a time. + 0 + 31 + read-only + + + + + VCR + Vertical Capture Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + VSZ + Vertical Capture Size Number of lines to be captured. + 16 + 27 + read-write + + + VST + Vertical Capture Start Line PositionNumber of the line where capture is to start. + 0 + 11 + read-write + + + + + HCR + Horizontal Capture Register + 0x018 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + HSZ + Horizontal Capture Size Number of bytes to capture horizontally. + 16 + 27 + read-write + + + HST + Horizontal Capture Start Byte Position Horizontal position in bytes where capture is to start. + 0 + 11 + read-write + + + + + + + R_PORT0 + I/O Ports + 0x40040000 + + 0x00000000 + 0x010 + registers + + + + PCNTR1 + Port Control Register 1 + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PODR + Pmn Output Data + 16 + 31 + read-write + + + 0 + Low output + #0 + + + 1 + High output. + #1 + + + + + PDR + Pmn Direction + 0 + 15 + read-write + + + 0 + Input (functions as an input pin) + #0 + + + 1 + Output (functions as an output pin). + #1 + + + + + + + PODR + Output data register + PCNTR1 + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + PODR%s + Pmn Output Data + 0 + 0 + read-write + + + 0 + Low output + #0 + + + 1 + High output. + #1 + + + + + + + PDR + Data direction register + PCNTR1 + 0x02 + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + PDR%s + Pmn Direction + 0 + 0 + read-write + + + 0 + Input (functions as an input pin) + #0 + + + 1 + Output (functions as an output pin). + #1 + + + + + + + PCNTR2 + Port Control Register 2 + 0x04 + 32 + read-only + 0x00000000 + 0xFFFF0000 + + + EIDR + Pmn Event Input Data + 16 + 31 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + PIDR + Pmn Input Data + 0 + 15 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + + + EIDR + Event input data register + PCNTR2 + 0x04 + 16 + read-only + 0x0000 + 0xFFFF + + + 16 + 1 + EIDR%s + Pmn Event Input Data + 0 + 0 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + + + PIDR + Input data register + PCNTR2 + 0x06 + 16 + read-only + 0x0000 + 0x0000 + + + 16 + 1 + PIDR%s + Pmn Input Data + 0 + 0 + read-only + + + 0 + Low input + #0 + + + 1 + High input. + #1 + + + + + + + PCNTR3 + Port Control Register 3 + 0x08 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + PORR + Pmn Output Reset + 16 + 31 + write-only + + + 0 + No affect to output + #0 + + + 1 + Low output. + #1 + + + + + POSR + Pmn Output Set + 0 + 15 + write-only + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + PORR + Output set register + PCNTR3 + 0x08 + 16 + write-only + 0x0000 + 0xFFFF + + + 16 + 1 + PORR%s + Pmn Output Reset + 0 + 0 + write-only + + + 0 + No affect to output + #0 + + + 1 + Low output. + #1 + + + + + + + POSR + Output reset register + PCNTR3 + 0x0A + 16 + write-only + 0x0000 + 0xFFFF + + + 16 + 1 + POSR%s + Pmn Output Set + 0 + 0 + write-only + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + PCNTR4 + Port Control Register 4 + 0x0C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EORR + Pmn Event Output Reset + 16 + 31 + read-write + + + 0 + No affect to output + #0 + + + 1 + Low output + #1 + + + + + EOSR + Pmn Event Output Set + 0 + 15 + read-write + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + EORR + Event output set register + PCNTR4 + 0x0C + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + EORR%s + Pmn Event Output Reset + 0 + 0 + read-write + + + 0 + No affect to output + #0 + + + 1 + Low output + #1 + + + + + + + EOSR + Event output reset register + PCNTR4 + 0x0E + 16 + read-write + 0x0000 + 0xFFFF + + + 16 + 1 + EOSR%s + Pmn Event Output Set + 0 + 0 + read-write + + + 0 + No affect to output + #0 + + + 1 + High output. + #1 + + + + + + + + + R_PORT1 + 0x40040020 + + + R_PORT2 + 0x40040040 + + + R_PORT3 + 0x40040060 + + + R_PORT4 + 0x40040080 + + + R_PORT5 + 0x400400A0 + + + R_PORT6 + 0x400400C0 + + + R_PORT7 + 0x400400E0 + + + R_PORT8 + 0x40040100 + + + R_PORT9 + 0x40040120 + + + R_PORT10 + 0x40040140 + + + R_PORT11 + 0x40040160 + + + R_PFS + I/O Ports-PFS + 0x40040800 + + 0x00000000 + 0x040 + registers + + + + 12 + 0x40 + PORT[%s] + Port %s + + 16 + 4 + PIN[%s] + Pin Function Selects + 0 - SSIFTDR - Transmit FIFO Data Register - 0x18 - 32 - write-only - 0x00000000 - 0x00000000 - - - SSIFTDR - SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs. - 0 - 31 - write-only - - + PmnPFS_BY + Pin Function Control Register + 0x003 + 8 + read-write + 0x00 + 0xFD + + + NCODR + N-Channel Open Drain Control + 6 + 6 + read-write + + + 0 + CMOS output + #0 + + + 1 + NMOS open-drain output + #1 + + + + + PIM + Port Input Mode Control + 5 + 5 + read-write + + + 0 + CMOS input + #0 + + + 1 + TTL input + #1 + + + + + PCR + Pull-up Control + 4 + 4 + read-write + + + 0 + Disables an input pull-up. + #0 + + + 1 + Enables an input pull-up. + #1 + + + + + PDR + Port Direction + 2 + 2 + read-write + + + 0 + Input (Functions as an input pin.) + #0 + + + 1 + Output (Functions as an output pin.) + #1 + + + + + PIDR + Port Input Data + 1 + 1 + read-only + + + 0 + Low input + #0 + + + 1 + High input + #1 + + + + + PODR + Port Output Data + 0 + 0 + read-write + + + 0 + Low output + #0 + + + 1 + High output + #1 + + + + - - SSIFTDR16 - Transmit FIFO Data Register - SSIFTDR - 0x18 - 16 - write-only - 0x00000000 - 0x00000000 + + PmnPFS_HA + Pin Function Control Register + 0x002 + 16 + read-write + 0x0000 + 0xFFFD + + + ASEL + Analog Input enable + 15 + 15 + read-write + + + 0 + Used other than as analog pin + #0 + + + 1 + Used as analog pin + #1 + + + + + ISEL + IRQ input enable + 14 + 14 + read-write + + + 0 + Not used as IRQn input pin + #0 + + + 1 + Used as IRQn input pin + #1 + + + + + EOFR + Event on Falling/Rising + 12 + 13 + read-write + + + 00 + Do not care + #00 + + + 01 + Detect rising edge + #01 + + + 10 + Detect falling edge + #10 + + + 11 + Detect rising and falling edge + #11 + + + + + DSCR + Drive Strength Control Register + 10 + 11 + read-write + + + 00 + Normal drive output + #00 + + + 01 + Middle drive output + #01 + + + 10 + Middle drive with IIC + #10 + + + 11 + High-drive output + #11 + + + + - - SSIFTDR8 - Transmit FIFO Data Register - SSIFTDR - 0x18 - 8 - write-only - 0x00000000 - 0x00000000 + + PmnPFS + Pin Function Control Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFD + + + PSEL + Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table + 24 + 28 + read-write + + + PMR + Port Mode Control + 16 + 16 + read-write + + + 0 + Uses the pin as a general I/O pin. + #0 + + + 1 + Uses the pin as an I/O port for peripheral functions. + #1 + + + + - - SSIFRDR - Receive FIFO Data Register - 0x1C - 32 + + + + + + R_PMISC + I/O Ports-MISC + 0x40040D00 + + 0x00000003 + 0x01 + registers + + + + PFENET + Ethernet Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + Reserved + These bits are read as 00. The write value should be 00. + 6 + 7 + read-write + + + PHYMODE1 + Ethernet Mode Setting ch1 + 5 + 5 + read-write + + + 0 + RMII mode (ETHERC channel 1) + #0 + + + 1 + MII mode (ETHERC channel 1) + #1 + + + + + PHYMODE0 + Ethernet Mode Setting ch0 + 4 + 4 + read-write + + + 0 + RMII mode (ETHERC channel 0) + #0 + + + 1 + MII mode (ETHERC channel 0) + #1 + + + + + Reserved + These bits are read as 0000. The write value should be 0000. + 0 + 3 + read-write + + + + + PWPR + Write-Protect Register + 3 + 8 + read-write + + + PFSWE + PmnPFS Register Write + 6 + 6 + read-write + + + 0 + Writing to the PmnPFS register is disabled + #0 + + + 1 + Writing to the PmnPFS register is enabled. + #1 + + + + + B0WI + PFSWE Bit Write Disable + 7 + 7 + + + 0 + Writing to the PFSWE bit is enabled + #0 + + + 1 + Writing to the PFSWE bit is disabled. + true + + + + + + + PWPRS + Write-Protect Register for Secure + 5 + 8 + read-write + + + PFSWE + PmnPFS Register Write + 6 + 6 + read-write + + + 0 + Writing to the PmnPFS register is disabled + #0 + + + 1 + Writing to the PmnPFS register is enabled. + #1 + + + + + B0WI + PFSWE Bit Write Disable + 7 + 7 + + + 0 + Writing to the PFSWE bit is enabled + #0 + + + 1 + Writing to the PFSWE bit is disabled. + true + + + + + + + 9 + 0x2 + PMSAR[%s] + Port Security Attribution Register + 0x10 + + PMSAR + Port Security Attribution Register + 0 + 16 + read-write + 0xFFFF + 0xFFFF + + + + + + R_QSPI + Quad Serial Peripheral Interface + 0x64000000 + + 0x00000000 + 0x01C + registers + + + 0x00000020 + 0x00C + registers + + + 0x00000030 + 0x008 + registers + + + 0x00000804 + 0x04 + registers + + + + SFMSMD + Transfer Mode Control Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SFMCCE + Read instruction code selection. + 15 + 15 + read-write + + + 0 + Default instruction code set for each instruction + #0 + + + 1 + Instruction code written in the SFMSIC register + #1 + + + + + SFMOSW + Setup time adjustment for serial transmission + 11 + 11 + read-write + + + 0 + Does not extend the low-level width of SCK at transmission time + #0 + + + 1 + Extends the low-level width of SCK by 1*PCLKA at transmission time + #1 + + + + + SFMOHW + Hold time adjustment for serial transmission + 10 + 10 + read-write + + + 0 + Does not extend the high-level width of SCK at transmission time + #0 + + + 1 + Extends the high-level width of SCK by 1*PCLKA at transmission time + #1 + + + + + SFMOEX + Extension of the I/O buffer output enable signal for the serial interface + 9 + 9 + read-write + + + 0 + Does not extend the output enable signal + #0 + + + 1 + Extends the output enable signal by 1*QSPCLK + #1 + + + + + SFMMD3 + SPI mode selection. An initial value is determined by input to CFGMD3. + 8 + 8 + read-write + + + 0 + SPI mode 0 + #0 + + + 1 + SPI mode 3 + #1 + + + + + SFMPAE + Selection of the function for stopping prefetch at locations other than on byte boundaries + 7 + 7 + read-write + + + 0 + Disables prefetch stopping at locations other than on byte boundaries + #0 + + + 1 + Enables prefetch stopping at locations other than on byte boundaries + #1 + + + + + SFMPFE + Selection of the prefetch function + 6 + 6 + read-write + + + 0 + Disables prefetch + #0 + + + 1 + Enables prefetch + #1 + + + + + SFMSE + Selection of the prefetch function + 4 + 5 + read-write + + + 00 + Does not extend QSSL + #00 + + + 01 + Extends QSSL by 33*QSPCLK + #01 + + + 10 + Extends QSSL by 129*QSPCLK + #10 + + + 11 + Extends QSSL infinitely + #11 + + + + + SFMRM + Serial interface read mode selection + 0 + 2 + read-write + + + 000 + Standard Read + #000 + + + 001 + Fast Read + #001 + + + 010 + Fast Read Dual Output + #010 + + + 011 + Fast Read Dual I/O + #011 + + + 100 + Fast Read Quad Output + #100 + + + 101 + Fast Read Quad I/O + #101 + + + 110 + Setting prohibited + #110 + + + 111 + Setting prohibited + #111 + + + + + + + SFMSSC + Chip Selection Control Register + 0x004 + 32 + read-write + 0x00000037 + 0xFFFFFFFF + + + SFMSLD + QSSL signal output timing selection + 5 + 5 + read-write + + + 0 + Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK + #0 + + + 1 + Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK + #1 + + + + + SFMSHD + QSSL signal release timing selection + 4 + 4 + read-write + + + 0 + Releases QSSL 0.5*SCK after the last rising edge of QSPCLK + #0 + + + 1 + Releases QSSL 1.5*SCK after the last rising edge of QSPCLK + #1 + + + + + SFMSW + Selection of a minimum high-level width of the QSSL signal + 0 + 3 + read-write + + + 0000 + 1 x QSPCLK + #0000 + + + 0001 + 2 x QSPCLK + #0001 + + + 0010 + 3 x QSPCLK + #0010 + + + 0011 + 4 x QSPCLK + #0011 + + + 0100 + 5 x QSPCLK + #0100 + + + 0101 + 6 x QSPCLK + #0101 + + + 0110 + 7 x QSPCLK + #0110 + + + 0111 + 8 x QSPCLK + #0111 + + + 1000 + 9 x QSPCLK + #1000 + + + 1001 + 10 x QSPCLK + #1001 + + + 1010 + 11 x QSPCLK + #1010 + + + 1011 + 12 x QSPCLK + #1011 + + + 1100 + 13 x QSPCLK + #1100 + + + 1101 + 14 x QSPCLK + #1101 + + + 1110 + 15 x QSPCLK + #1110 + + + 1111 + 16 x QSPCLK + #1111 + + + + + + + SFMSKC + Clock Control Register + 0x008 + 32 + read-write + 0x00000008 + 0xFFFFFFFF + + + SFMDTY + Selection of a duty ratio correction function for the SCK signal + 5 + 5 + read-write + + + 0 + Serial interface reference cycle selection (* Pay attention to the irregularity.) + #0 + + + 1 + Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number) + #1 + + + + + SFMDV + Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction. + 0 + 4 + read-write + + + 10000 + 18 x PCLKA + #10000 + + + 10001 + 20 x PCLKA + #10001 + + + 10010 + 22 x PCLKA + #10010 + + + 10011 + 24 x PCLKA + #10011 + + + 10100 + 26 x PCLKA + #10100 + + + 10101 + 28 x PCLKA + #10101 + + + 10110 + 30 x PCLKA + #10110 + + + 10111 + 32 x PCLKA + #10111 + + + 11000 + 34 x PCLKA + #11000 + + + 11001 + 36 x PCLKA + #11001 + + + 11010 + 38 x PCLKA + #11010 + + + 11011 + 40 x PCLKA + #11011 + + + 11100 + 42 x PCLKA + #11100 + + + 11101 + 44 x PCLKA + #11101 + + + 11110 + 46 x PCLKA + #11110 + + + 11111 + 48 x PCLKA + #11111 + + + others + ( SFMDV + 2 ) x PCLKA + true + + + + + + + SFMSST + Status Register + 0x00C + 32 + read-only + 0x00000080 + 0xFFFFFFFF + + + PFOFF + Prefetch function operation state + 7 + 7 + read-only + + + 0 + The prefetch function is operating. + #0 + + + 1 + The prefetch function is not enabled or is not operating. + #1 + + + + + PFFUL + Prefetch buffer state + 6 + 6 + read-only + + + 0 + The prefetch buffer has a free space. + #0 + + + 1 + The prefetch buffer is full. + #1 + + + + + PFCNT + Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.) + 0 + 4 + read-only + + + 00000 + Nodata has been prefetched. + #00000 + + + others + Data of (PFCNT) bytes hs been prefetched. + true + + + + + + + SFMCOM + Communication Port Register + 0x010 + 32 + read-write + 0x00000000 + 0xFFFFFF00 + + + SFMD + Port for direct communication with the SPI bus.Input/output to and from this port is converted to a SPIbus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode. + 0 + 7 + read-write + + + + + SFMCMD + Communication Mode Control Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DCOM + Selection of a mode of communication with the SPI bus + 0 + 0 + read-write + + + 0 + ROM access mode + #0 + + + 1 + Direct communication mode + #1 + + + + + + + SFMCST + Communication Status Register + 0x018 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + EROMR + Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored. + 7 + 7 + read-only + + + 0 + ROM access is not detected in direct communication mode + #0 + + + 1 + ROM access is detected in direct communication mode + #1 + + + + + COMBSY + SPI bus cycle completion state in direct communication + 0 + 0 + read-only + + + 0 + There is no serial transfer being processed. + #0 + + + 1 + There is a serial transfer being processed. + #1 + + + + + + + SFMSIC + Instruction Code Register + 0x020 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SFMCIC + Serial ROM instruction code to substitute + 0 + 7 + read-write + + + + + SFMSAC + Address Mode Control Register + 0x024 + 32 + read-write + 0x00000002 + 0xFFFFFFFF + + + SFM4BC + Selection of a default instruction code, when Serial Interface address width is selected 4 bytes. + 4 + 4 + read-write + + + 0 + Does not use 4 Byte address read Instruction code + #0 + + + 1 + Use 4 Byte address read Instruction code + #1 + + + + + SFMAS + Selection the number of address bits of the serial interface + 0 + 1 + read-write + + + 00 + 1byte + #00 + + + 01 + 2bytes + #01 + + + 10 + 3bytes + #10 + + + 11 + 4 bytes + #11 + + + + + + + SFMSDC + Dummy Cycle Control Register + 0x028 + 32 + read-write + 0x0000FF00 + 0xFFFFFFFF + + + SFMXD + Mode data for serial ROM. (Control XIP mode) + 8 + 15 + read-write + + + 0 + XIP mode is prohibited + #0 + + + 1 + XIP mode is permitted + #1 + + + + + SFMXEN + XIP mode permission + 7 + 7 + read-write + + + 0 + XIP mode is prohibited + #0 + + + 1 + XIP mode is permitted + #1 + + + + + SFMXST + XIP mode status + 6 + 6 + read-only + + + 0 + Normal (non-XIP) mode is operating + #0 + + + 1 + XIP mode is operating + #1 + + + + + SFMDN + Selection of the number of dummy cycles of Fast Read instructions + 0 + 3 + read-write + + + 0000 + Default dummy cycles of each instruction. + #0000 + + + others + ( SFMDN + 2 ) x SCK + true + + + + + + + SFMSPC + SPI Protocol Control Register + 0x030 + 32 + read-write + 0x00000010 + 0xFFFFFFFF + + + SFMSDE + Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected. + 4 + 4 + read-write + + + 0 + Does not allocate minimum switch time + #0 + + + 1 + Allocate the minimum switch time equivalent to 1*QSPXLK + #1 + + + + + SFMSPI + Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately. + 0 + 1 + read-write + + + 00 + Extended SPI protocol + #00 + + + 01 + Dual SPI protocol + #01 + + + 10 + Quad SPI protocol + #10 + + + 11 + Setting prohibited. + #11 + + + + + + + SFMPMD + Port Control Register + 0x034 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SFMWPL + Specify level of WP pin + 2 + 2 + read-write + + + 0 + Low level + #0 + + + 1 + High level + #1 + + + + + + + SFMCNT1 + External QSPI Address Register 1 + 0x804 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + QSPI_EXT + BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. + 26 + 31 + read-write + + + + + + + R_RTC + Realtime Clock + 0x40044000 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000006 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + 0x0000000A + 0x01 + registers + + + 0x0000000C + 0x01 + registers + + + 0x0000000E + 0x003 + registers + + + 0x00000012 + 0x01 + registers + + + 0x00000014 + 0x01 + registers + + + 0x00000016 + 0x01 + registers + + + 0x00000018 + 0x01 + registers + + + 0x0000001A + 0x01 + registers + + + 0x0000001C + 0x003 + registers + + + 0x00000022 + 0x01 + registers + + + 0x00000024 + 0x01 + registers + + + 0x00000028 + 0x01 + registers + + + 0x0000002A + 0x005 + registers + + + 0x00000040 + 0x01 + registers + + + 0x00000042 + 0x01 + registers + + + 0x00000044 + 0x01 + registers + + + 0x00000052 + 0x01 + registers + + + 0x00000054 + 0x01 + registers + + + 0x00000056 + 0x01 + registers + + + 0x0000005A + 0x01 + registers + + + 0x0000005C + 0x01 + registers + + + 0x00000062 + 0x01 + registers + + + 0x00000064 + 0x01 + registers + + + 0x00000066 + 0x01 + registers + + + 0x0000006A + 0x01 + registers + + + 0x0000006C + 0x01 + registers + + + 0x00000072 + 0x01 + registers + + + 0x00000074 + 0x01 + registers + + + 0x00000076 + 0x01 + registers + + + 0x0000007A + 0x01 + registers + + + 0x0000007C + 0x01 + registers + + + + 3 + 0x2 + RTCCR[%s] + Time Capture Control Register + 0x40 + + RTCCR + Time Capture Control Register + 0 + 8 + read-write + 0x00 + 0x00 + + + TCNF + Time Capture Noise Filter Control + 4 + 5 + read-write + + + 00 + The noise filter is off. + #00 + + + 01 + Setting prohibited + #01 + + + 10 + The noise filter is on (count source). + #10 + + + 11 + The noise filter is on (count source by divided by 32). + #11 + + + + + TCST + Time Capture Status + 2 + 2 read-only - 0x00000000 - 0x00000000 - - - SSIFRDR - SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data. - 0 - 31 - read-only - - - - - SSIFRDR16 - Receive FIFO Data Register - SSIFRDR - 0x1C - 16 + + + 0 + No event is detected. + #0 + + + 1 + An event is detected. + #1 + + + + + TCCT + Time Capture Control + 0 + 1 + read-write + + + 00 + No event is detected. + #00 + + + 01 + Rising edge is detected. + #01 + + + 10 + Falling edge is detected. + #10 + + + 11 + Both edges are detected. + #11 + + + + + + + + 3 + 0x10 + CP[%s] + Capture registers + 0x50 + + RSEC + Second Capture Register + 0x02 + 8 + read-only + 0x00 + 0x00 + + + SEC10 + 10-Second Capture Capture value for the tens place of seconds + 4 + 6 read-only - 0x00000000 - 0x00000000 - - - SSIFRDR8 - Receive FIFO Data Register - SSIFRDR - 0x1C - 8 + + + SEC1 + 1-Second Capture Capture value for the ones place of seconds + 0 + 3 read-only - 0x00000000 - 0x00000000 - - - SSIOFR - Audio Format Register - 0x20 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - BCKASTP - Whether to Enable Stopping BCK Output When SSIE is in Idle Status - 9 - 9 - read-write - - - 0 - Always outputs BCK to the SSIBCK pin. - #0 - - - 1 - Automatically controls output of BCK to the SSIBCK pin. - #1 - - - - - LRCONT - Whether to Enable LRCK/FS Continuation - 8 - 8 - read-write - - - 0 - Disables LRCK/FS continuation. - #0 - - - 1 - Enables LRCK/FS continuation. - #1 - - - - - OMOD - Audio Format Select - 0 - 1 - read-write - - - 00 - I2S format - #00 - - - 01 - TDM format - #01 - - - 10 - Monaural format - #10 - - - 11 - Setting prohibited. - #11 - - - - - - - SSISCR - Status Control Register - 0x24 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - TDES - TDE Setting Condition Select - 8 - 12 - read-write - - - 00000 - SSIFTDR has one stage or more free space - #00000 - - - 00001 - SSIFTDR has two stages or more free space (snip) - #00001 - - - 11110 - SSIFTDR has thirty-one stages or more free space - #11110 - - - 11111 - SSIFTDR has thirty-two stages or more free space. - #11111 - - - - - RDFS - RDF Setting Condition Select - 0 - 4 - read-write - - - 00000 - SSIFRDR has one stage or more data size - #00000 - - - 00001 - SSIFRDR has two stages or more data size (snip) - #00001 - - - 11110 - SSIFRDR has thirty-one stages or more data size - #11110 - - - 11111 - SSIFRDR has thirty-two stages or more data size. - #11111 - - - - - - + + + + + BCNT0 + BCNT0 Capture Register + RSEC + 0x02 + 8 + read-only + 0x00 + 0x00 + + + BCNT0CP + BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RMIN + Minute Capture Register + 0x04 + 8 + read-only + 0x00 + 0x00 + + + MIN10 + 10-Minute Capture Capture value for the tens place of minutes + 4 + 6 + read-only + + + MIN1 + 1-Minute Capture Capture value for the ones place of minutes + 0 + 3 + read-only + + + + + BCNT1 + BCNT1 Capture Register + RMIN + 0x04 + 8 + read-only + 0x00 + 0x00 + + + BCNT1CP + BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RHR + Hour Capture Register + 0x06 + 8 + read-only + 0x00 + 0x00 + + + PM + A.m./p.m. select for time counter setting. + 6 + 6 + read-only + + + 0 + a.m. + #0 + + + 1 + p.m. + #1 + + + + + HR10 + 10-Minute Capture Capture value for the tens place of minutes + 4 + 5 + read-only + + + HR1 + 1-Minute Capture Capture value for the ones place of minutes + 0 + 3 + read-only + + + + + BCNT2 + BCNT2 Capture Register + RHR + 0x06 + 8 + read-only + 0x00 + 0x00 + + + BCNT2CP + BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RDAY + Date Capture Register + 0x0A + 8 + read-only + 0x00 + 0x00 + + + DATE10 + 10-Day Capture Capture value for the tens place of minutes + 4 + 5 + read-only + + + DATE1 + 1-Day Capture Capture value for the ones place of minutes + 0 + 3 + read-only + + + + + BCNT3 + BCNT3 Capture Register + RDAY + 0x0A + 8 + read-only + 0x00 + 0x00 + + + BCNT3CP + BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. + 0 + 7 + read-only + + + + + RMON + Month Capture Register + 0x0C + 8 + read-only + 0x00 + 0x00 + + + MON10 + 10-Month Capture Capture value for the tens place of months + 4 + 4 + read-only + + + MON1 + 1-Month Capture Capture value for the ones place of months + 0 + 3 + read-only + + + + + + R64CNT + 64-Hz Counter + 0x00 + 8 + read-only + 0x00 + 0x80 + + + F1HZ + 1Hz + 6 + 6 + read-only + + + F2HZ + 2Hz + 5 + 5 + read-only + + + F4HZ + 4Hz + 4 + 4 + read-only + + + F8HZ + 8Hz + 3 + 3 + read-only + + + F16HZ + 16Hz + 2 + 2 + read-only + + + F32HZ + 32Hz + 1 + 1 + read-only + + + F64HZ + 64Hz + 0 + 0 + read-only + + + + + RSECCNT + Second Counter + 0x02 + 8 + read-write + 0x00 + 0x00 + + + SEC10 + 10-Second Count Counts from 0 to 5 for 60-second counting. + 4 + 6 + read-write + + + SEC1 + 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + BCNT0 + Binary Counter 0 + RSECCNT + 0x02 + 8 + read-write + 0x00 + 0x00 + + + BCNT0 + The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0. + 0 + 7 + read-write + + + + + RMINCNT + Minute Counter + 0x04 + 8 + read-write + 0x00 + 0x00 + + + MIN10 + 10-Minute Count Counts from 0 to 5 for 60-minute counting. + 4 + 6 + read-write + + + MIN1 + 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + BCNT1 + Binary Counter 1 + RMINCNT + 0x04 + 8 + read-write + 0x00 + 0x00 + + + BCNT1 + The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8. + 0 + 7 + read-write + + + + + RHRCNT + Hour Counter + 0x06 + 8 + read-write + 0x00 + 0x00 + + + PM + Time Counter Setting for a.m./p.m. + 6 + 6 + read-write + + + 0 + a.m. + #0 + + + 1 + p.m. + #1 + + + + + HR10 + 10-Hour Count Counts from 0 to 2 once per carry from the ones place. + 4 + 5 + read-write + + + HR1 + 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + BCNT2 + Binary Counter 2 + RHRCNT + 0x06 + 8 + read-write + 0x00 + 0x00 + + + BCNT2 + The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16. + 0 + 7 + read-write + + + + + RWKCNT + Day-of-Week Counter + 0x08 + 8 + read-write + 0x00 + 0x00 + + + DAYW + Day-of-Week Counting + 0 + 2 + read-write + + + 000 + Sunday + #000 + + + 001 + Monday + #001 + + + 010 + Tuesday + #010 + + + 011 + Wednesday + #011 + + + 100 + Thursday + #100 + + + 101 + Friday + #101 + + + 110 + Saturday + #110 + + + 111 + Setting Prohibited + #111 + + + + + + + BCNT3 + Binary Counter 3 + RWKCNT + 0x08 + 8 + read-write + 0x00 + 0x00 + + + BCNT3 + The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24. + 0 + 7 + read-write + + + + + RDAYCNT + Day Counter + 0x0A + 8 + read-write + 0x00 + 0xC0 + + + DATE10 + 10-Day Count Counts from 0 to 3 once per carry from the ones place. + 4 + 5 + read-write + + + DATE1 + 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + RMONCNT + Month Counter + 0x0C + 8 + read-write + 0x00 + 0xE0 + + + MON10 + 10-Month Count Counts from 0 to 1 once per carry from the ones place. + 4 + 4 + read-write + + + MON1 + 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + RYRCNT + Year Counter + 0x0E + 16 + read-write + 0x0000 + 0xFF00 + + + YR10 + 10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place. + 4 + 7 + read-write + + + YR1 + 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place. + 0 + 3 + read-write + + + + + RSECAR + Second Alarm Register + 0x10 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RSECCNT counter value. + #0 + + + 1 + The register value is compared with the RSECCNT counter value. + #1 + + + + + SEC10 + 10-Seconds Value for the tens place of seconds + 4 + 6 + read-write + + + SEC1 + 1-Second Value for the ones place of seconds + 0 + 3 + write-only + + + + + BCNT0AR + Binary Counter 0 Alarm Register + RSECAR + 0x10 + 8 + read-write + 0x00 + 0x00 + + + BCNT0AR + he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0. + 0 + 7 + read-write + + + + + RMINAR + Minute Alarm Register + 0x12 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RMINCNT counter value. + #0 + + + 1 + The register value is compared with the RMINCNT counter value. + #1 + + + + + MIN10 + 10-Minute Count Value for the tens place of minutes + 4 + 6 + read-write + + + MIN1 + 1-Minute Count Value for the ones place of minutes + 0 + 3 + read-write + + + + + BCNT1AR + Binary Counter 1 Alarm Register + RMINAR + 0x12 + 8 + read-write + 0x00 + 0x00 + + + BCNT1AR + he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8. + 0 + 7 + read-write + + + + + RHRAR + Hour Alarm Register + 0x14 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RHRCNT counter value. + #0 + + + 1 + The register value is compared with the RHRCNT counter value. + #1 + + + + + PM + Time Counter Setting for a.m./p.m. + 6 + 6 + read-write + + + 0 + a.m. + #0 + + + 1 + p.m. + #1 + + + + + HR10 + 10-Hour Count Value for the tens place of hours + 4 + 5 + read-write + + + HR1 + 1-Hour Count Value for the ones place of hours + 0 + 3 + read-write + + + + + BCNT2AR + Binary Counter 2 Alarm Register + RHRAR + 0x14 + 8 + read-write + 0x00 + 0x00 + + + BCNT2AR + The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16. + 0 + 7 + read-write + + + + + RWKAR + Day-of-Week Alarm Register + 0x16 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RWKCNT counter value. + #0 + + + 1 + The register value is compared with the RWKCNT counter value. + #1 + + + + + DAYW + Day-of-Week Counting + 0 + 2 + read-write + + + 000 + Sunday + #000 + + + 001 + Monday + #001 + + + 010 + Tuesday + #010 + + + 011 + Wednesday + #011 + + + 100 + Thursday + #100 + + + 101 + Friday + #101 + + + 110 + Saturday + #110 + + + 111 + Setting Prohibited + #111 + + + + + + + BCNT3AR + Binary Counter 3 Alarm Register + RWKAR + 0x16 + 8 + read-write + 0x00 + 0x00 + + + BCNT3AR + The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24. + 0 + 7 + read-write + + + + + RDAYAR + Date Alarm Register + 0x18 + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RDAYCNT counter value. + #0 + + + 1 + The register value is compared with the RDAYCNT counter value. + #1 + + + + + DATE10 + 10 Days Value for the tens place of days + 4 + 5 + read-write + + + DATE1 + 1 Day Value for the ones place of days + 0 + 3 + read-write + + + + + BCNT0AER + Binary Counter 0 Alarm Enable Register + RDAYAR + 0x18 + 8 + read-write + 0x00 + 0x00 + + + ENB + The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0. + 0 + 7 + read-write + + + + + RMONAR + Month Alarm Register + 0x1A + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RMONCNT counter value. + #0 + + + 1 + The register value is compared with the RMONCNT counter value. + #1 + + + + + MON10 + 10 Months Value for the tens place of months + 4 + 4 + read-write + + + MON1 + 1 Month Value for the ones place of months + 0 + 3 + read-write + + + + + BCNT1AER + Binary Counter 1 Alarm Enable Register + RMONAR + 0x1A + 8 + read-write + 0x00 + 0x00 + + + ENB + The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8. + 0 + 7 + read-write + + + + + RYRAR + Year Alarm Register + 0x1C + 16 + read-write + 0x0000 + 0xFF00 + + + YR10 + 10 Years Value for the tens place of years + 4 + 7 + read-write + + + YR1 + 1 Year Value for the ones place of years + 0 + 3 + read-write + + + + + BCNT2AER + Binary Counter 2 Alarm Enable Register + RYRAR + 0x1C + 16 + read-write + 0x0000 + 0xFF00 + + + ENB + The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16. + 0 + 7 + read-write + + + + + RYRAREN + Year Alarm Enable Register + 0x1E + 8 + read-write + 0x00 + 0x00 + + + ENB + Compare enable + 7 + 7 + read-write + + + 0 + The register value is not compared with the RYRCNT counter value. + #0 + + + 1 + The register value is compared with the RYRCNT counter value. + #1 + + + + + + + BCNT3AER + Binary Counter 3 Alarm Enable Register + RYRAREN + 0x1E + 8 + read-write + 0x00 + 0x00 + + + ENB + The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. + 0 + 7 + read-write + + + + + RCR1 + RTC Control Register 1 + 0x22 + 8 + read-write + 0x00 + 0x0A + + + PES + Periodic Interrupt Select + 4 + 7 + read-write + + + 0110 + A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1). + #0110 + + + 0111 + A periodic interrupt is generated every 1/128 second. + #0111 + + + 1000 + A periodic interrupt is generated every 1/64 second. + #1000 + + + 1001 + A periodic interrupt is generated every 1/32 second. + #1001 + + + 1010 + A periodic interrupt is generated every 1/16 second. + #1010 + + + 1011 + A periodic interrupt is generated every 1/8 second. + #1011 + + + 1100 + A periodic interrupt is generated every 1/4 second. + #1100 + + + 1101 + A periodic interrupt is generated every 1/2 second. + #1101 + + + 1110 + A periodic interrupt is generated every 1 second. + #1110 + + + 1111 + A periodic interrupt is generated every 2 seconds. + #1111 + + + others + No periodic interrupts are generated. + true + + + + + RTCOS + RTCOUT Output Select + 3 + 3 + read-write + + + 0 + RTCOUT outputs 1 Hz. + #0 + + + 1 + RTCOUT outputs 64 Hz. + #1 + + + + + PIE + Periodic Interrupt Enable + 2 + 2 + read-write + + + 0 + A periodic interrupt request is disabled. + #0 + + + 1 + A periodic interrupt request is enabled. + #1 + + + + + CIE + Carry Interrupt Enable + 1 + 1 + read-write + + + 0 + A carry interrupt request is disabled. + #0 + + + 1 + A carry interrupt request is enabled. + #1 + + + + + AIE + Alarm Interrupt Enable + 0 + 0 + read-write + + + 0 + An alarm interrupt request is disabled. + #0 + + + 1 + An alarm interrupt request is enabled. + #1 + + + + + + + RCR2 + RTC Control Register 2 + 0x24 + 8 + read-write + 0x00 + 0x0E + + + CNTMD + Count Mode Select + 7 + 7 + read-write + + + 0 + The calendar count mode. + #0 + + + 1 + The binary count mode. + #1 + + + + + HR24 + Hours Mode + 6 + 6 + read-write + + + 0 + The RTC operates in 12-hour mode. + #0 + + + 1 + The RTC operates in 24-hour mode. + #1 + + + + + AADJP + Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.) + 5 + 5 + read-write + + + 0 + The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute. + #0 + + + 1 + The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds. + #1 + + + + + AADJE + Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.) + 4 + 4 + read-write + + + 0 + Automatic adjustment is disabled. + #0 + + + 1 + Automatic adjustment is enabled. + #1 + + + + + RTCOE + RTCOUT Output Enable + 3 + 3 + read-write + + + 0 + RTCOUT output disabled. + #0 + + + 1 + RTCOUT output enabled. + #1 + + + + + ADJ30 + 30-Second Adjustment + 2 + 2 + read-write + + + 0 + Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read) + #0 + + + 1 + 30-second adjustment is executed.(write) / During 30-second adjustment.(read) + #1 + + + + + RESET + RTC Software Reset + 1 + 1 + read-write + + + 0 + Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read) + #0 + + + 1 + The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read) + #1 + + + + + START + Start + 0 + 0 + read-write + + + 0 + Prescaler and time counter are stopped. + #0 + + + 1 + Prescaler and time counter operate normally. + #1 + + + + + + + RCR4 + RTC Control Register 4 + 0x28 + 8 + read-write + 0x00 + 0xFE + + + RCKSEL + Count Source Select + 0 + 0 + read-write + + + 0 + Sub-clock oscillator is selected. + #0 + + + 1 + LOCO clock oscillator is selected. + #1 + + + + + ROPSEL + RTC Operation Mode Select + 7 + 7 + read-write + + + 0 + Normal operation mode is selected. + #0 + + + 1 + Low-consumption clock mode is selected. + #1 + + + + + + + RFRH + Frequency Register H + 0x2A + 16 + read-write + 0x0000 + 0xFFFE + + + RFC16 + Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle. + 0 + 0 + read-write + + + + + RFRL + Frequency Register L + 0x2C + 16 + read-write + 0x0000 + 0x0000 + + + RFC + Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle. + 0 + 15 + read-write + + + + + RADJ + Time Error Adjustment Register + 0x2E + 8 + read-write + 0x00 + 0x00 + + + PMADJ + Plus-Minus + 6 + 7 + read-write + + + 00 + Adjustment is not performed. + #00 + + + 01 + Adjustment is performed by the addition to the prescaler. + #01 + + + 10 + Adjustment is performed by the subtraction from the prescaler. + #10 + + + 11 + Setting prohibited + #11 + + + + + ADJ + Adjustment Value These bits specify the adjustment value from the prescaler. + 0 + 5 + read-write + + + + + + + R_SCI0 + Serial Communications Interface + 0x40070000 + + 0x00000000 + 0x01D + registers + + + + SMR + Serial Mode Register (SCMR.SMIF = 0) + 0x00 + 8 + read-write + 0x00 + 0xFF + + + CM + Communication Mode + 7 + 7 + read-write + + + 0 + Asynchronous mode or simple I2C mode + #0 + + + 1 + Clock synchronous mode + #1 + + + + + CHR + Character Length(Valid only in asynchronous mode) + 6 + 6 + read-write + + + 0 + Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) + #0 + + + 1 + Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) + #1 + + + + + PE + Parity Enable(Valid only in asynchronous mode) + 5 + 5 + read-write + + + 0 + Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) + #0 + + + 1 + The parity bit is added (transmitting) / The parity bit is checked (receiving) + #1 + + + + + PM + Parity Mode (Valid only when the PE bit is 1) + 4 + 4 + read-write + + + 0 + Selects even parity + #0 + + + 1 + Selects odd parity + #1 + + + + + STOP + Stop Bit Length(Valid only in asynchronous mode) + 3 + 3 + read-write + + + 0 + 1 stop bit + #0 + + + 1 + 2 stop bits + #1 + + + + + MP + Multi-Processor Mode(Valid only in asynchronous mode) + 2 + 2 + read-write + + + 0 + Multi-processor communications function is disabled + #0 + + + 1 + Multi-processor communications function is enabled + #1 + + + + + CKS + Clock Select + 0 + 1 + read-write + + + 00 + PCLK clock + #00 + + + 01 + PCLK/4 clock + #01 + + + 10 + PCLK/16 clock + #10 + + + 11 + PCLK/64 clock + #11 + + + + + + + SMR_SMCI + Serial mode register (SCMR.SMIF = 1) + SMR + 0x00 + 8 + read-write + 0x00 + 0xFF + + + GM + GSM Mode + 7 + 7 + read-write + + + 0 + Normal mode operation + #0 + + + 1 + GSM mode operation + #1 + + + + + BLK + Block Transfer Mode + 6 + 6 + read-write + + + 0 + Normal mode operation + #0 + + + 1 + Block transfer mode operation + #1 + + + + + PE + Parity Enable(Valid only in asynchronous mode) + 5 + 5 + read-write + + + 0 + Setting Prohibited + #0 + + + 1 + Set this bit to 1 in smart card interface mode. + #1 + + + + + PM + Parity Mode (Valid only when the PE bit is 1) + 4 + 4 + read-write + + + 0 + Selects even parity + #0 + + + 1 + Selects odd parity + #1 + + + + + BCP + Base Clock Pulse(Valid only in asynchronous mode) + 2 + 3 + read-write + + + 00 + 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) + #00 + + + 01 + 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) + #01 + + + 10 + 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) + #10 + + + 11 + 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) + #11 + + + + + CKS + Clock Select + 0 + 1 + read-write + + + 00 + PCLK clock + #00 + + + 01 + PCLK/4 clock + #01 + + + 10 + PCLK/16 clock + #10 + + + 11 + PCLK/64 clock + #11 + + + + + + + BRR + Bit Rate Register + 0x01 + 8 + read-write + 0xFF + 0xFF + + + BRR + BRR is an 8-bit register that adjusts the bit rate. + 0 + 7 + read-write + + + + + SCR + Serial Control Register (SCMR.SMIF = 0) + 0x02 + 8 + read-write + 0x00 + 0xFF + + + TIE + Transmit Interrupt Enable + 7 + 7 + read-write + + + 0 + SCI_TXI interrupt request is disabled + #0 + + + 1 + SCI_TXI interrupt request is enabled + #1 + + + + + RIE + Receive Interrupt Enable + 6 + 6 + read-write + + + 0 + SCI_RXI and SCI_ERI interrupt requests are disabled + #0 + + + 1 + SCI_RXI and SCI_ERI interrupt requests are enabled + #1 + + + + + TE + Transmit Enable + 5 + 5 + read-write + + + 0 + Serial transmission is disabled + #0 + + + 1 + Serial transmission is enabled + #1 + + + + + RE + Receive Enable + 4 + 4 + read-write + + + 0 + Serial reception is disabled + #0 + + + 1 + Serial reception is enabled + #1 + + + + + MPIE + Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) + 3 + 3 + read-write + + + 0 + Normal reception + #0 + + + 1 + When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. + #1 + + + + + TEIE + Transmit End Interrupt Enable + 2 + 2 + read-write + + + 0 + SCI_TEI interrupt request is disabled + #0 + + + 1 + SCI_TEI interrupt request is enabled + #1 + + + + + CKE + Clock Enable + 0 + 1 + read-write + + + 00 + The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) + #00 + + + 01 + The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) + #01 + + + others + The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) + true + + + + + + + SCR_SMCI + Serial Control Register (SCMR.SMIF =1) + SCR + 0x02 + 8 + read-write + 0x00 + 0xFF + + + TIE + Transmit Interrupt Enable + 7 + 7 + read-write + + + 0 + A SCI_TXI interrupt request is disabled + #0 + + + 1 + A SCI_TXI interrupt request is enabled + #1 + + + + + RIE + Receive Interrupt Enable + 6 + 6 + read-write + + + 0 + SCI_RXI and SCI_ERI interrupt requests are disabled + #0 + + + 1 + SCI_RXI and SCI_ERI interrupt requests are enabled + #1 + + + + + TE + Transmit Enable + 5 + 5 + read-write + + + 0 + Serial transmission is disabled + #0 + + + 1 + Serial transmission is enabled + #1 + + + + + RE + Receive Enable + 4 + 4 + read-write + + + 0 + Serial reception is disabled + #0 + + + 1 + Serial reception is enabled + #1 + + + + + MPIE + Multi-Processor Interrupt Enable + 3 + 3 + read-write + + + TEIE + Transmit End Interrupt Enable + 2 + 2 + read-write + + + CKE + Clock Enable + 0 + 1 + read-write + + + 00 + Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) + #00 + + + 01 + Clock Output + #01 + + + 10 + Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) + #10 + + + 11 + Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) + #11 + + + + + + + TDR + Transmit Data Register + 0x03 + 8 + read-write + 0xFF + 0xFF + + + TDR + TDR is an 8-bit register that stores transmit data. + 0 + 7 + read-write + + + + + SSR + Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) + 0x04 + 8 + read-write + 0x84 + 0xFF + + + TDRE + Transmit Data Empty Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Transmit data is in TDR register + #0 + + + 1 + No transmit data is in TDR register + #1 + + + + + RDRF + Receive Data Full Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No received data is in RDR register + #0 + + + 1 + Received data is in RDR register + #1 + + + + + ORER + Overrun Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + FER + Framing Error Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No framing error occurred + #0 + + + 1 + A framing error has occurred + #1 + + + + + PER + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred + #0 + + + 1 + A parity error has occurred + #1 + + + + + TEND + Transmit End Flag + 2 + 2 + read-only + + + 0 + A character is being transmitted. + #0 + + + 1 + Character transfer has been completed. + #1 + + + + + MPB + Multi-Processor + 1 + 1 + read-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + MPBT + Multi-Processor Bit Transfer + 0 + 0 + read-write + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + + + SSR_FIFO + Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) + SSR + 0x04 + 8 + read-write + 0x80 + 0xFD + + + TDFE + Transmit FIFO data empty flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. + #0 + + + 1 + The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number + #1 + + + + + RDF + Receive FIFO data full flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + The quantity of receive data written in FRDR falls below the specified receive triggering number. + #0 + + + 1 + The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. + #1 + + + + + ORER + Overrun Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + FER + Framing Error Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No framing error occurred. + #0 + + + 1 + A framing error has occurred. + #1 + + + + + PER + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred. + #0 + + + 1 + A parity error has occurred. + #1 + + + + + TEND + Transmit End Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + A character is being transmitted or standing by for transmission. + #0 + + + 1 + Character transfer has been completed. + #1 + + + + + DR + Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected) + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) + #0 + + + 1 + Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. + #1 + + + + + + + SSR_SMCI + Serial Status Register(SCMR.SMIF = 1) + SSR + 0x04 + 8 + read-write + 0x84 + 0xFF + + + TDRE + Transmit Data Empty Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Transmit data is in TDR register + #0 + + + 1 + No transmit data is in TDR register + #1 + + + + + RDRF + Receive Data Full Flag + 6 + 6 + read-write + zeroToClear + modify + + + 0 + No received data is in RDR register + #0 + + + 1 + Received data is in RDR register + #1 + + + + + ORER + Overrun Error Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + ERS + Error Signal Status Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Low error signal not responded + #0 + + + 1 + Low error signal responded + #1 + + + + + PER + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred + #0 + + + 1 + A parity error has occurred + #1 + + + + + TEND + Transmit End Flag + 2 + 2 + read-only + + + 0 + A character is being transmitted. + #0 + + + 1 + Character transfer has been completed. + #1 + + + + + MPB + Multi-ProcessorThis bit should be 0 in smart card interface mode. + 1 + 1 + read-only + + + MPBT + Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. + 0 + 0 + read-write + + + + + RDR + Receive Data Register + 0x05 + 8 + read-only + 0x00 + 0xFF + + + RDR + RDR is an 8-bit register that stores receive data. + 0 + 7 + read-only + + + + + SCMR + Smart Card Mode Register + 0x06 + 8 + read-write + 0xF2 + 0xFF + + + BCP2 + Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits + 7 + 7 + read-write + + + 0 + S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) + #0 + + + 1 + S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) + #1 + + + + + CHR1 + Character Length 1(Only valid in asynchronous mode) + 4 + 4 + read-write + + + 0 + Transmit/receive in 9-bit data length + #0 + + + 1 + Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) + #1 + + + + + SDIR + Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. + 3 + 3 + read-write + + + 0 + Transfer with LSB first + #0 + + + 1 + Transfer with MSB first + #1 + + + + + SINV + Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. + 2 + 2 + read-write + + + 0 + TDR contents are transmitted as they are. Receive data is stored as it is in RDR. + #0 + + + 1 + TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. + #1 + + + + + SMIF + Smart Card Interface Mode Select + 0 + 0 + read-write + + + 0 + Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) + #0 + + + 1 + Smart card interface mode + #1 + + + + + + + SEMR + Serial Extended Mode Register + 0x07 + 8 + read-write + 0x00 + 0xFF + + + RXDESEL + Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) + 7 + 7 + read-write + + + 0 + The low level on the RXDn pin is detected as the start bit. + #0 + + + 1 + A falling edge on the RXDn pin is detected as the start bit. + #1 + + + + + BGDM + Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). + 6 + 6 + read-write + + + 0 + Baud rate generator outputs the clock with normal frequency. + #0 + + + 1 + Baud rate generator outputs the clock with doubled frequency. + #1 + + + + + NFEN + Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. + 5 + 5 + read-write + + + 0 + Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. + #0 + + + 1 + Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. + #1 + + + + + ABCS + Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) + 4 + 4 + read-write + + + 0 + Selects 16 base clock cycles for 1-bit period. + #0 + + + 1 + Selects 8 base clock cycles for 1-bit period. + #1 + + + + + ABCSE + Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) + 3 + 3 + read-write + + + 0 + Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. + #0 + + + 1 + Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. + #1 + + + + + BRME + Bit Rate Modulation Enable + 2 + 2 + read-write + + + 0 + Bit rate modulation function is disabled. + #0 + + + 1 + Bit rate modulation function is enabled. + #1 + + + + + + + SNFR + Noise Filter Setting Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + NFCS + Noise Filter Clock Select + 0 + 2 + read-write + + + 000 + The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) + #000 + + + 001 + The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) + #001 + + + 010 + The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) + #010 + + + 011 + The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) + #011 + + + 100 + The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) + #100 + + + others + Settings prohibited. + true + + + + + + + SIMR1 + I2C Mode Register 1 + 0x09 + 8 + read-write + 0x00 + 0xFF + + + IICDL + SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. + 3 + 7 + read-write + + + 00000 + No output delay + #00000 + + + others + (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. + true + + + + + IICM + Simple I2C Mode Select + 0 + 0 + read-write + + + 0 + Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) + #0 + + + 1 + Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) + #1 + + + + + + + SIMR2 + I2C Mode Register 2 + 0x0A + 8 + read-write + 0x00 + 0xFF + + + IICACKT + ACK Transmission Data + 5 + 5 + read-write + + + 0 + ACK transmission + #0 + + + 1 + NACK transmission and reception of ACK/NACK + #1 + + + + + IICCSC + Clock Synchronization + 1 + 1 + read-write + + + 0 + No synchronization with the clock signal + #0 + + + 1 + Synchronization with the clock signal + #1 + + + + + IICINTM + I2C Interrupt Mode Select + 0 + 0 + read-write + + + 0 + Use ACK/NACK interrupts. + #0 + + + 1 + Use reception and transmission interrupts + #1 + + + + + + + SIMR3 + I2C Mode Register 3 + 0x0B + 8 + read-write + 0x00 + 0xFF + + + IICSCLS + SCL Output Select + 6 + 7 + read-write + + + 00 + Serial clock output + #00 + + + 01 + Generate a start, restart, or stop condition. + #01 + + + 10 + Output the low level on the SSCLn pin. + #10 + + + 11 + Place the SSCLn pin in the high-impedance state. + #11 + + + + + IICSDAS + SDA Output Select + 4 + 5 + read-write + + + 00 + Serial data output + #00 + + + 01 + Generate a start, restart, or stop condition. + #01 + + + 10 + Output the low level on the SSDAn pin. + #10 + + + 11 + Place the SSDAn pin in the high-impedance state. + #11 + + + + + IICSTIF + Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) + 3 + 3 + read-write + zeroToClear + modify + + + 0 + There are no requests for generating conditions or a condition is being generated. + #0 + + + 1 + A start, restart, or stop condition is completely generated. + #1 + + + + + IICSTPREQ + Stop Condition Generation + 2 + 2 + read-write + + + 0 + A stop condition is not generated. + #0 + + + 1 + A stop condition is generated. + #1 + + + + + IICRSTAREQ + Restart Condition Generation + 1 + 1 + read-write + + + 0 + A restart condition is not generated. + #0 + + + 1 + A restart condition is generated. + #1 + + + + + IICSTAREQ + Start Condition Generation + 0 + 0 + read-write + + + 0 + A start condition is not generated. + #0 + + + 1 + A start condition is generated. + #1 + + + + + + + SISR + I2C Status Register + 0x0C + 8 + read-only + 0x00 + 0xCB + + + IICACKR + ACK Reception Data Flag + 0 + 0 + read-only + + + 0 + ACK received + #0 + + + 1 + NACK received + #1 + + + + + + + SPMR + SPI Mode Register + 0x0D + 8 + read-write + 0x00 + 0xFF + + + CKPH + Clock Phase Select + 7 + 7 + read-write + + + 0 + Clock is not delayed. + #0 + + + 1 + Clock is delayed. + #1 + + + + + CKPOL + Clock Polarity Select + 6 + 6 + read-write + + + 0 + Clock polarity is not inverted. + #0 + + + 1 + Clock polarity is inverted + #1 + + + + + MFF + Mode Fault Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No mode fault error + #0 + + + 1 + Mode fault error + #1 + + + + + MSS + Master Slave Select + 2 + 2 + read-write + + + 0 + Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). + #0 + + + 1 + Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). + #1 + + + + + CTSE + CTS Enable + 1 + 1 + read-write + + + 0 + CTS function is disabled (RTS output function is enabled). + #0 + + + 1 + CTS function is enabled. + #1 + + + + + SSE + SSn Pin Function Enable + 0 + 0 + read-write + + + 0 + SSn pin function is disabled. + #0 + + + 1 + SSn pin function is enabled. + #1 + + + + + + + TDRHL + Transmit 9-bit Data Register + 0x0E + 16 + read-write + 0xFFFF + 0xFFFF + + + TDRHL + TDRHL is a 16-bit register that stores transmit data. + 0 + 15 + write-only + + + + + FTDRHL + Transmit FIFO Data Register HL + TDRHL + 0x0E + 16 + write-only + 0xFFFF + 0xFFFF + + + MPBT + Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) + 9 + 9 + write-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + TDAT + Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 8 + write-only + + + + + FTDRH + Transmit FIFO Data Register H + TDRHL + 0x0E + 8 + write-only + 0xFF + 0xFF + + + MPBT + Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) + 1 + 1 + write-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + TDATH + Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 0 + write-only + + + + + FTDRL + Transmit FIFO Data Register L + TDRHL + 0x0F + 8 + write-only + 0xFF + 0xFF + + + TDATL + Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 7 + write-only + + + + + RDRHL + Receive 9-bit Data Register + 0x10 + 16 + read-only + 0x0000 + 0xFFFF + + + RDRHL + RDRHL is an 16-bit register that stores receive data. + 0 + 15 + read-only + + + + + FRDRHL + Receive FIFO Data Register HL + RDRHL + 0x10 + 16 + read-only + 0x0000 + 0xFFFF + + + RDF + Receive FIFO data full flag(It is same as SSR.RDF) + 14 + 14 + read-only + + + 0 + The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. + #0 + + + 1 + The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. + #1 + + + + + ORER + Overrun error flag(It is same as SSR.ORER) + 13 + 13 + read-only + + + 0 + No overrun error occurred. + #0 + + + 1 + An overrun error has occurred. + #1 + + + + + FER + Framing error flag + 12 + 12 + read-only + + + 0 + No framing error occurred at the first data of FRDRH and FRDRL. + #0 + + + 1 + A framing error has occurred at the first data of FRDRH and FRDRL. + #1 + + + + + PER + Parity error flag + 11 + 11 + read-only + + + 0 + No parity error occurred at the first data of FRDRH and FRDRL. + #0 + + + 1 + A parity error has occurred at the first data of FRDRH and FRDRL. + #1 + + + + + DR + Receive data ready flag(It is same as SSR.DR) + 10 + 10 + read-only + + + 0 + Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. + #0 + + + 1 + Next receive data has not been received for a period after normal completed receiving. + #1 + + + + + MPB + Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) + 9 + 9 + read-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + RDAT + Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 8 + read-only + + + + + FRDRH + Receive FIFO Data Register H + RDRHL + 0x10 + 8 + read-only + 0x00 + 0xFF + + + RDF + Receive FIFO data full flag(It is same as SSR.RDF) + 6 + 6 + read-only + + + 0 + The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. + #0 + + + 1 + The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. + #1 + + + + + ORER + Overrun error flag(It is same as SSR.ORER) + 5 + 5 + read-only + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + FER + Framing error flag + 4 + 4 + read-only + + + 0 + No framing error occurred at the first data of FRDRH and FRDRL + #0 + + + 1 + A framing error has occurred at the first data of FRDRH and FRDRL + #1 + + + + + PER + Parity error flag + 3 + 3 + read-only + + + 0 + No parity error occurred at the first data of FRDRH and FRDRL + #0 + + + 1 + A parity error has occurred at the first data of FRDRH and FRDRL + #1 + + + + + DR + Receive data ready flag(It is same as SSR.DR) + 2 + 2 + read-only + + + 0 + Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. + #0 + + + 1 + Next receive data has not been received for a period after normal completed receiving. + #1 + + + + + MPB + Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) + 1 + 1 + read-only + + + 0 + Data transmission cycles + #0 + + + 1 + ID transmission cycles + #1 + + + + + RDATH + Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 0 + read-only + + + + + FRDRL + Receive FIFO Data Register L + RDRHL + 0x11 + 8 + read-only + 0x00 + 0xFF + + + RDATL + Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. + 0 + 7 + read-only + + + + + MDDR + Modulation Duty Register + 0x12 + 8 + read-write + 0xFF + 0xFF + + + MDDR + MDDR corrects the bit rate adjusted by the BRR register. + 0 + 7 + read-write + + + + + DCCR + Data Compare Match Control Register + 0x13 + 8 + read-write + 0x40 + 0xFF + + + DCME + Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) + 7 + 7 + read-write + + + 0 + Address match function is disabled. + #0 + + + 1 + Address match function is enabled + #1 + + + + + IDSEL + ID frame select(Valid only in asynchronous mode(including multi-processor) + 6 + 6 + read-write + + + 0 + Always compare data regardless of the value of the MPB bit. + #0 + + + 1 + Compare data when the MPB bit is 1 (ID frame) only. + #1 + + + + + DFER + Data Compare Match Framing Error Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + No framing error occurred + #0 + + + 1 + A framing error has occurred + #1 + + + + + DPER + Data Compare Match Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurred + #0 + + + 1 + A parity error has occurred + #1 + + + + + DCMF + Data Compare Match Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No matched + #0 + + + 1 + Matched + #1 + + + + + + + FCR + FIFO Control Register + 0x14 + 16 + read-write + 0xF800 + 0xFFFF + + + RSTRG + RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 12 + 15 + read-write + + + 0000 + Trigger number 0 + #0000 + + + others + Triger number n (n= 0-15) + true + + + + + RTRG + Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 8 + 11 + read-write + + + 0000 + Trigger number 0 + #0000 + + + others + Triger number n (n= 0-15) + true + + + + + TTRG + Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 4 + 7 + read-write + + + 0000 + Trigger number 0 + #0000 + + + others + Triger number n (n= 0-15) + true + + + + + DRES + Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) + 3 + 3 + read-write + + + 0 + reception data full interrupt (RXI) + #0 + + + 1 + receive error interrupt (ERI) + #1 + + + + + TFRST + Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) + 2 + 2 + read-write + + + 0 + The number of data stored in FTDRH and FTDRL register are NOT made 0 + #0 + + + 1 + The number of data stored in FTDRH and FTDRL register are made 0 + #1 + + + + + RFRST + Receive FIFO Data Register Reset(Valid only in FCR.FM=1) + 1 + 1 + read-write + + + 0 + The number of data stored in FRDRH and FRDRL register are NOT made 0 + #0 + + + 1 + The number of data stored in FRDRH and FRDRL register are made 0 + #1 + + + + + FM + FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) + 0 + 0 + read-write + + + 0 + Non-FIFO mode(Selects o TDR/RDR for communication) + #0 + + + 1 + FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication) + #1 + + + + + + + FDR + FIFO Data Count Register + 0x16 + 16 + read-only + 0x0000 + 0xFFFF + + + T + Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) + 8 + 12 + read-only + + + R + Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) + 0 + 4 + read-only + + + + + LSR + Line Status Register + 0x18 + 16 + read-only + 0x0000 + 0xFFFF + + + PNUM + Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). + 8 + 12 + read-only + + + FNUM + Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). + 2 + 6 + read-only + + + ORER + Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) + 0 + 0 + read-only + + + 0 + No overrun error occurred + #0 + + + 1 + An overrun error has occurred + #1 + + + + + + + CDR + Compare Match Data Register + 0x1A + 16 + read-write + 0x0000 + 0xFFFF + + + CMPD + Compare Match DataCompare data pattern for address match wake-up function + 0 + 8 + read-write + + + + + SPTR + Serial Port Register + 0x1C + 8 + read-write + 0x03 + 0xFF + + + SPB2IO + Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) + 2 + 2 + read-write + + + 0 + The value of SPB2DT bit is not output in TXD pin. + #0 + + + 1 + The value of SPB2DT bit is output in TXD pin. + #1 + + + + + SPB2DT + Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) + 1 + 1 + read-write + + + 0 + Low level is output on TXD pin + #0 + + + 1 + High level is output on TXD pin + #1 + + + + + RXDMON + Serial input data monitor bit(The state of the RXD terminal is shown.) + 0 + 0 + read-only + + + 0 + RXD pin is low. + #0 + + + 1 + RXD pin is high. + #1 + + + + + RINV + RXD invert bit + 4 + 4 + read-write + + + 0 + Received data from RXD is not inverted and input. + #0 + + + 1 + Received data from RXD is inverted and input. + #1 + + + + + TINV + TXD invert bit + 5 + 5 + read-write + + + 0 + Transmit data is not inverted and output to TXD. + #0 + + + 1 + Transmit data is inverted and output to TXD. + #1 + + + + + ASEN + Adjust receive sampling timing enable + 6 + 6 + read-write + + + 0 + Adjust sampling timing disable. + #0 + + + 1 + Adjust sampling timing enable. + #1 + + + + + ATEN + Adjust transmit timing enable + 7 + 7 + read-write + + + 0 + Adjust transmit timing disable. + #0 + + + 1 + Adjust transmit timing enable. + #1 + + + + + + + ACTR + Adjustment Communication Timing Register + 0x1D + 8 + read-write + 0x00 + 0xff + + + AST + Adjustment value for receive Sampling Timing + 0 + 2 + read-write + + + AJD + Adjustment Direction for receive sampling timing + 3 + 3 + read-write + + + 0 + The sampling timing is adjusted backward to the middle of bit. + #0 + + + 1 + The sampling timing is adjusted forward to the middle of bit. + #1 + + + + + ATT + Adjustment value for Transmit timing + 4 + 6 + read-write + + + AET + Adjustment edge for transmit timing + 7 + 7 + read-write + + + 0 + Adjust the rising edge timing. + #0 + + + 1 + Adjust the falling edge timing. + #1 + + + + + + + ESMER + Extended Serial Module Enable Register + 0x20 + 8 + read-write + 0x00 + 0xff + + + ESME + Extended Serial Mode Enable + 0 + 0 + read-write + + + 0 + The extended serial mode is disabled. + #0 + + + 1 + The extended serial mode is enabled. + #1 + + + + + + + CR0 + Control Register 0 + 0x21 + 8 + read-write + 0x00 + 0xff + + + SFSF + Start Frame Status Flag + 1 + 1 + read-only + + + 0 + Start Frame detection function is disabled. + #0 + + + 1 + Start Frame detection function is enabled. + #1 + + + + + RXDSF + RXDXn Input Status Flag + 2 + 2 + read-only + + + 0 + RXDXn input is enabled. + #0 + + + 1 + RXDXn input is disabled. + #1 + + + + + BRME + Bit Rate Measurement Enable + 3 + 3 + read-write + + + 0 + Measurement of bit rate is disabled. + #0 + + + 1 + Measurement of bit rate is enabled. + #1 + + + + + + + CR1 + Control Register 1 + 0x22 + 8 + read-write + 0x00 + 0xff + + + BFE + Break Field Enable + 0 + 0 + read-write + + + 0 + Break Field detection is disabled. + #0 + + + 1 + Break Field detection is enabled. + #1 + + + + + CF0RE + Control Field 0 Reception Enable + 1 + 1 + read-write + + + 0 + Reception of Control Field 0 is disabled. + #0 + + + 1 + Reception of Control Field 0 is enabled. + #1 + + + + + CF1DS + Control Field 1 Data Register Select + 2 + 3 + read-write + + + 00 + Selects comparison with the value in PCF1DR. + #00 + + + 01 + Selects comparison with the value in SCF1DR. + #01 + + + 10 + Selects comparison with the values in PCF1DR and SCF1DR. + #10 + + + 11 + Setting prohibited. + #11 + + + + + PIBE + Priority Interrupt Bit Enable + 4 + 4 + read-write + + + 0 + The priority interrupt bit is disabled. + #0 + + + 1 + The priority interrupt bit is enabled. + #1 + + + + + PIBS + Priority Interrupt Bit Select + 5 + 7 + read-write + + + 000 + 0th bit of Control Field 1 + #000 + + + 001 + 1st bit of Control Field 1 + #001 + + + 010 + 2nd bit of Control Field 1 + #010 + + + 011 + 3rd bit of Control Field 1 + #011 + + + 100 + 4th bit of Control Field 1 + #100 + + + 101 + 5th bit of Control Field 1 + #101 + + + 110 + 6th bit of Control Field 1 + #110 + + + 111 + 7th bit of Control Field 1 + #111 + + + + + + + CR2 + Control Register 2 + 0x23 + 8 + read-write + 0x00 + 0xff + + + DFCS + RXDXn Signal Digital Filter Clock Select + 0 + 2 + read-write + + + 000 + Filter is disabled. + #000 + + + 001 + Filter clock is SCI base clock + #001 + + + 010 + Filter clock is PCLK/8 + #010 + + + 011 + Filter clock is PCLK/16 + #011 + + + 100 + Filter clock is PCLK/32 + #100 + + + 101 + Filter clock is PCLK/64 + #101 + + + 110 + Filter clock is PCLK/128 + #110 + + + 111 + Setting prohibited + #111 + + + + + BCCS + Bus Collision Detection Clock Select + 4 + 5 + read-write + + + 00 + SCI base clock + #00 + + + 01 + SCI base clock frequency divided by 2 + #01 + + + 10 + SCI base clock frequency divided by 4 + #10 + + + 11 + Setting prohibited + #11 + + + + + RTS + RXDXn Reception Sampling Timing Select + 6 + 7 + read-write + + + 00 + Rising edge of the 8th cycle of SCI base clock + #00 + + + 01 + Rising edge of the 10th cycle of SCI base clock + #01 + + + 10 + Rising edge of the 12th cycle of SCI base clock + #10 + + + 11 + Rising edge of the 14th cycle of SCI base clock + #11 + + + + + + + CR3 + Control Register 3 + 0x24 + 8 + read-write + 0x00 + 0xff + + + SDST + Start Frame Detection Start + 0 + 0 + read-write + + + 0 + Detection of Start Frame is not performed. + #0 + + + 1 + Detection of Start Frame is performed. + #1 + + + + + + + PCR + Port Control Register + 0x25 + 8 + read-write + 0x00 + 0xff + + + TXDXPS + TXDXn Signal Polarity Select + 0 + 0 + read-write + + + 0 + The polarity of TXDXn signal is not inverted for output. + #0 + + + 1 + The polarity of TXDXn signal is inverted for output. + #1 + + + + + RXDXPS + RXDXn Signal Polarity Select + 1 + 1 + read-write + + + 0 + The polarity of RXDXn signal is not inverted for input. + #0 + + + 1 + The polarity of RXDXn signal is inverted for input. + #1 + + + + + SHARPS + TXDXn/RXDXn Pin Multiplexing Select + 4 + 4 + read-write + + + 0 + The TXDXn and RXDXn pins are independent. + #0 + + + 1 + The TXDXn and RXDXn signals are multiplexed on the same pin. + #1 + + + + + + + ICR + Interrupt Control Register + 0x26 + 8 + read-write + 0x00 + 0xff + + + BFDIE + Break Field Low Width Detected Interrupt Enable + 0 + 0 + read-write + + + 0 + Interrupts on detection of the low width for a Break Field are disabled. + #0 + + + 1 + Interrupts on detection of the low width for a Break Field are enabled. + #1 + + + + + CF0MIE + Control Field 0 Match Detected Interrupt Enable + 1 + 1 + read-write + + + 0 + Interrupts on detection of a match with Control Field 0 are disabled. + #0 + + + 1 + Interrupts on detection of a match with Control Field 0 are enabled. + #1 + + + + + CF1MIE + Control Field 1 Match Detected Interrupt Enable + 2 + 2 + read-write + + + 0 + Interrupts on detection of a match with Control Field 1 are disabled. + #0 + + + 1 + Interrupts on detection of a match with Control Field 1 are enabled. + #1 + + + + + PIBDIE + Priority Interrupt Bit Detected Interrupt Enable + 3 + 3 + read-write + + + 0 + Interrupts on detection of the priority interrupt bit are disabled. + #0 + + + 1 + Interrupts on detection of the priority interrupt bit are enabled. + #1 + + + + + BCDIE + Bus Collision Detected Interrupt Enable + 4 + 4 + read-write + + + 0 + Interrupts on detection of a bus collision are disabled. + #0 + + + 1 + Interrupts on detection of a bus collision are enabled. + #1 + + + + + AEDIE + Valid Edge Detected Interrupt Enable + 5 + 5 + read-write + + + 0 + Interrupts on detection of a valid edge are disabled. + #0 + + + 1 + Interrupts on detection of a valid edge are enabled. + #1 + + + + + + + STR + Status Register + 0x27 + 8 + read-only + 0x00 + 0xff + + + BFDF + Break Field Low Width Detection Flag + 0 + 0 + read-only + + + CF0MF + Control Field 0 Match Flag + 1 + 1 + read-only + + + CF1MF + Control Field 1 Match Flag + 2 + 2 + read-only + + + PIBDF + Priority Interrupt Bit Detection Flag + 3 + 3 + read-only + + + BCDF + Bus Collision Detected Flag + 4 + 4 + read-only + + + AEDF + Valid Edge Detection Flag + 5 + 5 + read-only + + + + + STCR + Status Clear Register + 0x28 + 8 + read-write + 0x00 + 0xff + + + BFDCL + BFDF Clear + 0 + 0 + read-write + + + CF0MCL + CF0MF Clear + 1 + 1 + read-write + + + CF1MCL + CF1MF Clear + 2 + 2 + read-write + + + PIBDCL + PIBDF Clear + 3 + 3 + read-write + + + BCDCL + BCDF Clear + 4 + 4 + read-write + + + AEDCL + AEDF Clear + 5 + 5 + read-write + + + + + CF0DR + Control Field 0 Data Register + 0x29 + 8 + read-write + 0x00 + 0xff + + + CF0CR + Control Field 0 Compare Enable Register + 0x2A + 8 + read-write + 0x00 + 0xff + + + CF0CE0 + Control Field 0 Bit 0 Compare Enable + 0 + 0 + read-write + + + 0 + Comparison with bit 0 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 0 of Control Field 0 is enabled. + #1 + + + + + CF0CE1 + Control Field 1 Bit 0 Compare Enable + 1 + 1 + read-write + + + 0 + Comparison with bit 1 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 1 of Control Field 0 is enabled. + #1 + + + + + CF0CE2 + Control Field 2 Bit 0 Compare Enable + 2 + 2 + read-write + + + 0 + Comparison with bit 2 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 2 of Control Field 0 is enabled. + #1 + + + + + CF0CE3 + Control Field 3 Bit 0 Compare Enable + 3 + 3 + read-write + + + 0 + Comparison with bit 3 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 3 of Control Field 0 is enabled. + #1 + + + + + CF0CE4 + Control Field 4 Bit 0 Compare Enable + 4 + 4 + read-write + + + 0 + Comparison with bit 4 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 4 of Control Field 0 is enabled. + #1 + + + + + CF0CE5 + Control Field 5 Bit 0 Compare Enable + 5 + 5 + read-write + + + 0 + Comparison with bit 5 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 5 of Control Field 0 is enabled. + #1 + + + + + CF0CE6 + Control Field 6 Bit 0 Compare Enable + 6 + 6 + read-write + + + 0 + Comparison with bit 6 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 6 of Control Field 0 is enabled. + #1 + + + + + CF0CE7 + Control Field 7 Bit 0 Compare Enable + 7 + 7 + read-write + + + 0 + Comparison with bit 7 of Control Field 0 is disabled. + #0 + + + 1 + Comparison with bit 7 of Control Field 0 is enabled. + #1 + + + + + + + CF0RR + Control Field 0 Receive Data Register + 0x2B + 8 + read-write + 0x00 + 0xff + + + PCF1DR + Primary Control Field 1 Data Register + 0x2C + 8 + read-write + 0x00 + 0xff + + + SCF1DR + Secondary Control Field 1 Data Register + 0x2D + 8 + read-write + 0x00 + 0xff + + + CF1CR + Control Field 1 Compare Enable Register + 0x2E + 8 + read-write + 0x00 + 0xff + + + CF1CE0 + Control Field 1 Bit 0 Compare Enable + 0 + 0 + read-write + + + 0 + Comparison with bit 0 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 0 of Control Field 1 is enabled. + #1 + + + + + CF1CE1 + Control Field 1 Bit 1 Compare Enable + 1 + 1 + read-write + + + 0 + Comparison with bit 1 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 1 of Control Field 1 is enabled. + #1 + + + + + CF1CE2 + Control Field 1 Bit 2 Compare Enable + 2 + 2 + read-write + + + 0 + Comparison with bit 2 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 2 of Control Field 1 is enabled. + #1 + + + + + CF1CE3 + Control Field 1 Bit 3 Compare Enable + 3 + 3 + read-write + + + 0 + Comparison with bit 3 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 3 of Control Field 1 is enabled. + #1 + + + + + CF1CE4 + Control Field 1 Bit 4 Compare Enable + 4 + 4 + read-write + + + 0 + Comparison with bit 4 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 4 of Control Field 1 is enabled. + #1 + + + + + CF1CE5 + Control Field 1 Bit 5 Compare Enable + 5 + 5 + read-write + + + 0 + Comparison with bit 5 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 5 of Control Field 1 is enabled. + #1 + + + + + CF1CE6 + Control Field 1 Bit 6 Compare Enable + 6 + 6 + read-write + + + 0 + Comparison with bit 6 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 6 of Control Field 1 is enabled. + #1 + + + + + CF1CE7 + Control Field 1 Bit 7 Compare Enable + 7 + 7 + read-write + + + 0 + Comparison with bit 7 of Control Field 1 is disabled. + #0 + + + 1 + Comparison with bit 7 of Control Field 1 is enabled. + #1 + + + + + + + CF1RR + Control Field 1 Receive Data Register + 0x2F + 8 + read-write + 0x00 + 0xff + + + TCR + Timer Control Register + 0x30 + 8 + read-write + 0x00 + 0xff + + + TCST + Timer Count Start + 0 + 0 + read-write + + + 0 + Stops the timer counting + #0 + + + 1 + Starts the timer counting + #1 + + + + + + + TMR + Timer Mode Register + 0x31 + 8 + read-write + 0x00 + 0xff + + + TOMS + Timer Operating Mode Select + 0 + 1 + read-write + + + 00 + Timer mode + #00 + + + 01 + Break Field low width determination mode + #01 + + + 10 + Break Field low width output mode + #10 + + + 11 + Setting prohibited + #11 + + + + + TWRC + Counter Write Control + 3 + 3 + read-write + + + 0 + Data is written to the reload register and counter + #0 + + + 1 + Data is written to the reload register only + #1 + + + + + TCSS + Timer Count Clock Source Select + 4 + 6 + read-write + + + 000 + PCLK + #000 + + + 001 + PCLK/2 + #001 + + + 010 + PCLK/4 + #010 + + + 011 + PCLK/8 + #011 + + + 100 + PCLK/16 + #100 + + + 101 + PCLK/32 + #101 + + + 110 + PCLK/64 + #110 + + + 111 + PCLK/128 + #111 + + + + + + + TPRE + Timer Prescaler Register + 0x32 + 8 + read-write + 0xff + 0xff + + + TCNT + Timer Count Register + 0x33 + 8 + read-write + 0xff + 0xff + + + + + R_SCI1 + 0x40070020 + + + R_SCI2 + 0x40070040 + + + R_SCI3 + 0x40070060 + + + R_SCI4 + 0x40070080 + + + R_SCI5 + 0x400700A0 + + + R_SCI6 + 0x400700C0 + + + R_SCI7 + 0x400700E0 + + + R_SCI8 + 0x40070100 + + + R_SCI9 + 0x40070120 + + + R_SDADC0 + + 0x4009C000 + + 0x00000000 + 0x02 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x019 + registers + + + 0x00000024 + 0x008 + registers + + + 0x00000030 + 0x01 + registers + + + 0x00000034 + 0x01 + registers + + + 0x0000003C + 0x01 + registers + + + + STC1 + Startup Control Register 1 + 0x0 + 16 + read-write + 0XFFFF + + + VSBIAS + Reference voltage select + 8 + 11 + read-write + + + 0000 + 0.8V + #0000 + + + 0001 + 1.0V + #0001 + + + 0010 + 1.2V + #0010 + + + 0011 + 1.4V + #0011 + + + 0100 + 1.6V + #0100 + + + 0101 + 1.8V + #0101 + + + 0110 + 2.0V + #0110 + + + 0111 + 2.2V + #0111 + + + 1111 + 2.4V(only available when VREFSEL=0) + #1111 + + + + + CLKDIV + SDADC24 Reference Clock Division + 0 + 3 + read-write + + + 0000 + No Division + #0000 + + + 0001 + SDADCCLK/2 + #0001 + + + 0010 + SDADCCLK/3 + #0010 + + + 0011 + SDADCCLK/4 + #0011 + + + 0100 + SDADCCLK/5 + #0100 + + + 0101 + SDADCCLK/6 + #0101 + + + 0110 + SDADCCLK/8 + #0110 + + + 0111 + SDADCCLK/12 + #0111 + + + 1000 + SDADCCLK/16 + #1000 + + + + + SDADLPM + A/D conversion operation model select + 7 + 7 + read-write + + + 0 + Normal A/D conversion mode, SDADC Reference Clock: 4 MHz, Oversampingly clock: 1MHz + #0 + + + + + VREFSEL + VREF mode select + 15 + 15 + read-write + + + 0 + Internal VREF Mode + #0 + + + + + + + STC2 + Startup Control Register 2 + 0x04 + 8 + read-write + 0x00 + 0xFF + + + BGRPON + BGR part power control + 0 + 0 + + + 0 + Turn off power to ADBGR, SBIAS, VREFI, and ADREG + #0 + + + 1 + Turn onpower to ADBGR, SBIAS, VREFI, and ADREG + #1 + + + + + ADFPWDS + ADC reference supply part + 2 + 2 + + + 0 + Power of ADREG controlled by BGRPON register + #0 + + + 1 + Power of ADREG is off regardless of BGRPON setting + #1 + + + + + ADCPON + ADREG forced power-down + 1 + 1 + + + 0 + Turn off power to VBIAS, PGA and sigma-delta A/D converter + #0 + + + 1 + Turn on power to VBIAS, PGA and sigma-delta A/D converter + #1 + + + + + + + 5 + 4 + PGAC[%s] + Input Multiplexer %s Setting Register + 0x08 + 32 + read-write + 0x00010040 + 0xFFFFFFFF + + + PGAASN + Selection of the mode for specifying the number of A/D conversions in ADSCAN + 31 + 31 + read-write + + + 0 + Specify 1 to 8,032 times by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits + #0 + + + 1 + Specify 1 to 255 times linearly by using the value set in the PGACTN[2:0] and PGACTM[4:0] bits + #1 + + + + + PGACVE + Calibration enable + 30 + 30 + read-write + + + 0 + Do not calculate the calibration correction factor + #0 + + + 1 + Calculate the calibration correction factor + #1 + + + + + PGAREV + Single-End Input A/D Converted Data Inversion Select + 28 + 28 + read-write + + + 0 + Do not invert the conversion result data + #0 + + + 1 + Invert the conversion result data + #1 + + + + + PGAAVE + Selection of averaging processing + 26 + 27 + read-write + + + 00 + Do not average the A/D conversion results + #00 + + + 01 + Do not average the A/D conversion results + #01 + + + 10 + Average the A/D conversion results and generates SDADC_ADI each time an A/D conversion occurs + #10 + + + 11 + Perform averaging, and generate SDADC_ADI at each time of average value output (A/D conversion is performed N times). + #11 + + + + + PGAAVN + Selection of the number of data to be averaged + 24 + 25 + read-write + + + 00 + 8 + #00 + + + 01 + 16 + #01 + + + 10 + 32 + #10 + + + 11 + 64 + #11 + + + + + PGACTN + Coefficient (n) selection of the A/D conversion count (N) in AUTOSCAN + 21 + 23 + read-write + + + 000 + 0 + #000 + + + 001 + 1 + #001 + + + 010 + 2 + #010 + + + 011 + 3 + #011 + + + 100 + 4 + #100 + + + 101 + 5 + #101 + + + 110 + 6 + #110 + + + 111 + 7 + #111 + + + + + PGACTM + Coefficient (m) selection of the A/D conversion count (N) in AUTOSCAN + 16 + 20 + read-write + + + PGASEL + Analog Channel Input Mode Select + 15 + 15 + read-write + + + 0 + Differential input mode + #0 + + + 1 + Single-end input mode + #1 + + + + + PGAPOL + Polarity select + 14 + 14 + read-write + + + 0 + Positive-side single-end input + #0 + + + 1 + Negative-side single-end input + #1 + + + + + PGAOFS + Offset voltage select + 8 + 12 + read-write + + + PGAOSR + Oversampling ratio select + 5 + 7 + read-write + + + 000 + 64 + #000 + + + 001 + 128 + #001 + + + 010 + 256 + #010 + + + 011 + 512 + #011 + + + 100 + 1024 + #100 + + + 101 + 2048 + #101 + + + others + Settings are prohibited. + true + + + + + PGAGC + Gain selection of a programmable gain instrumentation amplifier ( Gset1, Gset2, Gtotal ) + 0 + 4 + read-write + + + 00000 + (1, 1, 1) + #00000 + + + 00100 + (2, 1, 2) + #00100 + + + 01000 + (3, 1, 3) + #01000 + + + 01100 + (4, 1, 4) + #01100 + + + 10000 + (8, 1, 8) + #10000 + + + 00001 + (1, 2, 2) + #00001 + + + 00101 + (2, 2, 4) + #00101 + + + 01001 + (3, 2, 6) + #01001 + + + 01101 + (4, 2, 8) + #01101 + + + 10001 + (8, 2, 16) + #10001 + + + 00010 + (1, 4, 4) + #00010 + + + 00110 + (2, 4, 8) + #00110 + + + 01010 + (3, 4, 12) + #01010 + + + 01110 + (4, 4, 16) + #01110 + + + 10010 + (8, 4, 32) + #10010 + + + 00011 + (1, 8, 8) + #00011 + + + 00111 + (2, 8, 16) + #00111 + + + 01011 + (3, 8, 24) + #01011 + + + 01111 + (4, 8, 32). + #01111 + + + others + Settings are prohibited. + true + + + + + + + ADC1 + Sigma-Delta A/D Converter Control Register 1 + 0x1C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + PGASLFT + PGA offset self-diagnosis enable + 20 + 20 + read-write + + + 0 + Disable PGA offset self-diagnosis + #0 + + + 1 + Enable PGA offset self-diagnosis + #1 + + + + + PGADISC + Disconnection Detection Assist Setting + 17 + 17 + read-write + + + 0 + Discharge + #0 + + + 1 + Pre-charge + #1 + + + + + PGADISA + Control of disconnection detection + 16 + 16 + read-write + + + 0 + Normal operation + #0 + + + 1 + State of disconnection detection + #1 + + + + + SDADBMP + A/D conversion control of the signal from input multiplexer + 8 + 12 + read-write + + + SDADTMD + Selection of A/D conversion trigger signal + 4 + 4 + read-write + + + 0 + Software trigger (conversion is started by a write to SFR) + #0 + + + 1 + Hardware trigger (conversion is started in synchronization with the event signal selected by ELC_SDADC24). + #1 + + + + + SDADSCM + Selection of autoscan mode + 0 + 0 + read-write + + + 0 + Continuous scan mode + #0 + + + 1 + Single scan mode + #1 + + + + + + + ADC2 + Sigma-Delta A/D Converter Control Register 2 + 0x20 + 8 + read-write + 0x00 + 0xFF + + + SDADST + Control of A/D conversion + 0 + 0 + read-write + + + 0 + Stop A/D conversion + #0 + + + 1 + Start A/D conversion + #1 + + + + + + + ADCR + Sigma-delta A/D Converter Conversion Result Register + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SDADCRC + Channel number for an A/D conversion result + 25 + 27 + read-only + + + 000 + Reset value (Conversion result is invalid) + #000 + + + 001 + Input multiplexer 0 (ANSD0P / ANSD0N) + #001 + + + 010 + Input multiplexer 1 (ANSD1P / ANSD1N) + #010 + + + 011 + Input multiplexer 2 (ANSD2P / ANSD2N) + #011 + + + 100 + Input multiplexer 3 (ANSD3P / ANSD3N) + #100 + + + 101 + Input multiplexer 4 (AMP0O / AMP1O) + #101 + + + + + SDADCRS + Status of an A/D conversion result + 24 + 24 + read-only + + + 0 + Normal status (within the range) + #0 + + + 1 + Overflow occurred + #1 + + + + + SDADCRD + The 24-bit A/D conversion result + 0 + 23 + read-only + + + + + ADAR + Sigma-delta A/D Converter Average Value Register + 0x28 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SDADMVC + Channel number for an A/D conversion result + 25 + 27 + read-only + + + 000 + Reset value (Conversion result is invalid) + #000 + + + 001 + Input multiplexer 0 (ANSD0P / ANSD0N) + #001 + + + 010 + Input multiplexer 1 (ANSD1P / ANSD1N) + #010 + + + 011 + Input multiplexer 2 (ANSD2P / ANSD2N) + #011 + + + 100 + Input multiplexer 3 (ANSD3P / ANSD3N) + #100 + + + 101 + Input multiplexer 4 (AMP0O / AMP1O). + #101 + + + + + SDADMVS + Status of an A/D conversion result + 24 + 24 + read-only + + + 0 + Normal status (within the range) + #0 + + + 1 + Overflow occurred + #1 + + + + + SDADMVD + The 24-bit A/D average value + 0 + 23 + read-only + + + + + CLBC + Calibration Control Register + 0x30 + 8 + 0x00 + 0xFF + + + CLBMD + These bits are read as 0. The write value should be 0. + 0 + 1 + read-write + + + 00 + Internal calibration mode + #00 + + + 01 + External offset calibration mode + #01 + + + 10 + External gain calibration mode + #10 + + + 11 + Settings are prohibited + #11 + + + + + + + CLBSTR + Calibration Start Control Register + 0x34 + 8 + read-write + 0x00 + 0xFF + + + CLBST + Calibration start control + 0 + 0 + read-write + + + 0 + Disable writing + #0 + + + 1 + Start calibration + #1 + + + + + + + CLBSSR + Calibration Status Register + 0x3C + 8 + read-only + 0x00 + + + CLBSS + Calibration status + 0 + 0 + read-only + + + 0 + Calibration is not running + #0 + + + 1 + Calibration is running + #1 + + + + + + + + + R_SDHI0 + SD/MMC Host Interface + 0x40062000 + + 0x00000000 + 0x04 + registers + + + 0x00000008 + 0x04C + registers + + + 0x00000058 + 0x00C + registers + + + 0x00000068 + 0x00C + registers + + + 0x000001B0 + 0x04 + registers + + + 0x000001C0 + 0x04 + registers + + + 0x000001CC + 0x04 + registers + + + 0x000001E0 + 0x04 + registers + + + + SD_CMD + Command Type Register + 0x000 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CMD12AT + Multiple Block Transfer Mode (enabled at multiple block transfer) + 14 + 15 + read-write + + + 00 + CMD12 is automatically issued at multiple block transfer. + #00 + + + 01 + CMD12 is not automatically issued at multiple block transfer. + #01 + + + 10 + Setting prohibited + #10 + + + 11 + Setting prohibited + #11 + + + + + TRSTP + Single/Multiple Block Transfer (enabled when the command with data is handled) + 13 + 13 + read-write + + + 0 + Single block transfer + #0 + + + 1 + Multiple block transfer + #1 + + + + + CMDRW + Write/Read Mode (enabled when the command with data is handled) + 12 + 12 + read-write + + + 0 + Write (SD/MMC host interface -> SD card/MMC) + #0 + + + 1 + Read (SD/MMC host interface <- SD card/MMC) + #1 + + + + + CMDTP + Data Mode (Command Type) + 11 + 11 + read-write + + + 0 + Command does not include data transfer (bc, bcr, or ac) + #0 + + + 1 + Command includes data transfer (adtc) + #1 + + + + + RSPTP + Mode/Response TypeNOTE: As some commands cannot be used in normal mode, see section 1.4.10, Example of SD_CMD Register Setting to select mode/response type. + 8 + 10 + read-write + + + 000 + Normal mode The response type and the transfer mode are selected by SD_CMD[7:0], and the SD_CMD[15:11] setting is disabled. + #000 + + + 011 + Expansion mode and no response + #011 + + + 100 + Expansion mode and R1, R5, R6, or R7 response + #100 + + + 101 + Expansion mode and R1b response + #101 + + + 110 + Expansion mode and R2 response + #110 + + + 111 + Expansion mode and R3 or R4 response + #111 + + + others + Settings prohibited. + true + + + + + ACMD + Command Type Select + 6 + 7 + read-write + + + 00 + CMD + #00 + + + 01 + ACMD + #01 + + + others + Setting prohibited + true + + + + + CMDIDX + Command IndexThese bits specify Command Format[45:40] (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 + 0 + 5 + read-write + + + + + SD_ARG + SD Command Argument Register + 0x008 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SD_ARG + Argument RegisterSet command format[39:8] (argument) + 0 + 31 + read-write + + + + + SD_ARG1 + SD Command Argument Register 1 + 0x00C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SD_ARG1 + Argument Register 1Set command format[39:24] (argument) + 0 + 15 + read-write + + + + + SD_STOP + Data Stop Register + 0x010 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SEC + Block Count EnableSet SEC to 1 at multiple block transfer.When SD_CMD is set as follows to start the command sequence while SEC is set to 1, CMD12 is automatically issued to stop multi-block transfer with the number of blocks which is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is automatically issued, multiple block transfer)When the command sequence is halted because of a communications error or timeout, CMD12 is not automatically issued.NOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. + 8 + 8 + read-write + + + 0 + Disables SD_SECCNT setting value. + #0 + + + 1 + Enables SD_SECCNT setting value. + #1 + + + + + STP + Stop- When STP is set to 1 during multiple block transfer, CMD12 is issued to halt the transfer through the SD host interface.However, if a command sequence is halted because of a communications error or timeout, CMD12 is not issued. Although continued buffer access is possible even after STP has been set to 1, the buffer access error bit (ERR5 or ERR4) in SD_INFO2 will be set accordingly.- When STP has been set to 1 during transfer for single block write, the access end flag is set when SD_BUF becomes empty, and CMD12 is not issued. If SD_BUF does contain data, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP has been set to 1 during transfer for single block read, the access end flag is set immediately after setting of the STP bit and CMD12 is not issued.- When STP is set to 1 during reception of the busy state after an R1b response, the access end flag is set on completion of reception of the busy state without CMD12 having been issued.- When STP is set to 1 after a command sequence has been completed, CMD12 is not issued and the access end flag is not set.- Set STP to 1 after the response end flag has been set.- Set STP to 0 after the response end flag has been set. + 0 + 0 + read-write + + + + + SD_SECCNT + Block Count Register + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SD_SECCNT + Number of Transfer BlocksNOTE: Do not change the value of this bit when the CBSY bit in SD_INFO2 is set to 1. + 0 + 31 + read-write + + + + + SD_RSP10 + SD Card Response Register 10 + 0x018 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP10 + Store the response from the SD card/MMC + 0 + 31 + read-only + + + + + SD_RSP1 + SD Card Response Register 1 + 0x01C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP1 + Store the response from the SD card/MMC + 0 + 15 + read-only + + + + + SD_RSP32 + SD Card Response Register 32 + 0x020 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP32 + Store the response from the SD card/MMC + 0 + 31 + read-only + + + + + SD_RSP3 + SD Card Response Register 3 + 0x024 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP3 + Store the response from the SD card/MMC + 0 + 15 + read-only + + + + + SD_RSP54 + SD Card Response Register 54 + 0x028 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP54 + Store the response from the SD card/MMC + 0 + 31 + read-only + + + + + SD_RSP5 + SD Card Response Register 5 + 0x02C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP5 + Store the response from the SD card/MMC + 0 + 15 + read-only + + + + + SD_RSP76 + SD Card Response Register 76 + 0x030 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP76 + Store the response from the SD card/MMC + 0 + 23 + read-only + + + + + SD_RSP7 + SD Card Response Register 7 + 0x034 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SD_RSP7 + Store the response from the SD card/MMC + 0 + 7 + read-only + + + + + SD_INFO1 + SD Card Interrupt Flag Register 1 + 0x038 + 32 + read-write + 0x00000000 + 0xFFFFFB5F + + + SDD3MON + Inticates the SDnDAT3 State + 10 + 10 + read-only + + + 0 + SDnDAT3 is set to 0. + #0 + + + 1 + SDnDAT3 is set to 1. + #1 + + + + + SDD3IN + SDnDAT3 Card Insertion + 9 + 9 + read-write + zeroToClear + modify + + + 0 + SD card insertion not detected + #0 + + + 1 + SD card insertion detected + #1 + + + + + SDD3RM + SDnDAT3 Card Removal + 8 + 8 + read-write + zeroToClear + modify + + + 0 + SD card removal not detected + #0 + + + 1 + SD card removal detected + #1 + + + + + SDWPMON + Indicates the SDnWP state + 7 + 7 + read-only + + + 0 + SDnWP is set to 1. + #0 + + + 1 + SDnWP is set to 0. + #1 + + + + + SDCDMON + Indicates the SDnCD state + 5 + 5 + read-only + + + 0 + Indicates that Mcycle has elapsed with SDnCD held 1.(Mcycle is set by bits 3 to 0 in SD_OPTION.) + #0 + + + 1 + Indicates that Mcycle has elapsed with SDnCD held 0. (Mcycle is set by bits 3 to 0 in SD_OPTION.) + #1 + + + + + SDCDIN + SDnCD Card Insertion + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Card insertion not detected + #0 + + + 1 + Card insertion detected + #1 + + + + + SDCDRM + SDnCD Card Removal + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Card removal not detected + #0 + + + 1 + Card removal detected + #1 + + + + + ACEND + Access End + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Access end is not detected + #0 + + + 1 + Access end is detected + #1 + + + + + RSPEND + Response End Detection + 0 + 0 + read-write + + + 0 + Response end is not detected + #0 + + + 1 + Response end is detected + #1 + + + + + + + SD_INFO2 + SD Card Interrupt Flag Register 2 + 0x03C + 32 + read-write + 0x00002000 + 0xFFFFFF7F + + + ILA + Illegal Access Error + 15 + 15 + read-write + zeroToClear + modify + + + 0 + Illegal access error not detected + #0 + + + 1 + Illegal access error detected + #1 + + + + + CBSY + Command Type Register Busy + 14 + 14 + read-only + + + 0 + A command sequence is being executed. + #0 + + + 1 + A command sequence has been completed. + #1 + + + + + SD_CLK_CTRLEN + When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence. + 13 + 13 + read-only + + + 0 + The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible. + #0 + + + 1 + The SD/MMC bus (CMD, DAT) is not busy. + #1 + + + + + BWE + SD_BUF Write Enable + 9 + 9 + read-write + zeroToClear + modify + + + 1 + Data can be written in SD_BUF0. + #1 + + + 0 + Data cannot be written in SD_BUF0. + #0 + + + + + BRE + SD_BUF Read Enable + 8 + 8 + read-write + zeroToClear + modify + + + 1 + Data can be read from SD_BUF0. + #1 + + + 0 + Data cannot be read from SD_BUF0. + #0 + + + + + SDD0MON + SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL. + 7 + 7 + read-only + + + 1 + SDDAT0 is set to 1. + #1 + + + 0 + SDDAT0 is set to 0. + #0 + + + + + RSPTO + Response Timeout + 6 + 6 + read-write + zeroToClear + modify + + + 0 + Response timeout not detected + #0 + + + 1 + Response timeout detected + #1 + + + + + ILR + SD_BUF Illegal Read Access + 5 + 5 + read-write + zeroToClear + modify + + + 0 + Illegal read access to the SD_BUF register not detected + #0 + + + 1 + Illegal read access to the SD_BUF register detected + #1 + + + + + ILW + SD_BUF Illegal Write Access + 4 + 4 + read-write + zeroToClear + modify + + + 0 + Illegal write access to the SD_BUF register not detected + #0 + + + 1 + Illegal write access to the SD_BUF register detected + #1 + + + + + DTO + Data Timeout + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Data timeout not detected + #0 + + + 1 + Data timeout detected + #1 + + + + + ENDE + END Error + 2 + 2 + read-write + zeroToClear + modify + + + 0 + End bit error not detected + #0 + + + 1 + End bit error detected + #1 + + + + + CRCE + CRC Error + 1 + 1 + read-write + zeroToClear + modify + + + 0 + CRC error not detected + #0 + + + 1 + CRC error detected + #1 + + + + + CMDE + Command Error + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Command error not detected + #0 + + + 1 + Command error detected + #1 + + + + + + + SD_INFO1_MASK + SD_INFO1 Interrupt Mask Register + 0x040 + 32 + read-write + 0x0000031D + 0xFFFFFFFF + + + SDD3INM + SDnDAT3 Card Insertion Interrupt Request Mask + 9 + 9 + read-write + + + 0 + SD card insertion interrupt request by the SDnDAT3 is not masked + #0 + + + 1 + SD card insertion interrupt request by the SDnDAT3 is masked + #1 + + + + + SDD3RMM + SDnDAT3 Card Removal Interrupt Request Mask + 8 + 8 + read-write + + + 0 + SD card removal interrupt request by the SDnDAT3 is not masked + #0 + + + 1 + SD card removal interrupt request by the SDnDAT3 is masked + #1 + + + + + SDCDINM + SDnCD card Insertion Interrupt Request Mask + 4 + 4 + read-write + + + 0 + Card insertion interrupt request by the SDnCD is not masked + #0 + + + 1 + Card insertion interrupt request by the SDnCD is masked + #1 + + + + + SDCDRMM + SDnCD card Removal Interrupt Request Mask + 3 + 3 + read-write + + + 0 + Card removal interrupt request by the by the SDnCD is not masked + #0 + + + 1 + Card removal interrupt request by the by the SDnCD is masked + #1 + + + + + ACENDM + Access End Interrupt Request Mask + 2 + 2 + read-write + + + 0 + Access end interrupt request is not masked + #0 + + + 1 + Access end interrupt request is masked + #1 + + + + + RSPENDM + Response End Interrupt Request Mask + 0 + 0 + read-write + + + 0 + Response end interrupt request is not masked + #0 + + + 1 + Response end interrupt request is masked + #1 + + + + + + + SD_INFO2_MASK + SD_INFO2 Interrupt Mask Register + 0x044 + 32 + read-write + 0x00008B7F + 0xFFFFFFFF + + + ILAM + Illegal Access Error Interrupt Request Mask + 15 + 15 + read-write + + + 0 + Illegal access error interrupt request not masked + #0 + + + 1 + Illegal access error interrupt request masked + #1 + + + + + BWEM + BWE Interrupt Request Mask + 9 + 9 + read-write + + + 0 + Write enable interrupt request for the SD_BUF register not masked + #0 + + + 1 + Write enable interrupt request for the SD_BUF register masked + #1 + + + + + BREM + BRE Interrupt Request Mask + 8 + 8 + read-write + + + 0 + Read enable interrupt request for the SD buffer not masked + #0 + + + 1 + Read enable interrupt request for the SD buffer masked + #1 + + + + + RSPTOM + Response Timeout Interrupt Request Mask + 6 + 6 + read-write + + + 0 + Response timeout interrupt request not masked + #0 + + + 1 + Response timeout interrupt request masked + #1 + + + + + ILRM + SD_BUF Register Illegal Read Interrupt Request Mask + 5 + 5 + read-write + + + 0 + Illegal read detection interrupt request for the SD_BUF register not masked + #0 + + + 1 + Illegal read detection interrupt request for the SD_BUF register masked + #1 + + + + + ILWM + SD_BUF Register Illegal Write Interrupt Request Mask + 4 + 4 + read-write + + + 0 + Illegal write detection interrupt request for the SD_BUF register not masked + #0 + + + 1 + Illegal write detection interrupt request for the SD_BUF register masked + #1 + + + + + DTOM + Data Timeout Interrupt Request Mask + 3 + 3 + read-write + + + 0 + Data timeout interrupt request not masked + #0 + + + 1 + Data timeout interrupt request masked + #1 + + + + + ENDEM + End Bit Error Interrupt Request Mask + 2 + 2 + read-write + + + 0 + End bit detection error interrupt request not masked + #0 + + + 1 + End bit detection error interrupt request masked + #1 + + + + + CRCEM + CRC Error Interrupt Request Mask + 1 + 1 + read-write + + + 0 + CRC error interrupt request not masked + #0 + + + 1 + CRC error interrupt request masked + #1 + + + + + CMDEM + Command Error Interrupt Request Mask + 0 + 0 + read-write + + + 0 + Command error interrupt request not masked + #0 + + + 1 + Command error interrupt request masked + #1 + + + + + + + SD_CLK_CTRL + SD Clock Control Register + 0x048 + 32 + read-write + 0x00000020 + 0xFFFFFFFF + + + CLKCTRLEN + SD/MMC Clock Output Automatic Control Enable + 9 + 9 + read-write + + + 0 + Automatic control for SD/MMC Clock output is disabled. + #0 + + + 1 + Automatic control for SD/MMC Clock output is enabled. + #1 + + + + + CLKEN + SD/MMC Clock Output Control Enable + 8 + 8 + read-write + + + 0 + SD/MMC Clock output is disabled. The SDCLK signal is fixed 0. + #0 + + + 1 + SD/MMC Clock output is enabled. + #1 + + + + + CLKSEL + SDHI Clock Frequency Select + 0 + 7 + read-write + + + 0x00 + PCLKA divided by 2 + 0x00 + + + 0x01 + PCLKA divided by 4 + 0x01 + + + 0x02 + PCLKA divided by 8 + 0x02 + + + 0x04 + PCLKA divided by 16 + 0x04 + + + 0x08 + PCLKA divided by 32 + 0x08 + + + 0x10 + PCLKA divided by 64 + 0x10 + + + 0x20 + PCLKA divided by 128 + 0x20 + + + 0x40 + PCLKA divided by 256 + 0x40 + + + 0x80 + PCLKA divided by 512 + 0x80 + + + others + Settings prohibited. + true + + + + + + + SD_SIZE + Transfer Data Length Register + 0x04C + 32 + read-write + 0x00000200 + 0xFFFFFFFF + + + LEN + Transfer Data SizeThese bits specify a size between 1 and 512 bytes for the transfer of single blocks.In cases of multiple block transfer with automatic issuing of CMD12 (CMD18 and CMD25), the only specifiable transfer data size is 512 bytes. Furthermore, in cases of multiple block transfer without automatic issuing of CMD12, as well as 512 bytes, 32, 64, 128, and 256 bytes are specifiable. However, in the reading of 32, 64, 128, and 256 bytes for the transfer of multiple blocks, this is restricted to multiple block transfer by CMD53.Additionally, if a command accompanies data transfer, do not set these bits to 0. + 0 + 9 + read-write + + + + + SD_OPTION + SD Card Access Control Option Register + 0x050 + 32 + read-write + 0x000040EE + 0xFFFFFFFF + + + WIDTH + Bus WidthNOTE: The initial value is applied at a reset and when the SOFT_RST.SDRST flag is 0. + 15 + 15 + read-write + + + 0 + 4-bit width (WIDTH8=0) / 8-bit width (WIDTH8=1) + #0 + + + 1 + 1-bit width (WIDTH8=0 or 1 ) + #1 + + + + + WIDTH8 + Bus Widthsee b15, WIDTH bit + 13 + 13 + read-write + + + TOUTMASK + Timeout MASKWhen timeout occurs in case of inactivating timeout, software reset should be executed to terminate command sequence. + 8 + 8 + read-write + + + 0 + Activate Timeout + #0 + + + 1 + Inactivate Timeout(RSPTO bit and DTO bit of SD_INFO2 and SD_ERR_STS2 won't be set) + #1 + + + + + TOP + Timeout Counter + 4 + 7 + read-write + + + 1111 + Setting prohibited + #1111 + + + others + SDHI clock x 2^(TOP+13) + true + + + + + CTOP + Card Detect Time Counter + 0 + 3 + read-write + + + 1111 + Setting prohibited + #1111 + + + others + IMCLK x 2^(CTOP+10) + true + + + + + + + SD_ERR_STS1 + SD Error Status Register 1 + 0x058 + 32 + read-only + 0x00002000 + 0xFFFFFFFF + + + CRCTK + CRC Status TokenStore the CRC status token value (normal value is 010b) + 12 + 14 + read-only + + + CRCTKE + CRC Status Token Error + 11 + 11 + read-only + + + 0 + An error has not occured in the CRC status. + #0 + + + 1 + An error has occured in the CRC status. + #1 + + + + + RDCRCE + Read Data CRC Error + 10 + 10 + read-only + + + 0 + CRC error has detected in read data + #0 + + + 1 + CRC error has not detected in read data + #1 + + + + + RSPCRCE1 + Response CRC Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPCRCE0. + 9 + 9 + read-only + + + 0 + CRC error has not occured. + #0 + + + 1 + CRC error has occured in the response to a command issued within a command sequence. + #1 + + + + + RSPCRCE0 + Response CRC Error 0NOTE: other than a response to a command issued within a command sequence + 8 + 8 + read-only + + + 0 + A CRC error has not occur in a response + #0 + + + 1 + A CRC error has occured in a response + #1 + + + + + CRCLENE + CRC Status Token Length Error + 5 + 5 + read-only + + + 0 + An error has not occured in the CRC status length. + #0 + + + 1 + An error has occured in the CRC status length (and the end bit has not been detected) + #1 + + + + + RDLENE + Read Data Length Error + 4 + 4 + read-only + + + 0 + An error has occurred not in the read data length. + #0 + + + 1 + An error has occured in the read data length (and the end bit has not been detected among the valid bits). + #1 + + + + + RSPLENE1 + Response Length Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPLENE0. + 3 + 3 + read-only + + + 0 + An error has not occurred in the response length to a command issued within a command sequence. + #0 + + + 1 + An error has occured in the response length to a command issued within a command sequence. + #1 + + + + + RSPLENE0 + Response Length Error 0NOTE: other than a response to a command issued within a command sequence + 2 + 2 + read-only + + + 0 + An error has not occured in the response length + #0 + + + 1 + An error has occured in the response length + #1 + + + + + CMDE1 + Command Error 1NOTE: In cases where CMD12 is issued by setting a command index in SD_CMD, this is Indicated in CMDE0. + 1 + 1 + read-only + + + 0 + An error has not occurs in the command index of the response to a command issued within a command sequence. + #0 + + + 1 + An error has occured in the command index of the response to a command issued within a command sequence. + #1 + + + + + CMDE0 + Command Error 0NOTE: other than a response to a command issued within a command sequence + 0 + 0 + read-only + + + 0 + An error has not occured in the command index of a response. + #0 + + + 1 + An error has occured in the command index of a response. + #1 + + + + + + + SD_ERR_STS2 + SD Error Status Register 2 + 0x05C + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + CRCBSYTO + CRC Status Token Busy Timeout + 6 + 6 + read-only + + + 0 + Not timeout + #0 + + + 1 + The busy state continues for longer than N-cycle after the CRC status + #1 + + + + + CRCTO + CRC Status Token Timeout + 5 + 5 + read-only + + + 0 + Not timeout + #0 + + + 1 + The CRC status is not received though a longer time than N-cycle has elapsed after data writing. + #1 + + + + + RDTO + Read Data Timeout + 4 + 4 + read-only + + + 0 + Not timeout + #0 + + + 1 + The read data is not received though a longer time than N-cycle has elapsed after read command. / The read data for the next block are not received though a longer time than N-cycle has elapsed after the reception of read data. / The read data for the next block are not received though a longer time than N-cycle has elapsed after release of the read wait state. + #1 + + + + + BSYTO1 + Busy Timeout 1 + 3 + 3 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The busy state for longer than N-cycle continues after CMD12 has been issued within a command sequence. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in BSYTO0. + #1 + + + + + BSYTO0 + Busy Timeout 0 + 2 + 2 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The busy state for longer than N-cycle continues after R1b response. + #1 + + + + + RSPTO1 + Response Timeout 1 + 1 + 1 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The response to a command issued within a command sequence*2 is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. In cases where CMD12 is issued by setting a command index in SD_CMD, this is indicated in RSPTO0. + #1 + + + + + RSPTO0 + Response Timeout 0 + 0 + 0 + read-only + + + 0 + Not timeout. + #0 + + + 1 + The response (other than a response to a command issued within a command sequence) is not received though a longer time than 640 cycles of SD/MMC clock has elapsed. + #1 + + + + + + + SD_BUF0 + SD Buffer Register + 0x060 + 32 + read-write + 0x00000000 + 0x00000000 + + + SD_BUF + SD Buffer RegisterWhen writing to the SD card, the write data is written to this register. When reading from the SD card, the read data is read from this register. This register is internally connected to two 512-byte buffers.If both buffers are not empty when executing multiple block read, SD/MMC clock is stopped to suspend receiving data. When one of buffers is empty, SD/MMC clock is supplied to resume receiving data. + 0 + 31 + read-write + + + + + SDIO_MODE + SDIO Mode Control Register + 0x068 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + C52PUB + SDIO None AbortNOTE: See manual + 9 + 9 + read-write + + + IOABT + SDIO AbortNOTE: See manual + 8 + 8 + read-write + + + RWREQ + Read Wait Request + 2 + 2 + read-write + + + 0 + Allow SD/MMC to exit read wait state + #0 + + + 1 + Request for SD/MMC to enter read wait state. + #1 + + + + + INTEN + SDIO Mode + 0 + 0 + read-write + + + 1 + Enables the SD host interface to receive SDIO interrupt from the SDIO card + #1 + + + 0 + Disables the SD host interface to receive SDIO interrupt from the SDIO card + #0 + + + + + + + SDIO_INFO1 + SDIO Interrupt Flag Register 1 + 0x06C + 32 + read-write + 0x00000000 + 0xFFFFFFF9 + + + EXWT + EXWT Status FlagNOTE: See manual + 15 + 15 + read-write + zeroToClear + modify + + + EXPUB52 + EXPUB52 Status FlagNOTE: See manual + 14 + 14 + read-write + zeroToClear + modify + + + IOIRQ + SDIO Interrupt Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + SDIO interrupt not accepted + #0 + + + 1 + SDIO interrupt accepted + #1 + + + + + + + SDIO_INFO1_MASK + SDIO_INFO1 Interrupt Mask Register + 0x070 + 32 + read-write + 0x0000C007 + 0xFFFFFFFF + + + EXWTM + EXWT Interrupt Request Mask Control + 15 + 15 + read-write + + + 0 + EXWT interrupt request not masked + #0 + + + 1 + EXWT interrupt request masked + #1 + + + + + EXPUB52M + EXPUB52 Interrupt Request Mask Control + 14 + 14 + read-write + + + 0 + EXPUB52 interrupt request not masked + #0 + + + 1 + EXPUB52 interrupt request masked + #1 + + + + + IOIRQM + IOIRQ Interrupt Mask Control + 0 + 0 + read-write + + + 0 + IOIRQ interrupt not masked + #0 + + + 1 + IOIRQ interrupt masked + #1 + + + + + + + SD_DMAEN + DMA Mode Enable Register + 0x1B0 + 32 + read-write + 0x00001010 + 0xFFFFFFFF + + + DMAEN + SD_BUF Read/Write DMA Transfer + 1 + 1 + read-write + + + 0 + The SD_BUF read/write DMA transfer is disabled. + #0 + + + 1 + The SD_BUF read/write DMA transfer is enabled. + #1 + + + + + + + SOFT_RST + Software Reset Register + 0x1C0 + 32 + read-write + 0x00000007 + 0xFFFFFFFF + + + SDRST + Software Reset of SD I/F Unit + 0 + 0 + read-write + + + 0 + Reset + #0 + + + 1 + Reset released + #1 + + + + + + + SDIF_MODE + SD Interface Mode Setting Register + 0x1CC + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + NOCHKCR + CRC Check Mask (for MMC test commands) + 8 + 8 + read-write + + + 0 + CRC check is valid + #0 + + + 1 + CRC check is invalid(CRC16 value is ignored when read and CRC Status value is ignored when write) + #1 + + + + + + + EXT_SWAP + Swap Control Register + 0x1E0 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BRSWP + SD_BUF0 Swap Read + 7 + 7 + read-write + + + 0 + The current data are read without swapping. + #0 + + + 1 + Swapping of the positions of the higher- and lower-order bytes of data for reading proceeds. + #1 + + + + + BWSWP + SD_BUF0 Swap Write + 6 + 6 + read-write + + + 0 + The current data are written without swapping. + #0 + + + 1 + Swapping of the positions of the higher- and lower-order bytes of data for writing proceeds. + #1 + + + + + + + + + R_SDHI1 + 0x40062400 + + + R_SLCDC + Segment LCD Controller/Driver + 0x40082000 + + 0x00 + 4 + registers + + + 0x100 + 38 + registers + + + + LCDM0 + LCD Mode Register 0 + 0x000 + 8 + read-write + 0x00 + 0xFF + + + MDSET + LCD drive voltage generator selection + 6 + 7 + read-write + + + 00 + External resistance division method + #00 + + + 01 + Internal voltage boosting method + #01 + + + 10 + Capacitor split method + #10 + + + 11 + Setting prohibited + #11 + + + + + LWAVE + LCD display waveform selection + 5 + 5 + read-write + + + 0 + Waveform A + #0 + + + 1 + Waveform B + #1 + + + + + LDTY + Time Slice of LCD Display Select + 2 + 4 + read-write + + + 000 + Static + #000 + + + 001 + 2-time slice + #001 + + + 010 + 3-time slice + #010 + + + 011 + 4-time slice + #011 + + + 101 + 8-time slice + #101 + + + others + Setting prohibited + true + + + + + LBAS + LCD Display Bias Method Select + 0 + 1 + read-write + + + 00 + 1/2 bias method + #00 + + + 01 + 1/3 bias method + #01 + + + 10 + 1/4 bias method + #10 + + + 11 + Setting prohibited + #11 + + + + + + + LCDM1 + LCD Mode Register 1 + 0x001 + 8 + read-write + 0x00 + 0xFF + + + LCDON + LCD Display Enable/Disable + 7 + 7 + read-write + + + 0 + Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1) + #0 + + + 1 + Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1) + #1 + + + + + SCOC + LCD Display Enable/Disable + 6 + 6 + read-write + + + 0 + Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1) + #0 + + + 1 + Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1) + #1 + + + + + VLCON + Voltage boost circuit or capacitor split circuit operation enable/disable + 5 + 5 + read-write + + + 0 + Stops voltage boost circuit or capacitor split circuit operation + #0 + + + 1 + Enables voltage boost circuit or capacitor split circuit operation + #1 + + + + + BLON + Display data area control + 4 + 4 + read-write + + + 0 + Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1) + #0 + + + 1 + Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC)) + #1 + + + + + LCDSEL + Display data area control + 3 + 3 + read-write + + + 0 + Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) + #0 + + + 1 + Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) + #1 + + + + + Reserved + These bits are read as 00. The write value should be 00. + 1 + 2 + read-write + + + LCDVLM + Voltage Boosting Pin Initial Value Switching Control + 0 + 0 + read-write + + + 0 + Set when VDD >= 2.7 V + #0 + + + 1 + Set when VDD <= 4.2 V + #1 + + + + + + + LCDC0 + LCD Clock Control Register 0 + 0x002 + 8 + read-write + 0x00 + 0xFF + + + LCDC + LCD clock (LCDCL) + 0 + 5 + read-write + + + 000001 + (Sub clock)/22 or (LOCO clock)/22 + #000001 + + + 000010 + (Sub clock)/23 or (LOCO clock)/23 + #000010 + + + 000011 + (Sub clock)/24 or (LOCO clock)/24 + #000011 + + + 000100 + (Sub clock)/25 or (LOCO clock)/25 + #000100 + + + 000101 + (Sub clock)/26 or (LOCO clock)/26 + #000101 + + + 000110 + (Sub clock)/27 or (LOCO clock)/27 + #000110 + + + 000111 + (Sub clock)/28 or (LOCO clock)/28 + #000111 + + + 001000 + (Sub clock)/29 or (LOCO clock)/29 + #001000 + + + 001001 + (Sub clock)/210 or (LOCO clock)/210 + #001001 + + + 010001 + (Main clock)/28 or (HOCO clock)/28 + #010001 + + + 010010 + (Main clock)/29 or (HOCO clock)/29 + #010010 + + + 010011 + (Main clock)/210 or (HOCO clock)/210 + #010011 + + + 010100 + (Main clock)/211 or (HOCO clock)/211 + #010100 + + + 010101 + (Main clock)/212 or (HOCO clock)/212 + #010101 + + + 010110 + (Main clock)/213 or (HOCO clock)/213 + #010110 + + + 010111 + (Main clock)/214 or (HOCO clock)/214 + #010111 + + + 011000 + (Main clock)/215 or (HOCO clock)/215 + #011000 + + + 011001 + (Main clock)/216 or (HOCO clock)/216 + #011001 + + + 011010 + (Main clock)/217 or (HOCO clock)/217 + #011010 + + + 011011 + (Main clock)/218 or (HOCO clock)/218 + #011011 + + + 101011 + (Main clock)/219 or (HOCO clock)/219 + #101011 + + + others + Other than above Setting prohibited + true + + + + + + + VLCD + LCD Boost Level Control Register + 0x003 + 8 + read-write + 0x04 + 0xFF + + + VLCD + Reference Voltage(Contrast Adjustment) Select + 0 + 4 + read-write + + + 00100 + Reference voltageselection(contrast adjustment): 1.00 V (default) VL4 voltage: 3.00 V(1/3 bias method)/4.00 V(1/4 bias method) + #00100 + + + 00101 + Reference voltageselection(contrast adjustment): 1.05 V VL4 voltage: 3.15 V(1/3 bias method)/4.20 V(1/4 bias method) + #00101 + + + 00110 + Reference voltageselection(contrast adjustment): 1.10 V VL4 voltage: 3.30 V(1/3 bias method)/4.40 V(1/4 bias method) + #00110 + + + 00111 + Reference voltageselection(contrast adjustment): 1.15 V VL4 voltage: 3.45 V(1/3 bias method)/4.60 V(1/4 bias method) + #00111 + + + 01000 + Reference voltageselection(contrast adjustment): 1.20 V VL4 voltage: 3.60 V(1/3 bias method)/4.80 V(1/4 bias method) + #01000 + + + 01001 + Reference voltageselection(contrast adjustment): 1.25 V VL4 voltage: 3.75 V(1/3 bias method)/5.00 V(1/4 bias method) + #01001 + + + 01010 + Reference voltageselection(contrast adjustment): 1.30 V VL4 voltage: 3.90 V(1/3 bias method)/5.20 V(1/4 bias method) + #01010 + + + 01011 + Reference voltageselection(contrast adjustment): 1.35 V VL4 voltage: 4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01011 + + + 01100 + Reference voltageselection(contrast adjustment): 1.40 V VL4 voltage: 4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01100 + + + 01101 + Reference voltageselection(contrast adjustment): 1.45 V VL4 voltage: 4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01101 + + + 01110 + Reference voltageselection(contrast adjustment): 1.50 V VL4 voltage: 4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01110 + + + 01111 + Reference voltageselection(contrast adjustment): 1.55 V VL4 voltage: 4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #01111 + + + 10000 + Reference voltageselection(contrast adjustment): 1.60 V VL4 voltage: 4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10000 + + + 10001 + Reference voltageselection(contrast adjustment): 1.65 V VL4 voltage: 4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10001 + + + 10010 + Reference voltageselection(contrast adjustment): 1.70 V VL4 voltage: 5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10010 + + + 10011 + Reference voltageselection(contrast adjustment): 1.75 V VL4 voltage: 5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method) + #10011 + + + others + Setting prohibited + true + + + + + + + 64 + 0x1 + SEG[%s] + LCD Display Data Array + 0x100 + 8 + read-write + 0x00 + 0xFF + + + A + A-Pattern Area + 0 + 3 + read-write + + + B + B-Pattern Area + 4 + 7 + read-write + + + + + + + R_SPI0 + Serial Peripheral Interface + 0x40072000 + + 0x00000000 + 0x008 + registers + + + 0x0000000A + 0x008 + registers + + + + SPCR + SPI Control Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + SPRIE + SPI Receive Buffer Full Interrupt Enable + 7 + 7 + read-write + + + 0 + Disables the generation of SPI receive buffer full interrupt requests + #0 + + + 1 + Enables the generation of SPI receive buffer full interrupt requests + #1 + + + + + SPE + SPI Function Enable + 6 + 6 + read-write + + + 0 + Disables the SPI function + #0 + + + 1 + Enables the SPI function + #1 + + + + + SPTIE + Transmit Buffer Empty Interrupt Enable + 5 + 5 + read-write + + + 0 + Disables the generation of transmit buffer empty interrupt requests + #0 + + + 1 + Enables the generation of transmit buffer empty interrupt requests + #1 + + + + + SPEIE + SPI Error Interrupt Enable + 4 + 4 + read-write + + + 0 + Disables the generation of SPI error interrupt requests + #0 + + + 1 + Enables the generation of SPI error interrupt requests + #1 + + + + + MSTR + SPI Master/Slave Mode Select + 3 + 3 + read-write + + + 0 + Slave mode + #0 + + + 1 + Master mode + #1 + + + + + MODFEN + Mode Fault Error Detection Enable + 2 + 2 + read-write + + + 0 + Disables the detection of mode fault error + #0 + + + 1 + Enables the detection of mode fault error + #1 + + + + + TXMD + Communications Operating Mode Select + 1 + 1 + read-write + + + 0 + Full-duplex synchronous serial communications + #0 + + + 1 + Serial communications consisting of only transmit operations + #1 + + + + + SPMS + SPI Mode Select + 0 + 0 + read-write + + + 0 + SPI operation (4-wire method) + #0 + + + 1 + Clock synchronous operation (3-wire method) + #1 + + + + + + + SSLP + SPI Slave Select Polarity Register + 0x01 + 8 + read-write + 0x00 + 0xFF + + + SSL3P + SSL3 Signal Polarity Setting + 3 + 3 + read-write + + + 0 + SSL3 signal is active low + #0 + + + 1 + SSL3 signal is active high + #1 + + + + + SSL2P + SSL2 Signal Polarity Setting + 2 + 2 + read-write + + + 0 + SSL2 signal is active low + #0 + + + 1 + SSL2 signal is active high + #1 + + + + + SSL1P + SSL1 Signal Polarity Setting + 1 + 1 + read-write + + + 0 + SSL1 signal is active low + #0 + + + 1 + SSL1 signal is active high + #1 + + + + + SSL0P + SSL0 Signal Polarity Setting + 0 + 0 + read-write + + + 0 + SSL0 signal is active low + #0 + + + 1 + SSL0 signal is active high + #1 + + + + + SSL4P + SSL4 Signal Polarity Setting + 4 + 4 + read-write + + + 0 + SSL4 signal is active low + #0 + + + 1 + SSL4 signal is active high + #1 + + + + + SSL5P + SSL5 Signal Polarity Setting + 5 + 5 + read-write + + + 0 + SSL5 signal is active low + #0 + + + 1 + SSL5 signal is active high + #1 + + + + + SSL6P + SSL6 Signal Polarity Setting + 6 + 6 + read-write + + + 0 + SSL6 signal is active low + #0 + + + 1 + SSL6 signal is active high + #1 + + + + + SSL7P + SSL7 Signal Polarity Setting + 7 + 7 + read-write + + + 0 + SSL7 signal is active low + #0 + + + 1 + SSL7 signal is active high + #1 + + + + + + + SPPCR + SPI Pin Control Register + 0x02 + 8 + read-write + 0x00 + 0xFF + + + MOIFE + MOSI Idle Value Fixing Enable + 5 + 5 + read-write + + + 0 + MOSI output value equals final data from previous transfer + #0 + + + 1 + MOSI output value equals the value set in the MOIFV bit + #1 + + + + + MOIFV + MOSI Idle Fixed Value + 4 + 4 + read-write + + + 0 + The level output on the MOSIn pin during MOSI idling corresponds to low. + #0 + + + 1 + The level output on the MOSIn pin during MOSI idling corresponds to high. + #1 + + + + + SPLP2 + SPI Loopback 2 + 1 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Loopback mode (data is not inverted for transmission) + #1 + + + + + SPLP + SPI Loopback + 0 + 0 + read-write + + + 0 + Normal mode + #0 + + + 1 + Loopback mode (data is inverted for transmission) + #1 + + + + + + + SPSR + SPI Status Register + 0x03 + 8 + read-write + 0x20 + 0xFF + + + SPRF + SPI Receive Buffer Full Flag + 7 + 7 + read-write + zeroToClear + modify + + + 0 + No valid data in SPDR + #0 + + + 1 + Valid data found in SPDR + #1 + + + + + SPTEF + SPI Transmit Buffer Empty Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + Data found in the transmit buffer + #0 + + + 1 + No data in the transmit buffer + #1 + + + + + UDRF + Underrun Error Flag(When MODF is 0, This bit is invalid.) + 4 + 4 + read-write + zeroToClear + modify + + + 0 + A mode fault error occurs (MODF=1) + #0 + + + 1 + An underrun error occurs (MODF=1) + #1 + + + + + PERF + Parity Error Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + No parity error occurs + #0 + + + 1 + A parity error occurs + #1 + + + + + MODF + Mode Fault Error Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Neither mode fault error nor underrun error occurs + #0 + + + 1 + A mode fault error or an underrun error occurs. + #1 + + + + + IDLNF + SPI Idle Flag + 1 + 1 + read-only + + + 0 + SPI is in the idle state + #0 + + + 1 + SPI is in the transfer state + #1 + + + + + OVRF + Overrun Error Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No overrun error occurs + #0 + + + 1 + An overrun error occurs + #1 + + + + + CENDF + Communication End Flag + 6 + 6 + read-write + + + 0 + The RSPI is not communicating or communicating. + #0 + + + 1 + The RSPI communication completed. + #1 + + + + + + + SPDR + SPI Data Register + 0x04 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SPDR_HA + SPI Data Register ( halfword access ) + SPDR + 0x04 + 16 + read-write + 0x0000 + 0xFFFF + + + SPDR_BY + SPI Data Register ( byte access ) + SPDR + 0x04 + 8 + read-write + 0x00 + 0xFF + + + SPSCR + SPI Sequence Control Register + 0x08 + 8 + read-write + 0x00 + 0xFF + + + Reserved + These bits are read as 00000. The write value should be 00000. + 3 + 7 + read-write + + + SPSLN + RSPI Sequence Length Specification +The order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. + 0 + 2 + read-write + + + 000 + Length 1 SPDMDx x = 0->0->... + #000 + + + 001 + Length 2 SPDMDx x = 0->1->0->... + #001 + + + 010 + Length 3 SPDMDx x = 0->1->2->0->... + #010 + + + 011 + Length 4 SPDMDx x = 0->1->2->3->0->... + #011 + + + 100 + Length 5 SPDMDx x = 0->1->2->3->4->0->... + #100 + + + 101 + Length 6 SPDMDx x = 0->1->2->3->4->5->0->... + #101 + + + 110 + Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... + #110 + + + 111 + Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... + #111 + + + + + + + SPBR + SPI Bit Rate Register + 0x0A + 8 + read-write + 0xFF + 0xFF + + + SPR + SPBR sets the bit rate in master mode. + 0 + 7 + read-write + + + + + SPDCR + SPI Data Control Register + 0x0B + 8 + read-write + 0x00 + 0xFF + + + SPBYT + SPI Byte Access Specification + 6 + 6 + read-write + + + 0 + SPDR is accessed in halfword or word (SPLW is valid) + #0 + + + 1 + SPDR is accessed in byte (SPLW is invalid). + #1 + + + + + SPLW + SPI Word Access/Halfword Access Specification + 5 + 5 + read-write + + + 0 + Set SPDR_HA to valid for halfword access + #0 + + + 1 + Set SPDR to valid for word access. + #1 + + + + + SPRDTD + SPI Receive/Transmit Data Selection + 4 + 4 + read-write + + + 0 + SPDR values are read from the receive buffer + #0 + + + 1 + SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) + #1 + + + + + SPFC + Number of Frames Specification + 0 + 1 + read-write + + + 00 + 1 frame + #00 + + + 01 + 2 frames + #01 + + + 10 + 3 frames + #10 + + + 11 + 4 frames. + #11 + + + + + SLSEL + SSL Pin Output Select + 2 + 3 + read-write + + + 00 + SSL2 to SSL7->output, SSL1->output + #00 + + + 01 + SSL2 to SSL7->I/O, SSL1->I/O + #01 + + + 10 + SSL2 to SSL7->I/O, SSL1->output + #10 + + + 11 + Setting prohibited + #11 + + + + + + + SPCKD + SPI Clock Delay Register + 0x0C + 8 + read-write + 0x00 + 0xFF + + + SCKDL + RSPCK Delay Setting + 0 + 2 + read-write + + + 000 + 1 RSPCK + #000 + + + 001 + 2 RSPCK + #001 + + + 010 + 3 RSPCK + #010 + + + 011 + 4 RSPCK + #011 + + + 100 + 5 RSPCK + #100 + + + 101 + 6 RSPCK + #101 + + + 110 + 7 RSPCK + #110 + + + 111 + 8 RSPCK + #111 + + + + + + + SSLND + SPI Slave Select Negation Delay Register + 0x0D + 8 + read-write + 0x00 + 0xFF + + + SLNDL + SSL Negation Delay Setting + 0 + 2 + read-write + + + 000 + 1 RSPCK + #000 + + + 001 + 2 RSPCK + #001 + + + 010 + 3 RSPCK + #010 + + + 011 + 4 RSPCK + #011 + + + 100 + 5 RSPCK + #100 + + + 101 + 6 RSPCK + #101 + + + 110 + 7 RSPCK + #110 + + + 111 + 8 RSPCK + #111 + + + + + + + SPND + SPI Next-Access Delay Register + 0x0E + 8 + read-write + 0x00 + 0xFF + + + SPNDL + SPI Next-Access Delay Setting + 0 + 2 + read-write + + + 000 + 1 RSPCK + 2 PCLK + #000 + + + 001 + 2 RSPCK + 2 PCLK + #001 + + + 010 + 3 RSPCK + 2 PCLK + #010 + + + 011 + 4 RSPCK + 2 PCLK + #011 + + + 100 + 5 RSPCK + 2 PCLK + #100 + + + 101 + 6 RSPCK + 2 PCLK + #101 + + + 110 + 7 RSPCK + 2 PCLK + #110 + + + 111 + 8 RSPCK + 2 PCLK + #111 + + + + + + + SPCR2 + SPI Control Register 2 + 0x0F + 8 + read-write + 0x00 + 0xFF + + + SCKASE + RSPCK Auto-Stop Function Enable + 4 + 4 + read-write + + + 0 + Disables the RSPCK auto-stop function + #0 + + + 1 + Enables the RSPCK auto-stop function + #1 + + + + + PTE + Parity Self-Testing + 3 + 3 + read-write + + + 0 + Disables the self-diagnosis function of the parity circuit + #0 + + + 1 + Enables the self-diagnosis function of the parity circuit + #1 + + + + + SPIIE + SPI Idle Interrupt Enable + 2 + 2 + read-write + + + 0 + Disables the generation of idle interrupt requests + #0 + + + 1 + Enables the generation of idle interrupt requests + #1 + + + + + SPOE + Parity Mode + 1 + 1 + read-write + + + 0 + Selects even parity for use in transmission and reception + #0 + + + 1 + Selects odd parity for use in transmission and reception + #1 + + + + + SPPE + Parity Enable + 0 + 0 + read-write + + + 0 + Does not add the parity bit to transmit data and does not check the parity bit of receive data + #0 + + + 1 + Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) + #1 + + + + + SPTDDL + RSPI Transmit Data Delay + 5 + 7 + read-write + + + 010 + Same as above + #010 + + + 011 + Same as above + #011 + + + 100 + Same as above + #100 + + + 101 + Same as above + #101 + + + 110 + Same as above + #110 + + + 111 + Same as above + #111 + + + + + + + 8 + 0x02 + SPCMD[%s] + SPI Command Register %s + 0x10 + 16 + read-write + 0x070D + 0xFFFF + + + SCKDEN + RSPCK Delay Setting Enable + 15 + 15 + read-write + + + 0 + An RSPCK delay of 1 RSPCK + #0 + + + 1 + An RSPCK delay is equal to the setting of the SPI clock delay register (SPCKD) + #1 + + + + + SLNDEN + SSL Negation Delay Setting Enable + 14 + 14 + read-write + + + 0 + An SSL negation delay of 1 RSPCK + #0 + + + 1 + An SSL negation delay is equal to the setting of the SPI slave select negation delay register (SSLND) + #1 + + + + + SPNDEN + SPI Next-Access Delay Enable + 13 + 13 + read-write + + + 0 + A next-access delay of 1 RSPCK + 2 PCLK + #0 + + + 1 + A next-access delay is equal to the setting of the SPI next-access delay register (SPND) + #1 + + + + + LSBF + SPI LSB First + 12 + 12 + read-write + + + 0 + MSB first + #0 + + + 1 + LSB first + #1 + + + + + SPB + SPI Data Length Setting + 8 + 11 + read-write + + + 0100 + 8 bits + #0100 + + + 0101 + 8 bits + #0101 + + + 0110 + 8 bits + #0110 + + + 0111 + 8 bits + #0111 + + + 1000 + 9 bits + #1000 + + + 1001 + 10 bits + #1001 + + + 1010 + 11 bits + #1010 + + + 1011 + 12 bits + #1011 + + + 1100 + 13 bits + #1100 + + + 1101 + 14 bits + #1101 + + + 1110 + 15 bits + #1110 + + + 1111 + 16 bits + #1111 + + + others + Setting prohibited + true + + + + + SSLKP + SSL Signal Level Keeping + 7 + 7 + read-write + + + 0 + Negates all SSL signals upon completion of transfer + #0 + + + 1 + Keeps the SSL signal level from the end of transfer until the beginning of the next access + #1 + + + + + SSLA + SSL Signal Assertion Setting + 4 + 6 + read-write + + + 000 + SSL0 + #000 + + + 001 + SSL1 + #001 + + + 010 + SSL2 + #010 + + + 011 + SSL3 + #011 + + + others + Setting prohibited + true + + + + + BRDV + Bit Rate Division Setting + 2 + 3 + read-write + + + 00 + These bits select the base bit rate + #00 + + + 01 + These bits select the base bit rate divided by 2 + #01 + + + 10 + These bits select the base bit rate divided by 4 + #10 + + + 11 + These bits select the base bit rate divided by 8 + #11 + + + + + CPOL + RSPCK Polarity Setting + 1 + 1 + read-write + + + 0 + RSPCK is low when idle + #0 + + + 1 + RSPCK is high when idle + #1 + + + + + CPHA + RSPCK Phase Setting + 0 + 0 + read-write + + + 0 + Data sampling on odd edge, data variation on even edge + #0 + + + 1 + Data variation on odd edge, data sampling on even edge + #1 + + + + + + + SPDCR2 + SPI Data Control Register 2 + 0x20 + 8 + read-write + 0x00 + 0xFF + + + BYSW + Byte Swap Operating Mode Select + 0 + 0 + read-write + + + 0 + Byte Swap Operating Mode disabled + #0 + + + 1 + Byte Swap Operating Mode enabled + #1 + + + + + SINV + Serial data invert bit + 1 + 1 + read-write + + + 0 + Not invert serial data + #0 + + + 1 + Invert serial data. + #1 + + + + + + + SPSSR + SPI Sequence Status Register + 0x09 + 8 + read-only + 0x00 + 0xFF + + + SPCP + RSPI Command Pointer + 0 + 2 + read-only + + + 000 + SPCMD0 + #000 + + + 001 + SPCMD1 + #001 + + + 010 + SPCMD2 + #010 + + + 011 + SPCMD3 + #011 + + + 100 + SPCMD4 + #100 + + + 101 + SPCMD5 + #101 + + + 110 + SPCMD6 + #110 + + + 111 + SPCMD7 + #111 + + + + + Reserved + This bit is read as 0. + 3 + 3 + read-only + + + SPECM + RSPI Error Command + 4 + 6 + read-only + + + 000 + SPCMD0 + #000 + + + 001 + SPCMD1 + #001 + + + 010 + SPCMD2 + #010 + + + 011 + SPCMD3 + #011 + + + 100 + SPCMD4 + #100 + + + 101 + SPCMD5 + #101 + + + 110 + SPCMD6 + #110 + + + 111 + SPCMD7 + #111 + + + + + Reserved + This bit is read as 0. + 7 + 7 + read-only + + + + + SPCR3 + RSPI Control Register 3 + 0x21 + 8 + read-write + 0x00 + 0xFF + + + ETXMD + Extended Communication Mode Select + 0 + 0 + read-write + + + 0 + Full-duplex synchronous or transmit-only serial communications. + #0 + + + 1 + Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). + #1 + + + + + BFDS + Between Burst Transfer Frames Delay Select + 1 + 1 + read-write + + + 0 + Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer + #0 + + + 1 + Delay between frames is not inserted in burst transfer. + #1 + + + + + Reserved + These bits are read as 00. The write value should be 00. + 2 + 3 + read-write + + + CENDIE + RSPI Communication End Interrupt Enable + 4 + 4 + read-write + + + 0 + Communication end interrupt request is disabled. + #0 + + + 1 + Communication end interrupt request is enabled. + #1 + + + + + Reserved + These bits are read as 000. The write value should be 000. + 5 + 7 + read-write + + + + + SPPR + RSPI Parameter Read Register + 0x3E + 16 + read-write + 0x0000 + 0xFFFF + + + Reserved + These bits are read as 0000. The write value should be 0000. + 0 + 3 + read-write + + + BUFWID + Buffer Width check + 4 + 4 + read-write + + + 0 + 16bit + #0 + + + 1 + 32bit + #1 + + + + + Reserved + These bits are read as 000. The write value should be 000. + 5 + 7 + read-write + + + BUFNUM + Buffer Number check + 8 + 10 + read-write + + + 001 + 1 Buffer + #001 + + + 100 + 4 Buffer + #100 + + + + + Reserved + This bit is read as 0. The write value should be 0. + 11 + 11 + read-write + + + CMDNUM + Command Number check + 12 + 15 + read-write + + + 0001 + 1 Command + #0001 + + + 1000 + 8 Command + #1000 + + + + + + + + + R_SPI1 + 0x40072100 + + + R_SRAM + SRAM + 0x40002000 + + 0x00000000 + 0x01 + registers + + + 0x00000004 + 0x01 + registers + + + 0x00000008 + 0x01 + registers + + + 0x000000C0 + 0x005 + registers + + + 0x000000D0 + 0x01 + registers + + + 0x000000D4 + 0x01 + registers + + + 0x000000D8 + 0x01 + registers + + + + PARIOAD + SRAM Parity Error Operation After Detection Register + 0x00 + 8 + read-write + 0x00 + 0xFF + + + OAD + Operation after Detection + 0 + 0 + read-write + + + 1 + Reset + #1 + + + 0 + Non maskable interrupt. + #0 + + + + + + + SRAMPRCR + SRAM Protection Register + 0x04 + 8 + read-write + 0x00 + 0xFF + + + KW + Write Key Code + 1 + 7 + write-only + + + 1111000 + Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b. + #1111000 + + + others + Writing to the RAMPRCR bit is invalid. + true + + + + + SRAMPRCR + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to protected registers + #0 + + + 1 + Enable writes to protected registers. + #1 + + + + + + + SRAMWTSC + RAM Wait State Control Register + 0x08 + 8 + read-write + 0x0E + 0xFF + + + SRAMHSWTEN + SRAMHS Wait Enable + 4 + 4 + read-write + + + 0 + Not add wait state in read access cycle to SRAMHS + #0 + + + 1 + Add wait state in read access cycle to SRAMHS + #1 + + + + + SRAM1WTEN + SRAM1 Wait Enable + 3 + 3 + read-write + + + 0 + Not add wait state in read access cycle to SRAM1 + #0 + + + 1 + Add wait state in read access cycle to SRAM1 + #1 + + + + + SRAM0WTEN + SRAM0 Wait Enable + 2 + 2 + read-write + + + 0 + Not add wait state in read access cycle to SRAM0 + #0 + + + 1 + Add wait state in read access cycle to SRAM0 + #1 + + + + + ECCRAMRDWTEN + ECCRAM Read wait enable + 1 + 1 + read-write + + + 0 + Not add wait state in read access cycle to SRAM0 (ECC area) + #0 + + + 1 + Add wait state in read access cycle to SRAM0 (ECC area) + #1 + + + + + ECCRAMWRWTEN + ECCRAM Write Wait Enable + 0 + 0 + read-write + + + 0 + Not add wait state in write access cycle to SRAM0 (ECC area) + #0 + + + 1 + Add wait state in write access cycle to SRAM0 (ECC area) + #1 + + + + + + + ECCMODE + ECC Operating Mode Control Register + 0xC0 + 8 + read-write + 0x00 + 0xFF + + + ECCMOD + ECC Operating Mode Select + 0 + 1 + read-write + + + 00 + Disable ECC function + #00 + + + 01 + Setting prohibited + #01 + + + 10 + Enable ECC function without error checking + #10 + + + 11 + Enable ECC function with error checking + #11 + + + + + + + ECC2STS + ECC 2-Bit Error Status Register + 0xC1 + 8 + read-write + 0x00 + 0xFF + + + ECC2ERR + ECC 2-Bit Error Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No 2-bit ECC error occurred + #0 + + + 1 + 2-bit ECC error occurred. + #1 + + + + + + + ECC1STSEN + ECC 1-Bit Error Information Update Enable Register + 0xC2 + 8 + read-write + 0x00 + 0xFF + + + E1STSEN + ECC 1-Bit Error Information Update Enable + 0 + 0 + read-write + + + 0 + Disables updating of the 1-bit ECC error information. + #0 + + + 1 + Enables updating of the 1-bit ECC error information. + #1 + + + + + + + ECC1STS + ECC 1-Bit Error Status Register + 0xC3 + 8 + read-write + 0x00 + 0xFF + + + ECC1ERR + ECC 1-Bit Error Status + 0 + 0 + read-write + zeroToClear + modify + + + 0 + No 1-bit ECC error occurred + #0 + + + 1 + 1-bit ECC error occurred + #1 + + + + + + + ECCPRCR + ECC Protection Register + 0xC4 + 8 + read-write + 0x00 + 0xFF + + + KW + Write Key Code + 1 + 7 + write-only + + + 1111000 + Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b. + #1111000 + + + others + Writing to the ECCRAMPRCR bit is invalid. + true + + + + + ECCPRCR + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to the protected registers + #0 + + + 1 + Enable writes to the protected registers + #1 + + + + + + + ECCPRCR2 + ECC Protection Register 2 + 0xD0 + 8 + read-write + 0x00 + 0xFF + + + KW2 + Write Key Code + 1 + 7 + write-only + + + 1111000 + These bits enable or disable writes to the ECCPRCR2 bit.. + #1111000 + + + others + Writing to the ECCRAMPRCR2 bit is invalid. + true + + + + + ECCPRCR2 + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to the protected registers + #0 + + + 1 + Enable writes to the protected registers. + #1 + + + + + + + ECCETST + ECC Test Control Register + 0xD4 + 8 + read-write + 0x00 + 0xFF + + + TSTBYP + ECC Bypass Select + 0 + 0 + read-write + + + 0 + ECC bypass disabled. + #0 + + + 1 + ECC bypass enabled. + #1 + + + + + + + ECCOAD + SRAM ECC Error Operation After Detection Register + 0xD8 + 8 + read-write + 0x00 + 0xFF + + + OAD + Operation after Detection + 0 + 0 + read-write + + + 0 + Non-maskable interrupt + #0 + + + 1 + Reset + #1 + + + + + + + SRAMPRCR2 + SRAM Protection Register 2 + 0x0C + 8 + read-write + 0x00 + 0xff + + + SRAMPRCR2 + Register Write Control + 0 + 0 + read-write + + + 0 + Disable writes to protected registers + #0 + + + 1 + Enable writes to protected registers + #1 + + + + + KW + Write Key Code + 1 + 7 + write-only + + + + + + + R_SRC + Sampling Rate Converter + 0x40048000 + + 0x00000000 + 0x56C0 + registers + + + 0x00005FF0 + 0x010 + registers + + + + 5552 + 0x4 + SRCFCTR[%s] + Filter Coefficient Table [%s] + 0x00 + 32 + read-write + 0x00000000 + 0xFFC00000 + + + SRCFCOE + Stores a filter coefficient value. + 0 + 21 + read-write + + + + + SRCID + Input Data Register + 0x5FF0 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + SRCID + SRCID is a 32-bit writ-only register that is used to input the data before sampling rate conversion. All the bits are read as 0. + 0 + 31 + write-only + + + + + SRCOD + Output Data Register + 0x5FF4 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + SRCOD + SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again. + 0 + 31 + read-only + + + + + SRCIDCTRL + Input Data Control Register + 0x5FF8 + 16 + read-write + 0x0000 + 0xFFFF + + + IED + Input Data Endian + 9 + 9 + read-write + + + 0 + Endian formats 1 are the same between the CPU and input data. + #0 + + + 1 + Endian formats 1 are different between the CPU and input data. + #1 + + + + + IEN + Input FIFO Empty Interrupt Enable + 8 + 8 + read-write + + + 0 + Input FIFO empty interrupt is disabled. + #0 + + + 1 + Input FIFO empty interrupt is enabled. + #1 + + + + + IFTRG + Input FIFO Data Triggering Number + 0 + 1 + read-write + + + 00 + 0 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + 6 + #11 + + + + + + + SRCCTRL + Control Register + 0x5FFC + 16 + read-write + 0x0000 + 0xFFFF + + + FICRAE + Filter Coefficient Table Access Enable + 15 + 15 + read-write + + + 0 + Reading/writing to filter coefficient table RAM is disabled. + #0 + + + 1 + Reading/writing to filter coefficient table RAM is enabled. + #1 + + + + + CEEN + Conversion End Interrupt Enable + 13 + 13 + read-write + + + 0 + Disables conversion end interrupt requests. + #0 + + + 1 + Enables conversion end interrupt requests. + #1 + + + + + SRCEN + Module Enable + 12 + 12 + read-write + + + 0 + Disables this module operation. + #0 + + + 1 + Enables this module operation. + #1 + + + + + UDEN + Output Data FIFO Underflow Interrupt Enable + 11 + 11 + read-write + + + 0 + Disables output data FIFO underflow interrupt requests. + #0 + + + 1 + Enables output data FIFO underflow interrupt requests. + #1 + + + + + OVEN + Output Data FIFO Overwrite Interrupt Enable + 10 + 10 + read-write + + + 0 + Output data FIFO overwrite interrupt is disabled. + #0 + + + 1 + Output data FIFO overwrite interrupt is enabled. + #1 + + + + + FL + Internal Work Memory Flush + 9 + 9 + read-write + + + 0 + no effect + #0 + + + 1 + starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory(i.e., flush processing). + #1 + + + + + CL + Internal Work Memory Clear + 8 + 8 + read-write + + + 0 + no effect + #0 + + + 1 + Clears the input FIFO, output FIFO, input buffer memory, intermediate memory and accumulator. + #1 + + + + + IFS + Input Sampling Rate + 4 + 7 + read-write + + + 0000 + 8.0 kHz + #0000 + + + 0001 + 11.025 kHz + #0001 + + + 0010 + 12.0 kHz + #0010 + + + 0011 + Setting prohibited + #0011 + + + 0100 + 16.0 kHz + #0100 + + + 0101 + 22.05 kHz + #0101 + + + 0110 + 24.0 kHz + #0110 + + + 0111 + Setting prohibited + #0111 + + + 1000 + 32.0 kHz + #1000 + + + 1001 + 44.1 kHz + #1001 + + + 1010 + 48.0 kHz + #1010 + + + others + Settings prohibited. + true + + + + + OFS + Output Sampling Rate + 0 + 2 + read-write + + + 000 + 44.1 kHz + #000 + + + 001 + 48.0 kHz + #001 + + + 010 + 32.0 kHz + #010 + + + 011 + Setting prohibited + #011 + + + 100 + 8.0 kHz ( Valid only when IFS[3:0] =1001b ) + #100 + + + 101 + 16.0 kHz ( Valid only when IFS[3:0] =1001b ) + #101 + + + others + Settings other than above are prohibited. + true + + + + + + + SRCODCTRL + Output Data Control Register + 0x5FFA + 16 + read-write + 0x0000 + 0xFFFF + + + OCH + Output Data Channel Exchange + 10 + 10 + read-write + + + 0 + Does not exchange the channels (the same order as data input) + #0 + + + 1 + Exchanges the channels (the opposite order from data input) + #1 + + + + + OED + Output Data Endian + 9 + 9 + read-write + + + 0 + Endian formats are the same between the chip and input data. + #0 + + + 1 + Endian formats are different between the chip and input data. + #1 + + + + + OEN + Output Data FIFO Full Interrupt Enable + 8 + 8 + read-write + + + 0 + Output data FIFO full interrupt is disabled. + #0 + + + 1 + Output data FIFO full interrupt is enabled. + #1 + + + + + OFTRG + Output FIFO Data Trigger Number + 0 + 1 + read-write + + + 00 + 1 + #00 + + + 01 + 4 + #01 + + + 10 + 8 + #10 + + + 11 + 12 + #11 + + + + + + + SRCSTAT + Status Register + 0x5FFE + 16 + read-write + 0x0002 + 0xFFFF + + + OFDN + Output FIFO Data CountIndicates the number of data units in the output FIFO. + 11 + 15 + read-write + + + IFDN + Input FIFO Data CountIndicates the number of data units in the input FIFO. + 7 + 10 + read-write + + + CEF + Conversion End Flag + 5 + 5 + read-write + zeroToClear + modify + + + 0 + All of the output data has not been read out. + #0 + + + 1 + All of the output data has been read out. + #1 + + + + + FLF + Flush Processing Status Flag + 4 + 4 + read-only + + + 0 + Flash processing is completed. + #0 + + + 1 + Flash processing is in progress. + #1 + + + + + UDF + Output FIFO Underflow Interrupt Request Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Output data FIFO has not been read out. + #0 + + + 1 + Output data FIFO has been read out. + #1 + + + + + OVF + Output Data FIFO Overwrite Interrupt Request Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Next data conversion processing is not completed. + #0 + + + 1 + Next data conversion processing is completed. + #1 + + + + + IINT + Input Data FIFO Empty Interrupt Request Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Number of data units in the input FIFO has not become equal to or smaller than the specified triggering number. + #0 + + + 1 + Number of data units in the input FIFO has become equal to or smaller than the specified triggering number. + #1 + + + + + OINT + Output Data FIFO Full Interrupt Request Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Number of data units in the output FIFO has not become equal to or greater than the specified triggering number. + #0 + + + 1 + Number of data units in the output FIFO has become equal to or greater than the specified triggering number. + #1 + + + + + + + + + R_SSI0 + Serial Sound Interface Enhanced (SSIE) + 0x4004E000 + + 0x00 + 8 + registers + + + 0x10 + 24 + registers + + + + SSICR + Control Register + 0x00 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + CKS + Oversampling Clock Select + 30 + 30 + read-write + + + 0 + AUDIO_CLK input + #0 + + + 1 + Setting prohibited + #1 + + + + + TUIEN + Transmit Underflow Interrupt Enable + 29 + 29 + read-write + + + 0 + Disables an underflow interrupt. + #0 + + + 1 + Enables an underflow interrupt. + #1 + + + + + TOIEN + Transmit Overflow Interrupt Enable + 28 + 28 + read-write + + + 0 + Disables an overflow interrupt. + #0 + + + 1 + Enables an overflow interrupt. + #1 + + + + + RUIEN + Receive Underflow Interrupt Enable + 27 + 27 + read-write + + + 0 + Disables an underflow interrupt. + #0 + + + 1 + Enables an underflow interrupt. + #1 + + + + + ROIEN + Receive Overflow Interrupt Enable + 26 + 26 + read-write + + + 0 + Disables an overflow interrupt. + #0 + + + 1 + Enables an overflow interrupt. + #1 + + + + + IIEN + Idle Mode Interrupt Enable + 25 + 25 + read-write + + + 0 + Disables an idle mode interrupt. + #0 + + + 1 + Enables an idle mode interrupt. + #1 + + + + + FRM + Channels + 22 + 23 + read-write + + + 00 + One channel + #00 + + + others + Settings other than above are prohibited. + true + + + + + DWL + Data Word Length + 19 + 21 + read-write + + + 000 + 8 bits + #000 + + + 001 + 16 bits + #001 + + + 010 + 18 bits + #010 + + + 011 + 20 bits + #011 + + + 100 + 22 bits + #100 + + + 101 + 24 bits + #101 + + + others + Settings other than above are prohibited. + true + + + + + SWL + System Word LengthSet the system word length to the bit clock frequency/2 fs. + 16 + 18 + read-write + + + 000 + 8 bits (serial bit clock frequency = 16fs ) + #000 + + + 001 + 16 bits (serial bit clock frequency = 32fs ) + #001 + + + 010 + 24 bits (serial bit clock frequency = 48fs ) + #010 + + + 011 + 32 bits (serial bit clock frequency = 64fs ) + #011 + + + others + Settings other than above are prohibited. + true + + + + + MST + Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited. + 14 + 14 + read-write + + + 0 + Serial word select is input, slave mode. + #0 + + + 1 + Serial word select is output, master mode. + #1 + + + + + BCKP + Serial Bit Clock Polarity + 13 + 13 + read-write + + + 0 + SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge). + #0 + + + 1 + SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge). + #1 + + + + + LRCKP + Serial WS Polarity + 12 + 12 + read-write + + + 0 + SSIWS is low for 1st channel, high for 2nd channel. + #0 + + + 1 + SSIWS is high for 1st channel, low for 2nd channel. + #1 + + + + + SPDP + Serial Padding Polarity + 11 + 11 + read-write + + + 0 + Padding bits are low. + #0 + + + 1 + Padding bits are high. + #1 + + + + + SDTA + Serial Data Alignment + 10 + 10 + read-write + + + 0 + Transmitting and receiving in the order of serial data and padding bits + #0 + + + 1 + Transmitting and receiving in the order of padding bits and serial data + #1 + + + + + PDTA + Parallel Data Alignment + 9 + 9 + read-write + + + 0 + The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits) + #0 + + + 1 + The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits) + #1 + + + + + DEL + Serial Data Delay + 8 + 8 + read-write + + + 0 + 1 clock cycle delay between SSIWS and SSIDATA + #0 + + + 1 + No delay between SSIWS and SSIDATA + #1 + + + + + CKDV + Serial Oversampling Clock Division Ratio + 4 + 7 + read-write + + + 0x0 + CLK + 0x0 + + + 0x1 + CLK/2 + 0x1 + + + 0x2 + CLK/4 + 0x2 + + + 0x3 + CLK/8 + 0x3 + + + 0x4 + CLK/16 + 0x4 + + + 0x5 + CLK/32 + 0x5 + + + 0x6 + CLK/64 + 0x6 + + + 0x7 + CLK/128 + 0x7 + + + 0x8 + CLK/6 + 0x8 + + + 0x9 + CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) + 0x9 + + + 0xA + CLK/24 + 0xA + + + 0xB + CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) + 0xB + + + 0xC + CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.) + 0xC + + + others + Settings other than above are prohibited. + true + + + + + MUEN + Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing. + 3 + 3 + read-write + + + 0 + This module is not muted. + #0 + + + 1 + This module is muted. + #1 + + + + + TEN + Transmit Enable + 1 + 1 + read-write + + + 0 + Disables the transmit operation. + #0 + + + 1 + Enables the transmit operation. + #1 + + + + + REN + Receive Enable + 0 + 0 + read-write + + + 0 + Disables the receive operation. + #0 + + + 1 + Enables the receive operation. + #1 + + + + + + + SSISR + Status Register + 0x04 + 32 + read-write + 0x02000013 + 0x3E00007F + + + TUIRQ + Transmit Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 29 + 29 + read-write + zeroToClear + modify + + + 0 + No transmit underflow has occurred. + #0 + + + 1 + A transmit underflow has occurred. + #1 + + + + + TOIRQ + Transmit Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 28 + 28 + read-write + zeroToClear + modify + + + 0 + No transmit overflow has occurred. + #0 + + + 1 + A transmit overflow has occurred. + #1 + + + + + RUIRQ + Receive Underflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 27 + 27 + read-write + zeroToClear + modify + + + 0 + No receive underflow has occurred. + #0 + + + 1 + A receive underflow has occurred. + #1 + + + + + ROIRQ + Receive Overflow Error Interrupt Status Flag NOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 26 + 26 + read-write + zeroToClear + modify + + + 0 + No receive overflow has occurred. + #0 + + + 1 + A receive overflow has occurred. + #1 + + + + + IIRQ + Idle Mode Interrupt Status Flag + 25 + 25 + read-only + + + 0 + This module is not in idle state. + #0 + + + 1 + This module is in idle state. + #1 + + + + + TCHNO + Transmit Channel Number + 5 + 6 + read-only + + + TSWNO + Transmit Serial Word Number + 4 + 4 + read-only + + + RCHNO + Receive Channel Number.These bits are read as 00b. + 2 + 3 + read-only + + + RSWNO + Receive Serial Word Number + 1 + 1 + read-only + + + IDST + Idle Mode Status Flag + 0 + 0 + read-only + + + 0 + Serial bus is operating. + #0 + + + 1 + The current communication is stopped. + #1 + + + + + + + SSIFCR + FIFO Control Register + 0x10 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AUCKE + Oversampling Clock Enable + 31 + 31 + read-write + + + 0 + The oversampling clock is disabled. + #0 + + + 1 + The oversampling clock is enabled. + #1 + + + + + SSIRST + SSI soft ware reset + 16 + 16 + read-write + + + 0 + Clears the SSI software reset. + #0 + + + 1 + initiates the SSI software reset. + #1 + + + + + TTRG + Transmit Data Trigger Number NOTE: The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set. + 6 + 7 + read-write + + + 00 + 7 (1) + #00 + + + 01 + 6 (2) + #01 + + + 10 + 4 (4) + #10 + + + 11 + 2 (6) + #11 + + + + + RTRG + Receive Data Trigger Number + 4 + 5 + read-write + + + 00 + 1 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + 6 + #11 + + + + + TIE + Transmit Interrupt Enable NOTE: TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit. + 3 + 3 + read-write + + + 0 + Transmit data empty interrupt (TXI) request is disabled + #0 + + + 1 + Transmit data empty interrupt (TXI) request is enabled + #1 + + + + + RIE + Receive Interrupt Enable NOTE: RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit. + 2 + 2 + read-write + + + 0 + Receive data full interrupt (RXI) request is disabled + #0 + + + 1 + Receive data full interrupt (RXI) request is enabled + #1 + + + + + TFRST + Transmit FIFO Data Register Reset + 1 + 1 + read-write + + + 0 + Clears the transmit data FIFO reset. + #0 + + + 1 + Initiates the transmit data FIFO reset. + #1 + + + + + RFRST + Receive FIFO Data Register Reset + 0 + 0 + read-write + + + 0 + Clears the receive data FIFO reset. + #0 + + + 1 + Initiates the receive data FIFO reset. + #1 + + + + + BSW + Byte Swap Enable + 11 + 11 + read-write + + + 0 + Disables byte swap + #0 + + + 1 + Enables byte swap + #1 + + + + + + + SSIFSR + FIFO Status Register + 0x14 + 32 + read-write + 0x00010000 + 0xFFFFFFFF + + + TDC + Transmit Data Indicate Flag(Indicates the number of data units stored in SSIFTDR) + 24 + 29 + read-only + + + TDE + Transmit Data Empty Flag NOTE: Since the SSIFTDR register is a 32-byte FIFO register, the maximum number of bytes that can be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If writing data to the SSIFTDR register is continued after all the data is written, writing will be invalid and an overflow occurs. + 16 + 16 + read-write + zeroToClear + modify + + + 0 + Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number. + #0 + + + 1 + Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number. + #1 + + + + + RDC + Receive Data Indicate Flag(Indicates the number of data units stored in SSIFRDR) + 8 + 13 + read-only + + + RDF + Receive Data Full Flag NOTE: Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Number of received data bytes in SSIFRDR is less than the set receive trigger number. + #0 + + + 1 + Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number. + #1 + + + + + + + SSIFTDR + Transmit FIFO Data Register + 0x18 + 32 + write-only + 0x00000000 + 0x00000000 + + + SSIFTDR + SSIFTDR is a write-only FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. NOTE: that when the SSIFTDR register is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs. + 0 + 31 + write-only + + + + + SSIFTDR16 + Transmit FIFO Data Register + SSIFTDR + 0x18 + 16 + write-only + 0x00000000 + 0x00000000 + + + SSIFTDR8 + Transmit FIFO Data Register + SSIFTDR + 0x18 + 8 + write-only + 0x00000000 + 0x00000000 + + + SSIFRDR + Receive FIFO Data Register + 0x1C + 32 + read-only + 0x00000000 + 0x00000000 + + + SSIFRDR + SSIFRDR is a read-only FIFO register consisting of eight stages of 32-bit registers for storing serially received data. + 0 + 31 + read-only + + + + + SSIFRDR16 + Receive FIFO Data Register + SSIFRDR + 0x1C + 16 + read-only + 0x00000000 + 0x00000000 + + + SSIFRDR8 + Receive FIFO Data Register + SSIFRDR + 0x1C + 8 + read-only + 0x00000000 + 0x00000000 + + + SSIOFR + Audio Format Register + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + BCKASTP + Whether to Enable Stopping BCK Output When SSIE is in Idle Status + 9 + 9 + read-write + + + 0 + Always outputs BCK to the SSIBCK pin. + #0 + + + 1 + Automatically controls output of BCK to the SSIBCK pin. + #1 + + + + + LRCONT + Whether to Enable LRCK/FS Continuation + 8 + 8 + read-write + + + 0 + Disables LRCK/FS continuation. + #0 + + + 1 + Enables LRCK/FS continuation. + #1 + + + + + OMOD + Audio Format Select + 0 + 1 + read-write + + + 00 + I2S format + #00 + + + 01 + TDM format + #01 + + + 10 + Monaural format + #10 + + + 11 + Setting prohibited. + #11 + + + + + + + SSISCR + Status Control Register + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + TDES + TDE Setting Condition Select + 8 + 12 + read-write + + + 00000 + SSIFTDR has one stage or more free space + #00000 + + + 00001 + SSIFTDR has two stages or more free space (snip) + #00001 + + + 11110 + SSIFTDR has thirty-one stages or more free space + #11110 + + + 11111 + SSIFTDR has thirty-two stages or more free space. + #11111 + + + + + RDFS + RDF Setting Condition Select + 0 + 4 + read-write + + + 00000 + SSIFRDR has one stage or more data size + #00000 + + + 00001 + SSIFRDR has two stages or more data size (snip) + #00001 + + + 11110 + SSIFRDR has thirty-one stages or more data size + #11110 + + + 11111 + SSIFRDR has thirty-two stages or more data size. + #11111 + + + + + + - R_SSI1 - Serial Sound Interface Enhanced (SSIE) - 0x4004E100 + R_SSI1 + Serial Sound Interface Enhanced (SSIE) + 0x4004E100 R_SYSTEM @@ -64021,48 +71768,4484 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - SBYCR - Standby Control Register - 0x00C - 16 + SBYCR + Standby Control Register + 0x00C + 16 + read-write + 0x4000 + 0xFFFF + + + SSBY + Software Standby + 15 + 15 + read-write + + + 0 + Sleep mode + #0 + + + 1 + Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1) + #1 + + + + + OPE + Output Port Enable + 14 + 14 + read-write + + + 0 + In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state. + #0 + + + 1 + In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state.. + #1 + + + + + + + MSTPCRA + Module Stop Control Register A + 0x01C + 32 + read-write + 0xFFBFFF1C + 0xFFFFFFFF + + + MSTPA22 + DMA Controller/Data Transfer Controller Module Stop + 22 + 22 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA7 + Standby RAM Module Stop + 7 + 7 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA6 + ECCRAM Module Stop + 6 + 6 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA5 + High-Speed RAM Module Stop + 5 + 5 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA1 + RAM1 Module Stop + 1 + 1 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + MSTPA0 + RAM0 Module Stop + 0 + 0 + read-write + + + 0 + Cancel the module-stop state + #0 + + + 1 + Enter the module-stop state + #1 + + + + + + + SCKDIVCR + System Clock Division Control Register + 0x020 + 32 + read-write + 0x22022222 + 0xFFFFFFFF + + + FCK + Flash IF Clock (FCLK) Select + 28 + 30 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + ICK + System Clock (ICLK) Select + 24 + 26 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + BCK + External Bus Clock (BCLK) Select + 16 + 18 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKA + Peripheral Module Clock A (PCLKA) Select + 12 + 14 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKB + Peripheral Module Clock B (PCLKB) Select + 8 + 10 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKC + Peripheral Module Clock C (PCLKC) Select + 4 + 6 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + PCKD + Peripheral Module Clock D (PCLKD) Select + 0 + 2 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + others + Setting prohibited + true + + + + + + + SCKDIVCR2 + System Clock Division Control Register 2 + 0x024 + 8 + read-write + 0x40 + 0xFF + + + UCK + USB Clock (UCLK) Select + 4 + 6 + read-write + + + 010 + /3 + #010 + + + 011 + /4 + #011 + + + 100 + /5 + #100 + + + others + Setting prohibited + true + + + + + + + SCKSCR + System Clock Source Control Register + 0x026 + 8 + read-write + 0x01 + 0xFF + + + CKSEL + Clock Source Select + 0 + 2 + read-write + + + 000 + HOCO + #000 + + + 001 + MOCO + #001 + + + 010 + LOCO + #010 + + + 011 + Main clock oscillator + #011 + + + 100 + Sub-clock oscillator + #100 + + + 101 + PLL + #101 + + + others + Setting prohibited + true + + + + + + + PLLCCR + PLL Clock Control Register + 0x028 + 16 + read-write + 0x1300 + 0xFFFF + + + PLLMUL + PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0 + 8 + 13 + read-write + + + #010011 + #111011 + + + + + others + Setting prohibited + true + + + + + PLSRCSEL + PLL Clock Source Select + 4 + 4 + read-write + + + 0 + Main clock oscillator + #0 + + + 1 + HOCO + #1 + + + + + PLIDIV + PLL Input Frequency Division Ratio Select + 0 + 1 + read-write + + + 00 + /1 + #00 + + + 01 + /2 + #01 + + + 10 + /3 + #10 + + + 11 + Setting prohibited + #11 + + + + + + + PLLCR + PLL Control Register + 0x02A + 8 + read-write + 0x01 + 0xFF + + + PLLSTP + PLL Stop Control + 0 + 0 + read-write + + + 0 + Operate the PLL + #0 + + + 1 + Stop the PLL. + #1 + + + + + + + PLLCCR2 + PLL Clock Control Register2 + 0x02B + 8 + read-write + 0x07 + 0xFF + + + PLODIV + PLL Output Frequency Division Ratio Select + 6 + 7 + read-write + + + 00 + /1. + #00 + + + 01 + /2. + #01 + + + 10 + /4. + #10 + + + 11 + Setting prohibited. + #11 + + + + + PLLMUL + PLL Frequency Multiplication Factor Select + 0 + 4 + read-write + + + 1111 + Settings prohibited. + #1111 + + + others + x PLLMUL[4:0] +1 + true + + + + + + + BCKCR + External Bus Clock Control Register + 0x030 + 8 + read-write + 0x00 + 0xFF + + + BCLKDIV + BCLK Pin Output Select + 0 + 0 + read-write + + + 0 + BCLK + #0 + + + 1 + BCLK/2 + #1 + + + + + + + MEMWAIT + Memory Wait Cycle Control Register + 0x031 + 8 + read-write + 0x00 + 0xFF + + + MEMWAIT + Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz). + 0 + 0 + read-write + + + 0 + no wait + #0 + + + 1 + wait + #1 + + + + + + + MOSCCR + Main Clock Oscillator Control Register + 0x032 + 8 + read-write + 0x01 + 0xFF + + + MOSTP + Main Clock Oscillator Stop + 0 + 0 + read-write + + + 0 + Main clock oscillator is operating. + #0 + + + 1 + Main clock oscillator is stopped. + #1 + + + + + + + HOCOCR + High-Speed On-Chip Oscillator Control Register + 0x036 + 8 + read-write + 0x00 + 0xFE + + + HCSTP + HOCO Stop + 0 + 0 + read-write + + + 0 + Operate the HOCO clock + #0 + + + 1 + Stop the HOCO clock + #1 + + + + + + + MOCOCR + Middle-Speed On-Chip Oscillator Control Register + 0x038 + 8 + read-write + 0x00 + 0xFF + + + MCSTP + MOCO Stop + 0 + 0 + read-write + + + 0 + Operate the MOCO clock + #0 + + + 1 + Stop the MOCO clock + #1 + + + + + + + FLLCR1 + FLL Control Register 1 + 0x039 + 8 + read-write + 0x00 + 0xFF + + + FLLEN + FLL Enable + 0 + 0 + read-write + + + 0 + FLL function is disabled. + #0 + + + 1 + FLL function is enabled. + #1 + + + + + + + FLLCR2 + FLL Control Register 2 + 0x03A + 16 + read-write + 0x0000 + 0xFFFF + + + FLLCNTL + FLL Multiplication ControlMultiplication ratio of the FLL reference clock select + 0 + 10 + read-write + + + + + OSCSF + Oscillation Stabilization Flag Register + 0x03C + 8 + read-only + 0x00 + 0xFE + + + PLLSF + PLL Clock Oscillation Stabilization Flag + 5 + 5 + read-only + + + 0 + PLL clock is stopped or is not yet stable + #0 + + + 1 + PLL clock is stable, so is available for use as the system clock + #1 + + + + + MOSCSF + Main Clock Oscillation Stabilization Flag + 3 + 3 + read-only + + + 0 + Main clock oscillator is stopped (MOSTP = 1) or is not yet stable + #0 + + + 1 + Main clock oscillator is stable, so is available for use as the system clock + #1 + + + + + HOCOSF + HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. + 0 + 0 + read-only + + + 0 + HOCO clock is stopped or is not yet stable + #0 + + + 1 + HOCO clock is stable, so is available for use as the system clock + #1 + + + + + PLL2SF + PLL2 Clock Oscillation Stabilization Flag + 6 + 6 + read-only + + + 0 + The PLL2 clock is stopped, or oscillation of the PLL2 clock is not stable yet + #0 + + + 1 + The PLL2 clock is stable, so is available for use as the system clock + #1 + + + + + + + CKOCR + Clock Out Control Register + 0x03E + 8 + read-write + 0x00 + 0xFF + + + CKOEN + Clock out enable + 7 + 7 + read-write + + + 0 + Disable clock out + #0 + + + 1 + Enable clock out + #1 + + + + + CKODIV + Clock out input frequency Division Select + 4 + 6 + read-write + + + 000 + /1 + #000 + + + 001 + /2 + #001 + + + 010 + /4 + #010 + + + 011 + /8 + #011 + + + 100 + /16 + #100 + + + 101 + /32 + #101 + + + 110 + /64 + #110 + + + 111 + /128 + #111 + + + + + CKOSEL + Clock out source select + 0 + 2 + read-write + + + 000 + HOCO + #000 + + + 001 + MOCO + #001 + + + 010 + LOCO + #010 + + + 011 + MOSC + #011 + + + 100 + SOSC + #100 + + + others + Setting prohibited + true + + + + + + + TRCKCR + Trace Clock Control Register + 0x03F + 8 + read-write + 0x01 + 0xFF + + + TRCKEN + Trace Clock operating Enable + 7 + 7 + read-write + + + 0 + Disable operation + #0 + + + 1 + Enable operation + #1 + + + + + TRCK + Trace Clock operating frequency select + 0 + 3 + read-write + + + 0000 + /1 + #0000 + + + 0001 + /2 + #0001 + + + 0010 + /4 + #0010 + + + others + Setting prohibited + true + + + + + + + OSTDCR + Oscillation Stop Detection Control Register + 0x040 + 8 + read-write + 0x00 + 0xFF + + + OSTDE + Oscillation Stop Detection Function Enable + 7 + 7 + read-write + + + 0 + Disable oscillation stop detection function + #0 + + + 1 + Enable oscillation stop detection function + #1 + + + + + OSTDIE + Oscillation Stop Detection Interrupt Enable + 0 + 0 + read-write + + + 0 + Disable oscillation stop detection interrupt (do not notify the POEG) + #0 + + + 1 + Enable oscillation stop detection interrupt (notify the POEG) + #1 + + + + + + + OSTDSR + Oscillation Stop Detection Status Register + 0x041 + 8 + read-write + 0x00 + 0xFF + + + OSTDF + Oscillation Stop Detection Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Main clock oscillation stop not detected + #0 + + + 1 + Main clock oscillation stop detected + #1 + + + + + + + SLCDSCKCR + Segment LCD Source Clock Control Register + 0x050 + 8 + read-write + 0x00 + 0xFF + + + LCDSCKEN + LCD Source Clock Out Enable + 7 + 7 + read-write + + + 0 + LCD source clock out disabled + #0 + + + 1 + LCD source clock out enabled. + #1 + + + + + LCDSCKSEL + LCD Source Clock (LCDSRCCLK) Select + 0 + 2 + read-write + + + 000 + LOCO + #000 + + + 001 + SOSC + #001 + + + 010 + MOSC + #010 + + + 100 + HOCO + #100 + + + others + Settings other than above are prohibited. + true + + + + + + + EBCKOCR + External Bus Clock Output Control Register + 0x052 + 8 + read-write + 0x00 + 0xFF + + + EBCKOEN + BCLK Pin Output Control + 0 + 0 + read-write + + + 0 + Disable EBCLK pin output (fixed high) + #0 + + + 1 + Enable EBCLK pin output + #1 + + + + + + + SDCKOCR + SDRAM Clock Output Control Register + 0x053 + 8 + read-write + 0x00 + 0xFF + + + SDCKOEN + SDCLK Pin Output Control + 0 + 0 + read-write + + + 0 + Disable SDCLK pin output (fixed high) + #0 + + + 1 + Enable SDCLK pin output + #1 + + + + + + + MOCOUTCR + MOCO User Trimming Control Register + 0x061 + 8 + read-write + 0x00 + 0xFF + + + MOCOUTRM + MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits + 0 + 7 + read-write + + + + + HOCOUTCR + HOCO User Trimming Control Register + 0x062 + 8 + read-write + 0x00 + 0xFF + + + HOCOUTRM + HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits + 0 + 7 + read-write + + + + + SNZCR + Snooze Control Register + 0x092 + 8 + read-write + 0x00 + 0xFF + + + SNZE + Snooze Mode Enable + 7 + 7 + read-write + + + 0 + Disable Snooze Mode + #0 + + + 1 + Enable Snooze Mode + #1 + + + + + SNZDTCEN + DTC Enable in Snooze Mode + 1 + 1 + read-write + + + 0 + Disable DTC operation + #0 + + + 1 + Enable DTC operation + #1 + + + + + RXDREQEN + RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. + 0 + 0 + read-write + + + 0 + Ignore RXD0 falling edge in Standby mode. + #0 + + + 1 + Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. + #1 + + + + + + + SNZEDCR + Snooze End Control Register + 0x094 + 8 + read-write + 0x00 + 0xFF + + + SCI0UMTED + SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode. + 7 + 7 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD1UMTED + AD compare mismatch 1 Snooze End Enable + 6 + 6 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD1MATED + AD compare match 1 Snooze End Enable + 5 + 5 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD0UMTED + AD compare mismatch 0 Snooze End Enable + 4 + 4 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AD0MATED + AD compare match 0 Snooze End Enable + 3 + 3 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + DTCNZRED + Not Last DTC transmission completion Snooze End Enable + 2 + 2 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + DTCZRED + Last DTC transmission completion Snooze End Enable + 1 + 1 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + AGT1UNFED + AGT1 underflow Snooze End Enable + 0 + 0 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + + + SNZREQCR + Snooze Request Control Register + 0x098 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + SNZREQEN30 + Snooze Request Enable 30Enable AGT1 compare match B snooze request + 30 + 30 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN29 + Snooze Request Enable 29Enable AGT1 compare match A snooze request + 29 + 29 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN28 + Snooze Request Enable 28Enable AGT1 underflow snooze request + 28 + 28 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN25 + Snooze Request Enable 25Enable RTC period snooze request + 25 + 25 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN24 + Snooze Request Enable 24Enable RTC alarm snooze request + 24 + 24 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN23 + Snooze Request Enable 23Enable Comparator-LP0 snooze request + 23 + 23 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN22 + Snooze Request Enable 22Enable Comparator-HS0 snooze request + 22 + 22 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + SNZREQEN17 + Snooze Request Enable 17Enable KR snooze request + 17 + 17 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + 16 + 1 + SNZREQEN%s + Snooze Request Enable 0Enable IRQ %s pin snooze request + 0 + 0 + read-write + + + 0 + Disable snooze request + #0 + + + 1 + Enable snooze request + #1 + + + + + + + FLSTOP + Flash Operation Control Register + 0x09E + 8 + read-write + 0x00 + 0xFF + + + FLSTPF + Flash Memory Operation Status Flag + 4 + 4 + read-write + + + 0 + Transition completed + #0 + + + 1 + During transition (from the flash-stop-status to flash-operating-status or vice versa) + #1 + + + + + FLSTOP + Selecting ON/OFF of the Flash Memory Operation + 0 + 0 + read-write + + + 0 + Code flash and data flash memory operates + #0 + + + 1 + Code flash and data flash memory stops. + #1 + + + + + + + PSMCR + Power Save Memory Control Register + 0x09F + 8 + read-write + 0x00 + 0xFF + + + PSMC + Power save memory control. + 0 + 1 + read-write + + + 00 + All RAM is on Software Standby mode. + #00 + + + 01 + 48KB RAM is on in Software Standby mode. + #01 + + + others + Setting prohibited. + true + + + + + + + OPCCR + Operating Power Control Register + 0x0A0 + 8 + read-write + 0x00 + 0xFF + + + OPCMTSF + Operating Power Control Mode Transition Status Flag + 4 + 4 + read-only + + + 0 + Transition completed + #0 + + + 1 + During transition + #1 + + + + + OPCM + Operating Power Control Mode Select + 0 + 1 + read-write + + + 00 + High-speed mode + #00 + + + 01 + Prohibited + #01 + + + 10 + Prohibited + #10 + + + 11 + Low-speed mode + #11 + + + others + Setting prohibited + true + + + + + + + SOPCCR + Sub Operating Power Control Register + 0x0AA + 8 + read-write + 0x00 + 0xFF + + + SOPCMTSF + Sub Operating Power Control Mode Transition Status Flag + 4 + 4 + read-only + + + 0 + Transition completed + #0 + + + 1 + During transition + #1 + + + + + SOPCM + Sub Operating Power Control Mode Select + 0 + 0 + read-write + + + 0 + Other than Subosc-speed mode + #0 + + + 1 + Subosc-speed mode + #1 + + + + + + + MOSCWTCR + Main Clock Oscillator Wait Control Register + 0x0A2 + 8 + read-write + 0x05 + 0xFF + + + MSTS + Main clock oscillator wait time setting + 0 + 3 + read-write + + + 0001 + Wait time = 35 cycles (133.5 us) + #0001 + + + 0010 + Wait time = 67 cycles (255.6 us) + #0010 + + + 0011 + Wait time = 131 cycles (499.7 us) + #0011 + + + 0100 + Wait time = 259 cycles (988.0 us) + #0100 + + + 0101 + Wait time = 547 cycles (2086.6 us) (value after reset) + #0101 + + + 0110 + Wait time = 1059 cycles (4039.8 us) + #0110 + + + 0111 + Wait time = 2147 cycles (8190.2 us) + #0111 + + + 1000 + Wait time = 4291 cycles (16368.9 us) + #1000 + + + 1001 + Wait time = 8163 cycles (31139.4 us). + #1001 + + + others + settings prohibited. + true + + + + + + + HOCOWTCR + High-speed on-chip oscillator wait control register + 0x0A5 + 8 + read-write + 0x02 + 0xFF + + + HSTS + HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) + 0 + 2 + read-write + + + + + RSTSR1 + Reset Status Register 1 + 0x0C0 + 16 + read-write + 0x0000 + 0xE0F8 + + + SPERF + SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 12 + 12 + read-write + zeroToClear + modify + + + 0 + SP error reset not detected. + #0 + + + 1 + SP error reset detected. + #1 + + + + + BUSMRF + Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 11 + 11 + read-write + zeroToClear + modify + + + 0 + Bus Master MPU reset not detected. + #0 + + + 1 + Bus Master MPU reset detected. + #1 + + + + + BUSSRF + Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 10 + 10 + read-write + zeroToClear + modify + + + 0 + Bus Slave MPU reset not detected. + #0 + + + 1 + Bus Slave MPU reset detected. + #1 + + + + + REERF + RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 9 + 9 + read-write + zeroToClear + modify + + + 0 + RAM ECC error reset not detected. + #0 + + + 1 + RAM ECC error reset detected. + #1 + + + + + RPERF + RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 8 + 8 + read-write + zeroToClear + modify + + + 0 + RAM parity error reset not detected. + #0 + + + 1 + RAM parity error reset detected. + #1 + + + + + SWRF + Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Software reset not detected. + #0 + + + 1 + Software reset detected. + #1 + + + + + WDTRF + Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Watchdog timer reset not detected. + #0 + + + 1 + Watchdog timer reset detected. + #1 + + + + + IWDTRF + Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Independent watchdog timer reset not detected. + #0 + + + 1 + Independent watchdog timer reset detected. + #1 + + + + + TZERF + Trust Zone Error Reset Detect Flag + 13 + 13 + read-write + + + 0 + Trust Zone error reset not detected. + #0 + + + 1 + TrustZone error reset detected. + #1 + + + + + CPERF + Cache Parity Error Reset Detect Flag + 15 + 15 + read-write + + + 0 + Cache Parity error reset not detected. + #0 + + + 1 + Cache Parity error reset detected. + #1 + + + + + + + STCONR + Standby Condition Register + 0x40F + 8 + read-write + 0xC3 + 0xFF + + + STCON + SSTBY condition bit + 0 + 1 + read-write + + + 00 + set this value in case of transferring to Software Standby Mode in using HOCO. + #00 + + + 11 + set this value in case of transferring to Software Standby Mode in using expect for HOCO. + #11 + + + + + + + 2 + 0x2 + 1,2 + LVD%sCR1 + Voltage Monitor %s Circuit Control Register 1 + 0x0E0 + 8 + read-write + 0x01 + 0xFF + + + IRQSEL + Voltage Monitor Interrupt Type Select + 2 + 2 + read-write + + + 0 + Non-maskable interrupt + #0 + + + 1 + Maskable interrupt + #1 + + + + + IDTSEL + Voltage Monitor Interrupt Generation Condition Select + 0 + 1 + read-write + + + 00 + Generate when VCC>=Vdet (rise) is detected + #00 + + + 01 + Generate when VCC<Vdet (drop) is detected + #01 + + + 10 + Generate when drop and rise are detected + #10 + + + 11 + Settings prohibited + #11 + + + + + + + USBCKCR_ALT + USB Clock Control Register + 0xD0 + 8 + read-write + 0x00 + 0xFF + + + USBCLKSEL + The USBCLKSEL bit selects the source of the USB clock (UCLK). + 0 + 0 + read-write + + + 0 + PLL + #0 + + + 1 + HOCO + #1 + + + + + + + SDADCCKCR + 24-bit Sigma-Delta A/D Converter Clock Control Register + 0xD1 + 8 + read-write + 0x00 + 0xFF + + + SDADCCKSEL + 24-bit Sigma-Delta A/D Converter Clock Select + 0 + 0 + read-write + + + 0 + MOSC is chosen by a source clock of 24-bit Sigma-Delta A/D Converter Clock. + #0 + + + 1 + HOCO is chosen by a source clock of 24-bit Sigma-Delta AA/D Converter Clock. + #1 + + + + + SDADCCKEN + 24-bit Sigma-Delta A/D Converter Clock Enable + 7 + 7 + read-write + + + 0 + 24-bit Sigma-Delta A/D Converter Clock is disabled + #0 + + + 1 + 24-bit Sigma-Delta A/D Converter Clock is enabled. + #1 + + + + + + + 2 + 0x2 + 1,2 + LVD%sSR + Voltage Monitor %s Circuit Status Register + 0x0E1 + 8 + read-write + 0x02 + 0xFF + + + MON + Voltage Monitor 1 Signal Monitor Flag + 1 + 1 + read-only + + + 0 + VCC < Vdet + #0 + + + 1 + VCC >= Vdet or MON bit is disabled + #1 + + + + + DET + Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Not detected + #0 + + + 1 + Vdet1 passage detection + #1 + + + + + + + PRCR + Protect Register + 0x3FE + 16 + read-write + 0x0000 + 0xFFFF + + + PRKEY + PRKEY Key Code + 8 + 15 + write-only + + + 0x5A + Enables writing to the PRCR register. + 0x5A + + + others + Disables writing to the PRCR register. + true + + + + + PRC3 + Enables writing to the registers related to the LVD. + 3 + 3 + read-write + + + 0 + Writes protected. + #0 + + + 1 + Writes not protected. + #1 + + + + + PRC1 + Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function. + 1 + 1 + read-write + + + 0 + Writes protected. + #0 + + + 1 + Writes not protected. + #1 + + + + + PRC0 + Enables writing to the registers related to the clock generation circuit. + 0 + 0 + read-write + + + 0 + Writes protected. + #0 + + + 1 + Writes not protected. + #1 + + + + + PRC4 + 4 + 4 + read-write + + + 0 + Write disabled + #0 + + + 1 + Write enabled + #1 + + + + + + + DPSIER0 + Deep Standby Interrupt Enable Register 0 + 0x402 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + DIRQ%sE + IRQ-DS Pin Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIER1 + Deep Standby Interrupt Enable Register 1 + 0x403 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + 8-15 + DIRQ%sE + IRQ-DS Pin Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIER2 + Deep Standby Interrupt Enable Register 2 + 0x404 + 8 + read-write + 0x00 + 0xFF + + + DNMIE + NMI Pin Enable + 4 + 4 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DRTCAIE + RTC Alarm interrupt Deep Standby Cancel Signal Enable + 3 + 3 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DTRTCIIE + RTC Interval interrupt Deep Standby Cancel Signal Enable + 2 + 2 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DLVD2IE + LVD2 Deep Standby Cancel Signal Enable + 1 + 1 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DLVD1IE + LVD1 Deep Standby Cancel Signal Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + + + DPSIER3 + Deep Standby Interrupt Enable Register 3 + 0x405 + 8 + read-write + 0x00 + 0xFF + + + DAGT1IE + AGT1 Underflow Deep Standby Cancel Signal Enable + 2 + 2 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DUSBHSIE + USBHS Suspend/Resume Deep Standby Cancel Signal Enable + 1 + 1 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DUSBFSIE + USBFS Suspend/Resume Deep Standby Cancel Signal Enable + 0 + 0 + read-write + + + 0 + Canceling deep software standby mode is disabled + #0 + + + 1 + Canceling deep software standby mode is enabled + #1 + + + + + DAGT3IE + AGT3 Underflow Deep Standby Cancel Signal Enable + 3 + 3 + read-write + + + 0 + Cancelling deep standby mode is disabled + #0 + + + 1 + Cancelling deep standby mode is enabled + #1 + + + + + + + DPSIFR0 + Deep Standby Interrupt Flag Register 0 + 0x406 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + DIRQ%sF + IRQ-DS Pin Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + DPSIFR1 + Deep Standby Interrupt Flag Register 1 + 0x407 + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + 8-15 + DIRQ%sF + IRQ-DS Pin Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + DPSIFR2 + Deep Standby Interrupt Flag Register 2 + 0x408 + 8 + read-write + 0x00 + 0xFF + + + DNMIF + NMI Pin Deep Standby Cancel Flag + 4 + 4 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DRTCAIF + RTC Alarm interrupt Deep Standby Cancel Flag + 3 + 3 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DTRTCIIF + RTC Interval interrupt Deep Standby Cancel Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DLVD2IF + LVD2 Deep Standby Cancel Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DLVD1IF + LVD1 Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + + + DPSIFR3 + Deep Standby Interrupt Flag Register 3 + 0x409 + 8 + read-write + 0x00 + 0xFF + + + DAGT1IF + AGT1 Underflow Deep Standby Cancel Flag + 2 + 2 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DUSBHSIF + USBHS Suspend/Resume Deep Standby Cancel Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DUSBFSIF + USBFS Suspend/Resume Deep Standby Cancel Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + The cancel request is not generated + #0 + + + 1 + The cancel request is generated + #1 + + + + + DAGT3IF + AGT3 Underflow Deep Standby Cancel Flag + 3 + 3 + read-write + + + 0 + The cancel request is not generated. + #0 + + + 1 + The cancel request is generated. + #1 + + + + + + + 2 + 1 + DPSIEGR%s + Deep Standby Interrupt Edge Register %s + 0x40A + 8 + read-write + 0x00 + 0xFF + + + 8 + 1 + DIRQ%sEG + IRQ-DS Pin Edge Select + 0 + 0 + read-write + + + 0 + A cancel request is generated at a falling edge + #0 + + + 1 + A cancel request is generated at a rising edge + #1 + + + + + + + DPSIEGR2 + Deep Standby Interrupt Edge Register 2 + 0x40C + 8 + read-write + 0x00 + 0xFF + + + DNMIEG + NMI Pin Edge Select + 4 + 4 + read-write + + + 0 + A cancel request is generated at a falling edge + #0 + + + 1 + A cancel request is generated at a rising edge + #1 + + + + + DLVD2IEG + LVD2 Edge Select + 1 + 1 + read-write + + + 0 + A cancel request is generated when VCC<Vdet2 (fall) is detected + #0 + + + 1 + A cancel request is generated when VCC>=Vdet2 (rise) is detected + #1 + + + + + DLVD1IEG + LVD1 Edge Select + 0 + 0 + read-write + + + 0 + A cancel request is generated when VCC<Vdet1 (fall) is detected + #0 + + + 1 + A cancel request is generated when VCC>=Vdet1 (rise) is detected + #1 + + + + + + + DPSBYCR + Deep Standby Control Register + 0x400 + 8 + read-write + 0x01 + 0xFF + + + DPSBY + Deep Software Standby + 7 + 7 + read-write + + + 0 + Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) + #0 + + + 1 + Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) + #1 + + + + + IOKEEP + I/O Port Retention + 6 + 6 + read-write + + + 0 + When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. + #0 + + + 1 + When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. + #1 + + + + + DEEPCUT + Power-Supply Control + 0 + 1 + read-write + + + 00 + Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. + #00 + + + 01 + Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode. + #01 + + + 10 + Setting prohibited. + #10 + + + 11 + Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. + #11 + + + + + + + SYOCDCR + System Control OCD Control Register + 0x40E + 8 + read-write + 0x00 + 0xFE + + + DBGEN + Debugger Enable bit + 7 + 7 + read-write + + + 0 + On-chip debugger is disabled + #0 + + + 1 + On-chip debugger is enabled + #1 + + + + + DOCDF + Deep Standby OCD flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + On-chip debugger is disabled + #0 + + + 1 + On-chip debugger is enabled + #1 + + + + + + + MOMCR + Main Clock Oscillator Mode Oscillation Control Register + 0x413 + 8 + read-write + 0x00 + 0xFF + + + AUTODRVEN + Main Clock Oscillator Drive Capability Auto Switching Enable + 7 + 7 + read-write + + + 0 + Disable + #0 + + + 1 + Enable. + #1 + + + + + MOSEL + Main Clock Oscillator Switching + 6 + 6 + read-write + + + 0 + Resonator + #0 + + + 1 + External clock input + #1 + + + + + MODRV0 + Main Clock Oscillator Drive Capability 0 Switching + 4 + 5 + read-write + + + 00 + 20MHz to 24MHz + #00 + + + 01 + 16MHz to 20MHz + #01 + + + 10 + 8MHz to 16MHz + #10 + + + 11 + 8MHz + #11 + + + + + MODRV1 + Main Clock Oscillator Drive Capability 1 Switching + 3 + 3 + read-write + + + 0 + 10 MHz to 20 MHz + #0 + + + 1 + 1 MHz to 10 MHz. + #1 + + + + + + + RSTSR0 + Reset Status Register 0 + 0x410 + 8 + read-write + 0x00 + 0x70 + + + DPSRSTF + Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 7 + 7 + read-write + zeroToClear + modify + + + 0 + Deep software standby mode cancelation not requested by an interrupt. + #0 + + + 1 + Deep software standby mode cancelation requested by an interrupt. + #1 + + + + + LVD2RF + Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 3 + 3 + read-write + zeroToClear + modify + + + 0 + Voltage Monitor 2 reset not detected. + #0 + + + 1 + Voltage Monitor 2 reset detected. + #1 + + + + + LVD1RF + Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 2 + 2 + read-write + zeroToClear + modify + + + 0 + Voltage Monitor 1 reset not detected. + #0 + + + 1 + Voltage Monitor 1 reset detected. + #1 + + + + + LVD0RF + Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 1 + 1 + read-write + zeroToClear + modify + + + 0 + Voltage Monitor 0 reset not detected. + #0 + + + 1 + Voltage Monitor 0 reset detected. + #1 + + + + + PORF + Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. + 0 + 0 + read-write + zeroToClear + modify + + + 0 + Power-on reset not detected. + #0 + + + 1 + Power-on reset detected. + #1 + + + + + + + RSTSR2 + Reset Status Register 2 + 0x411 + 8 + read-write + 0x00 + 0xFE + + + CWSF + Cold/Warm Start Determination Flag + 0 + 0 + read-write + oneToSet + modify + + + 0 + Cold start + #0 + + + 1 + Warm start + #1 + + + + + + + LVCMPCR + Voltage Monitor Circuit Control Register + 0x417 + 8 + read-write + 0x00 + 0xFF + + + LVD2E + Voltage Detection 2 Enable + 6 + 6 + read-write + + + 0 + Voltage detection 2 circuit disabled + #0 + + + 1 + Voltage detection 2 circuit enabled + #1 + + + + + LVD1E + Voltage Detection 1 Enable + 5 + 5 + read-write + + + 0 + Voltage detection 1 circuit disabled + #0 + + + 1 + Voltage detection 1 circuit enabled + #1 + + + + + + + LVD1CMPCR + Voltage Monitoring 1 Comparator Control Register + 0x417 + 8 + read-write + 0x13 + 0xff + + + LVD1LVL + Voltage Detection 1 Level Select (Standard voltage during drop in voltage) + 0 + 4 + read-write + + + 0x11 + 2.99 V (Vdet1_11) + 0x11 + + + 0x12 + 2.92 V (Vdet1_12) + 0x12 + + + 0x13 + 2.85 V (Vdet1_13) + 0x13 + + + Others + Setting prohibited + true + + + + + LVD1E + Voltage Detection 1 Enable + 7 + 7 + read-write + + + 0 + Voltage detection 1 circuit disabled + #0 + + + 1 + Voltage detection 1 circuit enabled + #1 + + + + + + + LVDLVLR + Voltage Detection Level Select Register + 0x418 + 8 + read-write + 0xF3 + 0xFF + + + LVD2LVL + Voltage Detection 2 Level Select (Standard voltage during fall in voltage) + 5 + 7 + read-write + + + 101 + 2.99V (Vdet2_1) + #101 + + + 110 + 2.92V (Vdet2_2) + #110 + + + 111 + 2.85V (Vdet2_3) + #111 + + + others + Settings other than above are prohibited. + true + + + + + LVD1LVL + Voltage Detection 1 Level Select (Standard voltage during fall in voltage) + 0 + 4 + read-write + + + 10001 + 2.99V (Vdet1_1) + #10001 + + + 10010 + 2.92V (Vdet1_2) + #10010 + + + 10011 + 2.85V (Vdet1_3) + #10011 + + + others + Settings other than above are prohibited. + true + + + + + + + LVD2CMPCR + Voltage Monitoring 2 Comparator Control Register + 0x418 + 8 + read-write + 0x07 + 0xff + + + LVD2LVL + Voltage Detection 2 Level Select (Standard voltage during drop in voltage) + 0 + 2 + read-write + + + 101 + 2.99 V (Vdet2_5) + #101 + + + 110 + 2.92 V (Vdet2_6) + #110 + + + 111 + 2.85 V (Vdet2_7) + #111 + + + Others + Setting prohibited + true + + + + + LVD2E + Voltage Detection 2 Enable + 7 + 7 + read-write + + + 0 + Voltage detection 2 circuit disabled + #0 + + + 1 + Voltage detection 2 circuit enabled + #1 + + + + + + + 2 + 0x1 + 1,2 + LVD%sCR0 + Voltage Monitor %s Circuit Control Register 0 + 0x41A + 8 + read-write + 0x8A + 0xF7 + + + RN + Voltage Monitor Reset Negate Select + 7 + 7 + read-write + + + 0 + Negation follows a stabilization time (tLVD) after VCC > Vdet is detected. + #0 + + + 1 + Negation follows a stabilization time (tLVD) after assertion of the LVD reset. + #1 + + + + + RI + Voltage Monitor Circuit Mode Select + 6 + 6 + read-write + + + 0 + Voltage Monitor interrupt during Vdet1 passage + #0 + + + 1 + Voltage Monitor reset enabled when the voltage falls to and below Vdet1 + #1 + + + + + FSAMP + Sampling Clock Select + 4 + 5 + read-write + + + 00 + 1/2 LOCO frequency + #00 + + + 01 + 1/4 LOCO frequency + #01 + + + 10 + 1/8 LOCO frequency + #10 + + + 11 + 1/16 LOCO frequency + #11 + + + + + CMPE + Voltage Monitor Circuit Comparison Result Output Enable + 2 + 2 + read-write + + + 0 + Disable voltage monitor 1 circuit comparison result output + #0 + + + 1 + Enable voltage monitor 1 circuit comparison result output. + #1 + + + + + DFDIS + Voltage Monitor Digital Filter Disable Mode Select + 1 + 1 + read-write + + + 0 + Enable digital filter + #0 + + + 1 + Disable digital filter + #1 + + + + + RIE + Voltage Monitor Interrupt/Reset Enable + 0 + 0 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + VBTCR1 + VBATT Control Register1 + 0x41F + 8 + read-write + 0x00 + 0xFF + + + BPWSWSTP + Battery Power supply Switch Stop + 0 + 0 + read-write + + + 0 + Battery Power supply Switch Enable + #0 + + + 1 + Battery Power supply Switch stop + #1 + + + + + + + SOSCCR + Sub-Clock Oscillator Control Register + 0x480 + 8 + read-write + 0x01 + 0xFF + + + SOSTP + Sub-Clock Oscillator Stop + 0 + 0 + read-write + + + 0 + Sub-clock oscillator is operating. + #0 + + + 1 + Sub-clock oscillator is stopped. + #1 + + + + + + + SOMCR + Sub Clock Oscillator Mode Control Register + 0x481 + 8 + read-write + 0x00 + 0xFF + + + SODRV + Sub-Clock Oscillator Drive Capability Switching + 0 + 1 + read-write + + + 00 + Normal mode + #00 + + + 01 + Low power mode 1 + #01 + + + 10 + Low power mode 2 + #10 + + + 11 + Low power mode 3. + #11 + + + + + + + LOCOCR + Low-Speed On-Chip Oscillator Control Register + 0x490 + 8 + read-write + 0x00 + 0xFF + + + LCSTP + LOCO Stop + 0 + 0 + read-write + + + 0 + LOCO is operating. + #0 + + + 1 + LOCO is stopped. + #1 + + + + + + + LOCOUTCR + LOCO User Trimming Control Register + 0x492 + 8 + read-write + 0x00 + 0xFF + + + LOCOUTRM + LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits + 0 + 7 + read-write + + + + + VBTCR2 + VBATT Control Register2 + 0x4B0 + 8 + read-write + 0x00 + 0xFF + + + VBTLVDLVL + VBATT Pin Voltage Low Voltage Detect Level Select Bit + 6 + 7 + read-write + + + 00 + 2.7V + #00 + + + 01 + Setting prohibited + #01 + + + 10 + 2.3V + #10 + + + 11 + 2.1V + #11 + + + + + VBTLVDEN + VBATT Pin Low Voltage Detect Enable Bit + 4 + 4 + read-write + + + 0 + VBATT pin low voltage detect disable + #0 + + + 1 + VBATT pin low voltage detect enable + #1 + + + + + + + VBTSR + VBATT Status Register + 0x4B1 + 8 + read-write + 0x01 + 0xEC + + + VBTRVLD + VBATT_R Valid + 4 + 4 + read-only + + + 0 + VBATT_R area not valid + #0 + + + 1 + VBATT_R area valid + #1 + + + + + VBTBLDF + VBATT Battery Low voltage Detect Flag + 1 + 1 + read-write + zeroToClear + modify + + + 0 + VBATT pin low voltage not detected + #0 + + + 1 + VBATT pin low voltage detected. + #1 + + + + + VBTRDF + VBAT_R Reset Detect Flag + 0 + 0 + read-write + zeroToClear + modify + + + 0 + VBATT_R voltage power-on reset not detected + #0 + + + 1 + VBATT_R selected voltage power-on reset detected. + #1 + + + + + + + VBTCMPCR + VBATT Comparator Control Register + 0x4B2 + 8 + read-write + 0x00 + 0xFF + + + VBTCMPE + VBATT pin low voltage detect circuit output enable + 0 + 0 + read-write + + + 0 + VBATT pin low voltage detect circuit output disabled + #0 + + + 1 + VBATT pin low voltage detect circuit output enabled + #1 + + + + + + + VBTLVDICR + VBATT Pin Low Voltage Detect Interrupt Control Register + 0x4B4 + 8 read-write - 0x4000 - 0xFFFF + 0x00 + 0xFF - SSBY - Software Standby - 15 - 15 + VBTLVDISEL + Pin Low Voltage Detect Interrupt Select bit + 1 + 1 read-write 0 - Sleep mode + Non Maskable Interrupt #0 1 - Software Standby mode (DPSBYCR.DPSBY=0) / Deep Software Standby mode (DPSBYCR.DPSBY=1) + Maskable Interrupt #1 - OPE - Output Port Enable - 14 - 14 + VBTLVDIE + VBATT Pin Low Voltage Detect Interrupt Enable bit + 0 + 0 read-write 0 - In software standby mode or deep software standby mode, the address bus and bus control signals are set to the high-impedance state. + VBATT Pin Low Voltage Detect Interrupt Disable #0 1 - In software standby mode or deep software standby mode, the address bus and bus control signals retain the output state.. + VBATT Pin Low Voltage Detect Interrupt Enable #1 @@ -64070,124 +76253,135 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - MSTPCRA - Module Stop Control Register A - 0x01C - 32 + VBTWCTLR + VBATT Wakeup function Control Register + 0x4B6 + 8 read-write - 0xFFBFFF1C - 0xFFFFFFFF + 0x00 + 0xFF - MSTPA22 - DMA Controller/Data Transfer Controller Module Stop - 22 - 22 + VWEN + VBATT wakeup enable + 0 + 0 read-write 0 - Cancel the module-stop state + Disable Wakeup function #0 1 - Enter the module-stop state + Enable Wakeup function #1 + + + + VBTWCH0OTSR + VBATT Wakeup I/O 0 Output Trigger Select Register + 0x4B8 + 8 + read-write + 0x00 + 0xFF + - MSTPA7 - Standby RAM Module Stop - 7 - 7 + CH0VAGTUTE + CH0 Output AGT(ch1) underflow Signal Enable + 5 + 5 read-write 0 - Cancel the module-stop state + VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is disabled #0 1 - Enter the module-stop state + VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is enabled #1 - MSTPA6 - ECCRAM Module Stop - 6 - 6 + CH0VRTCATE + VBATWIO0 Output RTC Alarm Signal Enable + 4 + 4 read-write 0 - Cancel the module-stop state + VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled #0 1 - Enter the module-stop state + VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled. #1 - MSTPA5 - High-Speed RAM Module Stop - 5 - 5 + CH0VRTCTE + VBATWIO0 Output RTC Periodic Signal Enable + 3 + 3 read-write 0 - Cancel the module-stop state + VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled #0 1 - Enter the module-stop state + VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled. #1 - MSTPA1 - RAM1 Module Stop - 1 - 1 + CH0VCH2TE + VBATWIO0 Output VBATWIO2 Trigger Enable + 2 + 2 read-write 0 - Cancel the module-stop state + VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled #0 1 - Enter the module-stop state + VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled. #1 - MSTPA0 - RAM0 Module Stop - 0 - 0 + CH0VCH1TE + VBATWIO0 Output VBATWIO1 Trigger Enable + 1 + 1 read-write 0 - Cancel the module-stop state + VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled #0 1 - Enter the module-stop state + VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled. #1 @@ -64195,557 +76389,529 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - SCKDIVCR - System Clock Division Control Register - 0x020 - 32 + VBTWCH1OTSR + VBATT Wakeup I/O 1 Output Trigger Select Register + 0x4B9 + 8 read-write - 0x22022222 - 0xFFFFFFFF + 0x00 + 0xFF - FCK - Flash IF Clock (FCLK) Select - 28 - 30 + CH1VAGTUTE + CH1 Output AGT(ch1) underflow Signal Enable + 5 + 5 read-write - 000 - /1 - #000 - - - 001 - /2 - #001 - - - 010 - /4 - #010 - - - 011 - /8 - #011 - - - 100 - /16 - #100 - - - 101 - /32 - #101 - - - 110 - /64 - #110 + 0 + VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is disabled + #0 - others - Setting prohibited - true + 1 + VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is enabled + #1 - ICK - System Clock (ICLK) Select - 24 - 26 + CH1VRTCATE + VBATWIO1 Output RTC Alarm Signal Enable + 4 + 4 read-write - 000 - /1 - #000 - - - 001 - /2 - #001 - - - 010 - /4 - #010 - - - 011 - /8 - #011 - - - 100 - /16 - #100 - - - 101 - /32 - #101 - - - 110 - /64 - #110 + 0 + VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled + #0 - others - Setting prohibited - true + 1 + VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled. + #1 - BCK - External Bus Clock (BCLK) Select - 16 - 18 + CH1VRTCTE + VBATWIO1 Output RTC Periodic Signal Enable + 3 + 3 read-write - 000 - /1 - #000 - - - 001 - /2 - #001 - - - 010 - /4 - #010 - - - 011 - /8 - #011 - - - 100 - /16 - #100 - - - 101 - /32 - #101 - - - 110 - /64 - #110 + 0 + VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled + #0 - others - Setting prohibited - true + 1 + VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled + #1 - PCKA - Peripheral Module Clock A (PCLKA) Select - 12 - 14 + CH1VCH2TE + VBATWIO1 Output VBATWIO2 Trigger Enable + 2 + 2 read-write - 000 - /1 - #000 - - - 001 - /2 - #001 - - - 010 - /4 - #010 - - - 011 - /8 - #011 - - - 100 - /16 - #100 - - - 101 - /32 - #101 - - - 110 - /64 - #110 + 0 + VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled + #0 - others - Setting prohibited - true + 1 + VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled. + #1 - PCKB - Peripheral Module Clock B (PCLKB) Select - 8 - 10 + CH1VCH0TE + VBATWIO1 Output VBATWIO0 Trigger Enable + 0 + 0 read-write - 000 - /1 - #000 - - - 001 - /2 - #001 - - - 010 - /4 - #010 - - - 011 - /8 - #011 - - - 100 - /16 - #100 + 0 + VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled + #0 - 101 - /32 - #101 + 1 + VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled. + #1 + + + + + + VBTWCH2OTSR + VBATT Wakeup I/O 2 Output Trigger Select Register + 0x4BA + 8 + read-write + 0x00 + 0xFF + + + CH2VAGTUTE + CH2 Output AGT(CH2) underflow Signal Enable + 5 + 5 + read-write + - 110 - /64 - #110 + 0 + VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is disabled + #0 - others - Setting prohibited - true + 1 + VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is enabled + #1 - PCKC - Peripheral Module Clock C (PCLKC) Select + CH2VRTCATE + VBATWIO2 Output RTC Alarm Signal Enable 4 - 6 + 4 read-write - 000 - /1 - #000 + 0 + VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled + #0 - 001 - /2 - #001 + 1 + VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled. + #1 + + + + CH2VRTCTE + VBATWIO2 Output RTC Periodic Signal Enable + 3 + 3 + read-write + - 010 - /4 - #010 + 0 + VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled + #0 - 011 - /8 - #011 + 1 + VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled. + #1 + + + + CH2VCH1TE + VBATWIO2 Output VBATWIO1 Trigger Enable + 1 + 1 + read-write + - 100 - /16 - #100 + 0 + VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled + #0 - 101 - /32 - #101 + 1 + VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled. + #1 + + + + CH2VCH0TE + VBATWIO2 Output VBATWIO0 Trigger Enable + 0 + 0 + read-write + - 110 - /64 - #110 + 0 + VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled + #0 - others - Setting prohibited - true + 1 + VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled. + #1 + + + + VBTICTLR + VBATT Input Control Register + 0x4BB + 8 + read-write + 0x00 + 0xF8 + - PCKD - Peripheral Module Clock D (PCLKD) Select - 0 + VCH2INEN + RTCIC2 Input Enable + 2 2 read-write - 000 - /1 - #000 - - - 001 - /2 - #001 - - - 010 - /4 - #010 + 0 + Disabled + #0 - 011 - /8 - #011 + 1 + Enabled + #1 + + + + VCH1INEN + RTCIC1 Input Enable + 1 + 1 + read-write + - 100 - /16 - #100 + 0 + Disabled + #0 - 101 - /32 - #101 + 1 + Enabled + #1 + + + + VCH0INEN + RTCIC0 Input Enable + 0 + 0 + read-write + - 110 - /64 - #110 + 0 + Disabled + #0 - others - Setting prohibited - true + 1 + Enabled + #1 - SCKDIVCR2 - System Clock Division Control Register 2 - 0x024 + VBTOCTLR + VBATT Output Control Register + 0x4BC 8 read-write - 0x40 + 0x00 0xFF - UCK - USB Clock (UCLK) Select - 4 - 6 + VOUT2LSEL + VBATT Wakeup I/O 2 Output Level Selection + 5 + 5 read-write - 010 - /3 - #010 + 0 + Output L before VBATT wake up trigger + #0 - 011 - /4 - #011 + 1 + Output H before VBATT wake up trigger + #1 + + + + VCOU1LSEL + VBATT Wakeup I/O 1 Output Level Selection + 4 + 4 + read-write + - 100 - /5 - #100 + 0 + Output L before VBATT wake up trigger + #0 - others - Setting prohibited - true + 1 + Output H before VBATT wake up trigger + #1 - - - - SCKSCR - System Clock Source Control Register - 0x026 - 8 - read-write - 0x01 - 0xFF - - CKSEL - Clock Source Select - 0 - 2 + VOUT0LSEL + VBATT Wakeup I/O 0 Output Level Selection + 3 + 3 read-write - 000 - HOCO - #000 + 0 + Output L before VBATT wakeup trigger + #0 - 001 - MOCO - #001 + 1 + Output H before VBATT wakeup trigger + #1 + + + + VCH2OEN + VBATT Wakeup I/O 2 Output Enable + 2 + 2 + read-write + - 010 - LOCO - #010 + 0 + VBATWIO2 output disabled + #0 - 011 - Main clock oscillator - #011 + 1 + VBATWIO2 output enabled + #1 + + + + VCH1OEN + VBATT Wakeup I/O 1 Output Enable + 1 + 1 + read-write + - 100 - Sub-clock oscillator - #100 + 0 + VBATWIO1 output disabled + #0 - 101 - PLL - #101 + 1 + VBATWIO1 output enabled + #1 + + + + + VCH0OEN + VBATT Wakeup I/O 0 Output Enable + 0 + 0 + read-write + + + 0 + VBATWIO0 output disabled + #0 - others - Setting prohibited - true + 1 + VBATWIO0 output enabled + #1 - PLLCCR - PLL Clock Control Register - 0x028 - 16 + VBTWTER + VBATT Wakeup Trigger source Enable Register + 0x4BD + 8 read-write - 0x1300 - 0xFFFF + 0x00 + 0xFF - PLLMUL - PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 111011: x30.0 - 8 - 13 + VAGTUE + AGT(ch1) underflow Signal Enable + 5 + 5 read-write - - - #010011 - #111011 - - - others - Setting prohibited - true + 0 + VBATT wakeup triggered by the AGT(ch1) underflow signal is disabled + #0 + + + 1 + VBATT wakeup triggered by the AGT(ch1) underflow signal is enabled + #1 - PLSRCSEL - PLL Clock Source Select + VRTCAE + RTC Alarm Signal Enable 4 4 read-write 0 - Main clock oscillator + VBATT wakeup triggered by RTC alarm signal is disabled #0 1 - HOCO + VBATT wakeup triggered by RTC alarm signal is enabled. #1 - PLIDIV - PLL Input Frequency Division Ratio Select - 0 - 1 + VRTCIE + RTC Periodic Signal Enable + 3 + 3 read-write - 00 - /1 - #00 + 0 + VBATT wakeup triggered by RTC periodic signal is disabled + #0 - 01 - /2 - #01 + 1 + VBATT wakeup triggered by RTC periodic signal is enabled. + #1 + + + + VCH2E + VBATWIO2 Pin Enable + 2 + 2 + read-write + - 10 - /3 - #10 + 0 + VBATT wakeup triggered by the VBATWIO2 pin is disabled + #0 - 11 - Setting prohibited - #11 + 1 + VBATT wakeup triggered by the VBATWIO2 pin is enabled. + #1 - - - - PLLCR - PLL Control Register - 0x02A - 8 - read-write - 0x01 - 0xFF - - PLLSTP - PLL Stop Control + VCH1E + VBATWIO1 Pin Enable + 1 + 1 + read-write + + + 0 + VBATT wakeup triggered by the VBATWIO1 pin is disabled + #0 + + + 1 + VBATT wakeup triggered by the VBATWIO1 pin is enabled. + #1 + + + + + VCH0E + VBATWIO0 Pin Enable 0 0 read-write 0 - Operate the PLL + VBATT wakeup triggered by the VBATWIO0 pin is disabled #0 1 - Stop the PLL. + VBATT wakeup triggered by the VBATWIO0 pin is enabled. #1 @@ -64753,238 +76919,204 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - PLLCCR2 - PLL Clock Control Register2 - 0x02B + VBTWEGR + VBATT Wakeup Trigger source Edge Register + 0x4BE 8 read-write - 0x07 + 0x00 0xFF - PLODIV - PLL Output Frequency Division Ratio Select - 6 - 7 + VCH2EG + VBATWIO2 Wakeup Trigger Source Edge Select + 2 + 2 read-write - 00 - /1. - #00 + 0 + Wakeup trigger is generated at a falling edge + #0 - 01 - /2. - #01 + 1 + Wakeup trigger is generated at a rising edge. + #1 + + + + VCH1EG + VBATWIO1 Wakeup Trigger Source Edge Select + 1 + 1 + read-write + - 10 - /4. - #10 + 0 + Wakeup trigger is generated at a falling edge + #0 - 11 - Setting prohibited. - #11 + 1 + Wakeup trigger is generated at a rising edge. + #1 - PLLMUL - PLL Frequency Multiplication Factor Select + VCH0EG + VBATWIO0 Wakeup Trigger Source Edge Select 0 - 4 + 0 read-write - 1111 - Settings prohibited. - #1111 + 0 + Wakeup trigger is generated at a falling edge + #0 - others - x PLLMUL[4:0] +1 - true + 1 + Wakeup trigger is generated at a rising edge. + #1 - BCKCR - External Bus Clock Control Register - 0x030 + VBTWFR + VBATT Wakeup trigger source Flag Register + 0x4BF 8 read-write 0x00 0xFF - BCLKDIV - BCLK Pin Output Select - 0 - 0 + VAGTUF + AGT(ch1) underflow VBATT Wakeup Trigger Flag + 5 + 5 read-write + zeroToClear + modify 0 - BCLK + No wakeup trigger by the AGT(ch1) underflow is generated #0 1 - BCLK/2 + A wakeup trigger by the AGT(ch1) underflow is generated #1 - - - - MEMWAIT - Memory Wait Cycle Control Register - 0x031 - 8 - read-write - 0x00 - 0xFF - - MEMWAIT - Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz). - 0 - 0 + VRTCAF + VBATT RTC-Alarm Wakeup Trigger Flag + 4 + 4 read-write + zeroToClear + modify 0 - no wait + No wakeup trigger by the RTC alarm is generated #0 1 - wait + A wakeup trigger by the RTC alarm is generated #1 - - - - MOSCCR - Main Clock Oscillator Control Register - 0x032 - 8 - read-write - 0x01 - 0xFF - - MOSTP - Main Clock Oscillator Stop - 0 - 0 + VRTCIF + VBATT RTC-Interval Wakeup Trigger Flag + 3 + 3 read-write + zeroToClear + modify 0 - Main clock oscillator is operating. + No wakeup trigger by the RTC interval is generated #0 1 - Main clock oscillator is stopped. + A wakeup trigger by the RTC interval is generated #1 - - - - HOCOCR - High-Speed On-Chip Oscillator Control Register - 0x036 - 8 - read-write - 0x00 - 0xFE - - HCSTP - HOCO Stop - 0 - 0 + VCH2F + VBATWIO2 Wakeup Trigger Flag + 2 + 2 read-write + zeroToClear + modify 0 - Operate the HOCO clock + No wakeup trigger by the VBATWIO2 pin is generated #0 1 - Stop the HOCO clock + A wakeup trigger by the VBATWIO2 pin is generated #1 - - - - MOCOCR - Middle-Speed On-Chip Oscillator Control Register - 0x038 - 8 - read-write - 0x00 - 0xFF - - MCSTP - MOCO Stop - 0 - 0 + VCH1F + VBATWIO1 Wakeup Trigger Flag + 1 + 1 read-write + zeroToClear + modify 0 - Operate the MOCO clock + No wakeup trigger by the VBATWIO1 pin is generated #0 1 - Stop the MOCO clock + A wakeup trigger by the VBATWIO1 pin is generated #1 - - - - FLLCR1 - FLL Control Register 1 - 0x039 - 8 - read-write - 0x00 - 0xFF - - FLLEN - FLL Enable + VCH0F + VBATWIO0 Wakeup Trigger Flag 0 0 read-write + zeroToClear + modify 0 - FLL function is disabled. + No wakeup trigger by the VBATWIO0 pin is generated #0 1 - FLL function is enabled. + A wakeup trigger by the VBATWIO0 pin is generated #1 @@ -64992,203 +77124,245 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - FLLCR2 - FLL Control Register 2 - 0x03A - 16 + 512 + 0x1 + VBTBKR[%s] + VBATT Backup Register [%s] + 0x500 + 8 read-write - 0x0000 - 0xFFFF + 0x00 + 0x00 - FLLCNTL - FLL Multiplication ControlMultiplication ratio of the FLL reference clock select + VBTBKR + VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 - 10 + 7 read-write - OSCSF - Oscillation Stabilization Flag Register - 0x03C + FWEPROR + Flash P/E Protect Register + 0x416 8 - read-only - 0x00 - 0xFE + read-write + 0x02 + 0xFF - PLLSF - PLL Clock Oscillation Stabilization Flag - 5 - 5 - read-only + FLWE + Flash Programming and Erasure + 0 + 1 + read-write - 0 - PLL clock is stopped or is not yet stable - #0 + 00 + Prohibits programming and erasure of the code flash, data flash or blank checking. + #00 - 1 - PLL clock is stable, so is available for use as the system clock - #1 + 01 + Permits programming and erasure of the code flash, data flash or blank checking. + #01 + + + 10 + Prohibits programming and erasure of the code flash, data flash or blank checking. + #10 + + + 11 + Prohibits programming and erasure of the code flash, data flash or blank checking. + #11 + + + + PLL2CCR + PLL2 Clock Control Register + 0x048 + 16 + read-write + 0x1300 + 0xffff + - MOSCSF - Main Clock Oscillation Stabilization Flag - 3 - 3 - read-only + PL2IDIV + PLL2 Input Frequency Division Ratio Select + 0 + 1 + read-write - 0 - Main clock oscillator is stopped (MOSTP = 1) or is not yet stable - #0 + 00 + ∕ 1 (value after reset) + #00 - 1 - Main clock oscillator is stable, so is available for use as the system clock - #1 + 01 + ∕ 2 + #01 + + + 10 + ∕ 3 + #10 + + + Others + Setting prohibited. + true - HOCOSF - HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. - 0 - 0 - read-only + PL2SRCSEL + PLL2 Clock Source Select + 4 + 4 + read-write 0 - HOCO clock is stopped or is not yet stable + Main clock oscillator #0 1 - HOCO clock is stable, so is available for use as the system clock + HOCO. #1 + + PLL2MUL + PLL2 Frequency Multiplication Factor Select + 8 + 13 + read-write + - CKOCR - Clock Out Control Register - 0x03E + PLL2CR + PLL2 Control Register + 0x04A 8 read-write - 0x00 - 0xFF + 0x01 + 0xff - CKOEN - Clock out enable - 7 - 7 + PLL2STP + PLL2 Stop Control + 0 + 0 read-write 0 - Disable clock out + PLL2 is operating #0 1 - Enable clock out + PLL2 is stopped. #1 + + + + USBCKDIVCR + USB Clock Division Control Register + 0x06C + 8 + read-write + 0x00 + 0xff + - CKODIV - Clock out input frequency Division Select - 4 - 6 + USBCKDIV + USB Clock (USBCLK) Division Select + 0 + 2 read-write - - 000 - /1 - #000 - - - 001 - /2 - #001 - 010 - /4 + ∕ 4 #010 - - 011 - /8 - #011 - - - 100 - /16 - #100 - 101 - /32 + ∕ 3 #101 110 - /64 + ∕ 5 #110 - 111 - /128 - #111 + Others + Setting prohibited. + true + + + + OCTACKDIVCR + Octal-SPI Clock Division Control Register + 0x06D + 8 + read-write + 0x00 + 0xff + - CKOSEL - Clock out source select + OCTACKDIV + Octal-SPI Clock (OCTACLK) Division Select 0 2 read-write 000 - HOCO + ∕ 1 (value after reset) #000 001 - MOCO + ∕ 2 #001 010 - LOCO + ∕ 4 #010 011 - MOSC + ∕ 6 #011 100 - SOSC + ∕ 8 #100 - others - Setting prohibited + Others + Setting prohibited. true @@ -65196,139 +77370,72 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - TRCKCR - Trace Clock Control Register - 0x03F + USBCKCR + USB Clock Control Register + 0x074 8 read-write 0x01 - 0xFF + 0xff - TRCKEN - Trace Clock operating Enable - 7 - 7 - read-write - - - 0 - Disable operation - #0 - - - 1 - Enable operation - #1 - - - - - TRCK - Trace Clock operating frequency select + USBCKSEL + USB Clock (USBCLK) Source Select 0 - 3 + 2 read-write - 0000 - /1 - #0000 - - - 0001 - /2 - #0001 + 101 + PLL + #101 - 0010 - /4 - #0010 + 110 + PLL2 + #110 - others - Setting prohibited + Others + Setting prohibited. true - - - - OSTDCR - Oscillation Stop Detection Control Register - 0x040 - 8 - read-write - 0x00 - 0xFF - - - OSTDE - Oscillation Stop Detection Function Enable - 7 - 7 - read-write - - - 0 - Disable oscillation stop detection function - #0 - - - 1 - Enable oscillation stop detection function - #1 - - - - OSTDIE - Oscillation Stop Detection Interrupt Enable - 0 - 0 + USBCKSREQ + USB Clock (USBCLK) Switching Request + 6 + 6 read-write 0 - Disable oscillation stop detection interrupt (do not notify the POEG) + No request #0 1 - Enable oscillation stop detection interrupt (notify the POEG) + Request switching. #1 - - - - OSTDSR - Oscillation Stop Detection Status Register - 0x041 - 8 - read-write - 0x00 - 0xFF - - OSTDF - Oscillation Stop Detection Flag - 0 - 0 - read-write - zeroToClear - modify + USBCKSRDY + USB Clock (USBCLK) Switching Ready state flag + 7 + 7 + read-only 0 - Main clock oscillation stop not detected + Impossible to Switch #0 1 - Main clock oscillation stop detected + Possible to Switch #1 @@ -65336,123 +77443,97 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - SLCDSCKCR - Segment LCD Source Clock Control Register - 0x050 + OCTACKCR + Octal-SPI Clock Control Register + 0x075 8 read-write - 0x00 - 0xFF + 0x01 + 0xff - LCDSCKEN - LCD Source Clock Out Enable - 7 - 7 - read-write - - - 0 - LCD source clock out disabled - #0 - - - 1 - LCD source clock out enabled. - #1 - - - - - LCDSCKSEL - LCD Source Clock (LCDSRCCLK) Select + OCTACKSEL + Octal-SPI Clock (OCTACLK) Source Select 0 2 read-write 000 - LOCO + HOCO #000 001 - SOSC + MOCO (value after reset) #001 010 - MOSC + LOCO #010 + + 011 + Main clock oscillator + #011 + 100 - HOCO + Sub-clock oscillator #100 - others - Settings other than above are prohibited. + 101 + PLL + #101 + + + 110 + PLL2 + #110 + + + Others + Setting prohibited. true - - - - EBCKOCR - External Bus Clock Output Control Register - 0x052 - 8 - read-write - 0x00 - 0xFF - - EBCKOEN - BCLK Pin Output Control - 0 - 0 + OCTACKSREQ + Octal-SPI Clock (OCTACLK) Switching Request + 6 + 6 read-write 0 - Disable EBCLK pin output (fixed high) + No request #0 1 - Enable EBCLK pin output + Request switching. #1 - - - - SDCKOCR - SDRAM Clock Output Control Register - 0x053 - 8 - read-write - 0x00 - 0xFF - - SDCKOEN - SDCLK Pin Output Control - 0 - 0 - read-write + OCTACKSRDY + Octal-SPI Clock (OCTACLK) Switching Ready state flag + 7 + 7 + read-only 0 - Disable SDCLK pin output (fixed high) + Switching not possible #0 1 - Enable SDCLK pin output + Switching possible. #1 @@ -65460,103 +77541,67 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - MOCOUTCR - MOCO User Trimming Control Register - 0x061 - 8 - read-write - 0x00 - 0xFF - - - MOCOUTRM - MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits - 0 - 7 - read-write - - - - - HOCOUTCR - HOCO User Trimming Control Register - 0x062 - 8 + SNZREQCR1 + Snooze Request Control Register 1 + 0x088 + 32 read-write - 0x00 - 0xFF + 0x00000000 + 0xffffffff - HOCOUTRM - HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits + SNZREQEN0 + Enable AGT3 underflow snooze request 0 - 7 - read-write - - - - - SNZCR - Snooze Control Register - 0x092 - 8 - read-write - 0x00 - 0xFF - - - SNZE - Snooze Mode Enable - 7 - 7 + 0 read-write 0 - Disable Snooze Mode + Disable the snooze request #0 1 - Enable Snooze Mode + Enable the snooze request #1 - SNZDTCEN - DTC Enable in Snooze Mode + SNZREQEN1 + Enable AGT3 underflow snooze request 1 1 read-write 0 - Disable DTC operation + Disable the snooze request #0 1 - Enable DTC operation + Enable the snooze request #1 - RXDREQEN - RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. - 0 - 0 + SNZREQEN2 + Enable AGT3 underflow snooze request + 2 + 2 read-write 0 - Ignore RXD0 falling edge in Standby mode. + Disable the snooze request #0 1 - Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. + Enable the snooze request #1 @@ -65564,810 +77609,731 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - SNZEDCR - Snooze End Control Register - 0x094 + SNZEDCR1 + Snooze End Control Register 1 + 0x095 8 read-write 0x00 - 0xFF + 0xff - SCI0UMTED - SCI0 address unmatch Snooze End EnableNote: Do not set to 1 other than in asynchronous mode. - 7 - 7 + AGT3UNFED + AGT3 underflow Snooze End Enable + 0 + 0 + read-write + + + 0 + Disable the Snooze End request + #0 + + + 1 + Enable the Snooze End request + #1 + + + + + + + CGFSAR + Clock Generation Function Security Attribute Register + 0x3C0 + 32 + read-write + 0xffffffff + 0xffffffff + + + NONSEC00 + Non Secure Attribute bit 00 + 0 + 0 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - AD1UMTED - AD compare mismatch 1 Snooze End Enable - 6 - 6 + NONSEC02 + Non Secure Attribute bit 02 + 2 + 2 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - AD1MATED - AD compare match 1 Snooze End Enable - 5 - 5 + NONSEC03 + Non Secure Attribute bit 03 + 3 + 3 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - AD0UMTED - AD compare mismatch 0 Snooze End Enable + NONSEC04 + Non Secure Attribute bit 04 4 4 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - AD0MATED - AD compare match 0 Snooze End Enable - 3 - 3 + NONSEC05 + Non Secure Attribute bit 05 + 5 + 5 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - DTCNZRED - Not Last DTC transmission completion Snooze End Enable - 2 - 2 + NONSEC06 + Non Secure Attribute bit 06 + 6 + 6 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - DTCZRED - Last DTC transmission completion Snooze End Enable - 1 - 1 + NONSEC07 + Non Secure Attribute bit 07 + 7 + 7 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - AGT1UNFED - AGT1 underflow Snooze End Enable - 0 - 0 + NONSEC08 + Non Secure Attribute bit 08 + 8 + 8 read-write 0 - Disable the Snooze End request + Secure #0 1 - Enable the Snooze End request + Non Secure #1 - - - - SNZREQCR - Snooze Request Control Register - 0x098 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - SNZREQEN30 - Snooze Request Enable 30Enable AGT1 compare match B snooze request - 30 - 30 + NONSEC09 + Non Secure Attribute bit 09 + 9 + 9 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - SNZREQEN29 - Snooze Request Enable 29Enable AGT1 compare match A snooze request - 29 - 29 + NONSEC11 + Non Secure Attribute bit 11 + 11 + 11 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - SNZREQEN28 - Snooze Request Enable 28Enable AGT1 underflow snooze request - 28 - 28 + NONSEC12 + Non Secure Attribute bit 12 + 12 + 12 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - SNZREQEN25 - Snooze Request Enable 25Enable RTC period snooze request - 25 - 25 + NONSEC16 + Non Secure Attribute bit 16 + 16 + 16 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - SNZREQEN24 - Snooze Request Enable 24Enable RTC alarm snooze request - 24 - 24 + NONSEC17 + Non Secure Attribute bit 17 + 17 + 17 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 + + + + LPMSAR + Low Power Mode Security Attribution Register + 0x3C8 + 32 + read-write + 0xffffffff + 0xffffffff + - SNZREQEN23 - Snooze Request Enable 23Enable Comparator-LP0 snooze request - 23 - 23 + NONSEC0 + Non Secure Attribute bit 0 + 0 + 0 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - SNZREQEN22 - Snooze Request Enable 22Enable Comparator-HS0 snooze request - 22 - 22 + NONSEC2 + Non Secure Attribute bit 2 + 2 + 2 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - SNZREQEN17 - Snooze Request Enable 17Enable KR snooze request - 17 - 17 + NONSEC4 + Non Secure Attribute bit 4 + 4 + 4 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - 16 - 1 - SNZREQEN%s - Snooze Request Enable 0Enable IRQ %s pin snooze request - 0 - 0 + NONSEC8 + Non Secure Attribute bit 8 + 8 + 8 read-write 0 - Disable snooze request + Secure #0 1 - Enable snooze request + Non Secure #1 - - - - FLSTOP - Flash Operation Control Register - 0x09E - 8 - read-write - 0x00 - 0xFF - - FLSTPF - Flash Memory Operation Status Flag - 4 - 4 + NONSEC9 + Non Secure Attribute bit 9 + 9 + 9 read-write 0 - Transition completed + Secure #0 1 - During transition (from the flash-stop-status to flash-operating-status or vice versa) + Non Secure #1 + + + + LVDSAR + Low Voltage Detection Security Attribution Register + 0x3CC + 32 + read-write + 0xffffffff + 0xffffffff + - FLSTOP - Selecting ON/OFF of the Flash Memory Operation + NONSEC0 + Non Secure Attribute bit 0 0 0 read-write 0 - Code flash and data flash memory operates + Secure #0 1 - Code flash and data flash memory stops. + Non Secure #1 - - - - PSMCR - Power Save Memory Control Register - 0x09F - 8 - read-write - 0x00 - 0xFF - - PSMC - Power save memory control. - 0 + NONSEC1 + Non Secure Attribute bit 1 + 1 1 read-write - 00 - All RAM is on Software Standby mode. - #00 - - - 01 - 48KB RAM is on in Software Standby mode. - #01 + 0 + Secure + #0 - others - Setting prohibited. - true + 1 + Non Secure + #1 - OPCCR - Operating Power Control Register - 0x0A0 - 8 + RSTSAR + Reset Security Attribution Register + LVDSAR + 0x3CC + 32 read-write - 0x00 - 0xFF + 0xffffffff + 0xffffffff - OPCMTSF - Operating Power Control Mode Transition Status Flag - 4 - 4 - read-only + NONSEC0 + Non Secure Attribute bit 0 + 0 + 0 + read-write 0 - Transition completed + Secure #0 1 - During transition + Non Secure #1 - OPCM - Operating Power Control Mode Select - 0 + NONSEC1 + Non Secure Attribute bit 1 + 1 1 read-write - 00 - High-speed mode - #00 - - - 01 - Prohibited - #01 + 0 + Secure + #0 - 10 - Prohibited - #10 + 1 + Non Secure + #1 + + + + NONSEC2 + Non Secure Attribute bit 2 + 2 + 2 + read-write + - 11 - Low-speed mode - #11 + 0 + Secure + #0 - others - Setting prohibited - true + 1 + Non Secure + #1 - SOPCCR - Sub Operating Power Control Register - 0x0AA - 8 + BBFSAR + Battery Backup Function Security Attribute Register + 0x3D0 + 32 read-write - 0x00 - 0xFF + 0x0000ffff + 0xffffffff - SOPCMTSF - Sub Operating Power Control Mode Transition Status Flag - 4 - 4 - read-only + NONSEC0 + Non Secure Attribute bit 0 + 0 + 0 + read-write 0 - Transition completed + Secure #0 1 - During transition + Non Secure #1 - SOPCM - Sub Operating Power Control Mode Select - 0 - 0 + NONSEC1 + Non Secure Attribute bit 1 + 1 + 1 read-write 0 - Other than Subosc-speed mode + Secure #0 1 - Subosc-speed mode + Non Secure #1 - - - - MOSCWTCR - Main Clock Oscillator Wait Control Register - 0x0A2 - 8 - read-write - 0x05 - 0xFF - - MSTS - Main clock oscillator wait time setting - 0 - 3 + NONSEC2 + Non Secure Attribute bit 2 + 2 + 2 read-write - 0001 - Wait time = 35 cycles (133.5 us) - #0001 - - - 0010 - Wait time = 67 cycles (255.6 us) - #0010 - - - 0011 - Wait time = 131 cycles (499.7 us) - #0011 - - - 0100 - Wait time = 259 cycles (988.0 us) - #0100 - - - 0101 - Wait time = 547 cycles (2086.6 us) (value after reset) - #0101 - - - 0110 - Wait time = 1059 cycles (4039.8 us) - #0110 - - - 0111 - Wait time = 2147 cycles (8190.2 us) - #0111 - - - 1000 - Wait time = 4291 cycles (16368.9 us) - #1000 - - - 1001 - Wait time = 8163 cycles (31139.4 us). - #1001 + 0 + Secure + #0 - others - settings prohibited. - true + 1 + Non Secure + #1 - - - - HOCOWTCR - High-speed on-chip oscillator wait control register - 0x0A5 - 8 - read-write - 0x02 - 0xFF - - - HSTS - HOCO wait time settingWaiting time (sec) = setting of the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) - 0 - 2 - read-write - - - - - RSTSR1 - Reset Status Register 1 - 0x0C0 - 16 - read-write - 0x0000 - 0xE0F8 - - SPERF - SP Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 12 - 12 + NONSEC16 + Non Secure Attribute bit 16 + 16 + 16 read-write - zeroToClear - modify 0 - SP error reset not detected. + Secure #0 1 - SP error reset detected. + Non Secure #1 - BUSMRF - Bus Master MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 11 - 11 + NONSEC17 + Non Secure Attribute bit 17 + 17 + 17 read-write - zeroToClear - modify 0 - Bus Master MPU reset not detected. + Secure #0 1 - Bus Master MPU reset detected. + Non Secure #1 - BUSSRF - Bus Slave MPU Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 10 - 10 + NONSEC18 + Non Secure Attribute bit 18 + 18 + 18 read-write - zeroToClear - modify 0 - Bus Slave MPU reset not detected. + Secure #0 1 - Bus Slave MPU reset detected. + Non Secure #1 - REERF - RAM ECC Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 9 - 9 + NONSEC19 + Non Secure Attribute bit 19 + 19 + 19 read-write - zeroToClear - modify 0 - RAM ECC error reset not detected. + Secure #0 1 - RAM ECC error reset detected. + Non Secure #1 - RPERF - RAM Parity Error Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 8 - 8 + NONSEC20 + Non Secure Attribute bit 20 + 20 + 20 read-write - zeroToClear - modify 0 - RAM parity error reset not detected. + Secure #0 1 - RAM parity error reset detected. + Non Secure #1 - SWRF - Software Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 2 - 2 + NONSEC21 + Non Secure Attribute bit 21 + 21 + 21 read-write - zeroToClear - modify 0 - Software reset not detected. + Secure #0 1 - Software reset detected. + Non Secure #1 - WDTRF - Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 1 - 1 + NONSEC22 + Non Secure Attribute bit 22 + 22 + 22 read-write - zeroToClear - modify 0 - Watchdog timer reset not detected. + Secure #0 1 - Watchdog timer reset detected. + Non Secure #1 - IWDTRF - Independent Watchdog Timer Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 0 - 0 + NONSEC23 + Non Secure Attribute bit 23 + 23 + 23 read-write - zeroToClear - modify 0 - Independent watchdog timer reset not detected. + Secure #0 1 - Independent watchdog timer reset detected. + Non Secure #1 @@ -66375,550 +78341,466 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - STCONR - Standby Condition Register - 0x40F - 8 + DPFSAR + Deep Standby Interrupt Factor Security Attribution Register + 0x3E0 + 32 read-write - 0xC3 - 0xFF + 0xffffffff + 0xffffffff - STCON - SSTBY condition bit + DPFSA0 + Deep Standby Interrupt Factor Security Attribute bit 0 0 - 1 + 0 read-write - 00 - set this value in case of transferring to Software Standby Mode in using HOCO. - #00 + 0 + Secure + #0 - 11 - set this value in case of transferring to Software Standby Mode in using expect for HOCO. - #11 + 1 + Non Secure + #1 + + + + + DPFSA1 + Deep Standby Interrupt Factor Security Attribute bit 1 + 1 + 1 + read-write + + + 0 + Secure + #0 + + + 1 + Non Secure + #1 - - - - 2 - 0x2 - 1,2 - LVD%sCR1 - Voltage Monitor %s Circuit Control Register 1 - 0x0E0 - 8 - read-write - 0x01 - 0xFF - - IRQSEL - Voltage Monitor Interrupt Type Select + DPFSA2 + Deep Standby Interrupt Factor Security Attribute bit 2 2 2 read-write 0 - Non-maskable interrupt + Secure #0 1 - Maskable interrupt + Non Secure #1 - IDTSEL - Voltage Monitor Interrupt Generation Condition Select - 0 - 1 + DPFSA3 + Deep Standby Interrupt Factor Security Attribute bit 3 + 3 + 3 read-write - 00 - Generate when VCC>=Vdet (rise) is detected - #00 + 0 + Secure + #0 - 01 - Generate when VCC<Vdet (drop) is detected - #01 + 1 + Non Secure + #1 + + + + DPFSA4 + Deep Standby Interrupt Factor Security Attribute bit 4 + 4 + 4 + read-write + - 10 - Generate when drop and rise are detected - #10 + 0 + Secure + #0 - 11 - Settings prohibited - #11 + 1 + Non Secure + #1 - - - - USBCKCR - USB Clock Control Register - 0xD0 - 8 - read-write - 0x00 - 0xFF - - USBCLKSEL - The USBCLKSEL bit selects the source of the USB clock (UCLK). - 0 - 0 + DPFSA5 + Deep Standby Interrupt Factor Security Attribute bit 5 + 5 + 5 read-write 0 - PLL + Secure #0 1 - HOCO + Non Secure #1 - - - - SDADCCKCR - 24-bit Sigma-Delta A/D Converter Clock Control Register - 0xD1 - 8 - read-write - 0x00 - 0xFF - - SDADCCKSEL - 24-bit Sigma-Delta A/D Converter Clock Select - 0 - 0 + DPFSA6 + Deep Standby Interrupt Factor Security Attribute bit 6 + 6 + 6 read-write 0 - MOSC is chosen by a source clock of 24-bit Sigma-Delta A/D Converter Clock. + Secure #0 1 - HOCO is chosen by a source clock of 24-bit Sigma-Delta AA/D Converter Clock. + Non Secure #1 - SDADCCKEN - 24-bit Sigma-Delta A/D Converter Clock Enable + DPFSA7 + Deep Standby Interrupt Factor Security Attribute bit 7 7 7 read-write 0 - 24-bit Sigma-Delta A/D Converter Clock is disabled + Secure #0 1 - 24-bit Sigma-Delta A/D Converter Clock is enabled. + Non Secure #1 - - - - 2 - 0x2 - 1,2 - LVD%sSR - Voltage Monitor %s Circuit Status Register - 0x0E1 - 8 - read-write - 0x02 - 0xFF - - MON - Voltage Monitor 1 Signal Monitor Flag - 1 - 1 - read-only + DPFSA8 + Deep Standby Interrupt Factor Security Attribute bit 8 + 8 + 8 + read-write 0 - VCC < Vdet + Secure #0 1 - VCC >= Vdet or MON bit is disabled + Non Secure #1 - DET - Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. - 0 - 0 + DPFSA9 + Deep Standby Interrupt Factor Security Attribute bit 9 + 9 + 9 read-write - zeroToClear - modify 0 - Not detected + Secure #0 1 - Vdet1 passage detection + Non Secure #1 - - - - PRCR - Protect Register - 0x3FE - 16 - read-write - 0x0000 - 0xFFFF - - PRKEY - PRKEY Key Code - 8 - 15 - write-only + DPFSA10 + Deep Standby Interrupt Factor Security Attribute bit 10 + 10 + 10 + read-write - 0x5A - Enables writing to the PRCR register. - 0x5A + 0 + Secure + #0 - others - Disables writing to the PRCR register. - true + 1 + Non Secure + #1 - PRC3 - Enables writing to the registers related to the LVD. - 3 - 3 + DPFSA11 + Deep Standby Interrupt Factor Security Attribute bit 11 + 11 + 11 read-write 0 - Writes protected. + Secure #0 1 - Writes not protected. + Non Secure #1 - PRC1 - Enables writing to the registers related to the operating modes, the low power consumption modes and the battery backup function. - 1 - 1 + DPFSA12 + Deep Standby Interrupt Factor Security Attribute bit 12 + 12 + 12 read-write 0 - Writes protected. + Secure #0 1 - Writes not protected. + Non Secure #1 - PRC0 - Enables writing to the registers related to the clock generation circuit. - 0 - 0 + DPFSA13 + Deep Standby Interrupt Factor Security Attribute bit 13 + 13 + 13 read-write 0 - Writes protected. + Secure #0 1 - Writes not protected. + Non Secure #1 - - - - DPSIER0 - Deep Standby Interrupt Enable Register 0 - 0x402 - 8 - read-write - 0x00 - 0xFF - - 8 - 1 - DIRQ%sE - IRQ-DS Pin Enable - 0 - 0 + DPFSA14 + Deep Standby Interrupt Factor Security Attribute bit 14 + 14 + 14 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - - - - DPSIER1 - Deep Standby Interrupt Enable Register 1 - 0x403 - 8 - read-write - 0x00 - 0xFF - - 8 - 1 - 8-15 - DIRQ%sE - IRQ-DS Pin Enable - 0 - 0 + DPFSA15 + Deep Standby Interrupt Factor Security Attribute bit 15 + 15 + 15 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - - - - DPSIER2 - Deep Standby Interrupt Enable Register 2 - 0x404 - 8 - read-write - 0x00 - 0xFF - - DNMIE - NMI Pin Enable - 4 - 4 + DPFSA16 + Deep Standby Interrupt Factor Security Attribute bit 16 + 16 + 16 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - DRTCAIE - RTC Alarm interrupt Deep Standby Cancel Signal Enable - 3 - 3 + DPFSA17 + Deep Standby Interrupt Factor Security Attribute bit 17 + 17 + 17 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - DTRTCIIE - RTC Interval interrupt Deep Standby Cancel Signal Enable - 2 - 2 + DPFSA18 + Deep Standby Interrupt Factor Security Attribute bit 18 + 18 + 18 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - DLVD2IE - LVD2 Deep Standby Cancel Signal Enable - 1 - 1 + DPFSA19 + Deep Standby Interrupt Factor Security Attribute bit 19 + 19 + 19 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - DLVD1IE - LVD1 Deep Standby Cancel Signal Enable - 0 - 0 + DPFSA20 + Deep Standby Interrupt Factor Security Attribute bit 20 + 20 + 20 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - - - - DPSIER3 - Deep Standby Interrupt Enable Register 3 - 0x405 - 8 - read-write - 0x00 - 0xFF - - DAGT1IE - AGT1 Underflow Deep Standby Cancel Signal Enable - 2 - 2 + DPFSA24 + Deep Standby Interrupt Factor Security Attribute bit 24 + 24 + 24 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - DUSBHSIE - USBHS Suspend/Resume Deep Standby Cancel Signal Enable - 1 - 1 + DPFSA26 + Deep Standby Interrupt Factor Security Attribute bit 26 + 26 + 26 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 - DUSBFSIE - USBFS Suspend/Resume Deep Standby Cancel Signal Enable - 0 - 0 + DPFSA27 + Deep Standby Interrupt Factor Security Attribute bit 27 + 27 + 27 read-write 0 - Canceling deep software standby mode is disabled + Secure #0 1 - Canceling deep software standby mode is enabled + Non Secure #1 @@ -66926,68 +78808,64 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - DPSIFR0 - Deep Standby Interrupt Flag Register 0 - 0x406 + DPSWCR + Deep Standby Wait Control Register + 0x401 8 read-write - 0x00 - 0xFF + 0x19 + 0xff - 8 - 1 - DIRQ%sF - IRQ-DS Pin Deep Standby Cancel Flag + WTSTS + Deep Software Wait Standby Time Setting Bit 0 - 0 + 5 read-write - zeroToClear - modify - 0 - The cancel request is not generated - #0 + 0x0E + Wait cycle for fast recovery + 0x0e - 1 - The cancel request is generated - #1 + 0x19 + Wait cycle for slow recovery + 0x19 + + + Others + Setting prohibited + true - DPSIFR1 - Deep Standby Interrupt Flag Register 1 - 0x407 + VBATTMNSELR + Battery Backup Voltage Monitor Function Select Register + 0x41D 8 read-write 0x00 - 0xFF + 0xff - 8 - 1 - 8-15 - DIRQ%sF - IRQ-DS Pin Deep Standby Cancel Flag + VBATTMNSEL + VBATT Low Voltage Detect Function Select Bit 0 0 read-write - zeroToClear - modify 0 - The cancel request is not generated + Disables VBATT low voltage detect function #0 1 - The cancel request is generated + Enables VBATT low voltage detect function #1 @@ -66995,517 +78873,687 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - DPSIFR2 - Deep Standby Interrupt Flag Register 2 - 0x408 + VBATTMONR + Battery Backup Voltage Monitor Register + 0x41E 8 - read-write + read-only 0x00 - 0xFF + 0xff - DNMIF - NMI Pin Deep Standby Cancel Flag - 4 - 4 - read-write - zeroToClear - modify + VBATTMON + VBATT Voltage Monitor Bit + 0 + 0 + read-only 0 - The cancel request is not generated + VBATT ≥ Vbattldet #0 1 - The cancel request is generated + VBATT < Vbattldet #1 + + + + VBTBER + VBATT Backup Enable Register + 0x4C0 + 8 + read-write + 0x08 + 0xff + - DRTCAIF - RTC Alarm interrupt Deep Standby Cancel Flag + VBAE + VBATT backup register access enable bit 3 3 read-write - zeroToClear - modify 0 - The cancel request is not generated + Disable to access VBTBKR #0 1 - The cancel request is generated + Enable to access VBTBKR #1 + + + + + + R_TSN + Temperature Sensor + 0x407EC000 + + 0x00000228 + 0x002 + registers + + + + TSCDRH + Temperature Sensor Calibration Data Register H + 0x229 + 8 + read-only + 0x00 + 0x00 + - DTRTCIIF - RTC Interval interrupt Deep Standby Cancel Flag - 2 - 2 - read-write - zeroToClear - modify - - - 0 - The cancel request is not generated - #0 - - - 1 - The cancel request is generated - #1 - - + TSCDRH + The calibration data stores the higher 8 bits of the convertedvalue. + 0 + 7 + read-only + + + + TSCDRL + Temperature Sensor Calibration Data Register L + 0x228 + 8 + read-only + 0x00 + 0x00 + - DLVD2IF - LVD2 Deep Standby Cancel Flag - 1 - 1 - read-write - zeroToClear - modify - - - 0 - The cancel request is not generated - #0 - - - 1 - The cancel request is generated - #1 - - + TSCDRL + The calibration data stores the lower 8 bits of the convertedvalue. + 0 + 7 + read-only + + + + + + R_TSN_CAL + Temperature Sensor + 0x407FB17C + + 0x00 + 0x04 + registers + + + + TSCDR + Temperature Sensor 32 bit Calibration Data Register + 0x00 + 32 + read-only + 0x00 + 0x00 + - DLVD1IF - LVD1 Deep Standby Cancel Flag + TSCDR + The 32 bit TSCDR register stores temperature sensor calibration converted value. 0 - 0 - read-write - zeroToClear - modify - - - 0 - The cancel request is not generated - #0 - - - 1 - The cancel request is generated - #1 - - + 31 + read-only + + + + R_TSN_CTRL + Temperature Sensor + 0x4005D000 + + 0x00 + 1 + registers + + - DPSIFR3 - Deep Standby Interrupt Flag Register 3 - 0x409 + TSCR + Temperature Sensor Control Register + 0x00 8 read-write 0x00 0xFF - DAGT1IF - AGT1 Underflow Deep Standby Cancel Flag - 2 - 2 - read-write - zeroToClear - modify - - - 0 - The cancel request is not generated - #0 - - - 1 - The cancel request is generated - #1 - - - - - DUSBHSIF - USBHS Suspend/Resume Deep Standby Cancel Flag - 1 - 1 + TSEN + Temperature Sensor Output Enable + 7 + 7 read-write - zeroToClear - modify 0 - The cancel request is not generated + Stops the temperature sensor. #0 1 - The cancel request is generated + Starts the temperature sensor. #1 - DUSBFSIF - USBFS Suspend/Resume Deep Standby Cancel Flag - 0 - 0 + TSOE + Temperature Sensor Enable + 4 + 4 read-write - zeroToClear - modify 0 - The cancel request is not generated + Disables output from the temperature sensor to the 12-bit A/D converter. #0 1 - The cancel request is generated + Enables output from the temperature sensor to the 12-bit A/D converter. #1 + + + + R_USB_FS0 + USB 2.0 Module + 0x40090000 + + 0x00000000 + 0x00A + registers + + + 0x0000000C + 0x02 + registers + + + 0x00000014 + 0x010 + registers + + + 0x00000028 + 0x00C + registers + + + 0x00000036 + 0x00E + registers + + + 0x00000046 + 0x00C + registers + + + 0x00000054 + 0x00E + registers + + + 0x00000064 + 0x02 + registers + + + 0x00000068 + 0x02 + registers + + + 0x0000006C + 0x016 + registers + + + 0x00000090 + 0x014 + registers + + + 0x000000B0 + 0x02 + registers + + + 0x000000C4 + 0x02 + registers + + + 0x000000CC + 0x02 + registers + + + 0x000000D0 + 0x014 + registers + + + 0x000000F0 + 0x04 + registers + + + 0x00000100 + 0x004 + registers + + + 0x00000140 + 0x02 + registers + + + 0x00000144 + 0x008 + registers + + + 0x00000160 + 0x00C + registers + + + 0x00000400 + 0x008 + registers + + + + 5 + 0x004 + PIPE_TR[%s] + Pipe Transaction Counter Registers + 0x090 + + E + Pipe Transaction Counter Enable Register + 0x00 + 16 + read-write + 0x0000 + 0xFFFF + + + TRENB + Transaction Counter Enable + 9 + 9 + read-write + + + 0 + Transaction counter is disabled. + #0 + + + 1 + Transaction counter is enabled. + #1 + + + + + TRCLR + Transaction Counter Clear + 8 + 8 + read-write + + + 0 + Invalid + #0 + + + 1 + The current counter value is cleared. + #1 + + + + + + + N + Pipe Transaction Counter Register + 0x02 + 16 + read-write + 0x0000 + 0xFFFF + + + TRNCNT + Transaction Counter + 0 + 15 + read-write + + + + - 2 - 1 - DPSIEGR%s - Deep Standby Interrupt Edge Register %s - 0x40A - 8 + SYSCFG + System Configuration Control Register + 0x000 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - 8 - 1 - DIRQ%sEG - IRQ-DS Pin Edge Select - 0 - 0 + SCKE + USB Clock Enable + 10 + 10 read-write 0 - A cancel request is generated at a falling edge + Clock supply to the USBFS stopped #0 1 - A cancel request is generated at a rising edge + Clock supply to the USBFS enabled. #1 - - - - DPSIEGR2 - Deep Standby Interrupt Edge Register 2 - 0x40C - 8 - read-write - 0x00 - 0xFF - - DNMIEG - NMI Pin Edge Select - 4 - 4 + CNEN + CNEN Single End Receiver Enable + 8 + 8 read-write 0 - A cancel request is generated at a falling edge + Single end receiver disabled #0 1 - A cancel request is generated at a rising edge + Single end receiver enabled #1 - DLVD2IEG - LVD2 Edge Select - 1 - 1 + DCFM + Controller Function Select + 6 + 6 read-write 0 - A cancel request is generated when VCC<Vdet2 (fall) is detected + Device controller selected #0 1 - A cancel request is generated when VCC>=Vdet2 (rise) is detected + Host controller selected. #1 - DLVD1IEG - LVD1 Edge Select - 0 - 0 + DRPD + D+/D- Line Resistor Control + 5 + 5 read-write 0 - A cancel request is generated when VCC<Vdet1 (fall) is detected + Line pull-down disabled #0 1 - A cancel request is generated when VCC>=Vdet1 (rise) is detected + Line pull-down enabled. #1 - - - - DPSBYCR - Deep Standby Control Register - 0x400 - 8 - read-write - 0x01 - 0xFF - - DPSBY - Deep Software Standby - 7 - 7 + DPRPU + D+ Line Resistor Control + 4 + 4 read-write 0 - Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1) + Line pull-down disabled #0 1 - Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1) + Line pull-down enabled. #1 - IOKEEP - I/O Port Retention - 6 - 6 + DMRPU + D- Line Resistor Control + 3 + 3 read-write 0 - When the Deep Software Standby mode is canceled, the I/O ports are in the reset state. + Line pull-up disabled #0 1 - When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode. + Line pull-up enabled. #1 - DEEPCUT - Power-Supply Control + USBE + USB Operation Enable 0 - 1 + 0 read-write - 00 - Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. - #00 - - - 01 - Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is not supplied in deep software standby mode. - #01 - - - 10 - Setting prohibited. - #10 + 0 + Disabled + #0 - 11 - Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume detecting unit is supplied in deep software standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled. - #11 + 1 + Enabled. + #1 - SYOCDCR - System Control OCD Control Register - 0x40E - 8 + BUSWAIT + CPU Bus Wait Register + 0x002 + 16 read-write - 0x00 - 0xFE + 0x000F + 0x3F3F - DBGEN - Debugger Enable bit - 7 - 7 + BWAIT + CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) + 0 + 3 read-write - 0 - On-chip debugger is disabled - #0 - - - 1 - On-chip debugger is enabled - #1 + BWAIT + BWAIT wait(s) ( BWAIT + 2 access cycles ) + true + + + + SYSSTS0 + System Configuration Status Register 0 + 0x004 + 16 + read-only + 0x0000 + 0x0000 + + + OVCMON + External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. + 14 + 15 + read-only + - DOCDF - Deep Standby OCD flag - 0 - 0 - read-write - zeroToClear - modify + HTACT + USB Host Sequencer Status Monitor + 6 + 6 + read-only 0 - On-chip debugger is disabled + Host sequencer completely stopped #0 1 - On-chip debugger is enabled + Host sequencer not completely stopped. #1 - - - - MOMCR - Main Clock Oscillator Mode Oscillation Control Register - 0x413 - 8 - read-write - 0x00 - 0xFF - - AUTODRVEN - Main Clock Oscillator Drive Capability Auto Switching Enable - 7 - 7 - read-write + SOFEA + SOF Active Monitor While Host Controller Function is Selected. + 5 + 5 + read-only 0 - Disable + SOF output is stopped. #0 1 - Enable. + SOF output is operating. #1 - MOSEL - Main Clock Oscillator Switching - 6 - 6 - read-write + IDMON + External ID0 Input Pin Monitor + 2 + 2 + read-only 0 - Resonator + USB0_ID pin is low #0 1 - External clock input + USB0_ID pin is high #1 - MODRV0 - Main Clock Oscillator Drive Capability 0 Switching - 4 - 5 - read-write + LNST + USB Data Line Status Monitor + 0 + 1 + read-only 00 - 20MHz to 24MHz + SE0 #00 01 - 16MHz to 20MHz + K-State (FS) / J-State(LS) #01 10 - 8MHz to 16MHz + J-State(FS) / K-State(LS) #10 11 - 8MHz + SE1 #11 + + + + PLLSTA + PLL Status Register + 0x006 + 16 + read-only + 0x0000 + 0x0001 + - MODRV1 - Main Clock Oscillator Drive Capability 1 Switching - 3 - 3 - read-write + PLLLOCK + PLL Lock Flag + 0 + 0 + read-only 0 - 10 MHz to 20 MHz + PLL is not locked. #0 1 - 1 MHz to 10 MHz. + PLL is locked. #1 @@ -67513,1427 +79561,1404 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - RSTSR0 - Reset Status Register 0 - 0x410 - 8 + DVSTCTR0 + Device State Control Register 0 + 0x008 + 16 read-write - 0x00 - 0x70 + 0x0000 + 0xFFFF - DPSRSTF - Deep Software Standby Reset FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 7 - 7 + HNPBTOA + Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. + 11 + 11 read-write - zeroToClear - modify 0 - Deep software standby mode cancelation not requested by an interrupt. + Normal Operation #0 1 - Deep software standby mode cancelation requested by an interrupt. + Switching from device B to device A is enabled #1 - LVD2RF - Voltage Monitor 2 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 3 - 3 + EXICEN + USB_EXICEN Output Pin Control + 10 + 10 read-write - zeroToClear - modify 0 - Voltage Monitor 2 reset not detected. + External USB_EXICEN pin outputs low #0 1 - Voltage Monitor 2 reset detected. + External USB_EXICEN pin outputs high #1 - LVD1RF - Voltage Monitor 1 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 2 - 2 + VBUSEN + USB_VBUSEN Output Pin Control + 9 + 9 read-write - zeroToClear - modify 0 - Voltage Monitor 1 reset not detected. + External USB_VBUSEN pin outputs low #0 1 - Voltage Monitor 1 reset detected. + External USB_VBUSEN pin outputs high #1 - LVD0RF - Voltage Monitor 0 Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 1 - 1 + WKUP + Wakeup Output + 8 + 8 read-write - zeroToClear - modify 0 - Voltage Monitor 0 reset not detected. + Remote wakeup signal is not output. #0 1 - Voltage Monitor 0 reset detected. + Remote wakeup signal is output. #1 - PORF - Power-On Reset Detect FlagNOTE: Writable only to clear the flag. Confirm the value is 1 and then write 0. - 0 - 0 + RWUPE + Wakeup Detection Enable + 7 + 7 read-write - zeroToClear - modify 0 - Power-on reset not detected. + Downstream port wakeup is disabled. #0 1 - Power-on reset detected. + Downstream port wakeup is enabled. #1 - - - - RSTSR2 - Reset Status Register 2 - 0x411 - 8 - read-write - 0x00 - 0xFE - - CWSF - Cold/Warm Start Determination Flag - 0 - 0 + USBRST + USB Bus Reset Output + 6 + 6 read-write - oneToSet - modify 0 - Cold start + USB bus reset signal is not output. #0 1 - Warm start + USB bus reset signal is output. #1 - - - - LVCMPCR - Voltage Monitor Circuit Control Register - 0x417 - 8 - read-write - 0x00 - 0xFF - - LVD2E - Voltage Detection 2 Enable - 6 - 6 + RESUME + Resume Output + 5 + 5 read-write 0 - Voltage detection 2 circuit disabled + Resume signal is not output. #0 1 - Voltage detection 2 circuit enabled + Resume signal is output. #1 - LVD1E - Voltage Detection 1 Enable - 5 - 5 + UACT + USB Bus Enable + 4 + 4 read-write 0 - Voltage detection 1 circuit disabled + Downstream port is disabled (SOF transmission is disabled). #0 1 - Voltage detection 1 circuit enabled + Downstream port is enabled (SOF transmission is enabled). #1 - - - - LVDLVLR - Voltage Detection Level Select Register - 0x418 - 8 - read-write - 0xF3 - 0xFF - - LVD2LVL - Voltage Detection 2 Level Select (Standard voltage during fall in voltage) - 5 - 7 - read-write + RHST + USB Bus Reset Status + 0 + 2 + read-only - 101 - 2.99V (Vdet2_1) - #101 + 000 + Communication speed not determined + #000 - 110 - 2.92V (Vdet2_2) - #110 + 001 + Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected) + #001 - 111 - 2.85V (Vdet2_3) - #111 + 010 + Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected) + #010 + + + 011 + Setting prohibited + #011 others - Settings other than above are prohibited. + USB bus reset in progress(When the host controller function is selected) true + + + + TESTMODE + USB Test Mode Register + 0x00C + 16 + read-write + 0x0000 + 0x000F + - LVD1LVL - Voltage Detection 1 Level Select (Standard voltage during fall in voltage) + UTST + Test Mode 0 - 4 + 3 read-write - 10001 - 2.99V (Vdet1_1) - #10001 + 0000 + Normal operation + #0000 - 10010 - 2.92V (Vdet1_2) - #10010 + 0001 + Test_J TestMode(When the Function Controller Function is Selected) + #0001 - 10011 - 2.85V (Vdet1_3) - #10011 + 0010 + Test_K TestMode(When the Function Controller Function is Selected) + #0010 - others - Settings other than above are prohibited. - true + 0011 + Test_SE0_NAK TestMode(When the Function Controller Function is Selected) + #0011 - - - - - - 2 - 0x1 - 1,2 - LVD%sCR0 - Voltage Monitor %s Circuit Control Register 0 - 0x41A - 8 - read-write - 0x8A - 0xF7 - - - RN - Voltage Monitor Reset Negate Select - 7 - 7 - read-write - - 0 - Negation follows a stabilization time (tLVD) after VCC > Vdet is detected. - #0 + 0100 + Test_Packet TestMode(When the Function Controller Function is Selected) + #0100 - 1 - Negation follows a stabilization time (tLVD) after assertion of the LVD reset. - #1 + 0101 + Reserved TestMode(When the Function Controller Function is Selected) + #0101 - - - - RI - Voltage Monitor Circuit Mode Select - 6 - 6 - read-write - - 0 - Voltage Monitor interrupt during Vdet1 passage - #0 + 0110 + Reserved TestMode(When the Function Controller Function is Selected) + #0110 - 1 - Voltage Monitor reset enabled when the voltage falls to and below Vdet1 - #1 + 0111 + Reserved TestMode(When the Function Controller Function is Selected) + #0111 - - - - FSAMP - Sampling Clock Select - 4 - 5 - read-write - - 00 - 1/2 LOCO frequency - #00 + 1001 + Test_J TestMode(When the Host Controller Function is Selected) + #1001 - 01 - 1/4 LOCO frequency - #01 + 1010 + Test_K TestMode(When the Host Controller Function is Selected) + #1010 - 10 - 1/8 LOCO frequency - #10 + 1011 + Test_SE0_NAK TestMode(When the Host Controller Function is Selected) + #1011 - 11 - 1/16 LOCO frequency - #11 + 1100 + Test_Packet TestMode(When the Host Controller Function is Selected) + #1100 + + + 1101 + Test_Force_EnableTestMode(When the Host Controller Function is Selected) + #1101 + + + 1110 + Reserved TestMode(When the Host Controller Function is Selected) + #1110 + + + 1111 + Reserved TestMode(When the Host Controller Function is Selected) + #1111 - - CMPE - Voltage Monitor Circuit Comparison Result Output Enable - 2 - 2 + + + + CFIFOL + CFIFO Port Register L + 0x014 + 16 + read-write + 0x0000 + 0xFFFF + + + + CFIFOLL + CFIFO Port Register LL + CFIFOL + 0x014 + 8 + read-write + 0x00 + 0xFF + + + + CFIFO + CFIFO Port Register + CFIFOL + 0x014 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + CFIFOH + CFIFO Port Register H + CFIFO + 0x016 + 16 + read-write + 0x0000 + 0xFFFF + + + + CFIFOHH + CFIFO Port Register HH + CFIFOH + 0x017 + 8 + read-write + 0x00 + 0xFF + + + + D0FIFOL + D0FIFO Port Register L + 0x018 + 16 + read-write + 0x0000 + 0xFFFF + + + + D0FIFOLL + D0FIFO Port Register LL + D0FIFOL + 0x018 + 8 + read-write + 0x00 + 0xFF + + + + D0FIFO + D0FIFO Port Register + D0FIFOL + 0x018 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + D0FIFOH + D0FIFO Port Register H + D0FIFO + 0x01A + 16 + read-write + 0x0000 + 0xFFFF + + + + D0FIFOHH + D0FIFO Port Register HH + D0FIFOH + 0x01B + 8 + read-write + 0x00 + 0xFF + + + + D1FIFOL + D1FIFO Port Register L + 0x01C + 16 + read-write + 0x0000 + 0xFFFF + + + + D1FIFOLL + D1FIFO Port Register LL + D1FIFOL + 0x01C + 8 + read-write + 0x00 + 0xFF + + + + D1FIFO + D1FIFO Port Register + D1FIFOL + 0x01C + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + D1FIFOH + D1FIFO Port Register H + D1FIFO + 0x01E + 16 + read-write + 0x0000 + 0xFFFF + + + + D1FIFOHH + D1FIFO Port Register HH + D1FIFOH + 0x01F + 8 + read-write + 0x00 + 0xFF + + + + CFIFOSEL + CFIFO Port Select Register + 0x020 + 16 + read-write + 0x0000 + 0xFFFF + + + RCNT + Read Count Mode + 15 + 15 read-write 0 - Disable voltage monitor 1 circuit comparison result output + The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) #0 1 - Enable voltage monitor 1 circuit comparison result output. + The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. #1 - DFDIS - Voltage Monitor Digital Filter Disable Mode Select - 1 - 1 + REW + Buffer Pointer Rewind + 14 + 14 read-write 0 - Enable digital filter + The buffer pointer is not rewound. #0 1 - Disable digital filter + The buffer pointer is rewound. #1 - RIE - Voltage Monitor Interrupt/Reset Enable - 0 - 0 + MBW + CFIFO Port Access Bit Width + 10 + 11 read-write 0 - Disable - #0 + 8-bit width + 0 1 - Enable - #1 + 16-bit width + 1 + + + 2 + 32-bit width + 2 - - - - VBTCR1 - VBATT Control Register1 - 0x41F - 8 - read-write - 0x00 - 0xFF - - BPWSWSTP - Battery Power supply Switch Stop - 0 - 0 + BIGEND + CFIFO Port Endian Control + 8 + 8 read-write 0 - Battery Power supply Switch Enable + Little endian #0 1 - Battery Power supply Switch stop + Big endian #1 - - - - SOSCCR - Sub-Clock Oscillator Control Register - 0x480 - 8 - read-write - 0x01 - 0xFF - - SOSTP - Sub-Clock Oscillator Stop - 0 - 0 + ISEL + CFIFO Port Access Direction When DCP is Selected + 5 + 5 read-write 0 - Sub-clock oscillator is operating. + Reading from the buffer memory is selected #0 1 - Sub-clock oscillator is stopped. + Writing to the buffer memory is selected #1 - - - - SOMCR - Sub Clock Oscillator Mode Control Register - 0x481 - 8 - read-write - 0x00 - 0xFF - - SODRV - Sub-Clock Oscillator Drive Capability Switching + CURPIPE + CFIFO Port Access Pipe Specification 0 - 1 + 3 read-write - 00 - Normal mode - #00 - - - 01 - Low power mode 1 - #01 + 0000 + DCP (Default control pipe) + #0000 - 10 - Low power mode 2 - #10 + 0001 + Pipe 1 + #0001 - 11 - Low power mode 3. - #11 + 0010 + Pipe 2 + #0010 - - - - - - LOCOCR - Low-Speed On-Chip Oscillator Control Register - 0x490 - 8 - read-write - 0x00 - 0xFF - - - LCSTP - LOCO Stop - 0 - 0 - read-write - - 0 - LOCO is operating. - #0 + 0011 + Pipe 3 + #0011 - 1 - LOCO is stopped. - #1 + 0100 + Pipe 4 + #0100 - - - - - - LOCOUTCR - LOCO User Trimming Control Register - 0x492 - 8 - read-write - 0x00 - 0xFF - - - LOCOUTRM - LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits - 0 - 7 - read-write - - - - - VBTCR2 - VBATT Control Register2 - 0x4B0 - 8 - read-write - 0x00 - 0xFF - - - VBTLVDLVL - VBATT Pin Voltage Low Voltage Detect Level Select Bit - 6 - 7 - read-write - - 00 - 2.7V - #00 + 0101 + Pipe 5 + #0101 - 01 - Setting prohibited - #01 + 0110 + Pipe 6 + #0110 - 10 - 2.3V - #10 + 0111 + Pipe 7 + #0111 - 11 - 2.1V - #11 + 1000 + Pipe 8 + #1000 - - - - VBTLVDEN - VBATT Pin Low Voltage Detect Enable Bit - 4 - 4 - read-write - - 0 - VBATT pin low voltage detect disable - #0 + 1001 + Pipe 9 + #1001 - 1 - VBATT pin low voltage detect enable - #1 + others + Setting prohibited + true - VBTSR - VBATT Status Register - 0x4B1 - 8 + CFIFOCTR + CFIFO Port Control Register + 0x022 + 16 read-write - 0x01 - 0xEC + 0x0000 + 0xFFFF - VBTRVLD - VBATT_R Valid - 4 - 4 - read-only + BVAL + Buffer Memory Valid Flag + 15 + 15 + read-write 0 - VBATT_R area not valid + Invalid #0 1 - VBATT_R area valid + Writing ended #1 - VBTBLDF - VBATT Battery Low voltage Detect Flag - 1 - 1 + BCLR + CPU Buffer ClearNote: Only 0 can be read. + 14 + 14 read-write - zeroToClear - modify 0 - VBATT pin low voltage not detected + Does not operate #0 1 - VBATT pin low voltage detected. + FIFO buffer cleared on the CPU side. #1 - VBTRDF - VBAT_R Reset Detect Flag - 0 - 0 - read-write - zeroToClear - modify + FRDY + FIFO Port Ready + 13 + 13 + read-only 0 - VBATT_R voltage power-on reset not detected + FIFO port access is disabled. #0 1 - VBATT_R selected voltage power-on reset detected. + FIFO port access is enabled. #1 + + DTLN + Receive Data LengthIndicates the length of the receive data. + 0 + 11 + read-only + - VBTCMPCR - VBATT Comparator Control Register - 0x4B2 - 8 + D0FIFOSEL + D0FIFO Port Select Register + 0x028 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - VBTCMPE - VBATT pin low voltage detect circuit output enable - 0 - 0 + RCNT + Read Count Mode + 15 + 15 read-write 0 - VBATT pin low voltage detect circuit output disabled + The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 - VBATT pin low voltage detect circuit output enabled + The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 - - - - VBTLVDICR - VBATT Pin Low Voltage Detect Interrupt Control Register - 0x4B4 - 8 - read-write - 0x00 - 0xFF - - VBTLVDISEL - Pin Low Voltage Detect Interrupt Select bit - 1 - 1 + REW + Buffer Pointer RewindNote: Only 0 can be read. + 14 + 14 read-write 0 - Non Maskable Interrupt + The buffer pointer is not rewound. #0 1 - Maskable Interrupt + The buffer pointer is rewound. #1 - VBTLVDIE - VBATT Pin Low Voltage Detect Interrupt Enable bit - 0 - 0 + DCLRM + Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read + 13 + 13 read-write 0 - VBATT Pin Low Voltage Detect Interrupt Disable + Auto buffer clear mode is disabled. #0 1 - VBATT Pin Low Voltage Detect Interrupt Enable + Auto buffer clear mode is enabled. #1 - - - - VBTWCTLR - VBATT Wakeup function Control Register - 0x4B6 - 8 - read-write - 0x00 - 0xFF - - VWEN - VBATT wakeup enable - 0 - 0 + DREQE + DMA/DTC Transfer Request Enable + 12 + 12 read-write 0 - Disable Wakeup function + DMA/DTC transfer request is disabled. #0 1 - Enable Wakeup function + DMA/DTC transfer request is enabled. #1 - - - - VBTWCH0OTSR - VBATT Wakeup I/O 0 Output Trigger Select Register - 0x4B8 - 8 - read-write - 0x00 - 0xFF - - CH0VAGTUTE - CH0 Output AGT(ch1) underflow Signal Enable - 5 - 5 + MBW + FIFO Port Access Bit Width + 10 + 11 read-write 0 - VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is disabled - #0 + 8-bit width + 0 1 - VBATT CH0 wakeup triggered by the AGT(ch1) underflow signal is enabled - #1 + 16-bit width + 1 + + + 2 + 32-bit width + 2 - CH0VRTCATE - VBATWIO0 Output RTC Alarm Signal Enable - 4 - 4 + BIGEND + FIFO Port Endian Control + 8 + 8 read-write 0 - VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled + Little endian #0 1 - VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled. + Big endian #1 - CH0VRTCTE - VBATWIO0 Output RTC Periodic Signal Enable - 3 + CURPIPE + FIFO Port Access Pipe Specification + 0 3 read-write - 0 - VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled - #0 + 0000 + DCP (Default control pipe) + #0000 - 1 - VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled. - #1 + 0001 + Pipe 1 + #0001 - - - - CH0VCH2TE - VBATWIO0 Output VBATWIO2 Trigger Enable - 2 - 2 - read-write - - 0 - VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled - #0 + 0010 + Pipe 2 + #0010 - 1 - VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled. - #1 + 0011 + Pipe 3 + #0011 - - - - CH0VCH1TE - VBATWIO0 Output VBATWIO1 Trigger Enable - 1 - 1 - read-write - - 0 - VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled - #0 + 0100 + Pipe 4 + #0100 - 1 - VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled. - #1 + 0101 + Pipe 5 + #0101 + + + 0110 + Pipe 6 + #0110 + + + 0111 + Pipe 7 + #0111 + + + 1000 + Pipe 8 + #1000 + + + 1001 + Pipe 9 + #1001 + + + others + Setting prohibited + true - VBTWCH1OTSR - VBATT Wakeup I/O 1 Output Trigger Select Register - 0x4B9 - 8 + D0FIFOCTR + D0FIFO Port Control Register + 0x02A + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - CH1VAGTUTE - CH1 Output AGT(ch1) underflow Signal Enable - 5 - 5 + BVAL + Buffer Memory Valid Flag + 15 + 15 read-write 0 - VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is disabled + Invalid #0 1 - VBATT CH1 wakeup triggered by the AGT(ch1) underflow signal is enabled + Writing ended #1 - CH1VRTCATE - VBATWIO1 Output RTC Alarm Signal Enable - 4 - 4 + BCLR + CPU Buffer ClearNote: Only 0 can be read. + 14 + 14 read-write 0 - VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled + Does not operate #0 1 - VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled. + FIFO buffer cleared on the CPU side. #1 - CH1VRTCTE - VBATWIO1 Output RTC Periodic Signal Enable - 3 - 3 - read-write + FRDY + FIFO Port Ready + 13 + 13 + read-only 0 - VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled + FIFO port access is disabled. #0 1 - VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled + FIFO port access is enabled. #1 - CH1VCH2TE - VBATWIO1 Output VBATWIO2 Trigger Enable - 2 - 2 + DTLN + Receive Data LengthIndicates the length of the receive data. + 0 + 11 + read-only + + + + + D1FIFOSEL + D1FIFO Port Select Register + 0x02C + 16 + read-write + 0x0000 + 0xFFFF + + + RCNT + Read Count Mode + 15 + 15 read-write 0 - VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled + The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 - VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled. + The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 - CH1VCH0TE - VBATWIO1 Output VBATWIO0 Trigger Enable - 0 - 0 + REW + Buffer Pointer Rewind + 14 + 14 read-write 0 - VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled + The buffer pointer is not rewound. #0 1 - VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled. + The buffer pointer is rewound. #1 - - - - VBTWCH2OTSR - VBATT Wakeup I/O 2 Output Trigger Select Register - 0x4BA - 8 - read-write - 0x00 - 0xFF - - CH2VAGTUTE - CH2 Output AGT(CH2) underflow Signal Enable - 5 - 5 + DCLRM + Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read + 13 + 13 read-write 0 - VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is disabled + Auto buffer clear mode is disabled. #0 1 - VBATT CH2 wakeup triggered by the AGT(CH2) underflow signal is enabled + Auto buffer clear mode is enabled. #1 - CH2VRTCATE - VBATWIO2 Output RTC Alarm Signal Enable - 4 - 4 + DREQE + DMA/DTC Transfer Request Enable + 12 + 12 read-write 0 - VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled + DMA/DTC transfer request is disabled. #0 1 - VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled. + DMA/DTC transfer request is enabled. #1 - CH2VRTCTE - VBATWIO2 Output RTC Periodic Signal Enable - 3 - 3 + MBW + FIFO Port Access Bit Width + 10 + 11 read-write 0 - VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled - #0 + 8-bit width + 0 1 - VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled. - #1 + 16-bit width + 1 + + + 2 + 32-bit width + 2 - CH2VCH1TE - VBATWIO2 Output VBATWIO1 Trigger Enable - 1 - 1 + BIGEND + FIFO Port Endian Control + 8 + 8 read-write 0 - VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled + Little endian #0 1 - VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled. + Big endian #1 - CH2VCH0TE - VBATWIO2 Output VBATWIO0 Trigger Enable + CURPIPE + FIFO Port Access Pipe Specification 0 - 0 + 3 read-write - 0 - VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled - #0 + 0000 + DCP (Default control pipe) + #0000 - 1 - VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled. - #1 + 0001 + Pipe 1 + #0001 - - - - - - VBTICTLR - VBATT Input Control Register - 0x4BB - 8 - read-write - 0x00 - 0xF8 - - - VCH2INEN - RTCIC2 Input Enable - 2 - 2 - read-write - - 0 - Disabled - #0 + 0010 + Pipe 2 + #0010 - 1 - Enabled - #1 + 0011 + Pipe 3 + #0011 - - - - VCH1INEN - RTCIC1 Input Enable - 1 - 1 - read-write - - 0 - Disabled - #0 + 0100 + Pipe 4 + #0100 - 1 - Enabled - #1 + 0101 + Pipe 5 + #0101 - - - - VCH0INEN - RTCIC0 Input Enable - 0 - 0 - read-write - - 0 - Disabled - #0 + 0110 + Pipe 6 + #0110 - 1 - Enabled - #1 + 0111 + Pipe 7 + #0111 + + + 1000 + Pipe 8 + #1000 + + + 1001 + Pipe 9 + #1001 + + + others + Setting prohibited + true - VBTOCTLR - VBATT Output Control Register - 0x4BC - 8 + D1FIFOCTR + D1FIFO Port Control Register + 0x02E + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - VOUT2LSEL - VBATT Wakeup I/O 2 Output Level Selection - 5 - 5 + BVAL + Buffer Memory Valid Flag + 15 + 15 read-write 0 - Output L before VBATT wake up trigger + Invalid #0 1 - Output H before VBATT wake up trigger + Writing ended #1 - VCOU1LSEL - VBATT Wakeup I/O 1 Output Level Selection - 4 - 4 + BCLR + CPU Buffer ClearNote: Only 0 can be read. + 14 + 14 read-write 0 - Output L before VBATT wake up trigger + Does not operate #0 1 - Output H before VBATT wake up trigger + FIFO buffer cleared on the CPU side. #1 - VOUT0LSEL - VBATT Wakeup I/O 0 Output Level Selection - 3 - 3 - read-write + FRDY + FIFO Port Ready + 13 + 13 + read-only 0 - Output L before VBATT wakeup trigger + FIFO port access is disabled. #0 1 - Output H before VBATT wakeup trigger + FIFO port access is enabled. #1 - VCH2OEN - VBATT Wakeup I/O 2 Output Enable - 2 - 2 - read-write - - - 0 - VBATWIO2 output disabled - #0 - - - 1 - VBATWIO2 output enabled - #1 - - + DTLN + Receive Data LengthIndicates the length of the receive data. + 0 + 11 + read-only + + + + INTENB0 + Interrupt Enable Register 0 + 0x030 + 16 + read-write + 0x0000 + 0xFFFF + - VCH1OEN - VBATT Wakeup I/O 1 Output Enable - 1 - 1 + VBSE + VBUS Interrupt Enable + 15 + 15 read-write 0 - VBATWIO1 output disabled + Interrupt output disabled #0 1 - VBATWIO1 output enabled + Interrupt output enabled #1 - VCH0OEN - VBATT Wakeup I/O 0 Output Enable - 0 - 0 + RSME + Resume Interrupt Enable + 14 + 14 read-write 0 - VBATWIO0 output disabled + Interrupt output disabled #0 1 - VBATWIO0 output enabled + Interrupt output enabled #1 - - - - VBTWTER - VBATT Wakeup Trigger source Enable Register - 0x4BD - 8 - read-write - 0x00 - 0xFF - - VAGTUE - AGT(ch1) underflow Signal Enable - 5 - 5 + SOFE + Frame Number Update Interrupt Enable + 13 + 13 read-write 0 - VBATT wakeup triggered by the AGT(ch1) underflow signal is disabled + Interrupt output disabled #0 1 - VBATT wakeup triggered by the AGT(ch1) underflow signal is enabled + Interrupt output enabled #1 - VRTCAE - RTC Alarm Signal Enable - 4 - 4 + DVSE + Device State Transition Interrupt Enable + 12 + 12 read-write 0 - VBATT wakeup triggered by RTC alarm signal is disabled + Interrupt output disabled #0 1 - VBATT wakeup triggered by RTC alarm signal is enabled. + Interrupt output enabled #1 - VRTCIE - RTC Periodic Signal Enable - 3 - 3 + CTRE + Control Transfer Stage Transition Interrupt Enable + 11 + 11 read-write 0 - VBATT wakeup triggered by RTC periodic signal is disabled + Interrupt output disabled #0 1 - VBATT wakeup triggered by RTC periodic signal is enabled. + Interrupt output enabled #1 - VCH2E - VBATWIO2 Pin Enable - 2 - 2 + BEMPE + Buffer Empty Interrupt Enable + 10 + 10 read-write 0 - VBATT wakeup triggered by the VBATWIO2 pin is disabled + Interrupt output disabled #0 1 - VBATT wakeup triggered by the VBATWIO2 pin is enabled. + Interrupt output enabled #1 - VCH1E - VBATWIO1 Pin Enable - 1 - 1 + NRDYE + Buffer Not Ready Response Interrupt Enable + 9 + 9 read-write 0 - VBATT wakeup triggered by the VBATWIO1 pin is disabled + Interrupt output disabled #0 1 - VBATT wakeup triggered by the VBATWIO1 pin is enabled. + Interrupt output enabled #1 - VCH0E - VBATWIO0 Pin Enable - 0 - 0 + BRDYE + Buffer Ready Interrupt Enable + 8 + 8 read-write 0 - VBATT wakeup triggered by the VBATWIO0 pin is disabled + Interrupt output disabled #0 1 - VBATT wakeup triggered by the VBATWIO0 pin is enabled. + Interrupt output enabled #1 @@ -68941,204 +80966,162 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - VBTWEGR - VBATT Wakeup Trigger source Edge Register - 0x4BE - 8 + INTENB1 + Interrupt Enable Register 1 + 0x032 + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - VCH2EG - VBATWIO2 Wakeup Trigger Source Edge Select - 2 - 2 - read-write - - - 0 - Wakeup trigger is generated at a falling edge - #0 - - - 1 - Wakeup trigger is generated at a rising edge. - #1 - - - - - VCH1EG - VBATWIO1 Wakeup Trigger Source Edge Select - 1 - 1 + OVRCRE + Overcurrent Input Change Interrupt Enable + 15 + 15 read-write 0 - Wakeup trigger is generated at a falling edge + Interrupt output disabled #0 1 - Wakeup trigger is generated at a rising edge. + Interrupt output enabled #1 - VCH0EG - VBATWIO0 Wakeup Trigger Source Edge Select - 0 - 0 + BCHGE + USB Bus Change Interrupt Enable + 14 + 14 read-write 0 - Wakeup trigger is generated at a falling edge + Interrupt output disabled #0 1 - Wakeup trigger is generated at a rising edge. + Interrupt output enabled #1 - - - - VBTWFR - VBATT Wakeup trigger source Flag Register - 0x4BF - 8 - read-write - 0x00 - 0xFF - - VAGTUF - AGT(ch1) underflow VBATT Wakeup Trigger Flag - 5 - 5 + DTCHE + Disconnection Detection Interrupt Enable + 12 + 12 read-write - zeroToClear - modify 0 - No wakeup trigger by the AGT(ch1) underflow is generated + Interrupt output disabled #0 1 - A wakeup trigger by the AGT(ch1) underflow is generated + Interrupt output enabled #1 - VRTCAF - VBATT RTC-Alarm Wakeup Trigger Flag - 4 - 4 + ATTCHE + Connection Detection Interrupt Enable + 11 + 11 read-write - zeroToClear - modify 0 - No wakeup trigger by the RTC alarm is generated + Interrupt output disabled #0 1 - A wakeup trigger by the RTC alarm is generated + Interrupt output enabled #1 - VRTCIF - VBATT RTC-Interval Wakeup Trigger Flag - 3 - 3 + EOFERRE + EOF Error Detection Interrupt Enable + 6 + 6 read-write - zeroToClear - modify 0 - No wakeup trigger by the RTC interval is generated + Interrupt output disabled #0 1 - A wakeup trigger by the RTC interval is generated + Interrupt output enabled #1 - VCH2F - VBATWIO2 Wakeup Trigger Flag - 2 - 2 + SIGNE + Setup Transaction Error Interrupt Enable + 5 + 5 read-write - zeroToClear - modify 0 - No wakeup trigger by the VBATWIO2 pin is generated + Interrupt output disabled #0 1 - A wakeup trigger by the VBATWIO2 pin is generated + Interrupt output enabled #1 - VCH1F - VBATWIO1 Wakeup Trigger Flag - 1 - 1 + SACKE + Setup Transaction Normal Response Interrupt Enable + 4 + 4 read-write - zeroToClear - modify 0 - No wakeup trigger by the VBATWIO1 pin is generated + Interrupt output disabled #0 1 - A wakeup trigger by the VBATWIO1 pin is generated + Interrupt output enabled #1 - VCH0F - VBATWIO0 Wakeup Trigger Flag + PDDETINTE0 + PDDETINT0 Detection Interrupt Enable 0 0 read-write - zeroToClear - modify 0 - No wakeup trigger by the VBATWIO0 pin is generated + Interrupt output disabled #0 1 - A wakeup trigger by the VBATWIO0 pin is generated + Interrupt output enabled #1 @@ -69146,528 +81129,346 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - 512 - 0x1 - VBTBKR[%s] - VBATT Backup Register [%s] - 0x500 - 8 + BRDYENB + BRDY Interrupt Enable Register + 0x036 + 16 read-write - 0x00 - 0x00 + 0x0000 + 0xFFFF - VBTBKR - VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. + 10 + 1 + PIPE%sBRDYE + BRDY Interrupt Enable for PIPE 0 - 7 + 0 read-write + + + 0 + Interrupt output disabled + #0 + + + 1 + Interrupt output enabled + #1 + + - FWEPROR - Flash P/E Protect Register - 0x416 - 8 + NRDYENB + NRDY Interrupt Enable Register + 0x038 + 16 read-write - 0x02 - 0xFF + 0x0000 + 0xFFFF - FLWE - Flash Programming and Erasure + 10 + 1 + PIPE%sNRDYE + NRDY Interrupt Enable for PIPE 0 - 1 + 0 read-write - 00 - Prohibits programming and erasure of the code flash, data flash or blank checking. - #00 - - - 01 - Permits programming and erasure of the code flash, data flash or blank checking. - #01 - - - 10 - Prohibits programming and erasure of the code flash, data flash or blank checking. - #10 + 0 + Interrupt output disabled + #0 - 11 - Prohibits programming and erasure of the code flash, data flash or blank checking. - #11 + 1 + Interrupt output enabled + #1 - - - - R_TSN - Temperature Sensor - 0x407EC000 - - 0x00000228 - 0x002 - registers - - - - TSCDRH - Temperature Sensor Calibration Data Register H - 0x229 - 8 - read-only - 0x00 - 0x00 - - - TSCDRH - The calibration data stores the higher 8 bits of the convertedvalue. - 0 - 7 - read-only - - - - - TSCDRL - Temperature Sensor Calibration Data Register L - 0x228 - 8 - read-only - 0x00 - 0x00 - - - TSCDRL - The calibration data stores the lower 8 bits of the converted value. - 0 - 7 - read-only - - - - - - - R_TSN_CAL - Temperature Sensor - 0x407FB17C - - 0x00 - 0x04 - registers - - - - TSCDR - Temperature Sensor 32 bit Calibration Data Register - 0x00 - 32 - read-only - 0x00 - 0x00 - - - TSCDR - The 32 bit TSCDR register stores temperature sensor calibration converted value. - 0 - 31 - read-only - - - - - - - R_TSN_CTRL - Temperature Sensor - 0x4005D000 - - 0x00 - 1 - registers - - - TSCR - Temperature Sensor Control Register - 0x00 - 8 + BEMPENB + BEMP Interrupt Enable Register + 0x03A + 16 read-write - 0x00 - 0xFF + 0x0000 + 0xFFFF - TSEN - Temperature Sensor Output Enable - 7 - 7 + 10 + 1 + PIPE%sBEMPE + BEMP Interrupt Enable for PIPE + 0 + 0 read-write 0 - Stops the temperature sensor. + Interrupt output disabled #0 1 - Starts the temperature sensor. + Interrupt output enabled #1 + + + + SOFCFG + SOF Output Configuration Register + 0x03C + 16 + read-write + 0x0000 + 0xFFFF + - TSOE - Temperature Sensor Enable - 4 - 4 + TRNENSEL + Transaction-Enabled Time Select + 8 + 8 read-write 0 - Disables output from the temperature sensor to the 12-bit A/D converter. + Not low-speed communication #0 1 - Enables output from the temperature sensor to the 12-bit A/D converter. + Low-speed communication. #1 - - - - - - R_USB_FS0 - USB 2.0 Module - 0x40090000 - - 0x00000000 - 0x00A - registers - - - 0x0000000C - 0x02 - registers - - - 0x00000014 - 0x010 - registers - - - 0x00000028 - 0x00C - registers - - - 0x00000036 - 0x00E - registers - - - 0x00000046 - 0x00C - registers - - - 0x00000054 - 0x00E - registers - - - 0x00000064 - 0x02 - registers - - - 0x00000068 - 0x02 - registers - - - 0x0000006C - 0x016 - registers - - - 0x00000090 - 0x014 - registers - - - 0x000000B0 - 0x02 - registers - - - 0x000000C4 - 0x02 - registers - - - 0x000000CC - 0x02 - registers - - - 0x000000D0 - 0x014 - registers - - - 0x000000F0 - 0x04 - registers - - - 0x00000100 - 0x004 - registers - - - 0x00000140 - 0x02 - registers - - - 0x00000144 - 0x008 - registers - - - 0x00000160 - 0x00C - registers - - - 0x00000400 - 0x008 - registers - - - - 5 - 0x004 - PIPE_TR[%s] - Pipe Transaction Counter Registers - 0x090 - - E - Pipe Transaction Counter Enable Register - 0x00 - 16 - read-write - 0x0000 - 0xFFFF - - - TRENB - Transaction Counter Enable - 9 - 9 - read-write - - - 0 - Transaction counter is disabled. - #0 - - - 1 - Transaction counter is enabled. - #1 - - - - - TRCLR - Transaction Counter Clear - 8 - 8 - read-write - - - 0 - Invalid - #0 - - - 1 - The current counter value is cleared. - #1 - - - - - - - N - Pipe Transaction Counter Register - 0x02 - 16 - read-write - 0x0000 - 0xFFFF - - - TRNCNT - Transaction Counter - 0 - 15 - read-write - - - - - - SYSCFG - System Configuration Control Register - 0x000 - 16 - read-write - 0x0000 - 0xFFFF - - SCKE - USB Clock Enable - 10 - 10 + BRDYM + BRDY Interrupt Status Clear Timing + 6 + 6 read-write 0 - Clock supply to the USBFS stopped + BRDY flag cleared by software #0 1 - Clock supply to the USBFS enabled. + BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer. #1 - CNEN - CNEN Single End Receiver Enable - 8 - 8 + INTL + Interrupt Output Sense Select + 5 + 5 read-write 0 - Single end receiver disabled + Edge sense #0 1 - Single end receiver enabled + Level sense #1 - DCFM - Controller Function Select - 6 - 6 - read-write + EDGESTS + Edge Interrupt Output Status Monitor + 4 + 4 + read-only 0 - Device controller selected + before stopping the clock supply to the USB module #0 1 - Host controller selected. + the edge interrupt output signal is in the middle of the edge processing #1 + + + + PHYSET + PHY Setting Register + 0x03E + 16 + read-write + 0x0033 + 0x0B3B + - DRPD - D+/D- Line Resistor Control - 5 - 5 + HSEB + CL-Only Mode + 15 + 15 read-write 0 - Line pull-down disabled + CL-only mode is not activated. #0 1 - Line pull-down enabled. + CL-only mode is activated. #1 - DPRPU - D+ Line Resistor Control - 4 - 4 + REPSTART + Forcibly Start Terminating Resistance Adjustment + 11 + 11 read-write 0 - Line pull-down disabled + Terminating resistance adjustment is forcibly started #0 1 - Line pull-down enabled. + Terminating resistance adjustment is not forcibly started #1 - DMRPU - D- Line Resistor Control + REPSEL + Terminating Resistance Adjustment Cycle + 8 + 9 + read-write + + + 00 + No cycle is set. + #00 + + + 01 + Adjust terminating resistance at 16-second intervals. + #01 + + + 10 + Adjust terminating resistance at 64-second intervals. + #10 + + + 11 + Adjust terminating resistance at 128-second intervals. + #11 + + + + + CLKSEL + Input System Clock Frequency + 4 + 5 + read-write + + + 00 + Setting Prohibited + #00 + + + 01 + 12 MHz + #01 + + + 10 + 20 MHz + #10 + + + 11 + 24 MHz + #11 + + + + + CDPEN + Charging Downstream Port Enable 3 3 read-write 0 - Line pull-up disabled + Disable charging downstream port #0 1 - Line pull-up enabled. + Enable charging downstream port #1 - USBE - USB Operation Enable + PLLRESET + PLL Reset Control + 1 + 1 + read-write + + + 0 + Disable PLL reset control for UTMI_PHY + #0 + + + 1 + Enable PLL reset control for UTMI_PHY + #1 + + + + + DIRPD + Power-Down Control 0 0 read-write 0 - Disabled + Does not enter low-power consumption mode #0 1 - Enabled. + Enter low-power consumption mode #1 @@ -69675,1052 +81476,1063 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - BUSWAIT - CPU Bus Wait Register - 0x002 + INTSTS0 + Interrupt Status Register 0 + 0x040 16 read-write - 0x000F - 0x3F3F + 0x0000 + 0xFF7F - BWAIT - CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) - 0 - 3 + VBINT + VBUS Interrupt Status + 15 + 15 read-write + zeroToClear + modify - BWAIT - BWAIT wait(s) ( BWAIT + 2 access cycles ) - true + 0 + VBUS interrupts are not generated. + #0 + + + 1 + VBUS interrupts are generated. + #1 - - - - SYSSTS0 - System Configuration Status Register 0 - 0x004 - 16 - read-only - 0x0000 - 0x0000 - - OVCMON - External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. + RESM + Resume Interrupt Status 14 - 15 + 14 + read-write + zeroToClear + modify + + + 0 + Resume interrupts are not generated. + #0 + + + 1 + Resume interrupts are generated. + #1 + + + + + SOFR + Frame Number Refresh Interrupt Status + 13 + 13 + read-write + zeroToClear + modify + + + 0 + SOF interrupts are not generated. + #0 + + + 1 + SOF interrupts are generated. + #1 + + + + + DVST + Device State Transition Interrupt Status + 12 + 12 + read-write + zeroToClear + modify + + + 0 + Device state transition interrupts are not generated. + #0 + + + 1 + Device state transition interrupts are generated. + #1 + + + + + CTRT + Control Transfer Stage Transition Interrupt Status + 11 + 11 + read-write + zeroToClear + modify + + + 0 + Control transfer stage transition interrupts are not generated. + #0 + + + 1 + Control transfer stage transition interrupts are generated. + #1 + + + + + BEMP + Buffer Empty Interrupt Status + 10 + 10 read-only + + + 0 + BEMP interrupts are not generated. + #0 + + + 1 + BEMP interrupts are generated. + #1 + + - HTACT - USB Host Sequencer Status Monitor - 6 - 6 + NRDY + Buffer Not Ready Interrupt Status + 9 + 9 read-only 0 - Host sequencer completely stopped + NRDY interrupts are not generated. #0 1 - Host sequencer not completely stopped. + NRDY interrupts are generated. #1 - SOFEA - SOF Active Monitor While Host Controller Function is Selected. - 5 - 5 + BRDY + Buffer Ready Interrupt Status + 8 + 8 read-only 0 - SOF output is stopped. + BRDY interrupts are not generated. #0 1 - SOF output is operating. + BRDY interrupts are generated. #1 - IDMON - External ID0 Input Pin Monitor - 2 - 2 + VBSTS + VBUS Input Status + 7 + 7 read-only 0 - USB0_ID pin is low + USB_VBUS pin is low. #0 1 - USB0_ID pin is high + USB_VBUS pin is high. #1 - LNST - USB Data Line Status Monitor - 0 - 1 + DVSQ + Device State + 4 + 6 read-only - 00 - SE0 - #00 + 000 + Powered state + #000 - 01 - K-State (FS) / J-State(LS) - #01 + 001 + Default state + #001 - 10 - J-State(FS) / K-State(LS) - #10 + 010 + Address state + #010 - 11 - SE1 - #11 + 011 + Configured state + #011 + + + others + Suspended state + true - - - - PLLSTA - PLL Status Register - 0x006 - 16 - read-only - 0x0000 - 0x0001 - - PLLLOCK - PLL Lock Flag - 0 - 0 - read-only + VALID + USB Request Reception + 3 + 3 + read-write 0 - PLL is not locked. + Setup packet is not received #0 1 - PLL is locked. + Setup packet is received #1 + + CTSQ + Control Transfer Stage + 0 + 2 + read-only + + + 000 + Idle or setup stage + #000 + + + 001 + Control read data stage + #001 + + + 010 + Control read status stage + #010 + + + 011 + Control write data stage + #011 + + + 100 + Control write status stage + #100 + + + 101 + Control write (no data) status stage + #101 + + + 110 + Control transfer sequence error + #110 + + + others + Setting prohibited + true + + + - DVSTCTR0 - Device State Control Register 0 - 0x008 + INTSTS1 + Interrupt Status Register 1 + 0x042 16 read-write 0x0000 0xFFFF - HNPBTOA - Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. - 11 - 11 + OVRCR + Overcurrent Input Change Interrupt Status + 15 + 15 read-write + zeroToClear + modify 0 - Normal Operation + OVRCR interrupts are not generated. #0 1 - Switching from device B to device A is enabled + OVRCR interrupts are generated. #1 - EXICEN - USB_EXICEN Output Pin Control - 10 - 10 + BCHG + USB Bus Change Interrupt Status + 14 + 14 read-write + zeroToClear + modify 0 - External USB_EXICEN pin outputs low + BCHG interrupts are not generated. #0 1 - External USB_EXICEN pin outputs high + BCHG interrupts are generated. #1 - VBUSEN - USB_VBUSEN Output Pin Control - 9 - 9 + DTCH + USB Disconnection Detection Interrupt Status + 12 + 12 + read-write + zeroToClear + modify + + + 0 + DTCH interrupts are not generated. + #0 + + + 1 + DTCH interrupts are generated. + #1 + + + + + ATTCH + ATTCH Interrupt Status + 11 + 11 read-write + zeroToClear + modify 0 - External USB_VBUSEN pin outputs low + ATTCH interrupts are not generated. #0 1 - External USB_VBUSEN pin outputs high + ATTCH interrupts are generated. #1 - WKUP - Wakeup Output - 8 - 8 + L1RSMEND + L1 Resume End Interrupt Status + 9 + 9 read-write + zeroToClear + modify 0 - Remote wakeup signal is not output. + L1RSMEND interrupts are not generated #0 1 - Remote wakeup signal is output. + L1RSMEND interrupts are generated #1 - RWUPE - Wakeup Detection Enable - 7 - 7 + LPMEND + LPM Transaction End Interrupt Status + 8 + 8 read-write + zeroToClear + modify 0 - Downstream port wakeup is disabled. + LPMEND interrupts are not generated #0 1 - Downstream port wakeup is enabled. + LPMEND interrupts are generated #1 - USBRST - USB Bus Reset Output + EOFERR + EOF Error Detection Interrupt Status 6 6 read-write + zeroToClear + modify 0 - USB bus reset signal is not output. + EOFERR interrupts are not generated. #0 1 - USB bus reset signal is output. + EOFERR interrupts are generated. #1 - RESUME - Resume Output + SIGN + Setup Transaction Error Interrupt Status 5 5 read-write + zeroToClear + modify 0 - Resume signal is not output. + SIGN interrupts are not generated. #0 1 - Resume signal is output. + SIGN interrupts are generated. #1 - UACT - USB Bus Enable + SACK + Setup Transaction Normal Response Interrupt Status 4 4 read-write + zeroToClear + modify 0 - Downstream port is disabled (SOF transmission is disabled). + SACK interrupts are not generated. #0 1 - Downstream port is enabled (SOF transmission is enabled). + SACK interrupts are generated. #1 - RHST - USB Bus Reset Status + PDDETINT0 + PDDET0 Detection Interrupt Status 0 - 2 - read-only + 0 + read-write + zeroToClear + modify - 000 - Communication speed not determined - #000 - - - 001 - Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected) - #001 - - - 010 - Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected) - #010 - - - 011 - Setting prohibited - #011 + 0 + PDDET0 detection interrupts are not generated. + #0 - others - USB bus reset in progress(When the host controller function is selected) - true + 1 + PDDET0 detection interrupts are generated. + #1 - TESTMODE - USB Test Mode Register - 0x00C + BRDYSTS + BRDY Interrupt Status Register + 0x046 16 read-write 0x0000 - 0x000F + 0xFFFF - UTST - Test Mode + 10 + 1 + PIPE%sBRDY + BRDY Interrupt Status for PIPE 0 - 3 + 0 read-write + zeroToClear + modify - 0000 - Normal operation - #0000 - - - 0001 - Test_J TestMode(When the Function Controller Function is Selected) - #0001 - - - 0010 - Test_K TestMode(When the Function Controller Function is Selected) - #0010 - - - 0011 - Test_SE0_NAK TestMode(When the Function Controller Function is Selected) - #0011 - - - 0100 - Test_Packet TestMode(When the Function Controller Function is Selected) - #0100 - - - 0101 - Reserved TestMode(When the Function Controller Function is Selected) - #0101 - - - 0110 - Reserved TestMode(When the Function Controller Function is Selected) - #0110 - - - 0111 - Reserved TestMode(When the Function Controller Function is Selected) - #0111 - - - 1001 - Test_J TestMode(When the Host Controller Function is Selected) - #1001 - - - 1010 - Test_K TestMode(When the Host Controller Function is Selected) - #1010 - - - 1011 - Test_SE0_NAK TestMode(When the Host Controller Function is Selected) - #1011 - - - 1100 - Test_Packet TestMode(When the Host Controller Function is Selected) - #1100 - - - 1101 - Test_Force_EnableTestMode(When the Host Controller Function is Selected) - #1101 - - - 1110 - Reserved TestMode(When the Host Controller Function is Selected) - #1110 + 0 + Interrupts are not generated. + #0 - 1111 - Reserved TestMode(When the Host Controller Function is Selected) - #1111 + 1 + Interrupts are generated. + #1 - CFIFOL - CFIFO Port Register L - 0x014 - 16 - read-write - 0x0000 - 0xFFFF - - - - CFIFOLL - CFIFO Port Register LL - CFIFOL - 0x014 - 8 - read-write - 0x00 - 0xFF - - - - CFIFO - CFIFO Port Register - CFIFOL - 0x014 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - CFIFOH - CFIFO Port Register H - CFIFO - 0x016 - 16 - read-write - 0x0000 - 0xFFFF - - - - CFIFOHH - CFIFO Port Register HH - CFIFOH - 0x017 - 8 - read-write - 0x00 - 0xFF - - - - D0FIFOL - D0FIFO Port Register L - 0x018 - 16 - read-write - 0x0000 - 0xFFFF - - - - D0FIFOLL - D0FIFO Port Register LL - D0FIFOL - 0x018 - 8 - read-write - 0x00 - 0xFF - - - - D0FIFO - D0FIFO Port Register - D0FIFOL - 0x018 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - D0FIFOH - D0FIFO Port Register H - D0FIFO - 0x01A - 16 - read-write - 0x0000 - 0xFFFF - - - - D0FIFOHH - D0FIFO Port Register HH - D0FIFOH - 0x01B - 8 - read-write - 0x00 - 0xFF - - - - D1FIFOL - D1FIFO Port Register L - 0x01C - 16 - read-write - 0x0000 - 0xFFFF - - - - D1FIFOLL - D1FIFO Port Register LL - D1FIFOL - 0x01C - 8 - read-write - 0x00 - 0xFF - - - - D1FIFO - D1FIFO Port Register - D1FIFOL - 0x01C - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - D1FIFOH - D1FIFO Port Register H - D1FIFO - 0x01E - 16 - read-write - 0x0000 - 0xFFFF - - - - D1FIFOHH - D1FIFO Port Register HH - D1FIFOH - 0x01F - 8 - read-write - 0x00 - 0xFF - - - - CFIFOSEL - CFIFO Port Select Register - 0x020 + NRDYSTS + NRDY Interrupt Status Register + 0x048 16 read-write 0x0000 0xFFFF - RCNT - Read Count Mode - 15 - 15 + 10 + 1 + PIPE%sNRDY + NRDY Interrupt Status for PIPE + 0 + 0 read-write + zeroToClear + modify 0 - The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) + Interrupts are not generated. #0 1 - The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. + Interrupts are generated. #1 + + + + BEMPSTS + BEMP Interrupt Status Register + 0x04A + 16 + read-write + 0x0000 + 0xFFFF + - REW - Buffer Pointer Rewind - 14 - 14 + 10 + 1 + PIPE%sBEMP + BEMP Interrupt Status for PIPE + 0 + 0 read-write + zeroToClear + modify 0 - The buffer pointer is not rewound. + Interrupts are not generated. #0 1 - The buffer pointer is rewound. + Interrupts are generated. #1 + + + + FRMNUM + Frame Number Register + 0x04C + 16 + read-write + 0x0000 + 0xFFFF + - MBW - CFIFO Port Access Bit Width - 10 - 11 + OVRN + Overrun/Underrun Detection Status + 15 + 15 read-write 0 - 8-bit width - 0 + No error + #0 1 - 16-bit width - 1 - - - 2 - 32-bit width - 2 + An error occurred + #1 - BIGEND - CFIFO Port Endian Control - 8 - 8 + CRCE + Receive Data Error + 14 + 14 read-write 0 - Little endian + No error #0 1 - Big endian + An error occurred #1 - ISEL - CFIFO Port Access Direction When DCP is Selected - 5 - 5 + FRNM + Frame NumberLatest frame number + 0 + 10 + read-only + + + + + UFRMNUM + uFrame Number Register + 0x04E + 16 + read-write + 0x0000 + 0x8007 + + + DVCHG + Device State Change + 15 + 15 read-write 0 - Reading from the buffer memory is selected + Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. #0 1 - Writing to the buffer memory is selected + Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. #1 - CURPIPE - CFIFO Port Access Pipe Specification + UFRNM + MicroframeIndicate the microframe number. 0 - 3 + 2 + read-only + + + + + USBADDR + USB Address Register + 0x050 + 16 + read-write + 0x0000 + 0x077F + + + STSRECOV0 + Status Recovery + 8 + 10 read-write - - 0000 - DCP (Default control pipe) - #0000 - - - 0001 - Pipe 1 - #0001 - - - 0010 - Pipe 2 - #0010 - - - 0011 - Pipe 3 - #0011 + + 001 + Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) + #001 - 0100 - Pipe 4 - #0100 + 010 + Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected) + #010 - 0101 - Pipe 5 - #0101 + 011 + Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) + #011 - 0110 - Pipe 6 - #0110 + 100 + Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected) + #100 - 0111 - Pipe 7 - #0111 + 101 + Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) + #101 - 1000 - Pipe 8 - #1000 + 110 + Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected) + #110 - 1001 - Pipe 9 - #1001 + 111 + Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) + #111 others - Setting prohibited + Setting prohibited. true + + USBADDR + USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully. + 0 + 6 + read-only + - CFIFOCTR - CFIFO Port Control Register - 0x022 + USBREQ + USB Request Type Register + 0x054 16 read-write 0x0000 0xFFFF - BVAL - Buffer Memory Valid Flag - 15 + BREQUEST + RequestThese bits store the USB request bRequest value. + 8 15 read-write - - - 0 - Invalid - #0 - - - 1 - Writing ended - #1 - - - BCLR - CPU Buffer ClearNote: Only 0 can be read. - 14 - 14 + BMREQUESTTYPE + Request TypeThese bits store the USB request bmRequestType value. + 0 + 7 read-write - - - 0 - Does not operate - #0 - - - 1 - FIFO buffer cleared on the CPU side. - #1 - - + + + + USBVAL + USB Request Value Register + 0x056 + 16 + read-write + 0x0000 + 0xFFFF + - FRDY - FIFO Port Ready - 13 - 13 - read-only - - - 0 - FIFO port access is disabled. - #0 - - - 1 - FIFO port access is enabled. - #1 - - + WVALUE + ValueThese bits store the USB request Value value. + 0 + 15 + read-write + + + + USBINDX + USB Request Index Register + 0x058 + 16 + read-write + 0x0000 + 0xFFFF + - DTLN - Receive Data LengthIndicates the length of the receive data. + WINDEX + IndexThese bits store the USB request wIndex value. 0 - 11 - read-only + 15 + read-write - D0FIFOSEL - D0FIFO Port Select Register - 0x028 + USBLENG + USB Request Length Register + 0x05A 16 read-write 0x0000 0xFFFF - RCNT - Read Count Mode - 15 + WLENGTH + LengthThese bits store the USB request wLength value. + 0 15 read-write + + + + + DCPCFG + DCP Configuration Register + 0x05C + 16 + read-write + 0x0000 + 0xFFFF + + + CNTMD + Continuous Transfer Mode + 8 + 8 + read-write 0 - The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) + Non-continuous transfer mode #0 1 - The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) + Continuous transfer mode #1 - REW - Buffer Pointer RewindNote: Only 0 can be read. - 14 - 14 + SHTNAK + Pipe Disabled at End of Transfer + 7 + 7 read-write 0 - The buffer pointer is not rewound. + Pipe continued at the end of transfer #0 1 - The buffer pointer is rewound. + Pipe disabled at the end of transfer #1 - DCLRM - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read - 13 - 13 + DIR + Transfer Direction + 4 + 4 read-write 0 - Auto buffer clear mode is disabled. + Data receiving direction #0 1 - Auto buffer clear mode is enabled. + Data transmitting direction #1 + + + + DCPMAXP + DCP Maximum Packet Size Register + 0x05E + 16 + read-write + 0x0040 + 0xFFFF + - DREQE - DMA/DTC Transfer Request Enable + DEVSEL + Device Select 12 - 12 + 15 read-write - 0 - DMA/DTC transfer request is disabled. - #0 + 0000 + Address 0000 + #0000 - 1 - DMA/DTC transfer request is enabled. - #1 + 0001 + Address 0001 + #0001 - - - - MBW - FIFO Port Access Bit Width - 10 - 11 - read-write - - 0 - 8-bit width - 0 + 0010 + Address 0010 + #0010 - 1 - 16-bit width - 1 + 0011 + Address 0011 + #0011 - 2 - 32-bit width - 2 + 0100 + Address 0100 + #0100 - - - - BIGEND - FIFO Port Endian Control - 8 - 8 - read-write - - 0 - Little endian - #0 + 0101 + Address 0101 + #0101 - 1 - Big endian - #1 + others + Settings prohibited. + true - CURPIPE - FIFO Port Access Pipe Specification + MXPS + Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP. 0 - 3 + 6 read-write - 0000 - DCP (Default control pipe) - #0000 + 0x08 + 8 bytes + 0x08 - 0001 - Pipe 1 - #0001 + 0x10 + 16 bytes + 0x10 - 0010 - Pipe 2 - #0010 + 0x18 + 24 bytes + 0x18 - 0011 - Pipe 3 - #0011 + 0x20 + 32 bytes + 0x20 - 0100 - Pipe 4 - #0100 + 0x28 + 40 bytes + 0x28 - 0101 - Pipe 5 - #0101 + 0x30 + 48 bytes + 0x30 - 0110 - Pipe 6 - #0110 + 0x38 + 56 bytes + 0x38 - 0111 - Pipe 7 - #0111 + 0x40 + 64 bytes + 0x40 - 1000 - Pipe 8 - #1000 + 0x48 + 72 bytes + 0x48 - 1001 - Pipe 9 - #1001 + 0x50 + 80 bytes + 0x50 + + + 0x58 + 88 bytes + 0x58 + + + 0x60 + 96 bytes + 0x60 + + + 0x68 + 104 bytes + 0x68 + + + 0x70 + 112 bytes + 0x70 + + + 0x78 + 120 bytes + 0x78 others @@ -70732,268 +82544,266 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - D0FIFOCTR - D0FIFO Port Control Register - 0x02A + DCPCTR + DCP Control Register + 0x060 16 read-write - 0x0000 + 0x0040 0xFFFF - BVAL - Buffer Memory Valid Flag + BSTS + Buffer Status 15 15 - read-write + read-only 0 - Invalid + Buffer access is disabled. #0 1 - Writing ended + Buffer access is enabled. #1 - BCLR - CPU Buffer ClearNote: Only 0 can be read. + SUREQ + Setup Token Transmission 14 14 read-write 0 - Does not operate + Invalid #0 1 - FIFO buffer cleared on the CPU side. + Transmits the setup packet. #1 - FRDY - FIFO Port Ready - 13 - 13 - read-only + SUREQCLR + SUREQ Bit Clear + 11 + 11 + read-write 0 - FIFO port access is disabled. + Invalid #0 1 - FIFO port access is enabled. + Clears the SUREQ bit to 0. #1 - DTLN - Receive Data LengthIndicates the length of the receive data. - 0 - 11 - read-only - - - - - D1FIFOSEL - D1FIFO Port Select Register - 0x02C - 16 - read-write - 0x0000 - 0xFFFF - - - RCNT - Read Count Mode - 15 - 15 + SQCLR + Sequence Toggle Bit Clear + 8 + 8 read-write 0 - The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) + Invalid #0 1 - The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) + Specifies DATA0. #1 - REW - Buffer Pointer Rewind - 14 - 14 + SQSET + Sequence Toggle Bit Set + 7 + 7 read-write 0 - The buffer pointer is not rewound. + Invalid #0 1 - The buffer pointer is rewound. + Specifies DATA1. #1 - DCLRM - Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read - 13 - 13 - read-write + SQMON + Sequence Toggle Bit Monitor + 6 + 6 + read-only 0 - Auto buffer clear mode is disabled. + DATA0 #0 1 - Auto buffer clear mode is enabled. + DATA1 #1 - DREQE - DMA/DTC Transfer Request Enable - 12 - 12 - read-write + PBUSY + Pipe Busy + 5 + 5 + read-only 0 - DMA/DTC transfer request is disabled. + DCP is not used for the transaction. #0 1 - DMA/DTC transfer request is enabled. + DCP is used for the transaction. #1 - MBW - FIFO Port Access Bit Width - 10 - 11 + CCPL + Control Transfer End Enable + 2 + 2 read-write 0 - 8-bit width - 0 + Invalid + #0 1 - 16-bit width - 1 - - - 2 - 32-bit width - 2 + Completion of control transfer is enabled. + #1 - BIGEND - FIFO Port Endian Control - 8 - 8 + PID + Response PID + 0 + 1 read-write - 0 - Little endian - #0 + 00 + NAK response + #00 + + + 01 + BUF response (depending on the buffer state) + #01 - 1 - Big endian - #1 + 10 + STALL response + #10 + + + 11 + STALL response + #11 + + + + PIPESEL + Pipe Window Select Register + 0x064 + 16 + read-write + 0x0000 + 0xFFFF + - CURPIPE - FIFO Port Access Pipe Specification + PIPESEL + Pipe Window Select 0 3 read-write 0000 - DCP (Default control pipe) + No pipe selected #0000 0001 - Pipe 1 + PIPE1 #0001 0010 - Pipe 2 + PIPE2 #0010 0011 - Pipe 3 + PIPE3 #0011 0100 - Pipe 4 + PIPE4 #0100 0101 - Pipe 5 + PIPE5 #0101 0110 - Pipe 6 + PIPE6 #0110 0111 - Pipe 7 + PIPE7 #0111 1000 - Pipe 8 + PIPE8 #1000 1001 - Pipe 9 + PIPE9 #1001 others - Setting prohibited + Settings prohibited. true @@ -71001,747 +82811,751 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - D1FIFOCTR - D1FIFO Port Control Register - 0x02E + PIPECFG + Pipe Configuration Register + 0x068 16 read-write 0x0000 0xFFFF - BVAL - Buffer Memory Valid Flag - 15 + TYPE + Transfer Type + 14 15 read-write - 0 - Invalid - #0 + 00 + Pipe not used + #00 - 1 - Writing ended - #1 + 01 + Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9) + #01 + + + 10 + Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9) + #10 + + + 11 + Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) + #11 - BCLR - CPU Buffer ClearNote: Only 0 can be read. - 14 - 14 + BFRE + BRDY Interrupt Operation Specification + 10 + 10 read-write 0 - Does not operate + BRDY interrupt upon transmitting or receiving data #0 1 - FIFO buffer cleared on the CPU side. + BRDY interrupt upon completion of reading data #1 - FRDY - FIFO Port Ready - 13 - 13 - read-only + DBLB + Double Buffer Mode + 9 + 9 + read-write 0 - FIFO port access is disabled. + Single buffer #0 1 - FIFO port access is enabled. + Double buffer #1 - DTLN - Receive Data LengthIndicates the length of the receive data. - 0 - 11 - read-only - - - - - INTENB0 - Interrupt Enable Register 0 - 0x030 - 16 - read-write - 0x0000 - 0xFFFF - - - VBSE - VBUS Interrupt Enable - 15 - 15 + SHTNAK + Pipe Disabled at End of Transfer + 7 + 7 read-write 0 - Interrupt output disabled + Continue pipe operation after transfer ends #0 1 - Interrupt output enabled + Disable pipe operation after transfer ends. #1 - RSME - Resume Interrupt Enable - 14 - 14 + DIR + Transfer Direction + 4 + 4 read-write 0 - Interrupt output disabled + Receiving direction #0 1 - Interrupt output enabled + Transmitting direction #1 - SOFE - Frame Number Update Interrupt Enable - 13 - 13 + EPNUM + Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. + 0 + 3 + read-write + + + + + PIPEMAXP + Pipe Maximum Packet Size Register + 0x06C + 16 + read-write + 0x0000 + 0xFFBF + + + DEVSEL + Device Select + 12 + 15 read-write - 0 - Interrupt output disabled - #0 + 0000 + Address 0000 + #0000 - 1 - Interrupt output enabled - #1 + 0001 + Address 0001 + #0001 + + + 0010 + Address 0010 + #0010 + + + 0011 + Address 0011 + #0011 + + + 0100 + Address 0100 + #0100 + + + 0101 + Address 0101 + #0101 + + + others + Settings prohibited. + true - DVSE - Device State Transition Interrupt Enable + MXPS + Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.) + 0 + 8 + read-write + + + + + PIPEPERI + Pipe Cycle Control Register + 0x06E + 16 + read-write + 0x0000 + 0xFFFF + + + IFIS + Isochronous IN Buffer Flush 12 12 read-write 0 - Interrupt output disabled + The buffer is not flushed. #0 1 - Interrupt output enabled + The buffer is flushed. #1 - CTRE - Control Transfer Stage Transition Interrupt Enable - 11 - 11 + IITV + Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2. + 0 + 2 read-write + + + + + 9 + 0x002 + PIPE_CTR[%s] + Pipe %s Control Register + 0x070 + 16 + read-write + 0x0000 + 0xFFFF + + + BSTS + Buffer Status + 15 + 15 + read-only 0 - Interrupt output disabled + Buffer access by the CPU is disabled. #0 1 - Interrupt output enabled + Buffer access by the CPU is enabled. #1 - BEMPE - Buffer Empty Interrupt Enable - 10 - 10 - read-write + INBUFM + Transmit Buffer Monitor + 14 + 14 + read-only 0 - Interrupt output disabled + No data to be transmitted is in the FIFO buffer #0 1 - Interrupt output enabled + Data to be transmitted is in the FIFO buffer #1 - NRDYE - Buffer Not Ready Response Interrupt Enable - 9 - 9 + CSCLR + CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe + 13 + 13 read-write 0 - Interrupt output disabled + Writing is disabled. #0 1 - Interrupt output enabled + The CSSTS bit is cleared. #1 - BRDYE - Buffer Ready Interrupt Enable - 8 - 8 - read-write + CSSTS + CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe + 12 + 12 + read-only 0 - Interrupt output disabled + SSplit Transaction processing is in progress or transfer without Split Transaction is in progress. #0 1 - Interrupt output enabled + CSplit Transaction processing is in progress. #1 - - - - INTENB1 - Interrupt Enable Register 1 - 0x032 - 16 - read-write - 0x0000 - 0xFFFF - - OVRCRE - Overcurrent Input Change Interrupt Enable - 15 - 15 + ATREPM + Auto Response Mode + 10 + 10 read-write 0 - Interrupt output disabled + Auto response disabled. #0 1 - Interrupt output enabled + Auto response enabled. #1 - BCHGE - USB Bus Change Interrupt Enable - 14 - 14 + ACLRM + Auto Buffer Clear Mode + 9 + 9 read-write 0 - Interrupt output disabled + Disabled #0 1 - Interrupt output enabled + Enabled (all buffers are initialized) #1 - DTCHE - Disconnection Detection Interrupt Enable - 12 - 12 + SQCLR + Sequence Toggle Bit Clear + 8 + 8 read-write 0 - Interrupt output disabled + Write disabled #0 1 - Interrupt output enabled + Specifies DATA0. #1 - ATTCHE - Connection Detection Interrupt Enable - 11 - 11 + SQSET + Sequence Toggle Bit Set + 7 + 7 read-write 0 - Interrupt output disabled + Write disabled #0 1 - Interrupt output enabled + Specifies DATA1. #1 - EOFERRE - EOF Error Detection Interrupt Enable + SQMON + Sequence Toggle Bit Confirmation 6 6 - read-write + read-only 0 - Interrupt output disabled + DATA0 #0 1 - Interrupt output enabled + DATA1 #1 - SIGNE - Setup Transaction Error Interrupt Enable + PBUSY + Pipe Busy 5 5 - read-write + read-only 0 - Interrupt output disabled + Pipe n not in use for the transaction #0 1 - Interrupt output enabled + Pipe n in use for the transaction. #1 - SACKE - Setup Transaction Normal Response Interrupt Enable - 4 - 4 + PID + Response PID + 0 + 1 read-write - 0 - Interrupt output disabled - #0 + 00 + NAK response + #00 - 1 - Interrupt output enabled - #1 + 01 + BUF response (depending on the buffer state) + #01 - - - - PDDETINTE0 - PDDETINT0 Detection Interrupt Enable - 0 - 0 - read-write - - 0 - Interrupt output disabled - #0 + 10 + STALL response + #10 - 1 - Interrupt output enabled - #1 + 11 + STALL response + #11 - BRDYENB - BRDY Interrupt Enable Register - 0x036 + 10 + 0x002 + DEVADD[%s] + Device Address Configuration Register + 0x0D0 16 read-write 0x0000 0xFFFF - 10 - 1 - PIPE%sBRDYE - BRDY Interrupt Enable for PIPE - 0 - 0 + UPPHUB + Communication Target Connecting Hub Register + 11 + 14 read-write + + + 0x0000 + 0x1010 + + - 0 - Interrupt output disabled - #0 + 0000 + Directly connected to the port of the USBHS. + #0000 - 1 - Interrupt output enabled - #1 + UPPHUB + USB address of the hub + true - - - - NRDYENB - NRDY Interrupt Enable Register - 0x038 - 16 - read-write - 0x0000 - 0xFFFF - - 10 - 1 - PIPE%sNRDYE - NRDY Interrupt Enable for PIPE - 0 - 0 + HUBPORT + Communication Target Connecting Hub Port + 8 + 10 + read-write + + + 000 + Directly connected to the port of the USBHS. + #000 + + + others + Port number of the hub + true + + + + + USBSPD + Transfer Speed of Communication Target Device + 6 + 7 read-write - 0 - Interrupt output disabled - #0 + 00 + DEVADDn is not used + #00 - 1 - Interrupt output enabled - #1 + 01 + Low speed + #01 + + + 10 + Full speed + #10 + + + 11 + Setting prohibited + #11 - BEMPENB - BEMP Interrupt Enable Register - 0x03A + USBBCCTRL0 + BC Control Register 0 + 0x0B0 16 read-write 0x0000 0xFFFF - 10 - 1 - PIPE%sBEMPE - BEMP Interrupt Enable for PIPE - 0 - 0 - read-write + PDDETSTS0 + D+ Pin 0.6 V Input Detection Status + 9 + 9 + read-only 0 - Interrupt output disabled + Not detected #0 1 - Interrupt output enabled + Detected #1 - - - - SOFCFG - SOF Output Configuration Register - 0x03C - 16 - read-write - 0x0000 - 0xFFFF - - TRNENSEL - Transaction-Enabled Time Select + CHGDETSTS0 + D- Pin 0.6 V Input Detection Status 8 8 - read-write + read-only 0 - Not low-speed communication + Not detected #0 1 - Low-speed communication. + Detected #1 - BRDYM - BRDY Interrupt Status Clear Timing - 6 - 6 + BATCHGE0 + BC (Battery Charger) Function Ch0 General Enable Control + 7 + 7 read-write 0 - BRDY flag cleared by software + Disabled #0 1 - BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer. + Enabled #1 - INTL - Interrupt Output Sense Select + VDMSRCE0 + D- Pin VDMSRC (0.6 V) Output Control 5 5 read-write 0 - Edge sense + Stop #0 1 - Level sense + 0.6V output #1 - EDGESTS - Edge Interrupt Output Status Monitor + IDPSINKE0 + D+ Pin 0.6 V Input Detection (Comparator and Sink) Control 4 4 - read-only + read-write 0 - before stopping the clock supply to the USB module + Detection off #0 1 - the edge interrupt output signal is in the middle of the edge processing + Detection on ( Comparator and sink current on ) #1 - - - - PHYSET - PHY Setting Register - 0x03E - 16 - read-write - 0x0033 - 0x0B3B - - HSEB - CL-Only Mode - 15 - 15 + VDPSRCE0 + D+ Pin VDPSRC (0.6 V) Output Control + 3 + 3 read-write 0 - CL-only mode is not activated. + Stop #0 1 - CL-only mode is activated. + 0.6V output #1 - REPSTART - Forcibly Start Terminating Resistance Adjustment - 11 - 11 + IDMSINKE0 + D- Pin 0.6 V Input Detection (Comparator and Sink) Control + 2 + 2 read-write 0 - Terminating resistance adjustment is forcibly started + Detection off #0 1 - Terminating resistance adjustment is not forcibly started + Detection on ( Comparator and sink current on ) #1 - REPSEL - Terminating Resistance Adjustment Cycle - 8 - 9 - read-write - - - 00 - No cycle is set. - #00 - - - 01 - Adjust terminating resistance at 16-second intervals. - #01 - - - 10 - Adjust terminating resistance at 64-second intervals. - #10 - - - 11 - Adjust terminating resistance at 128-second intervals. - #11 - - - - - CLKSEL - Input System Clock Frequency - 4 - 5 - read-write - - - 00 - Setting Prohibited - #00 - - - 01 - 12 MHz - #01 - - - 10 - 20 MHz - #10 - - - 11 - 24 MHz - #11 - - - - - CDPEN - Charging Downstream Port Enable - 3 - 3 + IDPSRCE0 + D+ Pin IDPSRC Output Control + 1 + 1 read-write 0 - Disable charging downstream port + Stop #0 1 - Enable charging downstream port + 10uA output #1 - PLLRESET - PLL Reset Control - 1 - 1 + RPDME0 + D- Pin Pull-Down Control + 0 + 0 read-write 0 - Disable PLL reset control for UTMI_PHY + Pull-down off #0 1 - Enable PLL reset control for UTMI_PHY + Pull-down on #1 + + + + UCKSEL + USB Clock Selection Register + 0x0C4 + 16 + read-write + 0x0000 + 0xFFFF + - DIRPD - Power-Down Control + UCKSELC + USB Clock Selection 0 0 read-write 0 - Does not enter low-power consumption mode + High-speed on-chip oscillator clock (HOCO) is not selected as USB clock #0 1 - Enter low-power consumption mode + High-speed on-chip oscillator clock (HOCO) is selected as USB clock #1 @@ -71749,514 +83563,565 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - INTSTS0 - Interrupt Status Register 0 - 0x040 + USBMC + USB Module Control Register + 0x0CC 16 read-write - 0x0000 - 0xFF7F + 0x0002 + 0xFFFF - VBINT - VBUS Interrupt Status - 15 - 15 + VDCEN + USB Regulator On/Off Control + 7 + 7 read-write - zeroToClear - modify 0 - VBUS interrupts are not generated. + USB regulator off #0 1 - VBUS interrupts are generated. + USB regulator on #1 - RESM - Resume Interrupt Status - 14 - 14 + VDDUSBE + USB Reference Power Supply Circuit On/Off Control + 0 + 0 read-write - zeroToClear - modify 0 - Resume interrupts are not generated. + USB reference power supply circuit off #0 1 - Resume interrupts are generated. + USB reference power supply circuit on #1 + + + + PHYSLEW + PHY Cross Point Adjustment Register + 0x0F0 + 32 + read-write + 0x0000000E + 0xFF4CFFFF + - SOFR - Frame Number Refresh Interrupt Status - 13 - 13 + SLEWF01 + Receiver Cross Point Adjustment 01 + 3 + 3 read-write - zeroToClear - modify - - 0 - SOF interrupts are not generated. - #0 - 1 - SOF interrupts are generated. + Host or device controller mode. #1 - DVST - Device State Transition Interrupt Status - 12 - 12 + SLEWF00 + Receiver Cross Point Adjustment 00 + 2 + 2 read-write - zeroToClear - modify - - 0 - Device state transition interrupts are not generated. - #0 - 1 - Device state transition interrupts are generated. + Host or device controller mode. #1 - CTRT - Control Transfer Stage Transition Interrupt Status - 11 - 11 + SLEWR01 + Receiver Cross Point Adjustment 01 + 1 + 1 read-write - zeroToClear - modify - - 0 - Control transfer stage transition interrupts are not generated. - #0 - 1 - Control transfer stage transition interrupts are generated. + Host or device controller mode. #1 - BEMP - Buffer Empty Interrupt Status - 10 - 10 - read-only + SLEWR00 + Receiver Cross Point Adjustment 00 + 0 + 0 + read-write - - 0 - BEMP interrupts are not generated. - #0 - 1 - BEMP interrupts are generated. + Host or device controller mode. #1 + + + + LPCTRL + Low Power Control Register + 0x100 + 16 + read-write + 0x0000 + 0x0181 + - NRDY - Buffer Not Ready Interrupt Status - 9 - 9 - read-only + HWUPM + Resume Return Mode Setting + 7 + 7 + read-write 0 - NRDY interrupts are not generated. + Hardware does not recover while CPU clock inactive #0 1 - NRDY interrupts are generated. + Hardware recovers while CPU clock inactive. #1 + + + + LPSTS + Low Power Status Register + 0x102 + 16 + read-write + 0x0000 + 0x510B + - BRDY - Buffer Ready Interrupt Status - 8 - 8 - read-only + SUSPENDM + UTMI SuspendM Control + 14 + 14 + read-write 0 - BRDY interrupts are not generated. + UTMI suspension mode #0 1 - BRDY interrupts are generated. + UTMI normal mode #1 + + + + BCCTRL + Battery Charging Control Register + 0x140 + 16 + read-write + 0x0000 + 0x033F + - VBSTS - VBUS Input Status - 7 - 7 + PDDETSTS + PDDET Status + 9 + 9 read-only 0 - USB_VBUS pin is low. + The PDDET pin is at low level. #0 1 - USB_VBUS pin is high. + The PDDET pin is at high level. #1 - DVSQ - Device State - 4 - 6 + CHGDETSTS + CHGDET Status + 8 + 8 read-only - - - 000 - Powered state - #000 - - - 001 - Default state - #001 - - - 010 - Address state - #010 - - - 011 - Configured state - #011 - - - others - Suspended state - true - - - - - VALID - USB Request Reception - 3 - 3 - read-write 0 - Setup packet is not received + The CHGDET pin is at low level. #0 1 - Setup packet is received + The CHGDET pin is at high level. #1 - CTSQ - Control Transfer Stage - 0 - 2 - read-only - - - 000 - Idle or setup stage - #000 - - - 001 - Control read data stage - #001 - - - 010 - Control read status stage - #010 - - - 011 - Control write data stage - #011 - - - 100 - Control write status stage - #100 - - - 101 - Control write (no data) status stage - #101 - + DCPMODE + DCP Mode Control + 5 + 5 + read-write + - 110 - Control transfer sequence error - #110 + 0 + The RDCP_DAT resistor is disabled + #0 - others - Setting prohibited - true + 1 + The RDCP_DAT resistor is enabled. + #1 - - - - INTSTS1 - Interrupt Status Register 1 - 0x042 - 16 - read-write - 0x0000 - 0xFFFF - - OVRCR - Overcurrent Input Change Interrupt Status - 15 - 15 + VDMSRCE + VDMSRC Control + 4 + 4 read-write - zeroToClear - modify 0 - OVRCR interrupts are not generated. + The VDM_SRC circuit is disabled. (Initial value) #0 1 - OVRCR interrupts are generated. + The VDM_SRC circuit is enabled. #1 - BCHG - USB Bus Change Interrupt Status - 14 - 14 + IDPSINKE + IDPSINK Control + 3 + 3 read-write - zeroToClear - modify 0 - BCHG interrupts are not generated. + The IDP_SINK circuit is disabled. (Initial value) #0 1 - BCHG interrupts are generated. + The IDP_SINK circuit is enabled. #1 - DTCH - USB Disconnection Detection Interrupt Status - 12 - 12 + VDPSRCE + VDPSRC Control + 2 + 2 read-write - zeroToClear - modify 0 - DTCH interrupts are not generated. + The VDP_SRC circuit is disabled. (Initial value) #0 1 - DTCH interrupts are generated. + The VDP_SRC circuit is enabled. #1 - ATTCH - ATTCH Interrupt Status - 11 - 11 + IDMSINKE + IDMSINK Control + 1 + 1 read-write - zeroToClear - modify 0 - ATTCH interrupts are not generated. + The IDM_SINK circuit is disabled. (Initial value) #0 1 - ATTCH interrupts are generated. + The IDM_SINK circuit is enabled. #1 - L1RSMEND - L1 Resume End Interrupt Status - 9 - 9 + IDPSRCE + IDPSRC Control + 0 + 0 read-write - zeroToClear - modify 0 - L1RSMEND interrupts are not generated + The IDP_SRC circuit is disabled. (Initial value) #0 1 - L1RSMEND interrupts are generated + The IDP_SRC circuit is enabled. #1 + + + + PL1CTRL1 + Function L1 Control Register 1 + 0x144 + 16 + read-write + 0x0000 + 0x4FFF + - LPMEND - LPM Transaction End Interrupt Status - 8 - 8 + L1EXTMD + PHY Control Mode at L1 Return + 14 + 14 read-write - zeroToClear - modify 0 - LPMEND interrupts are not generated + SUSPENDM is not set by hardware when Host K is received. #0 1 - LPMEND interrupts are generated + SUSPENDM is set by hardware when Host K is received. #1 - EOFERR - EOF Error Detection Interrupt Status - 6 - 6 + HIRDTHR + L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL. + 8 + 11 + read-write + + + DVSQ + DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0]. + 4 + 7 + read-only + + + 0000 + Powered state + #0000 + + + 0001 + Default state + #0001 + + + 0010 + Address state + #0010 + + + 0011 + Configured state + #0011 + + + 0100 + Suspended state + #0100 + + + 0101 + Suspended state + #0101 + + + 0110 + Suspended state + #0110 + + + 0111 + Suspended state + #0111 + + + 1000 + L1 state + #1000 + + + 1001 + L1 state + #1001 + + + 1010 + L1 state + #1010 + + + 1011 + L1 state + #1011 + + + others + setting prohibited + true + + + + + L1NEGOMD + L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11. + 3 + 3 read-write - zeroToClear - modify 0 - EOFERR interrupts are not generated. + When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. #0 1 - EOFERR interrupts are generated. + When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. #1 - SIGN - Setup Transaction Error Interrupt Status - 5 - 5 + L1RESPMD + L1 Response Mode + 1 + 2 + read-write + + + 00 + NYET + #00 + + + 01 + ACK + #01 + + + 10 + STALL + #10 + + + 11 + According to the L1NEGOMD bit + #11 + + + + + L1RESPEN + L1 Response Enable + 0 + 0 read-write - zeroToClear - modify 0 - SIGN interrupts are not generated. + LPM is not supported. #0 1 - SIGN interrupts are generated. + LPM is supported. #1 + + + + PL1CTRL2 + Function L1 Control Register 2 + 0x146 + 16 + read-write + 0x0000 + 0x1F00 + - SACK - Setup Transaction Normal Response Interrupt Status - 4 - 4 + RWEMON + RWE Value Monitor + 12 + 12 read-write - zeroToClear - modify 0 - SACK interrupts are not generated. + The RWE bit value of the LPM token received last is reflected. #0 1 - SACK interrupts are generated. + The RWE bit value of the LPM token received last is reflected. #1 - PDDETINT0 - PDDET0 Detection Interrupt Status - 0 - 0 + HIRDMON + HIRD Value Monitor + 8 + 11 read-write - zeroToClear - modify 0 - PDDET0 detection interrupts are not generated. + The HIRD field value of the LPM token received last is reflected. #0 1 - PDDET0 detection interrupts are generated. + The HIRD field value of the LPM token received last is reflected. #1 @@ -72264,33 +84129,58 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - BRDYSTS - BRDY Interrupt Status Register - 0x046 + HL1CTRL1 + Host L1 Control Register 1 + 0x148 16 read-write 0x0000 - 0xFFFF + 0x0007 - 10 - 1 - PIPE%sBRDY - BRDY Interrupt Status for PIPE + L1STATUS + L1 Request Completion Status + 1 + 2 + read-only + + + 00 + ACK received + #00 + + + 01 + NYET received + #01 + + + 10 + STALL received + #10 + + + 11 + Transaction error + #11 + + + + + L1REQ + L1 Transition Request 0 0 read-write - zeroToClear - modify 0 - Interrupts are not generated. + This bit is cleared to 0 by hardware when the LPM transaction is completed. #0 1 - Interrupts are generated. + Set this bit to 1 when requesting a transition to the L1 state. #1 @@ -72298,374 +84188,378 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - NRDYSTS - NRDY Interrupt Status Register - 0x048 + HL1CTRL2 + Host L1 Control Register 2 + 0x14A 16 read-write 0x0000 - 0xFFFF + 0x9F0F - 10 - 1 - PIPE%sNRDY - NRDY Interrupt Status for PIPE + BESL + BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume. + 15 + 15 + read-write + + + L1RWE + LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token. + 12 + 12 + read-write + + + HIRD + LPM Token HIRD + 8 + 11 + read-write + + + 0000 + 50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1) + #0000 + + + 0001 + 125 us(BESL = 0) / 100 us(BESL = 1) + #0001 + + + 0010 + 200 us(BESL = 0) / 150 us(BESL = 1) + #0010 + + + 0011 + 275 us(BESL = 0) / 250 us(BESL = 1) + #0011 + + + 0100 + 350 us(BESL = 0) / 350 us(BESL = 1) + #0100 + + + 0101 + 425 us(BESL = 0) / 450 us(BESL = 1) + #0101 + + + 0110 + 500 us(BESL = 0) / 950 us(BESL = 1) + #0110 + + + 0111 + 575 us(BESL = 0) / 1950 us(BESL = 1) + #0111 + + + 1000 + 650 us(BESL = 0) / 2950 us(BESL = 1) + #1000 + + + 1001 + 725 us(BESL = 0) / 3950 us(BESL = 1) + #1001 + + + 1010 + 800 us(BESL = 0) / 4950 us(BESL = 1) + #1010 + + + 1011 + 875 us(BESL = 0) / 5950 us(BESL = 1) + #1011 + + + 1100 + 950 us(BESL = 0) / 6950 us(BESL = 1) + #1100 + + + 1101 + 1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1) + #1101 + + + 1110 + 1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1) + #1110 + + + 1111 + 1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1) + #1111 + + + + + L1ADDR + LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token. 0 - 0 + 3 read-write - zeroToClear - modify + + + + + DPUSR0R + Deep Standby USB Transceiver Control/Pin Monitor Register + 0x160 + 32 + read-only + 0x00000000 + 0xFF4FFFFF + + + DVBSTSHM + VBUS InputIndicates VBUS input signal on the HS side of USB port. + 23 + 23 + read-only + + + DOVCBHM + OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. + 21 + 21 + read-only + + + DOVCAHM + OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. + 20 + 20 + read-only + + + + + DPUSR1R + Deep Standby USB Suspend/Resume Interrupt Register + 0x164 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + DVBSTSH + Indication of Return from VBUS Interrupt Source + 23 + 23 + read-only 0 - Interrupts are not generated. + Indicates deep software standby mode #0 1 - Interrupts are generated. + Indicates return from deep software standby mode #1 - - - - BEMPSTS - BEMP Interrupt Status Register - 0x04A - 16 - read-write - 0x0000 - 0xFFFF - - 10 - 1 - PIPE%sBEMP - BEMP Interrupt Status for PIPE - 0 - 0 - read-write - zeroToClear - modify + DOVCBH + Indication of Return from OVRCURB Interrupt Source + 21 + 21 + read-only 0 - Interrupts are not generated. + Indicates deep software standby mode #0 1 - Interrupts are generated. + Indicates return from deep software standby mode #1 - - - - FRMNUM - Frame Number Register - 0x04C - 16 - read-write - 0x0000 - 0xFFFF - - OVRN - Overrun/Underrun Detection Status - 15 - 15 - read-write + DOVCAH + Indication of Return from OVRCURA Interrupt Source + 20 + 20 + read-only 0 - No error + Indicates deep software standby mode #0 1 - An error occurred + Indicates return from deep software standby mode #1 - CRCE - Receive Data Error - 14 - 14 + DVBSTSHE + VBUS Interrupt Enable/Clear + 7 + 7 read-write 0 - No error + Disables return from deep software standby mode #0 1 - An error occurred + Enables return from deep software standby mode #1 - FRNM - Frame NumberLatest frame number - 0 - 10 - read-only - - - - - UFRMNUM - uFrame Number Register - 0x04E - 16 - read-write - 0x0000 - 0x8007 - - - DVCHG - Device State Change - 15 - 15 + DOVCBHE + OVRCURB Interrupt Enable Clear + 5 + 5 read-write 0 - Disables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. + Disables return from deep software standby mode #0 1 - Enables the writing to the USBADDR.STSRECOV0[2:0] bits and USBADDR.USBADDR[6:0]. + Enables return from deep software standby mode #1 - UFRNM - MicroframeIndicate the microframe number. - 0 - 2 - read-only - - - - - USBADDR - USB Address Register - 0x050 - 16 - read-write - 0x0000 - 0x077F - - - STSRECOV0 - Status Recovery - 8 - 10 + DOVCAHE + OVRCURA Interrupt Enable Clear + 4 + 4 read-write - 001 - Return to the full-speed state(bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) - #001 - - - 010 - Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the low-speed state (bitsDVSTCTR0.RHST[2:0] = 001b)(host controller is selected) - #010 - - - 011 - Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) - #011 - - - 100 - Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b)(host controller selected) - #100 - - - 101 - Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 001b (Default state)(function controller selected) - #101 - - - 110 - Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 010b (Address state)(function controller selected)/ Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b)(host controller selected) - #110 - - - 111 - Return to the high-speed state (bits DVSTCTR0.RHST[2:0] = 011b), bits INTSTS0.DVSQ[2:0] = 011b (Configured state)(function controller selected) - #111 + 0 + Disables return from deep software standby mode + #0 - others - Setting prohibited. - true + 1 + Enables return from deep software standby mode + #1 - - USBADDR - USB Address In device controller mode, these flags indicate the USB address assigned by the host when the USBHS processed the SET_ADDRESS request successfully. - 0 - 6 - read-only - - - - - USBREQ - USB Request Type Register - 0x054 - 16 - read-write - 0x0000 - 0xFFFF - - - BREQUEST - RequestThese bits store the USB request bRequest value. - 8 - 15 - read-write - - - BMREQUESTTYPE - Request TypeThese bits store the USB request bmRequestType value. - 0 - 7 - read-write - - - - - USBVAL - USB Request Value Register - 0x056 - 16 - read-write - 0x0000 - 0xFFFF - - - WVALUE - ValueThese bits store the USB request Value value. - 0 - 15 - read-write - - - - - USBINDX - USB Request Index Register - 0x058 - 16 - read-write - 0x0000 - 0xFFFF - - - WINDEX - IndexThese bits store the USB request wIndex value. - 0 - 15 - read-write - - USBLENG - USB Request Length Register - 0x05A + DPUSR2R + Deep Standby USB Suspend/Resume Interrupt Register + 0x168 16 read-write 0x0000 0xFFFF - WLENGTH - LengthThese bits store the USB request wLength value. - 0 - 15 + DMINTE + DM Interrupt Enable Clear + 9 + 9 read-write + + + 0 + Disables return from deep software standby mode + #0 + + + 1 + Enables return from deep software standby mode + #1 + + - - - - DCPCFG - DCP Configuration Register - 0x05C - 16 - read-write - 0x0000 - 0xFFFF - - CNTMD - Continuous Transfer Mode + DPINTE + DP Interrupt Enable Clear 8 8 read-write 0 - Non-continuous transfer mode + Disables return from deep software standby mode #0 1 - Continuous transfer mode + Enables return from deep software standby mode #1 - SHTNAK - Pipe Disabled at End of Transfer - 7 - 7 - read-write + DMVAL + DM InputIndicates DM input signal on the HS side of USB port. + 5 + 5 + read-only + + + DPVAL + DP InputIndicates DP input signal on the HS side of USB port. + 4 + 4 + read-only + + + DMINT + Indication of Return from DM Interrupt Source + 1 + 1 + read-only 0 - Pipe continued at the end of transfer + Indicates deep software standby mode #0 1 - Pipe disabled at the end of transfer + Indicates return from deep software standby mode #1 - DIR - Transfer Direction - 4 - 4 - read-write + DPINT + Indication of Return from DP Interrupt Source + 0 + 0 + read-only 0 - Data receiving direction + Indicates deep software standby mode #0 1 - Data transmitting direction + Indicates return from deep software standby mode #1 @@ -72673,1162 +84567,1655 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - DCPMAXP - DCP Maximum Packet Size Register - 0x05E + DPUSRCR + Deep Standby USB Suspend/Resume Command Register + 0x16A 16 read-write - 0x0040 + 0x0000 0xFFFF - DEVSEL - Device Select - 12 - 15 + FIXPHYPD + USB Transceiver Control Fix for PLL + 1 + 1 read-write - 0000 - Address 0000 - #0000 - - - 0001 - Address 0001 - #0001 - - - 0010 - Address 0010 - #0010 - - - 0011 - Address 0011 - #0011 - - - 0100 - Address 0100 - #0100 - - - 0101 - Address 0101 - #0101 + 0 + Normal mode + #0 - others - Settings prohibited. - true + 1 + Go to/Return from deep software standby mode + #1 - MXPS - Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP. + FIXPHY + USB Transceiver Control Fix 0 - 6 + 0 read-write - 0x08 - 8 bytes - 0x08 - - - 0x10 - 16 bytes - 0x10 - - - 0x18 - 24 bytes - 0x18 - - - 0x20 - 32 bytes - 0x20 - - - 0x28 - 40 bytes - 0x28 - - - 0x30 - 48 bytes - 0x30 - - - 0x38 - 56 bytes - 0x38 - - - 0x40 - 64 bytes - 0x40 - - - 0x48 - 72 bytes - 0x48 - - - 0x50 - 80 bytes - 0x50 - - - 0x58 - 88 bytes - 0x58 - - - 0x60 - 96 bytes - 0x60 - - - 0x68 - 104 bytes - 0x68 - - - 0x70 - 112 bytes - 0x70 - - - 0x78 - 120 bytes - 0x78 + 0 + Normal mode + #0 - others - Setting prohibited - true + 1 + Go to/Return from deep software standby mode + #1 - DCPCTR - DCP Control Register - 0x060 - 16 + DPUSR0R_FS + Deep Software Standby USB Transceiver Control/Pin Monitor Register + 0x400 + 32 read-write - 0x0040 - 0xFFFF + 0x00000000 + 0xFF4CFFFF - BSTS - Buffer Status - 15 - 15 + DVBSTS0 + USB VBUS InputIndicates the VBUS input signal of the USB. + 23 + 23 + read-only + + + DOVCB0 + USB OVRCURB InputIndicates the OVRCURB input signal of the USB. + 21 + 21 + read-only + + + DOVCA0 + USB OVRCURA InputIndicates the OVRCURA input signal of the USB. + 20 + 20 + read-only + + + DM0 + USB D-InputIndicates the D- input signal of the USB. + 17 + 17 + read-only + + + DP0 + USB0 D+ InputIndicates the D+ input signal of the USB. + 16 + 16 read-only + + + FIXPHY0 + USB Transceiver Output Fix + 4 + 4 + read-write 0 - Buffer access is disabled. + The outputs are fixed in normal mode and on return from deep software standby mode. #0 1 - Buffer access is enabled. + The outputs are fixed on transitions to deep software standby mode. #1 - SUREQ - Setup Token Transmission - 14 - 14 + DRPD0 + D+/D- Pull-Down Resistor Control + 3 + 3 read-write 0 - Invalid + Disables DP/DM pull-down resistor. #0 1 - Transmits the setup packet. + Enables DP/DM pull-down resistor. #1 - SUREQCLR - SUREQ Bit Clear - 11 - 11 + RPUE0 + DP Pull-Up Resistor Control + 1 + 1 read-write 0 - Invalid + Disables DP pull-up resistor. #0 1 - Clears the SUREQ bit to 0. + Enables DP pull-up resistor. #1 - SQCLR - Sequence Toggle Bit Clear - 8 - 8 + SRPC0 + USB Single End Receiver Control + 0 + 0 read-write 0 - Invalid + Input through the DP and DM inputs is disabled. #0 1 - Specifies DATA0. + Input through the DP and DM inputs is enabled. #1 + + + + DPUSR1R_FS + Deep Software Standby USB Suspend/Resume Interrupt Register + 0x404 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + - SQSET - Sequence Toggle Bit Set - 7 - 7 - read-write + DVBINT0 + USB VBUS Interrupt Source Recovery + 23 + 23 + read-only 0 - Invalid + The system has not returned from deep software standby mode. #0 1 - Specifies DATA1. + The system has returned from deep software standby mode. #1 - SQMON - Sequence Toggle Bit Monitor - 6 - 6 + DOVRCRB0 + USB OVRCURB Interrupt Source Recovery + 21 + 21 read-only 0 - DATA0 + The system has not returned from deep software standby mode. #0 1 - DATA1 + The system has returned from deep software standby mode. #1 - PBUSY - Pipe Busy - 5 - 5 + DOVRCRA0 + USB OVRCURA Interrupt Source Recovery + 20 + 20 read-only 0 - DCP is not used for the transaction. + The system has not returned from deep software standby mode. #0 1 - DCP is used for the transaction. + The system has returned from deep software standby mode. #1 - CCPL - Control Transfer End Enable - 2 - 2 - read-write + DMINT0 + USB DM Interrupt Source Recovery + 17 + 17 + read-only 0 - Invalid + The system has not returned from deep software standby mode. #0 1 - Completion of control transfer is enabled. + The system has returned from deep software standby mode. #1 - PID - Response PID - 0 - 1 - read-write - - - 00 - NAK response - #00 - - - 01 - BUF response (depending on the buffer state) - #01 - - - 10 - STALL response - #10 - - - 11 - STALL response - #11 - - - - - - - PIPESEL - Pipe Window Select Register - 0x064 - 16 - read-write - 0x0000 - 0xFFFF - - - PIPESEL - Pipe Window Select - 0 - 3 - read-write + DPINT0 + USB DP Interrupt Source Recovery + 16 + 16 + read-only - 0000 - No pipe selected - #0000 - - - 0001 - PIPE1 - #0001 - - - 0010 - PIPE2 - #0010 - - - 0011 - PIPE3 - #0011 - - - 0100 - PIPE4 - #0100 - - - 0101 - PIPE5 - #0101 - - - 0110 - PIPE6 - #0110 - - - 0111 - PIPE7 - #0111 - - - 1000 - PIPE8 - #1000 - - - 1001 - PIPE9 - #1001 + 0 + The system has not returned from deep software standby mode. + #0 - others - Settings prohibited. - true + 1 + The system has returned from deep software standby mode. + #1 - - - - PIPECFG - Pipe Configuration Register - 0x068 - 16 - read-write - 0x0000 - 0xFFFF - - TYPE - Transfer Type - 14 - 15 + DVBSE0 + USB VBUS Interrupt Enable/Clear + 7 + 7 read-write - 00 - Pipe not used - #00 - - - 01 - Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9) - #01 - - - 10 - Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9) - #10 + 0 + Recovery from deep software standby mode is disabled. + #0 - 11 - Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) - #11 + 1 + Recovery from deep software standby mode is enabled. + #1 - BFRE - BRDY Interrupt Operation Specification - 10 - 10 + DOVRCRBE0 + USB OVRCURB Interrupt Enable/Clear + 5 + 5 read-write 0 - BRDY interrupt upon transmitting or receiving data + Recovery from deep software standby mode is disabled. #0 1 - BRDY interrupt upon completion of reading data + Recovery from deep software standby mode is enabled. #1 - DBLB - Double Buffer Mode - 9 - 9 + DOVRCRAE0 + USB OVRCURA Interrupt Enable/Clear + 4 + 4 read-write 0 - Single buffer + Recovery from deep software standby mode is disabled. #0 1 - Double buffer + Recovery from deep software standby mode is enabled. #1 - SHTNAK - Pipe Disabled at End of Transfer - 7 - 7 + DMINTE0 + USB DM Interrupt Enable/Clear + 1 + 1 read-write 0 - Continue pipe operation after transfer ends + Recovery from deep software standby mode is disabled. #0 1 - Disable pipe operation after transfer ends. + Recovery from deep software standby mode is enabled. #1 - DIR - Transfer Direction - 4 - 4 + DPINTE0 + USB DP Interrupt Enable/Clear + 0 + 0 read-write 0 - Receiving direction + Recovery from deep software standby mode is disabled. #0 1 - Transmitting direction + Recovery from deep software standby mode is enabled. #1 + + + + + + R_USB_HS0 + 0x40060000 + + + R_WDT + Watchdog Timer + 0x40044200 + + 0x00000000 + 0x01 + registers + + + 0x00000002 + 0x005 + registers + + + 0x00000008 + 0x01 + registers + + + + WDTRR + WDT Refresh Register + 0x00 + 8 + read-write + 0xFF + 0xFF + - EPNUM - Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. + WDTRR + WDTRR is an 8-bit register that refreshes the down-counter of the WDT. 0 - 3 + 7 read-write - PIPEMAXP - Pipe Maximum Packet Size Register - 0x06C + WDTCR + WDT Control Register + 0x02 16 read-write - 0x0000 - 0xFFBF + 0x33F3 + 0xFFFF - DEVSEL - Device Select + RPSS + Window Start Position Selection 12 - 15 + 13 read-write - 0000 - Address 0000 - #0000 + 00 + 25% + #00 - 0001 - Address 0001 - #0001 + 01 + 50% + #01 - 0010 - Address 0010 - #0010 + 10 + 75% + #10 - 0011 - Address 0011 - #0011 + 11 + 100% (window start position is not specified) + #11 + + + + RPES + Window End Position Selection + 8 + 9 + read-write + - 0100 - Address 0100 - #0100 + 00 + 75% + #00 - 0101 - Address 0101 - #0101 + 01 + 50% + #01 - others - Settings prohibited. - true + 10 + 25% + #10 + + + 11 + 0% (window end position is not specified) + #11 - MXPS - Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.) - 0 - 8 - read-write - - - - - PIPEPERI - Pipe Cycle Control Register - 0x06E - 16 - read-write - 0x0000 - 0xFFFF - - - IFIS - Isochronous IN Buffer Flush - 12 - 12 + CKS + Clock Division Ratio Selection + 4 + 7 read-write - 0 - The buffer is not flushed. - #0 + 0001 + PCLK/4 + #0001 - 1 - The buffer is flushed. - #1 + 0100 + PCLK/64 + #0100 + + + 1111 + PCLK/128 + #1111 + + + 0110 + PCLK/512 + #0110 + + + 0111 + PCLK/2048 + #0111 + + + 1000 + PCLK/8192 + #1000 + + + others + setting prohibited + true - IITV - Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2. + TOPS + Timeout Period Selection 0 - 2 + 1 read-write + + + 00 + 1,024 cycles (03FFh) + #00 + + + 01 + 4,096 cycles (0FFFh) + #01 + + + 10 + 8,192 cycles (1FFFh) + #10 + + + 11 + 16,384 cycles (3FFFh) + #11 + + - 9 - 0x002 - PIPE_CTR[%s] - Pipe %s Control Register - 0x070 + WDTSR + WDT Status Register + 0x04 16 read-write 0x0000 0xFFFF - BSTS - Buffer Status + REFEF + Refresh Error Flag 15 15 - read-only + read-write + zeroToClear + modify 0 - Buffer access by the CPU is disabled. + No refresh error occurred #0 1 - Buffer access by the CPU is enabled. + Refresh error occurred #1 - INBUFM - Transmit Buffer Monitor + UNDFF + Underflow Flag 14 14 - read-only + read-write + zeroToClear + modify 0 - No data to be transmitted is in the FIFO buffer + No underflow occurred #0 1 - Data to be transmitted is in the FIFO buffer + Underflow occurred #1 - CSCLR - CSPLIT Status ClearSet this bit to 1 when clearing the CSSTS bit of the relevant pipe - 13 + CNTVAL + Down-Counter Value + 0 13 + read-only + + + + + WDTRCR + WDT Reset Control Register + 0x06 + 8 + read-write + 0x80 + 0xFF + + + RSTIRQS + Reset Interrupt Request Selection + 7 + 7 read-write 0 - Writing is disabled. + Non-maskable interrupt request or interrupt request output is enabled #0 1 - The CSSTS bit is cleared. + Reset output is enabled. #1 + + + + WDTCSTPR + WDT Count Stop Control Register + 0x08 + 8 + read-write + 0x80 + 0xFF + - CSSTS - CSSTS StatusThis bit indicates the CSPLIT status of Split Transaction of the relevant pipe - 12 - 12 - read-only + SLCSTP + Sleep-Mode Count Stop Control + 7 + 7 + read-write 0 - SSplit Transaction processing is in progress or transfer without Split Transaction is in progress. + Count stop is disabled. #0 1 - CSplit Transaction processing is in progress. + Count is stopped at a transition to sleep mode. #1 + + + + + + R_TZF + TrustZone Filter + 0x40000E00 + + 0x00 + 2 + registers + + + 0x04 + 2 + registers + + + 0x180 + 4 + registers + + + + TZFOAD + TrustZone Filter Operation After Detection Register + 0x00 + 16 + read-write + 0x0000 + 0xffff + - ATREPM - Auto Response Mode - 10 - 10 + OAD + Operation after detection + 0 + 0 read-write 0 - Auto response disabled. + Reset #0 1 - Auto response enabled. + Non-maskable interrupt #1 - ACLRM - Auto Buffer Clear Mode - 9 - 9 + KEY + KeyCode + 8 + 15 + write-only + + + + + TZFPT + TrustZone Filter Protect Register + 0x04 + 16 + read-write + 0x0000 + 0xffff + + + PROTECT + Protection of register + 0 + 0 read-write 0 - Disabled + All Bus TrustZone Filter register writing is protected. Read is possible. #0 1 - Enabled (all buffers are initialized) + All Bus TrustZone Filter register writing is possible. #1 - SQCLR - Sequence Toggle Bit Clear + KEY + KeyCode 8 - 8 + 15 + write-only + + + + + TZFSAR + TrustZone Filter Security Attribution Register + 0x180 + 32 + read-write + 0xffffffff + 0xffffffff + + + TZFSA0 + Security attributes of registers for TrustZone Filter + 0 + 0 read-write 0 - Write disabled + Secure #0 1 - Specifies DATA0. + Non-secure #1 + + + + + + R_CPSCU + CPU System Security Control Unit + 0x40008000 + + 0x10 + 4 + registers + + + 0x14 + 4 + registers + + + 0x30 + 8 + registers + + + 0x40 + 0x12 + registers + + + 0x70 + 0x0C + registers + + + 0x100 + 8 + registers + + + 0x130 + 8 + registers + + + 0x1B0 + 4 + registers + + + + SRAMSAR + SRAM Security Attribution Register + 0x10 + 32 + read-write + 0xffffffff + 0xffffffff + - SQSET - Sequence Toggle Bit Set - 7 - 7 + SRAMSA0 + Security attributes of registers for SRAM Protection + 0 + 0 read-write - 0 - Write disabled - #0 + 0x0 + Secure + 0x0 - 1 - Specifies DATA1. - #1 + 0x1 + Nonsecure + 0x1 - SQMON - Sequence Toggle Bit Confirmation - 6 - 6 - read-only + SRAMSA1 + Security attributes of registers for SRAM Protection 2 + 1 + 1 + read-write - 0 - DATA0 - #0 + 0x0 + Secure + 0x0 - 1 - DATA1 - #1 + 0x1 + Nonsecure + 0x1 - PBUSY - Pipe Busy - 5 - 5 - read-only + SRAMSA2 + Security attributes of registers for ECC Relation + 2 + 2 + read-write - 0 - Pipe n not in use for the transaction - #0 + 0x0 + Secure + 0x0 - 1 - Pipe n in use for the transaction. - #1 + 0x1 + Nonsecure + 0x1 + + + + STBRAMSAR + Standby RAM memory Security Attribution Register + 0x014 + 32 + read-write + 0xfffffff0 + 0xffffffff + - PID - Response PID + NSBSTBR + Security attributes of each region for Standby RAM 0 - 1 + 3 read-write - 00 - NAK response - #00 + 0x0 + Region7-0 are all Secure. + 0x0 - 01 - BUF response (depending on the buffer state) - #01 + 0x1 + Region7 is Non-secure. Region6-0 are Secure + 0x1 - 10 - STALL response - #10 + 0x2 + Region7-6 are Non-secure. Region5-0 are Secure. + 0x2 - 11 - STALL response - #11 + 0x3 + Region7-5 are Non-secure. Region4-0 are Secure. + 0x3 + + + 0x4 + Region7-4 are Non-secure. Region 3-0 are Secure. + 0x4 + + + 0x5 + Region7-3 are Non-secure. Region 2-0 are Secure. + 0x5 + + + 0x6 + Region7-2 are Non-secure. Region 1-0 are Secure. + 0x6 + + + 0x7 + Region7-1 are Non-Secure. Region0 is Secure. + 0x7 + + + Others + Region7-0 are all Non-Secure. + true - 10 - 0x002 - DEVADD[%s] - Device Address Configuration Register - 0x0D0 - 16 + DTCSAR + DTC Controller Security Attribution Register + 0x30 + 32 read-write - 0x0000 - 0xFFFF + 0xffffffff + 0xffffffff - UPPHUB - Communication Target Connecting Hub Register - 11 - 14 + DTCSTSA + DTC Security Attribution + 0 + 0 read-write - - - 0x0000 - 0x1010 - - - 0000 - Directly connected to the port of the USBHS. - #0000 + 0 + Secure. + #0 - UPPHUB - USB address of the hub - true + 1 + Non-Secure. + #1 + + + + + + + DMACSAR + DMAC Controller Security Attribution Register + 0x34 + 32 + read-write + 0xffffffff + 0xffffffff + + + DMASTSA + DMAST Security Attribution + 0 + 0 + read-write + + + 0 + Secure + #0 + + + 1 + Non-secure + #1 + + + + ICUSARA + ICU Security Attribution Register A + 0x40 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SAIRQCRn + Security Attributes of registers for the IRQCRn registers + 0 + 15 + read-write + + + + + ICUSARB + ICU Security Attribution Register B + 0x44 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SANMI + Security Attributes of nonmaskable interrupt + 0 + 0 + read-write + + + + + ICUSARC + ICU Security Attribution Register C + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SADMACn + Security Attributes of registers for DMAC channel + 0 + 7 + read-write + + + + + ICUSARD + ICU Security Attribution Register D + 0x4C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SASELSR0 + Security Attributes of registers for SELSR0 + 0 + 0 + read-write + + + + + ICUSARE + ICU Security Attribution Register E + 0x50 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SAIWDTWUP + Security Attributes of registers for WUPEN0.b 16 + 16 + 16 + read-write + + + SALVD1WUP + Security Attributes of registers for WUPEN0.b 18 + 18 + 18 + read-write + + + SALVD2WUP + Security Attributes of registers for WUPEN0.b 19 + 19 + 19 + read-write + + + SARTCALMWUP + Security Attributes of registers for WUPEN0.b 24 + 24 + 24 + read-write + + + SARTCPRDWUP + Security Attributes of registers for WUPEN0.b 25 + 25 + 25 + read-write + + + SAUSBFS0WUP + Security Attributes of registers for WUPEN0.b 27 + 27 + 27 + read-write + + + SAAGT1UDWUP + Security Attributes of registers for WUPEN0.b 28 + 28 + 28 + read-write + + + SAAGT1CAWUP + Security Attributes of registers for WUPEN0.b 29 + 29 + 29 + read-write + + + SAAGT1CBWUP + Security Attributes of registers for WUPEN0.b 30 + 30 + 30 + read-write + + + SAIIC0WUP + Security Attributes of registers for WUPEN0.b 31 + 31 + 31 + read-write + + + + + ICUSARF + ICU Security Attribution Register F + 0x54 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SAAGT3UDWUP + Security Attributes of registers for WUPEN1.b 0 + 0 + 0 + read-write + + + SAAGT3CAWUP + Security Attributes of registers for WUPEN1.b 1 + 1 + 1 + read-write + + + SAAGT3CBWUP + Security Attributes of registers for WUPEN1.b 2 + 2 + 2 + read-write + + + + + ICUSARG + ICU Security Attribution Register G + 0x70 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + SAIELSRn + Security Attributes of registers for IELSR31 to IELSR0 + 0 + 31 + read-write + + + + + ICUSARH + ICU Security Attribution Register H + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + - HUBPORT - Communication Target Connecting Hub Port - 8 - 10 + SAIELSRn + Security Attributes of registers for IELSR63 to IELSR32 + 0 + 31 read-write - - - 000 - Directly connected to the port of the USBHS. - #000 - - - others - Port number of the hub - true - - + + + + ICUSARI + ICU Security Attribution Register I + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + - USBSPD - Transfer Speed of Communication Target Device - 6 - 7 + SAIELSRn + Security Attributes of registers for IELSR95 to IELSR64 + 0 + 31 read-write - - - 00 - DEVADDn is not used - #00 - - - 01 - Low speed - #01 - - - 10 - Full speed - #10 - - - 11 - Setting prohibited - #11 - - - USBBCCTRL0 - BC Control Register 0 - 0x0B0 - 16 + BUSSARA + Bus Security Attribution Register A + 0x100 + 32 read-write - 0x0000 - 0xFFFF + 0xffffffff + 0xffffffff - PDDETSTS0 - D+ Pin 0.6 V Input Detection Status - 9 - 9 - read-only + BUSSA0 + BUS Security Attribution A0 + 0 + 0 + read-write 0 - Not detected + Secure #0 1 - Detected + Non-Secure #1 + + + + BUSSARB + Bus Security Attribution Register B + 0x104 + 32 + read-write + 0xffffffff + 0xffffffff + - CHGDETSTS0 - D- Pin 0.6 V Input Detection Status - 8 - 8 - read-only + BUSSB0 + BUS Security Attribution B0 + 0 + 0 + read-write 0 - Not detected + Secure #0 1 - Detected + Non-Secure #1 + + + + MMPUSARA + Master Memory Protection Unit Security Attribution Register A + 0x130 + 32 + read-write + 0xffffffff + 0xffffffff + - BATCHGE0 - BC (Battery Charger) Function Ch0 General Enable Control - 7 + MMPUAnSA + MMPUAn Security Attribution (n = 0 to 7) + 0 7 read-write 0 - Disabled + Secure #0 1 - Enabled + Non-Secure #1 + + + + MMPUSARB + Master Memory Protection Unit Security Attribution Register B + 0x134 + 32 + read-write + 0xffffffff + 0xffffffff + - VDMSRCE0 - D- Pin VDMSRC (0.6 V) Output Control - 5 - 5 + MMPUB0SA + MMPUB0 Security Attribution + 0 + 0 read-write 0 - Stop + Secure #0 1 - 0.6V output + Non-Secure #1 + + + + CPUDSAR + CPU Debug Security Attribution Register + 0x1B0 + 32 + read-write + 0xffffffff + 0xffffffff + - IDPSINKE0 - D+ Pin 0.6 V Input Detection (Comparator and Sink) Control - 4 - 4 + CPUDSA0 + CPU Debug Security Attribution 0 + 0 + 0 read-write 0 - Detection off + Secure #0 1 - Detection on ( Comparator and sink current on ) + Non-secure #1 + + + + + + R_OSPI + Octa Serial Peripheral Interface + 0x400A6000 + + 0x00 + 36 + registers + + + 0x34 + 52 + registers + + + 0x7C + 8 + registers + + + + DCR + Device Command Register + 0x00 + 32 + read-write + 0x00000000 + 0xffffffff + + + DVCMD0 + Device Command data + 0 + 7 + read-write + - VDPSRCE0 - D+ Pin VDPSRC (0.6 V) Output Control - 3 - 3 + DVCMD1 + Device Command data + 8 + 15 + read-write + + + + + DAR + Device Address Register + 0x04 + 32 + read-write + 0x00000000 + 0xffffffff + + + DVAD0 + Device Address data 0 + 0 + 7 + read-write + + + DVAD1 + Device Address data 1 + 8 + 15 + read-write + + + DVAD2 + Device Address data 2 + 16 + 23 + read-write + + + DVAD3 + Device Address data 3 + 24 + 31 + read-write + + + + + DCSR + Device Command Setting Register + 0x08 + 32 + read-write + 0x00000000 + 0xffffffff + + + DALEN + Transfer data length setting + 0 + 7 + read-write + + + DMLEN + Dummy cycle setting + 8 + 15 + read-write + + + ACDV + Access Device setting + 19 + 19 read-write 0 - Stop + Send commands to device 0. #0 1 - 0.6V output + Send commands to device 1. #1 - IDMSINKE0 - D- Pin 0.6 V Input Detection (Comparator and Sink) Control - 2 - 2 + CMDLEN + Transfer command length setting + 20 + 22 + read-write + + + DAOR + Data order setting + 23 + 23 read-write 0 - Detection off + byte0, byte1, byte2, byte3 #0 1 - Detection on ( Comparator and sink current on ) + byte1, byte0, byte3, byte2 #1 - IDPSRCE0 - D+ Pin IDPSRC Output Control - 1 - 1 + ADLEN + Transfer address length setting + 24 + 26 + read-write + + + DOPI + DOPI single byte setting + 27 + 27 read-write 0 - Stop + Each cycle has two bytes data. (normal DOPI mode) #0 1 - 10uA output + Each cycle has one byte data. (The byte data changes at the rising edge of the + clock and does not change at the falling edge of the clock.) #1 - RPDME0 - D- Pin Pull-Down Control - 0 - 0 + ACDA + Data Access Control + 28 + 28 read-write 0 - Pull-down off + Register access +Do not arrange the transfer data. + #0 1 - Pull-down on + Data access #1 - - - - UCKSEL - USB Clock Selection Register - 0x0C4 - 16 - read-write - 0x0000 - 0xFFFF - - UCKSELC - USB Clock Selection - 0 - 0 + PREN + Preamble bit enable for OctaRAM + 29 + 29 read-write 0 - High-speed on-chip oscillator clock (HOCO) is not selected as USB clock + No check preamble bit from OctaRAM #0 1 - High-speed on-chip oscillator clock (HOCO) is selected as USB clock + Check preamble bit from OctaRAM #1 @@ -73836,1052 +86223,1189 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - USBMC - USB Module Control Register - 0x0CC - 16 + 2 + 4 + DSR[%s] + Device Size Register 0 + 0x0C + 32 read-write - 0x0002 - 0xFFFF + 0x00000000 + 0xffffffff - VDCEN - USB Regulator On/Off Control - 7 - 7 + DVSZ + Device size setting + 0 + 29 + read-write + + + DVTYP + Device type setting + 30 + 31 read-write - 0 - USB regulator off - #0 + 00 + flash on device 0 + #00 - 1 - USB regulator on - #1 + 01 + RAM on device 0 + #01 - - - - VDDUSBE - USB Reference Power Supply Circuit On/Off Control - 0 - 0 - read-write - - 0 - USB reference power supply circuit off - #0 + 10 + no connection on device 0 + #10 - 1 - USB reference power supply circuit on - #1 + 11 + forbidden + #11 - PHYSLEW - PHY Cross Point Adjustment Register - 0x0F0 + MDTR + Memory Delay Trim Register + 0x14 32 read-write - 0x0000000E - 0xFF4CFFFF + 0x06009400 + 0xffffffff - SLEWF01 - Receiver Cross Point Adjustment 01 - 3 - 3 + DV0DEL + Device 0 delay setting + 0 + 7 read-write - - - 1 - Host or device controller mode. - #1 - - - SLEWF00 - Receiver Cross Point Adjustment 00 - 2 - 2 + DQSERAM + OM_DQS enable counter + 8 + 11 read-write - - - 1 - Host or device controller mode. - #1 - - - SLEWR01 - Receiver Cross Point Adjustment 01 - 1 - 1 + DQSESOPI + OM_DQS enable counter + 12 + 15 read-write - - - 1 - Host or device controller mode. - #1 - - - SLEWR00 - Receiver Cross Point Adjustment 00 + DV1DEL + Device 1 delay setting + 16 + 23 + read-write + + + DQSEDOPI + OM_DQS enable counter + 24 + 27 + read-write + + + + + ACTR + Auto-Calibration Timer Register + 0x18 + 32 + read-write + 0x10000000 + 0xffffffff + + + CTP + Automatic calibration cycle time setting 0 - 0 + 31 read-write - - - 1 - Host or device controller mode. - #1 - - - LPCTRL - Low Power Control Register - 0x100 - 16 + 2 + 4 + ACAR[%s] + Auto-Calibration Address Register + 0x1C + 32 read-write - 0x0000 - 0x0181 + 0x00000000 + 0xffffffff - HWUPM - Resume Return Mode Setting - 7 - 7 + CAD + Automatic calibration address + 0 + 31 read-write - - - 0 - Hardware does not recover while CPU clock inactive - #0 - - - 1 - Hardware recovers while CPU clock inactive. - #1 - - - LPSTS - Low Power Status Register - 0x102 - 16 + DRCSTR + Device Memory Map Read Chip Select Timing Setting Register + 0x34 + 32 read-write - 0x0000 - 0x510B + 0x00000000 + 0xffffffff - SUSPENDM - UTMI SuspendM Control - 14 - 14 + CTRW0 + Device 0 single continuous read waiting cycle setting in PCLKH units + 0 + 6 + read-write + + + CTR0 + Device 0 single continuous read mode setting + 7 + 7 read-write 0 - UTMI suspension mode + Single continuous read mode is disabled for device 0. #0 1 - UTMI normal mode + Single continuous read mode is enabled for device 0. #1 - - - - BCCTRL - Battery Charging Control Register - 0x140 - 16 - read-write - 0x0000 - 0x033F - - PDDETSTS - PDDET Status - 9 - 9 - read-only + DVRDCMD0 + Device 0 Command execution interval setting + 8 + 10 + read-write - 0 - The PDDET pin is at low level. - #0 + 000 + 2 clock cycles + #000 + + + 001 + 5 clock cycles + #001 + + + 010 + 7 clock cycles + #010 + + + 011 + 9 clock cycles + #011 + + + 100 + 11 clock cycles + #100 + + + 101 + 13 clock cycles + #101 + + + 110 + 15 clock cycles + #110 - 1 - The PDDET pin is at high level. - #1 + 111 + 17 clock cycles + #111 - CHGDETSTS - CHGDET Status - 8 - 8 - read-only + DVRDHI0 + Device 0 select signal pull-up timing setting + 11 + 13 + read-write - 0 - The CHGDET pin is at low level. - #0 + 000 + Setting prohibit + #000 - 1 - The CHGDET pin is at high level. - #1 + 001 + Setting prohibit + #001 - - - - DCPMODE - DCP Mode Control - 5 - 5 - read-write - - 0 - The RDCP_DAT resistor is disabled - #0 + 010 + Setting prohibit + #010 - 1 - The RDCP_DAT resistor is enabled. - #1 + 011 + Setting prohibit (DOPI mode) +5 clock cycles (Other mode) + + #011 + + + 100 + Setting prohibit (DOPI mode) +6 clock cycles (Other mode) + + #100 + + + 101 + 6.5 clock cycles (DOPI mode) +7 clock cycles (Other mode) + + #101 + + + 110 + 7.5 clock cycles (DOPI mode) +8 clock cycles (Other mode) + + #110 + + + 111 + 8.5 clock cycles (DOPI mode) +9 clock cycles (Other mode) + + #111 - VDMSRCE - VDMSRC Control - 4 - 4 + DVRDLO0 + Device 0 select signal pull-down timing setting + 14 + 15 read-write - 0 - The VDM_SRC circuit is disabled. (Initial value) - #0 + 00 + Setting prohibit + #00 - 1 - The VDM_SRC circuit is enabled. - #1 + 01 + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + + #01 + + + 10 + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + + #10 + + + 11 + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + + #11 - IDPSINKE - IDPSINK Control - 3 - 3 + CTRW1 + Device 1 single continuous read waiting cycle setting in PCLKH units + 16 + 22 + read-write + + + CTR1 + Device 1 single continuous read mode setting + 23 + 23 read-write 0 - The IDP_SINK circuit is disabled. (Initial value) + Single continuous read mode is disabled for device 1. #0 1 - The IDP_SINK circuit is enabled. + Single continuous read mode is enabled for device 1. #1 - VDPSRCE - VDPSRC Control - 2 - 2 + DVRDCMD1 + Device 1 Command execution interval + 24 + 26 read-write - 0 - The VDP_SRC circuit is disabled. (Initial value) - #0 + 000 + 2 clock cycles + #000 - 1 - The VDP_SRC circuit is enabled. - #1 + 001 + 5 clock cycles + #001 + + + 010 + 7 clock cycles + #010 + + + 011 + 9 clock cycles + #011 + + + 100 + 11 clock cycles + #100 + + + 101 + 13 clock cycles + #101 + + + 110 + 15 clock cycles + #110 + + + 111 + 17 clock cycles + #111 - IDMSINKE - IDMSINK Control - 1 - 1 + DVRDHI1 + Device 1 select signal High timing setting + 27 + 29 read-write - 0 - The IDM_SINK circuit is disabled. (Initial value) - #0 + 000 + Setting prohibit + #000 - 1 - The IDM_SINK circuit is enabled. - #1 + 001 + Setting prohibit + #001 + + + 010 + Setting prohibit + #010 + + + 011 + Setting prohibit (DOPI mode) +5 clock cycles (Other mode) + + #011 + + + 100 + Setting prohibit (DOPI mode) +6 clock cycles (Other mode) + + #100 + + + 101 + 6.5 clock cycles (DOPI mode) +7 clock cycles (Other mode) + + #101 + + + 110 + 7.5 clock cycles (DOPI mode) +8 clock cycles (Other mode) + + #110 + + + 111 + 8.5 clock cycles (DOPI mode) +9 clock cycles (Other mode) + + #111 - IDPSRCE - IDPSRC Control - 0 - 0 + DVRDLO1 + Device 1 select signal pull-down timing setting + 30 + 31 read-write - 0 - The IDP_SRC circuit is disabled. (Initial value) - #0 + 00 + Setting prohibited + #00 - 1 - The IDP_SRC circuit is enabled. - #1 + 01 + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + + #01 + + + 10 + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + + #10 + + + 11 + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + + #11 - PL1CTRL1 - Function L1 Control Register 1 - 0x144 - 16 + DWCSTR + Device Memory Map Write Chip Select Timing Setting Register + 0x38 + 32 read-write - 0x0000 - 0x4FFF + 0x00000000 + 0xffffffff - L1EXTMD - PHY Control Mode at L1 Return - 14 - 14 + CTWW0 + Device 0 single continuous write waiting cycle setting in PCLKH units + 0 + 6 + read-write + + + CTW0 + Device 0 single continuous write mode setting + 7 + 7 read-write 0 - SUSPENDM is not set by hardware when Host K is received. + Single continuous write mode is disabled for device 0 #0 1 - SUSPENDM is set by hardware when Host K is received. + Single continuous write mode is enabled for device 0 #1 - HIRDTHR - L1 Response Negotiation Threshold ValueHIRD threshold value used for L1NEGOMD.The format is the same as the HIRD field in HL1CTRL. + DVWCMD0 + Device 0 Command execution interval setting 8 - 11 + 10 read-write - - - DVSQ - DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates the L1 state together with the device state bits DVSQ[2:0]. - 4 - 7 - read-only - 0000 - Powered state - #0000 + 000 + 2 clock cycles + #000 - 0001 - Default state - #0001 + 001 + 5 clock cycles + #001 - 0010 - Address state - #0010 + 010 + 7 clock cycles + #010 - 0011 - Configured state - #0011 + 011 + 9 clock cycles + #011 - 0100 - Suspended state - #0100 + 100 + 11 clock cycles + #100 - 0101 - Suspended state - #0101 + 101 + 13 clock cycles + #101 - 0110 - Suspended state - #0110 + 110 + 15 clock cycles + #110 - 0111 - Suspended state - #0111 + 111 + 17 clock cycles + #111 + + + + DVWHI0 + Device 0 select signal pull-up timing setting + 11 + 13 + read-write + - 1000 - L1 state - #1000 + 000 + 1.5 clock cycles (DOPI mode) +2 clock cycles (Other mode) + + #000 - 1001 - L1 state - #1001 + 001 + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + + #001 - 1010 - L1 state - #1010 + 010 + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + + #010 - 1011 - L1 state - #1011 + 011 + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + + #011 - others - setting prohibited - true + 100 + 5.5 clock cycles (DOPI mode) +6 clock cycles (Other mode) + + #100 - - - - L1NEGOMD - L1 Response Negotiation Control.NOTE: This bit is valid only when the L1RESPMD[1:0] value is 2'b11. - 3 - 3 - read-write - - 0 - When receive HIRD is larger than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. - #0 + 101 + 6.5 clock cycles (DOPI mode) +7 clock cycles (Other mode) + + #101 - 1 - When receive HIRD is smaller than HIRDTHR[3:0], ACK response is returned. In other cases (including HIRD = HIRDTHR[3:0]), NYET response is returned. - #1 + 110 + 7.5 clock cycles (DOPI mode) +8 clock cycles (Other mode) + + #110 + + + 111 + 8.5 clock cycles (DOPI mode) +9 clock cycles (Other mode) + + #111 - L1RESPMD - L1 Response Mode - 1 - 2 + DVWLO0 + Device 0 select signal pull-down timing setting + 14 + 15 read-write 00 - NYET + Setting prohibit #00 01 - ACK + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + #01 10 - STALL + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + #10 11 - According to the L1NEGOMD bit + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + #11 - L1RESPEN - L1 Response Enable - 0 - 0 + CTWW1 + Device 1 single continuous write waiting cycle setting in PCLKH units + 16 + 22 + read-write + + + CTW1 + Device 1 single continuous write mode setting + 23 + 23 read-write 0 - LPM is not supported. + Single continuous write mode is disabled for device 1 #0 1 - LPM is supported. + Single continuous write mode is enabled for device 1 #1 - - - - PL1CTRL2 - Function L1 Control Register 2 - 0x146 - 16 - read-write - 0x0000 - 0x1F00 - - RWEMON - RWE Value Monitor - 12 - 12 + DVWCMD1 + Device 1 Command execution interval setting + 24 + 26 read-write - 0 - The RWE bit value of the LPM token received last is reflected. - #0 + 000 + setting prohibited + #000 - 1 - The RWE bit value of the LPM token received last is reflected. - #1 + 001 + 5 clock cycles + #001 + + + 010 + 7 clock cycles + #010 + + + 011 + 9 clock cycles + #011 + + + 100 + 11 clock cycles + #100 + + + 101 + 13 clock cycles + #101 + + + 110 + 15 clock cycles + #110 + + + 111 + 17 clock cycles + #111 - HIRDMON - HIRD Value Monitor - 8 - 11 + DVWHI1 + Device 1 select signal pull-up timing setting + 27 + 29 read-write - 0 - The HIRD field value of the LPM token received last is reflected. - #0 + 000 + 1.5 clock cycles (DOPI mode) +2 clock cycles (Other mode) + + #000 - 1 - The HIRD field value of the LPM token received last is reflected. - #1 + 001 + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + + #001 + + + 010 + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + + #010 + + + 011 + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + + #011 + + + 100 + 5.5 clock cycles (DOPI mode) +6 clock cycles (Other mode) + + #100 + + + 101 + 6.5 clock cycles (DOPI mode) +7 clock cycles (Other mode) + + #101 + + + 110 + 7.5 clock cycles (DOPI mode) +8 clock cycles (Other mode) + + #110 + + + 111 + 8.5 clock cycles (DOPI mode) +9 clock cycles (Other mode) + + #111 - - - - HL1CTRL1 - Host L1 Control Register 1 - 0x148 - 16 - read-write - 0x0000 - 0x0007 - - L1STATUS - L1 Request Completion Status - 1 - 2 - read-only + DVWLO1 + Device 1 select signal pull-down timing setting + 30 + 31 + read-write 00 - ACK received + Setting prohibit #00 01 - NYET received + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + #01 10 - STALL received + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + #10 11 - Transaction error + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + #11 - - L1REQ - L1 Transition Request - 0 - 0 - read-write - - - 0 - This bit is cleared to 0 by hardware when the LPM transaction is completed. - #0 - - - 1 - Set this bit to 1 when requesting a transition to the L1 state. - #1 - - - - HL1CTRL2 - Host L1 Control Register 2 - 0x14A - 16 + DCSTR + Device Chip Select Timing Setting Register + 0x3C + 32 read-write - 0x0000 - 0x9F0F - - - BESL - BESL & Alternate HIRDThis bit selects the K-State drive period at the time of L1 Resume. - 15 - 15 - read-write - - - L1RWE - LPM Token L1 RemoteWake EnableThese bits specify the value to be set in the RWE field of LPM token. - 12 - 12 - read-write - + 0x00000000 + 0xffffffff + - HIRD - LPM Token HIRD + DVSELCMD + Device Command execution interval setting 8 - 11 + 10 read-write - 0000 - 50 us(Setting prohibited(BESL = 0)) / 75 us(BESL = 1) - #0000 + 000 + 2 clock cycles + #000 - 0001 - 125 us(BESL = 0) / 100 us(BESL = 1) - #0001 + 001 + 5 clock cycles + #001 - 0010 - 200 us(BESL = 0) / 150 us(BESL = 1) - #0010 + 010 + 7 clock cycles + #010 - 0011 - 275 us(BESL = 0) / 250 us(BESL = 1) - #0011 + 011 + 9 clock cycles + #011 - 0100 - 350 us(BESL = 0) / 350 us(BESL = 1) - #0100 + 100 + 11 clock cycles + #100 - 0101 - 425 us(BESL = 0) / 450 us(BESL = 1) - #0101 + 101 + 13 clock cycles + #101 - 0110 - 500 us(BESL = 0) / 950 us(BESL = 1) - #0110 + 110 + 15 clock cycles + #110 - 0111 - 575 us(BESL = 0) / 1950 us(BESL = 1) - #0111 + 111 + 17 clock cycles + #111 + + + + DVSELHI + Device select signal pull-up timing setting + 11 + 13 + read-write + - 1000 - 650 us(BESL = 0) / 2950 us(BESL = 1) - #1000 + 000 + Setting prohibited + #000 - 1001 - 725 us(BESL = 0) / 3950 us(BESL = 1) - #1001 + 001 + Setting prohibited + #001 - 1010 - 800 us(BESL = 0) / 4950 us(BESL = 1) - #1010 + 010 + Setting prohibited + #010 - 1011 - 875 us(BESL = 0) / 5950 us(BESL = 1) - #1011 + 011 + Setting prohibited (DOPI mode) +5 clock cycles (Other mode) + + #011 - 1100 - 950 us(BESL = 0) / 6950 us(BESL = 1) - #1100 + 100 + Setting prohibited (DOPI mode) +6 clock cycles (Other mode) + + #100 - 1101 - 1025 us(Setting prohibited(BESL = 0)) / 7950 us(BESL = 1) - #1101 + 101 + 6.5 clock cycles (DOPI mode) +7 clock cycles (Other mode) + + #101 - 1110 - 1100 us(Setting prohibited(BESL = 0)) / 8950 us(BESL = 1) - #1110 + 110 + 7.5 clock cycles (DOPI mode) +8 clock cycles (Other mode) + + #110 - 1111 - 1175 us(Setting prohibited(BESL = 0)) / 9950 us(BESL = 1) - #1111 + 111 + 8.5 clock cycles (DOPI mode) +9 clock cycles (Other mode) + + #111 - L1ADDR - LPM Token DeviceAddressThese bits specify the value to be set in the ADDR field of LPM token. - 0 - 3 + DVSELLO + Device select signal pull-down timing setting + 14 + 15 read-write + + + 00 + Setting prohibit + #00 + + + 01 + 2.5 clock cycles (DOPI mode) +3 clock cycles (Other mode) + + #01 + + + 10 + 3.5 clock cycles (DOPI mode) +4 clock cycles (Other mode) + + #10 + + + 11 + 4.5 clock cycles (DOPI mode) +5 clock cycles (Other mode) + + #11 + + - DPUSR0R - Deep Standby USB Transceiver Control/Pin Monitor Register - 0x160 - 32 - read-only - 0x00000000 - 0xFF4FFFFF - - - DVBSTSHM - VBUS InputIndicates VBUS input signal on the HS side of USB port. - 23 - 23 - read-only - - - DOVCBHM - OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. - 21 - 21 - read-only - - - DOVCAHM - OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. - 20 - 20 - read-only - - - - - DPUSR1R - Deep Standby USB Suspend/Resume Interrupt Register - 0x164 + CDSR + Controller and Device Setting Register + 0x40 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - DVBSTSH - Indication of Return from VBUS Interrupt Source - 23 - 23 - read-only - - - 0 - Indicates deep software standby mode - #0 - - - 1 - Indicates return from deep software standby mode - #1 - - - - - DOVCBH - Indication of Return from OVRCURB Interrupt Source - 21 - 21 - read-only + DV0TTYP + Device0_transfer_type setting + 0 + 1 + read-write - 0 - Indicates deep software standby mode - #0 + 00 + SPI mode + #00 - 1 - Indicates return from deep software standby mode - #1 + 01 + SOPI mode + #01 - - - - DOVCAH - Indication of Return from OVRCURA Interrupt Source - 20 - 20 - read-only - - 0 - Indicates deep software standby mode - #0 + 10 + DOPI mode + #10 - 1 - Indicates return from deep software standby mode - #1 + 11 + Setting prohibited + #11 - DVBSTSHE - VBUS Interrupt Enable/Clear - 7 - 7 + DV1TTYP + Device1_transfer_type setting + 2 + 3 read-write - 0 - Disables return from deep software standby mode - #0 + 00 + SPI mode + #00 - 1 - Enables return from deep software standby mode - #1 + 01 + SOPI mode + #01 - - - - DOVCBHE - OVRCURB Interrupt Enable Clear - 5 - 5 - read-write - - 0 - Disables return from deep software standby mode - #0 + 10 + DOPI mode + #10 - 1 - Enables return from deep software standby mode - #1 + 11 + Setting prohibited + #11 - DOVCAHE - OVRCURA Interrupt Enable Clear + DV0PC + Device0_memory precycle setting 4 4 read-write 0 - Disables return from deep software standby mode + Disable #0 1 - Enables return from deep software standby mode + Enable #1 - - - - DPUSR2R - Deep Standby USB Suspend/Resume Interrupt Register - 0x168 - 16 - read-write - 0x0000 - 0xFFFF - - DMINTE - DM Interrupt Enable Clear - 9 - 9 + DV1PC + Device1_memory precycle setting + 5 + 5 read-write 0 - Disables return from deep software standby mode + Disable #0 1 - Enables return from deep software standby mode + Enable #1 - DPINTE - DP Interrupt Enable Clear - 8 - 8 + ACMEME0 + Automatic calibration memory enable setting for device 0 + 10 + 10 read-write 0 - Disables return from deep software standby mode + Disable #0 1 - Enables return from deep software standby mode + Enable #1 - DMVAL - DM InputIndicates DM input signal on the HS side of USB port. - 5 - 5 - read-only - - - DPVAL - DP InputIndicates DP input signal on the HS side of USB port. - 4 - 4 - read-only - - - DMINT - Indication of Return from DM Interrupt Source - 1 - 1 - read-only + ACMEME1 + Automatic calibration memory enable setting for device 1 + 11 + 11 0 - Indicates deep software standby mode + Disable #0 1 - Indicates return from deep software standby mode + Enable #1 - DPINT - Indication of Return from DP Interrupt Source - 0 - 0 - read-only + ACMODE + Automatic calibration mode + 12 + 13 + read-write - 0 - Indicates deep software standby mode - #0 + 00 + Automatic calibration is disabled + #00 - 1 - Indicates return from deep software standby mode - #1 + 01 + Automatic calibration is enabled and modify MDTR + #01 - - - - - - DPUSRCR - Deep Standby USB Suspend/Resume Command Register - 0x16A - 16 - read-write - 0x0000 - 0xFFFF - - - FIXPHYPD - USB Transceiver Control Fix for PLL - 1 - 1 - read-write - - 0 - Normal mode - #0 + 10 + Automatic calibration immediately is executed for all trim code, but + it will not modify MDTR + #10 - 1 - Go to/Return from deep software standby mode - #1 + 11 + Setting prohibited + #11 - FIXPHY - USB Transceiver Control Fix - 0 - 0 + DLFT + Deadlock Free Timer Enable + 31 + 31 read-write 0 - Normal mode + Enable timer #0 1 - Go to/Return from deep software standby mode + Disable timer #1 @@ -74889,635 +87413,558 @@ The order in which the SPCMD0 to SPCMD07 registers are to be referenced is chang - DPUSR0R_FS - Deep Software Standby USB Transceiver Control/Pin Monitor Register - 0x400 + MDLR + Memory Map Dummy Length Register + 0x44 32 read-write 0x00000000 - 0xFF4CFFFF + 0xffffffff - DVBSTS0 - USB VBUS InputIndicates the VBUS input signal of the USB. - 23 - 23 - read-only - - - DOVCB0 - USB OVRCURB InputIndicates the OVRCURB input signal of the USB. - 21 - 21 - read-only + DV0RDL + Device 0 Read dummy length setting + 0 + 7 + read-write - DOVCA0 - USB OVRCURA InputIndicates the OVRCURA input signal of the USB. - 20 - 20 - read-only + DV0WDL + Device 0 Write dummy length setting + 8 + 15 + read-write - DM0 - USB D-InputIndicates the D- input signal of the USB. - 17 - 17 - read-only + DV1RDL + Device 1 Read dummy length setting + 16 + 23 + read-write - DP0 - USB0 D+ InputIndicates the D+ input signal of the USB. - 16 - 16 - read-only + DV1WDL + Device 1 Write dummy length setting + 24 + 31 + read-write + + + + 2 + 4 + MRWCR[%s] + Memory Map Read/Write Command Register + 0x48 + 32 + read-write + 0x00000000 + 0xffffffff + - FIXPHY0 - USB Transceiver Output Fix - 4 - 4 + DMRCMD0 + Memory map read command 0 setting + 0 + 7 read-write - - - 0 - The outputs are fixed in normal mode and on return from deep software standby mode. - #0 - - - 1 - The outputs are fixed on transitions to deep software standby mode. - #1 - - - DRPD0 - D+/D- Pull-Down Resistor Control - 3 - 3 + DMRCMD1 + Memory map read command 1 setting + 8 + 15 read-write - - - 0 - Disables DP/DM pull-down resistor. - #0 - - - 1 - Enables DP/DM pull-down resistor. - #1 - - - RPUE0 - DP Pull-Up Resistor Control - 1 - 1 + DMWCMD0 + Memory map write command 0 setting + 16 + 23 read-write - - - 0 - Disables DP pull-up resistor. - #0 - - - 1 - Enables DP pull-up resistor. - #1 - - - SRPC0 - USB Single End Receiver Control - 0 - 0 + DMWCMD1 + Memory map write command 1 setting + 24 + 31 read-write - - - 0 - Input through the DP and DM inputs is disabled. - #0 - - - 1 - Input through the DP and DM inputs is enabled. - #1 - - - DPUSR1R_FS - Deep Software Standby USB Suspend/Resume Interrupt Register - 0x404 + MRWCSR + Memory Map Read/Write Setting Register + 0x50 32 read-write 0x00000000 - 0xFFFFFFFF + 0xffffffff - DVBINT0 - USB VBUS Interrupt Source Recovery - 23 - 23 - read-only + MRAL0 + Device 0 read address length setting + 0 + 2 + read-write + + + MRCL0 + Device 0 read command length setting + 3 + 5 + read-write + + + MRO0 + Device 0 read order setting + 6 + 6 + read-write 0 - The system has not returned from deep software standby mode. + Read order is byte0, byte1, byte2, byte3. #0 1 - The system has returned from deep software standby mode. + Read order is byte1, byte0, byte3, byte2. #1 - DOVRCRB0 - USB OVRCURB Interrupt Source Recovery - 21 - 21 - read-only + PREN0 + Preamble bit enable for mem0 memory-map read + 7 + 7 + read-write 0 - The system has not returned from deep software standby mode. + No check preamble bit #0 1 - The system has returned from deep software standby mode. + Check preamble bit from OctaFlash (if OctaFlash is connected to device 0) #1 - DOVRCRA0 - USB OVRCURA Interrupt Source Recovery - 20 - 20 - read-only - - - 0 - The system has not returned from deep software standby mode. - #0 - - - 1 - The system has returned from deep software standby mode. - #1 - - + MWAL0 + Device 0 write address length setting + 8 + 10 + read-write - DMINT0 - USB DM Interrupt Source Recovery - 17 - 17 - read-only + MWCL0 + Device 0 write command length setting + 11 + 13 + read-write + + + MWO0 + Device 0 write order setting + 14 + 14 + read-write 0 - The system has not returned from deep software standby mode. + Write order is byte0, byte1, byte2, byte3. #0 1 - The system has returned from deep software standby mode. + Write order is byte1, byte0, byte3, byte2. #1 - DPINT0 - USB DP Interrupt Source Recovery + MRAL1 + Device 1 read address length setting 16 - 16 - read-only - - - 0 - The system has not returned from deep software standby mode. - #0 - - - 1 - The system has returned from deep software standby mode. - #1 - - + 18 + read-write - DVBSE0 - USB VBUS Interrupt Enable/Clear - 7 - 7 + MRCL1 + Device 1 read command length setting + 19 + 21 read-write - - - 0 - Recovery from deep software standby mode is disabled. - #0 - - - 1 - Recovery from deep software standby mode is enabled. - #1 - - - DOVRCRBE0 - USB OVRCURB Interrupt Enable/Clear - 5 - 5 + MRO1 + Device 1 read order setting + 22 + 22 read-write 0 - Recovery from deep software standby mode is disabled. + Read order is byte0, byte1, byte2, byte3. #0 1 - Recovery from deep software standby mode is enabled. + Read order is byte1, byte0, byte3, byte2. #1 - DOVRCRAE0 - USB OVRCURA Interrupt Enable/Clear - 4 - 4 + PREN1 + Preamble bit enable for mem1 memory-map read + 23 + 23 read-write 0 - Recovery from deep software standby mode is disabled. + No check preamble bit #0 1 - Recovery from deep software standby mode is enabled. + Check preamble bit from OctaFlash (if OctaFlash is connected to device 1) #1 - DMINTE0 - USB DM Interrupt Enable/Clear - 1 - 1 + MWAL1 + Device 1 write address length setting + 24 + 26 read-write - - - 0 - Recovery from deep software standby mode is disabled. - #0 - - - 1 - Recovery from deep software standby mode is enabled. - #1 - - - DPINTE0 - USB DP Interrupt Enable/Clear - 0 - 0 + MWCL1 + Device 1 write command length setting + 27 + 29 + read-write + + + MWO1 + Device 1 write order setting + 30 + 30 read-write 0 - Recovery from deep software standby mode is disabled. + Write order is byte0, byte1, byte2, byte3. #0 1 - Recovery from deep software standby mode is enabled. + Write order is byte1, byte0, byte3, byte2. #1 - - - - R_USB_HS0 - 0x40060000 - - - R_WDT - Watchdog Timer - 0x40044200 - - 0x00000000 - 0x01 - registers - - - 0x00000002 - 0x005 - registers - - - 0x00000008 - 0x01 - registers - - - WDTRR - WDT Refresh Register - 0x00 - 8 - read-write - 0xFF - 0xFF + ESR + Error Status Register + 0x54 + 32 + read-only + 0x00000000 + 0xffffffff - WDTRR - WDTRR is an 8-bit register that refreshes the down-counter of the WDT. + MRESR + Memory map read error status 0 7 - read-write - - - - - WDTCR - WDT Control Register - 0x02 - 16 - read-write - 0x33F3 - 0xFFFF - - - RPSS - Window Start Position Selection - 12 - 13 - read-write + read-only - 00 - 25% - #00 + 0x01 + ECC error + 0x01 - 01 - 50% - #01 + 0x02 + Preamble error + 0x02 - 10 - 75% - #10 + 0x03 + Wait OM_DQS timeout + 0x03 - 11 - 100% (window start position is not specified) - #11 + 0x80 + Invalid command + 0x80 + + + Others + Reserved + true - RPES - Window End Position Selection + MWESR + Memory map write error status 8 - 9 - read-write + 15 + read-only - 00 - 75% - #00 - - - 01 - 50% - #01 - - - 10 - 25% - #10 + 0x80 + Invalid command + 0x80 - 11 - 0% (window end position is not specified) - #11 + Others + Reserved + true + + + + CWNDR + Configure Write without Data Register + 0x58 + 32 + write-only + 0x00000000 + 0xffffffff + + + WND + The write value should be 0. + 0 + 31 + write-only + + + + + CWDR + Configure Write Data Register + 0x5C + 32 + write-only + 0x00000000 + 0xffffffff + - CKS - Clock Division Ratio Selection - 4 + WD0 + Write data 0 + 0 + 7 + write-only + + + WD1 + Write data 1 + 8 + 15 + write-only + + + WD2 + Write data 2 + 16 + 23 + write-only + + + WD3 + Write data 3 + 24 + 31 + write-only + + + + + CRR + Configure Read Register + 0x60 + 32 + read-only + 0x00000000 + 0xffffffff + + + RD0 + Read data 0 + 0 7 + read-only + + + RD1 + Read data 1 + 8 + 15 + read-only + + + RD2 + Read data 2 + 16 + 23 + read-only + + + RD3 + Read data 3 + 24 + 31 + read-only + + + + + ACSR + Auto-Calibration Status Register + 0x64 + 32 + read-write + 0x00000000 + 0xffffffff + + + ACSR0 + Auto-calibration status of device 0 + 0 + 2 read-write - 0001 - PCLK/4 - #0001 - - - 0100 - PCLK/64 - #0100 - - - 1111 - PCLK/128 - #1111 + 000 + Initial state + #000 - 0110 - PCLK/512 - #0110 + 001 + Reserved + #001 - 0111 - PCLK/2048 - #0111 + 010 + Reserved + #010 - 1000 - PCLK/8192 - #1000 + 011 + Normal end + #011 - others - setting prohibited - true + 100 + Error end + #100 - TOPS - Timeout Period Selection - 0 - 1 + ACSR1 + Auto-calibration status of device 1 + 3 + 5 read-write - 00 - 1,024 cycles (03FFh) - #00 + 000 + Initial state + #000 - 01 - 4,096 cycles (0FFFh) - #01 + 001 + Reserved + #001 - 10 - 8,192 cycles (1FFFh) - #10 + 010 + Reserved + #010 - 11 - 16,384 cycles (3FFFh) - #11 + 011 + Normal end + #011 + + + 100 + Error end + #100 - WDTSR - WDT Status Register - 0x04 - 16 + DCSMXR + Device Chip Select Maximum Period Register + 0x7C + 32 read-write - 0x0000 - 0xFFFF + 0x00000000 + 0xffffffff - REFEF - Refresh Error Flag - 15 - 15 + CTWMX0 + Indicates the maximum period that OM_CS0 and OM_CS1 are Low + in single continuous write of OctaRAM. + 0 + 8 read-write - zeroToClear - modify - - - 0 - No refresh error occurred - #0 - - - 1 - Refresh error occurred - #1 - - - UNDFF - Underflow Flag - 14 - 14 + CTWMX1 + Indicates the maximum period that OM_CS0 and OM_CS1 are Low + in single continuous read of OctaRAM. + 16 + 24 read-write - zeroToClear - modify - - - 0 - No underflow occurred - #0 - - - 1 - Underflow occurred - #1 - - - - - CNTVAL - Down-Counter Value - 0 - 13 - read-only - WDTRCR - WDT Reset Control Register - 0x06 - 8 + DWSCTSR + Device Memory Map Write single continuous translating size Register + 0x80 + 32 read-write - 0x80 - 0xFF + 0x00000000 + 0xffffffff - RSTIRQS - Reset Interrupt Request Selection - 7 - 7 + CTSN0 + Indicates the number of bytes to translate in single continuous write of device 0. + 0 + 10 read-write - - - 0 - Non-maskable interrupt request or interrupt request output is enabled - #0 - - - 1 - Reset output is enabled. - #1 - - - - - - WDTCSTPR - WDT Count Stop Control Register - 0x08 - 8 - read-write - 0x80 - 0xFF - - SLCSTP - Sleep-Mode Count Stop Control - 7 - 7 + CTSN1 + Indicates the number of bytes to translate in single continuous write of device 1. + 16 + 26 read-write - - - 0 - Count stop is disabled. - #0 - - - 1 - Count is stopped at a transition to sleep mode. - #1 - - - \ No newline at end of file + diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c index dfb1c8b7e..2a10e92eb 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -100,6 +100,7 @@ BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP #pragma weak MemManage_Handler = Default_Handler #pragma weak BusFault_Handler = Default_Handler #pragma weak UsageFault_Handler = Default_Handler + #pragma weak SecureFault_Handler = Default_Handler #pragma weak SVC_Handler = Default_Handler #pragma weak DebugMon_Handler = Default_Handler #pragma weak PendSV_Handler = Default_Handler @@ -114,6 +115,7 @@ void HardFault_Handler(void) WEAK_REF_ATTRIBUTE; void MemManage_Handler(void) WEAK_REF_ATTRIBUTE; void BusFault_Handler(void) WEAK_REF_ATTRIBUTE; void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE; +void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE; void SVC_Handler(void) WEAK_REF_ATTRIBUTE; void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE; void PendSV_Handler(void) WEAK_REF_ATTRIBUTE; @@ -130,7 +132,7 @@ BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_P MemManage_Handler, /* MPU Fault Handler */ BusFault_Handler, /* Bus Fault Handler */ UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ + SecureFault_Handler, /* Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c index 27aa39457..60815a7c8 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -26,16 +26,16 @@ /*********************************************************************************************************************** * Includes , "Project Includes" **********************************************************************************************************************/ +#include #include "bsp_api.h" #include "../../../../mcu/all/bsp_clocks.h" -#include /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ /* Mask to select CP bits( 0xF00000 ) */ -#define CP_MASK (0x0000000FU << 20) +#define CP_MASK (0xFU << 20) /* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */ #define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U) @@ -45,6 +45,18 @@ #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U) #define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#if defined(__ICCARM__) + #define BSP_PRV_STACK_LIMIT ((uint32_t) __section_begin(".stack")) + #define BSP_PRV_STACK_TOP ((uint32_t) __section_end(".stack")) +#elif defined(__ARMCC_VERSION) + #define BSP_PRV_STACK_LIMIT ((uint32_t) &Image$$STACK$$ZI$$Base) + #define BSP_PRV_STACK_TOP ((uint32_t) &Image$$STACK$$ZI$$Base + \ + (uint32_t) &Image$$STACK$$ZI$$Length) +#elif defined(__GNUC__) + #define BSP_PRV_STACK_LIMIT ((uint32_t) &__StackLimit) + #define BSP_PRV_STACK_TOP ((uint32_t) &__StackTop) +#endif + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -62,8 +74,8 @@ extern uint32_t Image$$BSS$$ZI$$Length; extern uint32_t Load$$DATA$$Base; extern uint32_t Image$$DATA$$Base; extern uint32_t Image$$DATA$$Length; -extern uint32_t Image$$STACK$$RW$$Base; -extern uint32_t Image$$STACK$$RW$$Length; +extern uint32_t Image$$STACK$$ZI$$Base; +extern uint32_t Image$$STACK$$ZI$$Length; #elif defined(__GNUC__) /* Generated by linker. */ @@ -99,6 +111,8 @@ extern void __call_ctors(void const *, void const *); extern void * __Vectors[]; +extern void R_BSP_SecurityInit(void); + /*********************************************************************************************************************** * Private global variables and functions **********************************************************************************************************************/ @@ -127,18 +141,20 @@ void SystemInit (void) { #if __FPU_USED - /* Enable the Cortex-M4 FPU only when -mfloat-abi=hard. + /* Enable the FPU only when it is used. * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */ - /* Set bits 20-23 to enable CP10 and CP11 coprocessor */ - /* SCB is a CMSIS defined element over which we have no control. */ - SCB->CPACR |= (uint32_t) CP_MASK; + /* Set bits 20-23 (CP10 and CP11) to enable FPU. */ + SCB->CPACR = (uint32_t) CP_MASK; #endif -/* Set the VTOR to the vector table address based on the build. */ +/* Set the Secure/Non-Secure VTOR to the vector table address based on the build. */ +#if FSP_PRIV_TZ_USE_SECURE_REGS SCB->VTOR = (uint32_t) &__Vectors; +#endif -#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP +#if !BSP_TZ_CFG_SKIP_INIT + #if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP /* Unlock VBTCR1 register. */ R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK; @@ -152,87 +168,46 @@ void SystemInit (void) /* Lock VBTCR1 register. */ R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; + #endif #endif /* Call pre clock initialization hook. */ R_BSP_WarmStart(BSP_WARM_START_RESET); +#if BSP_TZ_CFG_SKIP_INIT + + /* Initialize clock variables to be used with R_BSP_SoftwareDelay. */ + bsp_clock_freq_var_init(); +#else + /* Configure system clocks. */ bsp_clock_init(); -#if BSP_FEATURE_BSP_RESET_TRNG + #if BSP_FEATURE_BSP_RESET_TRNG /* To prevent an undesired current draw, this MCU requires a reset * of the TRNG circuit after the clocks are initialized */ + bsp_reset_trng_circuit(); + #endif #endif /* Call post clock initialization hook. */ R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); - /* Initialize C runtime environment. */ - /* Zero out BSS */ -#if defined(__ARMCC_VERSION) - memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length); -#elif defined(__GNUC__) - memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__)); -#elif defined(__ICCARM__) - memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss")); -#endif - - /* Copy initialized RAM data from ROM to RAM. */ -#if defined(__ARMCC_VERSION) - memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length); -#elif defined(__GNUC__) - memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__)); -#elif defined(__ICCARM__) - memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"), - (uint32_t) __section_size(".data")); - - /* Copy functions to be executed from RAM. */ - #pragma section=".code_in_ram" - #pragma section=".code_in_ram_init" - memcpy((uint32_t *) __section_begin(".code_in_ram"), - (uint32_t *) __section_begin(".code_in_ram_init"), - (uint32_t) __section_size(".code_in_ram")); - - /* Copy main thread TLS to RAM. */ - #pragma section="__DLIB_PERTHREAD_init" - #pragma section="__DLIB_PERTHREAD" - memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"), - (uint32_t) __section_size("__DLIB_PERTHREAD_init")); -#endif +#if BSP_FEATURE_BSP_HAS_SP_MON /* Disable MSP monitoring */ R_MPU_SPMON->SP[0].CTL = 0; /* Setup NMI interrupt */ R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION; -#if defined(__ICCARM__) - - /* Setup start address */ - R_MPU_SPMON->SP[0].SA = (uint32_t) __section_begin(".stack"); - - /* Setup end address */ - R_MPU_SPMON->SP[0].EA = (uint32_t) __section_end(".stack"); -#elif defined(__ARMCC_VERSION) - - /* Setup start address */ - R_MPU_SPMON->SP[0].SA = (uint32_t) &Image$$STACK$$RW$$Base; - - /* Setup end address */ - R_MPU_SPMON->SP[0].EA = (uint32_t) &Image$$STACK$$RW$$Base + (uint32_t) &Image$$STACK$$RW$$Length; -#elif defined(__GNUC__) /* Setup start address */ - R_MPU_SPMON->SP[0].SA = (uint32_t) &__StackLimit; + R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT; /* Setup end address */ - R_MPU_SPMON->SP[0].EA = (uint32_t) &__StackTop; -#endif - - /* Disable stack monitoring for FreeRTOS. Not yet supported. */ -#if (BSP_CFG_RTOS == 0) + R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP; /* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need * to read-modify-write. */ @@ -242,19 +217,49 @@ void SystemInit (void) R_MPU_SPMON->SP[0].CTL = 1U; #endif - /* Initialize SystemCoreClock variable. */ - SystemCoreClockUpdate(); +#if BSP_FEATURE_TZ_HAS_TRUSTZONE -#if !BSP_CFG_PFS_PROTECT - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + /* Use CM33 stack monitor. */ + __set_MSPLIM(BSP_PRV_STACK_LIMIT); #endif - /* Call Post C runtime initialization hook. */ - R_BSP_WarmStart(BSP_WARM_START_POST_C); +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize C runtime environment. */ + /* Zero out BSS */ + #if defined(__ARMCC_VERSION) + memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length); + #elif defined(__GNUC__) + memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__)); + #elif defined(__ICCARM__) + memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss")); + #endif + + /* Copy initialized RAM data from ROM to RAM. */ + #if defined(__ARMCC_VERSION) + memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length); + #elif defined(__GNUC__) + memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__)); + #elif defined(__ICCARM__) + memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"), + (uint32_t) __section_size(".data")); + + /* Copy functions to be executed from RAM. */ + #pragma section=".code_in_ram" + #pragma section=".code_in_ram_init" + memcpy((uint32_t *) __section_begin(".code_in_ram"), + (uint32_t *) __section_begin(".code_in_ram_init"), + (uint32_t) __section_size(".code_in_ram")); + + /* Copy main thread TLS to RAM. */ + #pragma section="__DLIB_PERTHREAD_init" + #pragma section="__DLIB_PERTHREAD" + memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"), + (uint32_t) __section_size("__DLIB_PERTHREAD_init")); + #endif /* Initialize static constructors */ -#if defined(__ARMCC_VERSION) + #if defined(__ARMCC_VERSION) int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base; for (int32_t i = 0; i < count; i++) { @@ -263,19 +268,52 @@ void SystemInit (void) p_init_func(); } -#elif defined(__GNUC__) + #elif defined(__GNUC__) int32_t count = __init_array_end - __init_array_start; for (int32_t i = 0; i < count; i++) { __init_array_start[i](); } -#elif defined(__ICCARM__) + #elif defined(__ICCARM__) void const * pibase = __section_begin("SHT$$PREINIT_ARRAY"); void const * ilimit = __section_end("SHT$$INIT_ARRAY"); __call_ctors(pibase, ilimit); + #endif +#endif // BSP_CFG_C_RUNTIME_INIT + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + +#if !BSP_CFG_PFS_PROTECT + #if BSP_TZ_SECURE_BUILD + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif #endif + /* Ensure that the PMSAR registers are reset (Soft reset does not reset PMSAR). */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + for (uint32_t i = 0; i < 9; i++) + { + R_PMISC->PMSAR[i].PMSAR = UINT16_MAX; + } + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); + +#if BSP_TZ_SECURE_BUILD + + /* Initialize security features. */ + R_BSP_SecurityInit(); +#endif + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); + /* Initialize ELC events that will be used to trigger NVIC interrupts. */ bsp_irq_cfg(); diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index 2da78b629..0855b1a0b 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -23,57 +23,82 @@ **********************************************************************************************************************/ #include "bsp_clocks.h" +#if BSP_TZ_NONSECURE_BUILD + #include "bsp_guard.h" +#endif + /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ /* Key code for writing PRCR register. */ -#define BSP_PRV_PRCR_KEY (0xA500U) -#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) -#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x3U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) -#define BSP_PRV_MAXIMUM_HOCOWTR_HSTS ((uint8_t) 0x6U) +#define BSP_PRV_MAXIMUM_HOCOWTR_HSTS ((uint8_t) 0x6U) /* Wait state definitions for MEMWAIT. */ -#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U) -#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (1U) -#define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ (32000000U) +#define BSP_PRV_MEMWAIT_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_MEMWAIT_TWO_WAIT_CYCLES (1U) +#define BSP_PRV_MEMWAIT_MAX_ZERO_WAIT_FREQ (32000000U) /* Wait state definitions for FLDWAITR. */ -#define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES (0U) -#define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES (1U) -#define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ (32000000U) +#define BSP_PRV_FLDWAITR_ONE_WAIT_CYCLES (0U) +#define BSP_PRV_FLDWAITR_TWO_WAIT_CYCLES (1U) +#define BSP_PRV_FLDWAITR_MAX_ONE_WAIT_FREQ (32000000U) /* Temporary solution until R_FACI is added to renesas.h. */ -#define BSP_PRV_FLDWAITR_REG_ACCESS (*((volatile uint8_t *) (0x407EFFC4U))) +#define BSP_PRV_FLDWAITR_REG_ACCESS (*((volatile uint8_t *) (0x407EFFC4U))) /* Wait state definitions for MCUS with SRAMWTSC and FLWT. */ -#define BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) -#define BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) -#define BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS (80000000U) -#define BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES (0U) -#define BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES (0xEU) -#define BSP_PRV_ROM_ZERO_WAIT_CYCLES (0U) -#define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U) -#define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U) -#define BSP_PRV_SRAM_PRCR_KEY (0x78U) -#define BSP_PRV_SRAM_UNLOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x1U) -#define BSP_PRV_SRAM_LOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x0U) +#define BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES (0xEU) +#define BSP_PRV_ROM_ZERO_WAIT_CYCLES (0U) +#define BSP_PRV_ROM_ONE_WAIT_CYCLES (1U) +#define BSP_PRV_ROM_TWO_WAIT_CYCLES (2U) +#define BSP_PRV_ROM_THREE_WAIT_CYCLES (3U) +#define BSP_PRV_SRAM_PRCR_KEY (0x78U) +#define BSP_PRV_SRAM_UNLOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x1U) +#define BSP_PRV_SRAM_LOCK (((BSP_PRV_SRAM_PRCR_KEY) << 1) | 0x0U) /* Calculate value to write to MOMCR (MODRV controls main clock drive strength and MOSEL determines the source of the * main oscillator). */ -#define BSP_PRV_MOMCR_MOSEL_BIT (6) -#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ - BSP_FEATURE_CGC_MODRV_MASK) -#define BSP_PRV_MOSEL (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << BSP_PRV_MOMCR_MOSEL_BIT) -#define BSP_PRV_MOMCR (BSP_PRV_MODRV | BSP_PRV_MOSEL) +#define BSP_PRV_MOMCR_MOSEL_BIT (6) +#define BSP_PRV_MODRV ((CGC_MAINCLOCK_DRIVE << BSP_FEATURE_CGC_MODRV_SHIFT) & \ + BSP_FEATURE_CGC_MODRV_MASK) +#define BSP_PRV_MOSEL (BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE << BSP_PRV_MOMCR_MOSEL_BIT) +#define BSP_PRV_MOMCR (BSP_PRV_MODRV | BSP_PRV_MOSEL) /* Locations of bitfields used to configure CLKOUT. */ -#define BSP_PRV_CKOCR_CKODIV_BIT (4U) -#define BSP_PRV_CKOCR_CKOEN_BIT (7U) +#define BSP_PRV_CKOCR_CKODIV_BIT (4U) +#define BSP_PRV_CKOCR_CKOEN_BIT (7U) + +#ifdef BSP_CFG_UCK_DIV + +/* If the MCU has SCKDIVCR2. */ + #if !BSP_FEATURE_BSP_HAS_USBCKDIVCR /* Location of bitfield used to configure USB clock divider. */ -#define BSP_PRV_SCKDIVCR2_UCK_BIT (4U) + #define BSP_PRV_SCKDIVCR2_UCK_BIT (4U) + #define BSP_PRV_UCK_DIV (BSP_CFG_UCK_DIV) + +/* If the MCU has USBCKDIVCR. */ + #elif BSP_FEATURE_BSP_HAS_USBCKDIVCR + + #if BSP_CLOCKS_USB_CLOCK_DIV_3 == BSP_CFG_UCK_DIV + #define BSP_PRV_UCK_DIV (5U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_4 == BSP_CFG_UCK_DIV + #define BSP_PRV_UCK_DIV (2U) + #elif BSP_CLOCKS_USB_CLOCK_DIV_5 == BSP_CFG_UCK_DIV + #define BSP_PRV_UCK_DIV (6U) + #else + + #error "BSP_CFG_UCK_DIV not supported." + + #endif + #endif +#endif /* Calculate the value to write to SCKDIVCR. */ #define BSP_PRV_STARTUP_SCKDIVCR_ICLK_BITS ((BSP_CFG_ICLK_DIV & 7U) << 24U) @@ -152,6 +177,17 @@ #endif #endif +#if BSP_FEATURE_CGC_HAS_PLL2 + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PL2SRCSEL (0) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PL2SRCSEL (1) + #endif + #define BSP_PRV_PLL2CCR ((BSP_CFG_PLL2_MUL << R_SYSTEM_PLL2CCR_PLL2MUL_Pos) | \ + (BSP_CFG_PLL2_DIV << R_SYSTEM_PLL2CCR_PL2IDIV_Pos) | \ + (BSP_PRV_PL2SRCSEL << R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos)) +#endif + /* Determine the optimal operating speed mode to apply after clock configuration based on the startup clock * frequency. */ #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ && \ @@ -190,7 +226,76 @@ static void bsp_prv_clock_set_hard_reset(void); /* This array stores the clock frequency of each system clock. This section of RAM should not be initialized by the C * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime * environment is initialized. */ -static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(".noinit"); +static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT); + +#if BSP_TZ_SECURE_BUILD + +/* Callback used to notify the nonsecure project that the clock settings have changed. */ +static bsp_clock_update_callback_t g_bsp_clock_update_callback = NULL; + +/* Pointer to nonsecure memory to store the callback args. */ +static bsp_clock_update_callback_args_t * gp_callback_memory = NULL; + +/* Reentrant method of calling the clock_update_callback. */ +static void r_bsp_clock_update_callback_call (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_args) +{ + /* Allocate memory for saving global callback args on the secure stack. */ + bsp_clock_update_callback_args_t callback_args; + + /* Save current info stored in callback memory. */ + callback_args = *gp_callback_memory; + + /* Write the callback args to the nonsecure callback memory. */ + *gp_callback_memory = *p_callback_args; + + /* Call the callback to notifiy ns project about clock changes. */ + p_callback(gp_callback_memory); + + /* Restore the info in callback memory. */ + *gp_callback_memory = callback_args; +} + +/* Initialize the callback, callback memory and invoke the callback to ensure the nonsecure project has the correct clock settings. */ +void r_bsp_clock_update_callback_set (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + /* Store pointer to nonsecure callback memory. */ + gp_callback_memory = p_callback_memory; + + /* Store callback. */ + g_bsp_clock_update_callback = p_callback; + + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); +} + +#elif BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU + +bsp_clock_update_callback_args_t g_callback_memory; + #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +static void BSP_CMSE_NONSECURE_CALL g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #elif defined(__GNUC__) + +static BSP_CMSE_NONSECURE_CALL void g_bsp_clock_update_callback (bsp_clock_update_callback_args_t * p_callback_args) + #endif + +{ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = p_callback_args->pll_freq; + + /* Update the SystemCoreClock value based on the new g_clock_freq settings. */ + SystemCoreClockUpdate(); +} + + #endif +#endif #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED @@ -423,7 +528,6 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr) /* Set the system source clock */ R_SYSTEM->SCKSCR = (uint8_t) clock; } - /* If the current ICLK divider is greater (lower frequency) than the requested ICLK divider, set the clock * source first. If the ICLK divider is the same, order does not matter. */ else @@ -440,6 +544,20 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr) /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ SystemCoreClock = clock_freq_hz_post_change; +#if BSP_TZ_SECURE_BUILD + if (NULL != g_bsp_clock_update_callback) + { + /* Set callback args. */ + bsp_clock_update_callback_args_t callback_args = + { + .pll_freq = g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] + }; + + /* Call the callback. */ + r_bsp_clock_update_callback_call(g_bsp_clock_update_callback, &callback_args); + } +#endif + /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be * set is lower than previous. */ bsp_clock_set_postchange(SystemCoreClock, new_rom_wait_state); @@ -460,13 +578,16 @@ static void bsp_prv_clock_set_hard_reset (void) /* Calculate the wait states for ROM */ #if BSP_FEATURE_CGC_HAS_FLWT - #if BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS + #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS /* Do nothing. Default setting in FLWT is correct. */ - #elif BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS + #elif BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS R_FCACHE->FLWT = BSP_PRV_ROM_ONE_WAIT_CYCLES; - #else + #elif 0 == BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS || \ + (BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS) R_FCACHE->FLWT = BSP_PRV_ROM_TWO_WAIT_CYCLES; + #else + R_FCACHE->FLWT = BSP_PRV_ROM_THREE_WAIT_CYCLES; #endif #endif @@ -512,10 +633,16 @@ static void bsp_prv_clock_set_hard_reset (void) /* Adjust the MCU specific wait state soon after the system clock is set, if the system clock frequency to be * set is lower than previous. */ #if BSP_FEATURE_CGC_HAS_SRAMWTSC - #if BSP_STARTUP_ICLK_HZ <= BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS + #if BSP_STARTUP_ICLK_HZ <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES; R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif #endif #endif @@ -525,37 +652,68 @@ static void bsp_prv_clock_set_hard_reset (void) #endif /*******************************************************************************************************************//** - * Initializes system clocks. Makes no assumptions about current register settings. + * Initializes variable to store system clock frequencies. **********************************************************************************************************************/ -void bsp_clock_init (void) -{ - /* Unlock CGC and LPM protection registers. */ - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; - -#if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE - - /* Disable ROM cache. */ - R_FCACHE->FCACHEE = 0U; -#endif -#if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER - - /* Disable the flash prefetch buffer. */ - R_FACI_LP->PFBER = 0; +#if BSP_TZ_NONSECURE_BUILD +void bsp_clock_freq_var_init (void) +#else +static void bsp_clock_freq_var_init (void) #endif - +{ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_HOCO] = BSP_HOCO_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MOCO] = BSP_MOCO_FREQ_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_LOCO] = BSP_LOCO_FREQ_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC] = BSP_CFG_XTAL_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK] = BSP_SUBCLOCK_FREQ_HZ; #if BSP_PRV_PLL_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + + /* The PLL Is the startup clock. */ + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ; + #else /* The PLL value will be calculated at initialization. */ g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_XTAL_HZ; + #endif +#endif + +#if BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU + + /* If the CGC is secure and this is a non secure project, register a callback for getting clock settings. */ + R_BSP_ClockUpdateCallbackSet(g_bsp_clock_update_callback, &g_callback_memory); #endif /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ SystemCoreClockUpdate(); +} + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + /* Unlock CGC and LPM protection registers. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_UNLOCK; + +#if BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM + #if !BSP_CFG_USE_LOW_VOLTAGE_MODE && BSP_FEATURE_BSP_FLASH_CACHE + + /* Disable flash cache before modifying MEMWAIT, SOPCCR, or OPCCR. */ + R_BSP_FlashCacheDisable(); + #endif +#else + + /* Enable the flash cache and don't disable it while running from flash. On these MCUs, the flash cache does not + * need to be disabled when adjusting the operating power mode. */ + R_BSP_FlashCacheEnable(); +#endif +#if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER + + /* Disable the flash prefetch buffer. */ + R_FACI_LP->PFBER = 0; +#endif + + bsp_clock_freq_var_init(); #if BSP_CFG_SOFT_RESET_SUPPORTED @@ -572,6 +730,7 @@ void bsp_clock_init (void) /* Set the main oscillator wait time. */ R_SYSTEM->MOSCWTCR = (uint8_t) BSP_CLOCK_CFG_MAIN_OSC_WAIT; } + #else /* Configure main oscillator drive. */ @@ -596,6 +755,7 @@ void bsp_clock_init (void) R_BSP_SoftwareDelay(BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS, BSP_DELAY_UNITS_MILLISECONDS); #endif } + #else R_SYSTEM->SOSCCR = 1U; #endif @@ -659,9 +819,6 @@ void bsp_clock_init (void) R_SYSTEM->MOSCCR = 0U; #endif - /* Store PLL frequency. */ - g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_STARTUP_SOURCE_CLOCK_HZ; - /* Configure the PLL registers. */ #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; @@ -717,6 +874,7 @@ void bsp_clock_init (void) R_SYSTEM->LOCOCR = 0U; R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); } + #else R_SYSTEM->LOCOCR = 0U; R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS); @@ -762,27 +920,6 @@ void bsp_clock_init (void) #endif #endif - /* Set USB clock divisor if it exists on the MCU. */ -#ifdef BSP_CFG_UCK_DIV - R_SYSTEM->SCKDIVCR2 = BSP_CFG_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT; -#endif - -#if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL - - /* Some MCUs have an alternate register for selecting the USB clock source. */ - #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT - #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCK_SOURCE - - /* Write to USBCKCR to select the PLL. */ - R_SYSTEM->USBCKCR = 0; - #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCK_SOURCE - - /* Write to USBCKCR to select the HOCO. */ - R_SYSTEM->USBCKCR = 1; - #endif - #endif -#endif - /* Configure BCLK if it exists on the MCU. */ #ifdef BSP_CFG_BCLK_OUTPUT #if BSP_CFG_BCLK_OUTPUT > 0U @@ -801,7 +938,7 @@ void bsp_clock_init (void) #endif /* Configure CLKOUT. */ -#if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLKOUT_DISABLED +#if BSP_CFG_CLKOUT_SOURCE == BSP_CLOCKS_CLOCK_DISABLED #if BSP_CFG_SOFT_RESET_SUPPORTED R_SYSTEM->CKOCR = 0U; #endif @@ -812,17 +949,102 @@ void bsp_clock_init (void) R_SYSTEM->CKOCR = ckocr; #endif - /* Lock CGC and LPM protection registers. */ - R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; +#if BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED + #if BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + + /* Start PLL source clock. */ + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + R_SYSTEM->HOCOCR = 0U; + #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL2_SOURCE + R_SYSTEM->MOSCCR = 0U; + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.MOSCSF, 1U); + #endif /* BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE */ + + R_SYSTEM->PLL2CCR = BSP_PRV_PLL2CCR; + + /* Start the PLL. */ + R_SYSTEM->PLL2CR = 0U; + + /* Wait for the PLL to stabilize. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OSCSF_b.PLL2SF, 1U); + #endif /* BSP_FEATURE_CGC_HAS_PLL2 && BSP_CFG_PLL2_ENABLE */ + + #if BSP_CFG_UCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + + /* If the USB clock has a divider setting in SCKDIVCR2. */ + #if BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV && !BSP_FEATURE_BSP_HAS_USBCKDIVCR + R_SYSTEM->SCKDIVCR2 = BSP_PRV_UCK_DIV << BSP_PRV_SCKDIVCR2_UCK_BIT; + #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV && !BSP_FEATURE_BSP_HAS_USBCKDIVCR */ + + /* If there is a REQ bit in USBCKCR than follow sequence from section 8.2.29 in RA6M4 hardware manual R01UH0890EJ0050. */ + #if BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ + + /* Request to change the USB Clock. */ + R_SYSTEM->USBCKCR_b.USBCKSREQ = 1; + + /* Wait for the clock to be stopped. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 1U); + + /* Write the settings. */ + R_SYSTEM->USBCKDIVCR = BSP_PRV_UCK_DIV; + + /* Select the USB Clock without enabling it. */ + R_SYSTEM->USBCKCR = BSP_CFG_UCK_SOURCE | R_SYSTEM_USBCKCR_USBCKSREQ_Msk; + #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ */ + + #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL + + /* Some MCUs use an alternate register for selecting the USB clock source. */ + #if BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT + #if BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_UCK_SOURCE + + /* Write to USBCKCR to select the PLL. */ + R_SYSTEM->USBCKCR_ALT = 0; + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_UCK_SOURCE + + /* Write to USBCKCR to select the HOCO. */ + R_SYSTEM->USBCKCR_ALT = 1; + #endif + #else + + /* Select the USB Clock. */ + R_SYSTEM->USBCKCR = BSP_CFG_UCK_SOURCE; + #endif + #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ */ + + #if BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ + + /* Wait for the USB Clock to be started. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->USBCKCR_b.USBCKSRDY, 0U); + #endif /* BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ */ + #endif /* BSP_CFG_USB_ENABLE */ +#endif /* BSP_PRV_STARTUP_OPERATING_MODE != BSP_PRV_OPERATING_MODE_LOW_SPEED */ + + /* Set the OCTASPI clock if it exists on the MCU (See section 8.2.30 of the RA6M4 hardware manual R01UH0890EJ0050). */ +#if BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK && BSP_CFG_OCTA_SOURCE != BSP_CLOCKS_CLOCK_DISABLED + + /* Request to change the OCTASPI Clock. */ + R_SYSTEM->OCTACKCR_b.OCTACKSREQ = 1; -#if BSP_FEATURE_BSP_FLASH_CACHE + /* Wait for the clock to be stopped. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 1U); - /* Invalidate flash cache. */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + /* Write the settings. */ + R_SYSTEM->OCTACKDIVCR = BSP_CFG_OCTA_DIV; + R_SYSTEM->OCTACKCR = BSP_CFG_OCTA_SOURCE | R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk; + + /* Start the OCTASPI Clock. */ + R_SYSTEM->OCTACKCR = BSP_CFG_OCTA_SOURCE; + + /* Wait for the OCTASPI Clock to be started. */ + FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OCTACKCR_b.OCTACKSRDY, 0U); +#endif /* BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK && BSP_CFG_OCTASPI_CLOCK_ENABLE */ + + /* Lock CGC and LPM protection registers. */ + R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK; - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; +#if BSP_FEATURE_BSP_FLASH_CACHE && BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM + R_BSP_FlashCacheEnable(); #endif #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER @@ -844,30 +1066,46 @@ static uint8_t bsp_clock_set_prechange (uint32_t requested_freq_hz) #if BSP_FEATURE_CGC_HAS_SRAMWTSC /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ - if (requested_freq_hz > BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS) + if (requested_freq_hz > BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS) { + #ifdef BSP_FEATURE_CGC_HAS_SRAMPRCR2 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ONE_WAIT_CYCLES; R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif } #endif #if BSP_FEATURE_CGC_HAS_FLWT /* Calculate the wait states for ROM */ - if (requested_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_ONE_ROM_WAITS) + if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS) { new_rom_wait_state = BSP_PRV_ROM_ZERO_WAIT_CYCLES; } - else if (requested_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_TWO_ROM_WAITS) + else if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS) { new_rom_wait_state = BSP_PRV_ROM_ONE_WAIT_CYCLES; } else + #if BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS > 0 + if (requested_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS) + #endif { new_rom_wait_state = BSP_PRV_ROM_TWO_WAIT_CYCLES; } + #if BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS > 0 + else + { + new_rom_wait_state = BSP_PRV_ROM_THREE_WAIT_CYCLES; + } + #endif + /* If more wait states are required after the change, then set the wait states before changing the clock. */ if (new_rom_wait_state > R_FCACHE->FLWT) { @@ -911,11 +1149,17 @@ static void bsp_clock_set_postchange (uint32_t updated_freq_hz, uint8_t new_rom_ #if BSP_FEATURE_CGC_HAS_SRAMWTSC /* Wait states for SRAM (SRAM0, SRAM1 and SRAM0 (DED)). */ - if (updated_freq_hz <= BSP_PRV_SYS_CLOCK_FREQ_NO_RAM_WAITS) + if (updated_freq_hz <= BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS) { + #if BSP_FEATURE_CGC_HAS_SRAMPRCR2 == 1 + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_UNLOCK; + R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES; + R_SRAM->SRAMPRCR2 = BSP_PRV_SRAM_LOCK; + #else R_SRAM->SRAMPRCR = BSP_PRV_SRAM_UNLOCK; R_SRAM->SRAMWTSC = BSP_PRV_SRAMWTSC_ZERO_WAIT_CYCLES; R_SRAM->SRAMPRCR = BSP_PRV_SRAM_LOCK; + #endif } #endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index 817e1357b..0491b67b9 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -42,8 +42,9 @@ FSP_HEADER #define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. #define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. #define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. -/* PLL is not supported in the following scenarios: +/* PLLs are not supported in the following scenarios: * - When using low voltage mode * - When using an MCU that does not have a PLL * - When the PLL only accepts the main oscillator as a source and XTAL is not used @@ -51,8 +52,14 @@ FSP_HEADER #if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) #define BSP_PRV_PLL_SUPPORTED (1) + #if BSP_FEATURE_CGC_HAS_PLL2 + #define BSP_PRV_PLL2_SUPPORTED (1) + #else + #define BSP_PRV_PLL2_SUPPORTED (0) + #endif #else #define BSP_PRV_PLL_SUPPORTED (0) + #define BSP_PRV_PLL2_SUPPORTED (0) #endif /* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency @@ -64,6 +71,13 @@ FSP_HEADER #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) #endif #endif +#if BSP_PRV_PLL2_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif /* Frequencies of clocks with fixed freqencies. */ #define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz @@ -121,6 +135,13 @@ FSP_HEADER #define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 #define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 +/* OCTA clock divider options. */ +#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 + /* PLL divider options. */ #define BSP_CLOCKS_PLL_DIV_1 (0) #define BSP_CLOCKS_PLL_DIV_2 (1) @@ -173,8 +194,8 @@ FSP_HEADER #define BSP_CLOCKS_PLL_MUL_30_0 (0x3B) #define BSP_CLOCKS_PLL_MUL_31_0 (0x3D) -/* Configuration option used to disable CLKOUT output. */ -#define BSP_CLOCKS_CLKOUT_DISABLED (0xFFU) +/* Configuration option used to disable clock output. */ +#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) /* HOCO cycles per microsecond. */ #define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) @@ -234,6 +255,22 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +typedef struct +{ + uint32_t pll_freq; +} bsp_clock_update_callback_args_t; + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #endif + +#endif + /*********************************************************************************************************************** * Exported global variables **********************************************************************************************************************/ @@ -245,6 +282,17 @@ FSP_HEADER /* Public functions defined in bsp.h */ void bsp_clock_init(void); // Used internally by BSP +#if BSP_TZ_NONSECURE_BUILD +void bsp_clock_freq_var_init(void); // Used internally by BSP + +#endif + +#if BSP_TZ_SECURE_BUILD +void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + /* Used internally by CGC */ #if !BSP_CFG_USE_LOW_VOLTAGE_MODE diff --git a/ra/fsp/src/bsp/mcu/all/bsp_common.h b/ra/fsp/src/bsp/mcu/all/bsp_common.h index ef18258a8..62214275d 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_common.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -174,8 +174,12 @@ extern const fsp_version_t g_bsp_version; /* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */ #define FSP_PRIV_SCKDIVCR_DIV_MASK (7) -#define BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) -#define BSP_UNIQUE_ID_OFFSET (0x14) +/* Use the secure registers for secure projects and flat projects. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + #define FSP_PRIV_TZ_USE_SECURE_REGS (1) +#else + #define FSP_PRIV_TZ_USE_SECURE_REGS (0) +#endif /*********************************************************************************************************************** * Typedef definitions @@ -256,7 +260,29 @@ __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) **********************************************************************************************************************/ __STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet () { - return (bsp_unique_id_t *) ((*(uint32_t *) BSP_MCU_INFO_POINTER_LOCATION) + BSP_UNIQUE_ID_OFFSET); + return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; +} + +/*******************************************************************************************************************//** + * Disables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheDisable () +{ + R_FCACHE->FCACHEE = 0U; +} + +/*******************************************************************************************************************//** + * Enables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheEnable () +{ + /* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache + * in the RA6M3 manual R01UH0878EJ0100). */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; } /*********************************************************************************************************************** diff --git a/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h index e0dfd42d0..544b579b5 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -26,27 +26,38 @@ #ifndef BSP_COMPILER_SUPPORT_H #define BSP_COMPILER_SUPPORT_H +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include +#endif + /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ #if defined(__ARMCC_VERSION) /* AC6 compiler */ - #define BSP_SECTION_HEAP ".bss.heap" + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" #define BSP_DONT_REMOVE #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) #define BSP_FORCE_INLINE __attribute__((always_inline)) #elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX #define BSP_SECTION_HEAP ".heap" #define BSP_DONT_REMOVE #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) #define BSP_FORCE_INLINE __attribute__((always_inline)) #elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX #define BSP_SECTION_HEAP "HEAP" #define BSP_DONT_REMOVE __root #define BSP_ATTRIBUTE_STACKLESS __stackless #define BSP_FORCE_INLINE _Pragma("inline=forced") #endif -#define BSP_SECTION_STACK ".stack" +#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" +#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" #define BSP_SECTION_ROM_REGISTERS ".rom_registers" @@ -57,16 +68,28 @@ #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) -#define BSP_PACKED __attribute__((aligned(1))) +#define BSP_PACKED __attribute__((aligned(1))) -#define BSP_WEAK_REFERENCE __attribute__((weak)) +#define BSP_WEAK_REFERENCE __attribute__((weak)) /** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ -#define BSP_STACK_ALIGNMENT (8) +#define BSP_STACK_ALIGNMENT (8) /*********************************************************************************************************************** - * Typedef definitions + * TrustZone definitions **********************************************************************************************************************/ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #if defined(__ICCARM__) /* IAR compiler */ + #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call + #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry + #else + #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) + #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) + #endif +#else + #define BSP_CMSE_NONSECURE_CALL + #define BSP_CMSE_NONSECURE_ENTRY +#endif /*********************************************************************************************************************** * Exported global variables diff --git a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c index 5098697f3..e6b2a60c3 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c @@ -26,7 +26,7 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BSP_GRP_IRQ_TOTAL_ITEMS (13U) +#define BSP_GRP_IRQ_TOTAL_ITEMS (16U) /*********************************************************************************************************************** * Typedef definitions @@ -105,7 +105,7 @@ void NMI_Handler (void) uint16_t nmisr = R_ICU->NMISR; /* Loop over all NMI status flags */ - for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_MPU_STACK; irq++) + for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_CACHE_PARITY; irq++) { /* If the current irq status register is set call the irq callback. */ if (0U != (nmisr & (1U << irq))) diff --git a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h index a51e154e5..2e910b362 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h @@ -53,6 +53,8 @@ typedef enum e_bsp_grp_irq BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error + BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error + BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error } bsp_grp_irq_t; /* Callback type. */ diff --git a/ra/fsp/src/r_sce/ra2/SC324_p99.prc.c b/ra/fsp/src/bsp/mcu/all/bsp_guard.c similarity index 64% rename from ra/fsp/src/r_sce/ra2/SC324_p99.prc.c rename to ra/fsp/src/bsp/mcu/all/bsp_guard.c index 1f57caa37..fe06756cb 100644 --- a/ra/fsp/src/r_sce/ra2/SC324_p99.prc.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_guard.c @@ -18,30 +18,38 @@ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. **********************************************************************************************************************/ -////////////////////////////////////////////////////////////////////////// -// // -// Procedure number: 99 // -// File name : SC324_p99.prc // -// State Diagram : main(FSM1) // -// Start State : main02 // -// End State : main03 // -// Input Data : void // -// Output Data : void // -// Return value : Pass, Resource_Conflict // -// ----------------------------------------------------------------------// -// total cycle : polling + write access + read access // -// polling : // -// polling access : // -// write access : // -// read access : // -////////////////////////////////////////////////////////////////////////// - -#include "hw_sce_private.h" +#include "bsp_guard.h" + +/* Only the secure project has nonsecure callable functions. */ +#if BSP_TZ_SECURE_BUILD + +/* If the CGG Security Attribution is configured to secure access only. */ + #if BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU /*******************************************************************************************************************//** - * Secure Boot procedure - * @retval FSP_SUCCESS The operation completed successfully. + * Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed. + * + * @retval FSP_SUCCESS Callback set. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. **********************************************************************************************************************/ -fsp_err_t HW_SCE_secureBoot (void) { +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet (bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory) +{ + bsp_clock_update_callback_t p_callback_checked = + (bsp_clock_update_callback_t) cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE); + + bsp_clock_update_callback_args_t * p_callback_memory_checked = + (bsp_clock_update_callback_args_t *) cmse_check_address_range(p_callback_memory, + sizeof(bsp_clock_update_callback_args_t), + CMSE_AU_NONSECURE); + FSP_ASSERT(p_callback == p_callback_checked); + FSP_ASSERT(p_callback_memory == p_callback_memory_checked); + + r_bsp_clock_update_callback_set(p_callback_checked, p_callback_memory_checked); + return FSP_SUCCESS; } + + #endif + +#endif diff --git a/ra/fsp/src/r_sce/ra2/SC324_SoftReset.prc.c b/ra/fsp/src/bsp/mcu/all/bsp_guard.h similarity index 68% rename from ra/fsp/src/r_sce/ra2/SC324_SoftReset.prc.c rename to ra/fsp/src/bsp/mcu/all/bsp_guard.h index 8dd759290..81a284c3d 100644 --- a/ra/fsp/src/r_sce/ra2/SC324_SoftReset.prc.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_guard.h @@ -18,21 +18,29 @@ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. **********************************************************************************************************************/ -///////////////////////////////////////////////////////////////////////// -// // -// File name : SC324_SoftReset.prc // -// State Diagram : All state transition // -// Start State : All state // -// End State : main00 // -// Input Data : void // -// Output Data : void // -// return value : void // -// ---------------------------------------------------------------------// -// total cycle : write access // -// write access : 3 times // -///////////////////////////////////////////////////////////////////////// - -#include "hw_sce_private.h" - -void HW_SCE_SoftReset () { -} +#ifndef BSP_GUARD_H +#define BSP_GUARD_H + +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/ra/fsp/src/bsp/mcu/all/bsp_io.h b/ra/fsp/src/bsp/mcu/all/bsp_io.h index 4eec4289d..9e8958c81 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_io.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_io.h @@ -336,8 +336,13 @@ __STATIC_INLINE void R_BSP_PinAccessEnable (void) /** If this is first entry then allow writing of PFS. */ if (0 == g_protect_pfswe_counter) { - R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #if BSP_TZ_SECURE_BUILD + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif } /** Increment the protect counter */ @@ -370,8 +375,13 @@ __STATIC_INLINE void R_BSP_PinAccessDisable (void) /** Is it safe to disable writing of PFS? */ if (0 == g_protect_pfswe_counter) { - R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled - R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + #if BSP_TZ_SECURE_BUILD + R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + #endif } /** Restore the interrupt state */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.c b/ra/fsp/src/bsp/mcu/all/bsp_irq.c index edd9e64fe..5a7fe5b6e 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.c @@ -28,7 +28,8 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ -#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) +#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) +#define BSP_PRV_BITS_PER_WORD (32) /*********************************************************************************************************************** * Typedef definitions @@ -62,6 +63,45 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT **********************************************************************************************************************/ void bsp_irq_cfg (void) { +#if FSP_PRIV_TZ_USE_SECURE_REGS + + /* Unprotect security registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + #if !BSP_TZ_SECURE_BUILD + + /* Set the DMAC channels to secure access. */ + R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk; + #endif + + /* Place all vectors in non-secure state unless they are used in the secure project. */ + uint32_t interrupt_security_state[BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD]; + memset(&interrupt_security_state, UINT8_MAX, sizeof(interrupt_security_state)); + + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++) + { + if (0U != g_interrupt_event_link_select[i]) + { + /* This is a secure vector. Clear the associated bit. */ + uint32_t index = i / BSP_PRV_BITS_PER_WORD; + uint32_t bit = i % BSP_PRV_BITS_PER_WORD; + interrupt_security_state[index] &= ~(1U << bit); + } + } + + /* The Secure Attribute managed within the ARM CPU NVIC must match the security attribution of IELSEn + * (Reference section 13.2.9 in the RA6M4 manual R01UH0890EJ0050). */ + uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARG; + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD; i++) + { + p_icusarg[i] = interrupt_security_state[i]; + NVIC->ITNS[i] = interrupt_security_state[i]; + } + + /* Protect security registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +#endif + for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++) { R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i]; diff --git a/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/ra/fsp/src/bsp/mcu/all/bsp_irq.h index 768a84fe5..a439eab00 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_irq.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -107,6 +107,8 @@ __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * every time a priority is configured in the NVIC. */ #if (4U == __CORTEX_M) NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); +#elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); #elif (23 == __CORTEX_M) NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index 85c06bef7..f4092b359 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -35,9 +35,10 @@ FSP_HEADER * @param ip fsp_ip_t enum value for the module to be stopped * @param channel The channel. Use channel 0 for modules without channels. **********************************************************************************************************************/ -#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip &= ~BSP_MSTP_BIT_ ## ip(channel); \ +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ FSP_CRITICAL_SECTION_EXIT;} /*******************************************************************************************************************//** @@ -46,92 +47,105 @@ FSP_HEADER * @param ip fsp_ip_t enum value for the module to be stopped * @param channel The channel. Use channel 0 for modules without channels. **********************************************************************************************************************/ -#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ - FSP_CRITICAL_SECTION_ENTER; \ - BSP_MSTP_REG_ ## ip |= BSP_MSTP_BIT_ ## ip(channel); \ +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ FSP_CRITICAL_SECTION_EXIT;} /** @} (end addtogroup BSP_MCU) */ -#define BSP_MSTP_REG_FSP_IP_GPT R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ +#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ channel) ? (1U << 5U) : (1U << 6U)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); +#else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U)))); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); +#endif -#define BSP_MSTP_REG_FSP_IP_DMAC R_SYSTEM->MSTPCRA +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_SYSTEM->MSTPCRA #define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); -#define BSP_MSTP_REG_FSP_IP_DTC R_SYSTEM->MSTPCRA +#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_SYSTEM->MSTPCRA #define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); -#define BSP_MSTP_REG_FSP_IP_CAN R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_FSP_IP_IRDA R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_FSP_IP_QSPI R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_FSP_IP_IIC R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_FSP_IP_USBFS R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); -#define BSP_MSTP_REG_FSP_IP_USBHS R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_FSP_IP_EPTPC R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_FSP_IP_ETHER R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); -#define BSP_MSTP_REG_FSP_IP_SPI R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); -#define BSP_MSTP_REG_FSP_IP_SCI R_MSTP->MSTPCRB +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB #define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_CAC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); -#define BSP_MSTP_REG_FSP_IP_CRC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); -#define BSP_MSTP_REG_FSP_IP_PDC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); -#define BSP_MSTP_REG_FSP_IP_CTSU R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_FSP_IP_SLCDC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_FSP_IP_GLCDC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); -#define BSP_MSTP_REG_FSP_IP_JPEG R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); -#define BSP_MSTP_REG_FSP_IP_DRW R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); -#define BSP_MSTP_REG_FSP_IP_SSI R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); -#define BSP_MSTP_REG_FSP_IP_SRC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); -#define BSP_MSTP_REG_FSP_IP_SDHIMMC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); -#define BSP_MSTP_REG_FSP_IP_DOC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); -#define BSP_MSTP_REG_FSP_IP_ELC R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); -#define BSP_MSTP_REG_FSP_IP_TRNG R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_FSP_IP_SCE R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_AES R_MSTP->MSTPCRC +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC #define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); -#define BSP_MSTP_REG_FSP_IP_AGT R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); -#define BSP_MSTP_REG_FSP_IP_POEG R_MSTP->MSTPCRD -#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); -#define BSP_MSTP_REG_FSP_IP_ADC R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); -#define BSP_MSTP_REG_FSP_IP_SDADC R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); -#define BSP_MSTP_REG_FSP_IP_DAC8 R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); -#define BSP_MSTP_REG_FSP_IP_DAC R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); -#define BSP_MSTP_REG_FSP_IP_TSN R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); -#define BSP_MSTP_REG_FSP_IP_ACMPHS R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); -#define BSP_MSTP_REG_FSP_IP_ACMPLP R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); -#define BSP_MSTP_REG_FSP_IP_OPAMP R_MSTP->MSTPCRD +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c index e19c87250..e5cfd06c7 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -45,7 +45,7 @@ /** Used for holding reference counters for protection bits. */ static volatile uint16_t g_protect_counters[] = { - 0U, 0U, 0U + 0U, 0U, 0U, 0U }; /** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ @@ -54,6 +54,7 @@ static const uint16_t g_prcr_masks[] = 0x0001U, /* PRC0. */ 0x0002U, /* PRC1. */ 0x0008U, /* PRC3. */ + 0x0010U, /* PRC4. */ }; /*******************************************************************************************************************//** diff --git a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h index 7bd186c00..6b0621b59 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -50,6 +50,9 @@ typedef enum e_bsp_reg_protect /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, * LVD2CR1, LVD2SR. */ BSP_REG_PROTECT_LVD, + + /** Enables writing to the registers related to the security function. */ + BSP_REG_PROTECT_SAR, } bsp_reg_protect_t; /** @} (end addtogroup BSP_MCU) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c index 1d1f63f93..f4ab0b686 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c @@ -26,6 +26,7 @@ /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ +#define RA_NOT_DEFINED (0) /** OR in the HOCO frequency setting from bsp_clock_cfg.h with the OFS1 setting from bsp_cfg.h. */ #define BSP_ROM_REG_OFS1_SETTING \ @@ -59,6 +60,8 @@ * Private global variables and functions **********************************************************************************************************************/ +#if 33U != __CORTEX_M // NOLINT(readability-magic-numbers) + /** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) = { @@ -83,18 +86,82 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) = { BSP_CFG_ID_CODE_LONG_1, -#if BSP_FEATURE_BSP_OSIS_PADDING + #if BSP_FEATURE_BSP_OSIS_PADDING 0xFFFFFFFFU, -#endif + #endif BSP_CFG_ID_CODE_LONG_2, -#if BSP_FEATURE_BSP_OSIS_PADDING + #if BSP_FEATURE_BSP_OSIS_PADDING 0xFFFFFFFFU, -#endif + #endif BSP_CFG_ID_CODE_LONG_3, -#if BSP_FEATURE_BSP_OSIS_PADDING + #if BSP_FEATURE_BSP_OSIS_PADDING 0xFFFFFFFFU, -#endif + #endif BSP_CFG_ID_CODE_LONG_4 }; +#else /* CM33 parts */ + + #if !BSP_TZ_NONSECURE_BUILD + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 = + BSP_CFG_ROM_REG_OFS0; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_rom_dualsel = + BSP_CFG_ROM_REG_DUALSEL; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas = + 0xFFFFFFFF; + + #else + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_rom_ofs1 = + BSP_ROM_REG_OFS1_SETTING; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_rom_banksel = + 0xFFFFFFFF; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps0") g_bsp_rom_bps0 = + BSP_CFG_ROM_REG_BPS0; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps1") g_bsp_rom_bps1 = + BSP_CFG_ROM_REG_BPS1; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps2") g_bsp_rom_bps2 = + BSP_CFG_ROM_REG_BPS2; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps0") g_bsp_rom_pbps0 = + BSP_CFG_ROM_REG_PBPS0; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps1") g_bsp_rom_pbps1 = + BSP_CFG_ROM_REG_PBPS1; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps2") g_bsp_rom_pbps2 = + BSP_CFG_ROM_REG_PBPS2; + + #endif + + #if !BSP_TZ_NONSECURE_BUILD + +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1_sec = + BSP_ROM_REG_OFS1_SETTING; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_rom_banksel_sec = + 0xFFFFFFFF; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps_sec0 = + BSP_CFG_ROM_REG_BPS0; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec1") g_bsp_rom_bps_sec1 = + BSP_CFG_ROM_REG_BPS1; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec2") g_bsp_rom_bps_sec2 = + BSP_CFG_ROM_REG_BPS2; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps_sec0 = + BSP_CFG_ROM_REG_PBPS0; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec1") g_bsp_rom_pbps_sec1 = + BSP_CFG_ROM_REG_PBPS1; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec2") g_bsp_rom_pbps_sec2 = + BSP_CFG_ROM_REG_PBPS2; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_rom_ofs1_sel = + BSP_CFG_ROM_REG_OFS1_SEL; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_rom_banksel_sel = + 0xFFFFFFFF; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel0") g_bsp_rom_bps_sel0 = + BSP_CFG_ROM_REG_BPS_SEL0; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel1") g_bsp_rom_bps_sel1 = + BSP_CFG_ROM_REG_BPS_SEL1; +BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel2") g_bsp_rom_bps_sel2 = + BSP_CFG_ROM_REG_BPS_SEL2; + + #endif +#endif + /** @} (end addtogroup BSP_MCU) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c new file mode 100644 index 000000000..537b07b60 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if BSP_TZ_SECURE_BUILD + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_PRV_TZ_REG_KEY (0xA500U) + #define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U) + #define RA_NOT_DEFINED (0) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_SecurityInit(void); +void R_BSP_PinCfgSecurityInit(void); +void R_BSP_ElcCfgSecurityInit(void); + +/*********************************************************************************************************************** + * External symbols + **********************************************************************************************************************/ +extern const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES]; + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile bsp_nonsecure_func_t)(void); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); + #endif + + #if defined(__IAR_SYSTEMS_ICC__) + #pragma section=".tz_flash_nsc_start" + #pragma section=".tz_flash_ns_start" + #pragma section=".tz_ram_nsc_start" + #pragma section=".tz_ram_ns_start" + #pragma section=".tz_data_flash_ns_start" + #pragma section=".tz_sdram_ns_start" + #pragma section=".tz_qspi_flash_ns_start" + +/* &__tz__C is the address of the non-secure callable section. */ +/* &__tz__N is the start address of the non-secure region. */ +BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start"; +BSP_DONT_REMOVE void const * const __tz_FLASH_N BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start"; +BSP_DONT_REMOVE void const * const __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start"; +BSP_DONT_REMOVE void const * const __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start"; +BSP_DONT_REMOVE void const * const __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start"; + + #if BSP_FEATURE_SDRAM_START_ADDRESS +BSP_DONT_REMOVE void const * const __tz_SDRAM_N @".tz_sdram_ns_start"; + #endif +BSP_DONT_REMOVE void const * const __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start"; + #if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS +BSP_DONT_REMOVE void const * const __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start"; + #endif + #if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS +BSP_DONT_REMOVE void const * const __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start"; + #endif + +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N; + #elif defined(__ARMCC_VERSION) +extern const uint32_t Image$$__tz_FLASH_N$$Base; +extern const uint32_t Image$$__tz_FLASH_C$$Base; +extern const uint32_t Image$$__tz_FLASH_S$$Base; +extern const uint32_t Image$$__tz_RAM_N$$Base; +extern const uint32_t Image$$__tz_RAM_C$$Base; +extern const uint32_t Image$$__tz_RAM_S$$Base; +extern const uint32_t Image$$__tz_DATA_FLASH_N$$Base; +extern const uint32_t Image$$__tz_DATA_FLASH_S$$Base; +extern const uint32_t Image$$__tz_QSPI_FLASH_N$$Base; +extern const uint32_t Image$$__tz_QSPI_FLASH_S$$Base; +extern const uint32_t Image$$__tz_SDRAM_N$$Base; +extern const uint32_t Image$$__tz_SDRAM_S$$Base; +extern const uint32_t Image$$__tz_OSPI_DEVICE_0_N$$Base; +extern const uint32_t Image$$__tz_OSPI_DEVICE_0_S$$Base; +extern const uint32_t Image$$__tz_OSPI_DEVICE_1_N$$Base; +extern const uint32_t Image$$__tz_OSPI_DEVICE_1_S$$Base; + + #define __tz_FLASH_N Image$$__tz_FLASH_N$$Base + #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base + #define __tz_FLASH_S Image$$__tz_FLASH_S$$Base + #define __tz_RAM_N Image$$__tz_RAM_N$$Base + #define __tz_RAM_C Image$$__tz_RAM_C$$Base + #define __tz_RAM_S Image$$__tz_RAM_S$$Base + #define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base + #define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base + #define __tz_QSPI_FLASH_N Image$$__tz_QSPI_FLASH_N$$Base + #define __tz_QSPI_FLASH_S Image$$__tz_QSPI_FLASH_S$$Base + #define __tz_SDRAM_N Image$$__tz_SDRAM_N$$Base + #define __tz_SDRAM_S Image$$__tz_SDRAM_S$$Base + #define __tz_OSPI_DEVICE_0_N Image$$__tz_OSPI_DEVICE_0_N$$Base + #define __tz_OSPI_DEVICE_0_S Image$$__tz_OSPI_DEVICE_0_S$$Base + #define __tz_OSPI_DEVICE_1_N Image$$__tz_OSPI_DEVICE_1_N$$Base + #define __tz_OSPI_DEVICE_1_S Image$$__tz_OSPI_DEVICE_1_S$$Base + +/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the + * start addresses of Secure, Non-secure and Non-secure Callable regions. */ +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = &__tz_FLASH_C; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_flash = &__tz_FLASH_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = &__tz_RAM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = &__tz_RAM_C; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ram = &__tz_RAM_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = &__tz_DATA_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_data_flash = &__tz_DATA_FLASH_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_qspi_flash = &__tz_QSPI_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_qspi_flash = &__tz_QSPI_FLASH_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_sdram = &__tz_SDRAM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_sdram = &__tz_SDRAM_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_0 = &__tz_OSPI_DEVICE_0_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_0 = &__tz_OSPI_DEVICE_0_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_1 = &__tz_OSPI_DEVICE_1_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_1 = &__tz_OSPI_DEVICE_1_S; + #elif defined(__GNUC__) +extern const uint32_t __tz_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N; + #endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enter the non-secure code environment. + * + * This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler. + * + * @note This function (and therefore the non-secure code) should not return. + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter (void) +{ + /* The NS vector table is at the start of the NS section in flash */ + uint32_t const * p_ns_vector_table = gp_start_of_nonsecure_flash; + + /* Set up the NS Reset_Handler to be called */ + uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t)); + bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address); + + /* Set the NS vector table address */ + SCB_NS->VTOR = (uint32_t) p_ns_vector_table; + + /* Set the NS stack pointer to the first entry in the NS vector table */ + __TZ_set_MSP_NS(p_ns_vector_table[0]); + + /* Jump to the NS Reset_Handler */ + p_ns_reset(); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Initialize security features for TrustZone. + * + * This function initializes ARM security register and Renesas SAR registers for secure projects. + * + * @note IDAU settings must be configured to match project settings with a separate configuration tool. + **********************************************************************************************************************/ +void R_BSP_SecurityInit (void) +{ + /* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the + * system. */ + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + + /* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from + * system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the + * SCB->SCR SLEEPDEEP bit is ignored on RA MCUs. */ + #if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + + /* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target + * secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */ + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + BSP_PRV_AIRCR_VECTKEY | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif + + #if defined(__FPU_USED) && (__FPU_USED == 1U) && \ + defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + /* Configure whether the FPU can be accessed in the non-secure project. */ + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + /* Configure whether FPU registers are always treated as non-secure (and therefore not preserved on the stack when + * switching from secure to non-secure), and whether the FPU registers should be cleared on exception return. */ + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); + #endif + + /* Disable PRCR for SARs. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR); + + /* Set TrustZone filter to Secure. */ + R_TZF->TZFSAR = ~R_TZF_TZFSAR_TZFSA0_Msk; + + /* Set TrustZone filter exception response. */ + R_TZF->TZFPT = BSP_PRV_TZ_REG_KEY + 1U; + R_TZF->TZFOAD = BSP_PRV_TZ_REG_KEY + BSP_TZ_CFG_EXCEPTION_RESPONSE; + R_TZF->TZFPT = BSP_PRV_TZ_REG_KEY + 0U; + + /* Initialize PSARs. */ + R_PSCU->PSARB = BSP_TZ_CFG_PSARB; + R_PSCU->PSARC = BSP_TZ_CFG_PSARC; + R_PSCU->PSARD = BSP_TZ_CFG_PSARD; + R_PSCU->PSARE = BSP_TZ_CFG_PSARE; + R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR; + + /* Initialize Type 2 SARs. */ + R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */ + R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */ + R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */ + R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */ + R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */ + R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */ + R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */ + R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */ + R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */ + R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */ + R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */ + R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */ + R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */ + R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */ + R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */ + R_CPSCU->MMPUSARA = BSP_TZ_CFG_MMPUSARA; /* Security Attribution for the DMAC Bus Master MPU. */ + R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */ + R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */ + + #if BSP_TZ_CFG_ICUSARC != UINT32_MAX + R_BSP_MODULE_START(FSP_IP_DMAC, 0); + + /* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST + * in order to prevent the nonsecure program from disabling all DMAC channels. */ + R_CPSCU->DMACSAR = ~1U; /* Protect DMAST from nonsecure write access. */ + + /* Ensure that DMAST is set so that the nonsecure program can use DMA. */ + R_DMA->DMAST = 1U; + #endif + + #if BSP_TZ_CFG_DTC_USED + R_BSP_MODULE_START(FSP_IP_DTC, 0); + + /* If the DTC is used by the secure program, disable nonsecure write access to DTCST + * in order to prevent the nonsecure program from disabling all DTC transfers. */ + R_CPSCU->DTCSAR = ~1U; + + /* Ensure that DTCST is set so that the nonsecure program can use DTC. */ + R_DTC->DTCST = 1U; + #endif + + /* Initialize security attribution registers for Pins. */ + R_BSP_PinCfgSecurityInit(); + + /* Initialize security attribution registers for ELC. */ + R_BSP_ElcCfgSecurityInit(); + + /* Reenable PRCR for SARs. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR); +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_PinCfgSecurityInit (void) +{ +} + +/* This function is overridden by tooling. */ +BSP_WEAK_REFERENCE void R_BSP_ElcCfgSecurityInit (void) +{ +} + +#else + + #if defined(__ARMCC_VERSION) && BSP_FEATURE_TZ_HAS_TRUSTZONE + +/* These symbols are required to allocate non-secure memory in flat projects on MCUs that support TrustZone. */ + +extern const uint32_t Image$$__tz_FLASH_N$$Base; +extern const uint32_t Image$$__tz_FLASH_C$$Base; +extern const uint32_t Image$$__tz_FLASH_S$$Base; +extern const uint32_t Image$$__tz_RAM_N$$Base; +extern const uint32_t Image$$__tz_RAM_C$$Base; +extern const uint32_t Image$$__tz_RAM_S$$Base; +extern const uint32_t Image$$__tz_DATA_FLASH_N$$Base; +extern const uint32_t Image$$__tz_DATA_FLASH_S$$Base; + + #define __tz_FLASH_N Image$$__tz_FLASH_N$$Base + #define __tz_FLASH_C Image$$__tz_FLASH_C$$Base + #define __tz_FLASH_S Image$$__tz_FLASH_S$$Base + #define __tz_RAM_N Image$$__tz_RAM_N$$Base + #define __tz_RAM_C Image$$__tz_RAM_C$$Base + #define __tz_RAM_S Image$$__tz_RAM_S$$Base + #define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base + #define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base + +/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the + * start addresses of Secure, Non-secure and Non-secure Callable regions. */ +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = &__tz_FLASH_C; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_flash = &__tz_FLASH_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = &__tz_RAM_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = &__tz_RAM_C; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ram = &__tz_RAM_S; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = &__tz_DATA_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_data_flash = &__tz_DATA_FLASH_S; + #endif + +#endif diff --git a/ra/fsp/src/r_sce/ra2/SC324_p01.prc.c b/ra/fsp/src/bsp/mcu/all/bsp_security.h similarity index 59% rename from ra/fsp/src/r_sce/ra2/SC324_p01.prc.c rename to ra/fsp/src/bsp/mcu/all/bsp_security.h index a6e3a8382..ed40b6684 100644 --- a/ra/fsp/src/r_sce/ra2/SC324_p01.prc.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_security.h @@ -18,31 +18,30 @@ * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. **********************************************************************************************************************/ -///////////////////////////////////////////////////////////////////////// -// // -// Procedure number: 01 // -// File name : SC324_p01.prc // -// State Diagram : main(FSM1) // -// Start State : main00 // -// End State : Pass :main01, Fail :stop // -// Input Data : void // -// Output Data : void // -// Return value : Pass, Fail or Resource_Conflict // -// ---------------------------------------------------------------------// -// total cycle : polling + write access + read access // -// polling : cycle // -// polling access : times // -// write access : times // -// read access : times // -///////////////////////////////////////////////////////////////////////// - -#include "hw_sce_private.h" -#include "fsp_common_api.h" - -/*******************************************************************************************************************//** - * TSIP Selftest Function1 - * @retval FSP_SUCCESS The operation completed successfully. +#ifndef BSP_SECURITY_H +#define BSP_SECURITY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables **********************************************************************************************************************/ -fsp_err_t HW_SCE_Initialization1 () { - return FSP_SUCCESS; -} + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index 4f759ed3d..08243533b 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -48,192 +48,236 @@ * Private global variables and functions **********************************************************************************************************************/ -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (3U) // This comes from the Electrical Characteristics in the hardware manual. Can be 1 us if AVCC0 >= 3.3V. Using the largest minimum in this API. -#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF5) - -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) - -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (0U) -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (1U) -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKD) -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (0U) -#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (16U) -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) -#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0xFF01FF) // 0 to 8, 16 to 23 in unit 0 -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (1U) - -#define BSP_FEATURE_BSP_FLASH_CACHE (1) -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) -#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) -#define BSP_FEATURE_BSP_OSIS_PADDING (1) -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) -#define BSP_FEATURE_BSP_RESET_TRNG (1U) -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) - -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) -#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) -#define BSP_FEATURE_CAN_MCLOCK_ONLY (1U) -#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) - -#define BSP_FEATURE_CGC_HAS_BCLK (0U) -#define BSP_FEATURE_CGC_HAS_FCLK (1U) -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) -#define BSP_FEATURE_CGC_HAS_FLWT (0U) -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) -#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) -#define BSP_FEATURE_CGC_HAS_PCLKA (0U) -#define BSP_FEATURE_CGC_HAS_PCLKB (1U) -#define BSP_FEATURE_CGC_HAS_PCLKC (0U) -#define BSP_FEATURE_CGC_HAS_PCLKD (1U) -#define BSP_FEATURE_CGC_HAS_PLL (0U) -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) -#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) -#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) -#define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) -#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) -#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) - -#define BSP_FEATURE_CRYPTO_HAS_AES (1) -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_HAS_ECC (0) -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_RSA (0) -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) - -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (4U) -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (4U) -#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) -#define BSP_FEATURE_CTSU_VERSION (1) - -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (1U) -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (1U) -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (1U) -#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) - -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (1U) -#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) -#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) - -#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU - -#define BSP_FEATURE_DWT_CYCCNT (0U) - -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x005CD30FU) // Positions of event link set registers (ELSRs) available on this MCU - -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA2A1 FlashIF uses FCLK -#define BSP_FEATURE_FLASH_LP_VERSION (3) - -#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) - -#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) - -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x7F) -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x7U) -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (1U) -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (1U) -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (1U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (2U) - -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) -#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB8F00FFU) - -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) - -#define BSP_FEATURE_IOPORT_ELC_PORTS (4) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) - -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize - -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (220U) // This information comes from the Electrical Characteristics chapter of the hardware manual. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) - -#define BSP_FEATURE_SCI_CHANNELS (0x203U) -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) - -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU - -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU - -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) -#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) - -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (3U) // This comes from the Electrical Characteristics in the hardware manual. Can be 1 us if AVCC0 >= 3.3V. Using the largest minimum in this API. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF5) + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (0U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (1U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKD) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (0U) +#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (1U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (16U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0xFF01FF) // 0 to 8, 16 to 23 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x000FFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + \ + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (1U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) + +#define BSP_FEATURE_CGC_HAS_BCLK (0U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_PCLKA (0U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (0U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (0U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (0U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // This MCU does not have PLL +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (0U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_HASH (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (4U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (4U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (1U) +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (1U) +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (1U) +#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (1U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (0) // Feature not available on this MCU + +#define BSP_FEATURE_DWT_CYCCNT (0U) + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x005CD30FU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA2A1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_VERSION (3) +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x7F) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB8F00FFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (2U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (1U) +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (1U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (4U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (220U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (10U) +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (1U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x7U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x203U) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x1U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (0) // Feature not available on this MCU +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h index 3de911579..d5f67db1d 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h @@ -33,8 +33,8 @@ **********************************************************************************************************************/ /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/ra2a1/bsp_elc.h" -#include "../../src/bsp/mcu/ra2a1/bsp_feature.h" +#include "bsp_elc.h" +#include "bsp_feature.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index ed6a3fa2b..d0970e23c 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -48,192 +48,236 @@ * Private global variables and functions **********************************************************************************************************************/ -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU -#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU - -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) - -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) -#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (14U) -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) -#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x3FF7FFF) // 0 to 14, 16 to 25 in unit 0 -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) - -#define BSP_FEATURE_BSP_FLASH_CACHE (1) -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) -#define BSP_FEATURE_BSP_HAS_SCE5 (1) -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (1U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) -#define BSP_FEATURE_BSP_OSIS_PADDING (1) -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) -#define BSP_FEATURE_BSP_RESET_TRNG (1U) -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (1U) - -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) -#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) -#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) - -#define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK -#define BSP_FEATURE_CGC_HAS_FCLK (1U) -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) -#define BSP_FEATURE_CGC_HAS_FLWT (0U) -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) -#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) -#define BSP_FEATURE_CGC_HAS_PCLKA (1U) -#define BSP_FEATURE_CGC_HAS_PCLKB (1U) -#define BSP_FEATURE_CGC_HAS_PCLKC (1U) -#define BSP_FEATURE_CGC_HAS_PCLKD (1U) -#define BSP_FEATURE_CGC_HAS_PLL (1U) -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) -#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) -#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) -#define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4M1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB -#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) -#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) - -#define BSP_FEATURE_CRYPTO_HAS_AES (1) -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC (0) -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_RSA (0) -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) - -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (5U) -#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) -#define BSP_FEATURE_CTSU_VERSION (1) - -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0U) -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) -#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) - -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) -#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) - -#define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) - -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register - -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Positions of event link set registers (ELSRs) available on this MCU - -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4M1 FlashIF uses FCLK -#define BSP_FEATURE_FLASH_LP_VERSION (3) - -#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) - -#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) - -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFF) - -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xDFFFU) -#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB9FDFFFU) - -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) - -#define BSP_FEATURE_IOPORT_ELC_PORTS (4) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382DFFFU) - -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize - -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) - -#define BSP_FEATURE_SCI_CHANNELS (0x207U) -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) - -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU - -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1U) -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1U) - -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) -#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) - -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (14U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x3FF7FFF) // 0 to 14, 16 to 25 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (1) +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (1U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + \ + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (1U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) + +#define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (0U) // This MCU does not use PLLCCR to set PLL frequency +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4M1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB +#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_HASH (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (5U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0U) +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) +#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4M1 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4M1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_VERSION (3) +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0xFF) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xDFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB9FDFFFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382DFFFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (1U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x207U) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1U) +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1U) +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (0U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h index 1a14b5c80..fc43b7bda 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h @@ -35,8 +35,8 @@ **********************************************************************************************************************/ /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/ra4m1/bsp_elc.h" -#include "../../src/bsp/mcu/ra4m1/bsp_feature.h" +#include "bsp_elc.h" +#include "bsp_feature.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index 385e9ac15..11e3c09e6 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -48,192 +48,236 @@ * Private global variables and functions **********************************************************************************************************************/ -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU -#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU - -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) - -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) -#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (14U) -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) -#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1A0670) // 4 to 6, 9, 10, 17, 19, 20 in unit 0 -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) - -#define BSP_FEATURE_BSP_FLASH_CACHE (1U) -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) -#define BSP_FEATURE_BSP_HAS_SCE5 (1) -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) -#define BSP_FEATURE_BSP_OSIS_PADDING (1) -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) -#define BSP_FEATURE_BSP_RESET_TRNG (1U) -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (1U) - -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) -#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) -#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) - -#define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK -#define BSP_FEATURE_CGC_HAS_FCLK (1U) -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) -#define BSP_FEATURE_CGC_HAS_FLWT (0U) -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) -#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) -#define BSP_FEATURE_CGC_HAS_PCLKA (1U) -#define BSP_FEATURE_CGC_HAS_PCLKB (1U) -#define BSP_FEATURE_CGC_HAS_PCLKC (1U) -#define BSP_FEATURE_CGC_HAS_PCLKD (1U) -#define BSP_FEATURE_CGC_HAS_PLL (1U) -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) -#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) -#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) -#define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB -#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) -#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) - -#define BSP_FEATURE_CRYPTO_HAS_AES (1) -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC (0) -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) -#define BSP_FEATURE_CRYPTO_HAS_HASH (0) -#define BSP_FEATURE_CRYPTO_HAS_RSA (0) -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) - -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (5U) -#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) -#define BSP_FEATURE_CTSU_VERSION (1) - -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0U) -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) -#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) - -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) -#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) - -#define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) - -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register - -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Positions of event link set registers (ELSRs) available on this MCU - -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4W1 FlashIF uses FCLK -#define BSP_FEATURE_FLASH_LP_VERSION (3) - -#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) - -#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) - -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xF) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x13F) - -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xCBDFU) -#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB97CADFU) - -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) - -#define BSP_FEATURE_IOPORT_ELC_PORTS (4) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382CADFU) - -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize - -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported -#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x4U) -#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) -#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) -#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) -#define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) - -#define BSP_FEATURE_SCI_CHANNELS (0x213U) -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) - -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU - -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0U) -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0U) - -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) -#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) - -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (1) +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100U) + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (14U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_SLOPE (-3650) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1A0670) // 4 to 6, 9, 10, 17, 19, 20 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (1U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1U) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (1) +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (1U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (3U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_OSIS_PADDING (1) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (1U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + \ + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (1U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) +#define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (1U) + +#define BSP_FEATURE_CGC_HAS_BCLK (0U) // This MCU does not have a BCLK +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (0U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (1U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (4000000U) // This MCU does have Low Voltage Mode, up to 4MHz +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000U) // This MCU does have Middle Speed Mode, up to 8MHz +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x08U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x3U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (2U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (1U) // 1 us wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (0U) // This MCU does not use PLLCCR to set PLL frequency +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (1U) // RA4W1 requires that bits 16-18 of SCKDIVCR be the same as the bits for PCKB +#define BSP_FEATURE_CGC_SODRV_MASK (0x03U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x0U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (2) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (0) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (0) +#define BSP_FEATURE_CRYPTO_HAS_HASH (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA (0) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (5U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (0) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0U) +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) +#define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (1U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (4U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA4W1 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007D3FFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0xFFFU) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (10) +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x800U) +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (8) +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x400U) +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (1) +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC ((fsp_priv_clock_t) FSP_PRIV_CLOCK_FCLK) // RA4W1 FlashIF uses FCLK +#define BSP_FEATURE_FLASH_LP_VERSION (3) +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0xF) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x13F) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xCBDFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB97CADFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382CADFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // 1.65V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_4_29V) // 4.29V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_84V) // 3.84V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (300U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (1U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0U) +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (1U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (13U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (650U) // This information comes from the Electrical Characteristics chapter of the hardware manual. +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0xFFFFU) // Middle speed mode not supported +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x213U) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0) // Feature not available on this MCU + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0U) +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0U) +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (8U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h index b6af370b9..f70eec58b 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h @@ -35,8 +35,8 @@ **********************************************************************************************************************/ /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/ra4w1/bsp_elc.h" -#include "../../src/bsp/mcu/ra4w1/bsp_feature.h" +#include "bsp_elc.h" +#include "bsp_feature.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index 1a3c995c1..dd1cbb0a7 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -52,185 +52,236 @@ * Private global variables and functions **********************************************************************************************************************/ -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. -#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) - -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU - -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) -#define BSP_FEATURE_ADC_HAS_PGA (1U) -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_SLOPE (4000) -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1700EF) // 0 to 3, 5 to 7, 16 to 18, and 20 in unit 0 and 0 to 2, 5 to 7, 16 to 17 in unit 1 -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x300E7) -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) - -#define BSP_FEATURE_BSP_FLASH_CACHE (1) -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) -#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) -#define BSP_FEATURE_BSP_OSIS_PADDING (0U) -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) -#define BSP_FEATURE_BSP_RESET_TRNG (0U) -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) - -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) -#define BSP_FEATURE_CAN_CLOCK (0U) -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) -#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) - -#define BSP_FEATURE_CGC_HAS_BCLK (1U) -#define BSP_FEATURE_CGC_HAS_FCLK (1U) -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) -#define BSP_FEATURE_CGC_HAS_FLWT (1U) -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) -#define BSP_FEATURE_CGC_HAS_PCLKA (1U) -#define BSP_FEATURE_CGC_HAS_PCLKB (1U) -#define BSP_FEATURE_CGC_HAS_PCLKC (1U) -#define BSP_FEATURE_CGC_HAS_PCLKD (1U) -#define BSP_FEATURE_CGC_HAS_PLL (1U) -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) ///< This MCU does have Low Speed Mode, up to 1MHz -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) ///< This MCU does not have Low Voltage Mode -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) ///< This MCU does not have Middle Speed Mode -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) -#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) -#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) -#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) -#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) - -#define BSP_FEATURE_CRYPTO_HAS_AES (1) -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_RSA (1) -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) - -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (2U) -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (2U) -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) -#define BSP_FEATURE_CTSU_VERSION (1) - -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) -#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) - -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) - -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register - -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU - -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU -#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) -#define BSP_FEATURE_FLASH_HP_VERSION (40U) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU - -#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) -#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1FFF) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFF) - -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) -#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) - -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) - -#define BSP_FEATURE_IOPORT_ELC_PORTS (4) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{1, 31}, {2, 5}} -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00133FFFU) -#define BSP_FEATURE_LPM_DPSIER_MASK (0x051F3FFFU) -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) - -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize - -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) - -#define BSP_FEATURE_SCI_CHANNELS (0x31FU) -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x31FU) -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) - -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x3U) - -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU - -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) -#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) - -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (1U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1700EF) // 0 to 3, 5 to 7, 16 to 18, and 20 in unit 0 and 0 to 2, 5 to 7, 16 to 17 in unit 1 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x300E7) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (800000000U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + \ + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) ///< This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) ///< This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) ///< This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (2U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (2U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M1 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0) // Feature not available on this MCU +#define BSP_FEATURE_ETHER_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x1FFF) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFF) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{1, 31}, {2, 5}} +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00133FFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x051F3FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (1U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x31FU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x31FU) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (1U) // 2 (2^1) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h index 161d54a09..de79681d1 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h @@ -35,8 +35,8 @@ **********************************************************************************************************************/ /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/ra6m1/bsp_elc.h" -#include "../../src/bsp/mcu/ra6m1/bsp_feature.h" +#include "bsp_elc.h" +#include "bsp_feature.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index 217c2b3e8..e040345a2 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -52,187 +52,236 @@ * Private global variables and functions **********************************************************************************************************************/ -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. -#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) - -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU - -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) -#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_SLOPE (4000) -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F00FF) // 0 to 7, 16 to 20 in unit 0 and 0 to 2, 5 to 7, 16 to 18 in unit 1 -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x700E7) -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) - -#define BSP_FEATURE_BSP_FLASH_CACHE (1) -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) -#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) -#define BSP_FEATURE_BSP_OSIS_PADDING (0U) -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) -#define BSP_FEATURE_BSP_RESET_TRNG (0U) -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) - -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) -#define BSP_FEATURE_CAN_CLOCK (0U) -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) -#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) - -#define BSP_FEATURE_CGC_HAS_BCLK (1U) -#define BSP_FEATURE_CGC_HAS_FCLK (1U) -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) -#define BSP_FEATURE_CGC_HAS_FLWT (1U) -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) -#define BSP_FEATURE_CGC_HAS_PCLKA (1U) -#define BSP_FEATURE_CGC_HAS_PCLKB (1U) -#define BSP_FEATURE_CGC_HAS_PCLKC (1U) -#define BSP_FEATURE_CGC_HAS_PCLKD (1U) -#define BSP_FEATURE_CGC_HAS_PLL (1U) -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) -#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) -#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) -#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) -#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) - -#define BSP_FEATURE_CRYPTO_HAS_AES (1) -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_RSA (1) -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) - -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) -#define BSP_FEATURE_CTSU_VERSION (1) - -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) -#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) - -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) - -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M2 has Data Watchpoint Cycle Count Register - -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU - -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) - -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) -#define BSP_FEATURE_FLASH_HP_VERSION (40U) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU - -#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) - -#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) - -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFF) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFF) - -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) -#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) - -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) - -#define BSP_FEATURE_IOPORT_ELC_PORTS (4) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {1, 31}, {2, 5}} -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00133FFFU) -#define BSP_FEATURE_LPM_DPSIER_MASK (0x051F3FFFU) -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) - -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize - -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) - -#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) - -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x3U) - -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU - -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) -#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) - -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0) // Feature not available on this MCU +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F00FF) // 0 to 7, 16 to 20 in unit 0 and 0 to 2, 5 to 7, 16 to 18 in unit 1 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x700E7) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (800000000U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + \ + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M2 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFF) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {1, 31}, {2, 5}} +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00133FFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x051F3FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (1U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabilize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (1U) // 2 (2^1) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x90000000U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h index 4e45c3228..d0f14bb1f 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h @@ -35,8 +35,8 @@ **********************************************************************************************************************/ /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/ra6m2/bsp_elc.h" -#include "../../src/bsp/mcu/ra6m2/bsp_feature.h" +#include "bsp_elc.h" +#include "bsp_feature.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index e1d5bfe6c..72dac32f3 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -52,187 +52,236 @@ * Private global variables and functions **********************************************************************************************************************/ -#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. -#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) - -#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU -#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU - -#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) -#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) -#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) -#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) -#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) -#define BSP_FEATURE_ADC_HAS_PGA (1U) -#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) -#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) -#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) -#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) -#define BSP_FEATURE_ADC_TSN_SLOPE (4000) -#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F00FF) // 0 to 7, 16 to 20 in unit 0 and 0 to 3, 5 to 7, 16 to 19 in unit 1 -#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0xF00EF) -#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) -#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) - -#define BSP_FEATURE_BSP_FLASH_CACHE (1) -#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) -#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) -#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) -#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) -#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) -#define BSP_FEATURE_BSP_OSIS_PADDING (0U) -#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) -#define BSP_FEATURE_BSP_RESET_TRNG (0U) -#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) - -#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) -#define BSP_FEATURE_CAN_CLOCK (0U) -#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) -#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) - -#define BSP_FEATURE_CGC_HAS_BCLK (1U) -#define BSP_FEATURE_CGC_HAS_FCLK (1U) -#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) -#define BSP_FEATURE_CGC_HAS_FLWT (1U) -#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) -#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) -#define BSP_FEATURE_CGC_HAS_PCLKA (1U) -#define BSP_FEATURE_CGC_HAS_PCLKB (1U) -#define BSP_FEATURE_CGC_HAS_PCLKC (1U) -#define BSP_FEATURE_CGC_HAS_PCLKD (1U) -#define BSP_FEATURE_CGC_HAS_PLL (1U) -#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) -#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) -#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) -#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) -#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz -#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode -#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode -#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) -#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) -#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) -#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) -#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP -#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) -#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) -#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) -#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) - -#define BSP_FEATURE_CRYPTO_HAS_AES (1) -#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC (1) -#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) -#define BSP_FEATURE_CRYPTO_HAS_HASH (1) -#define BSP_FEATURE_CRYPTO_HAS_RSA (1) -#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) - -#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) -#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) -#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) -#define BSP_FEATURE_CTSU_VERSION (1) - -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU - -#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) -#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) -#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) -#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) - -#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) - -#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M3 has Data Watchpoint Cycle Count Register - -#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU - -#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) -#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) - -#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) -#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) -#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) -#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) -#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) -#define BSP_FEATURE_FLASH_HP_VERSION (40U) -#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU -#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU - -#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) - -#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) - -#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFF) -#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFF) - -#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) -#define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) - -#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) - -#define BSP_FEATURE_IOPORT_ELC_PORTS (4) -#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) - -#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, {2, 5}} -#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) -#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU) -#define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU) -#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) -#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) -#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) - -#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) -#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V -#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V -#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V -#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize - -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU -#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU - -#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) - -#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) -#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) -#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) - -#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) -#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) -#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x3U) - -#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU -#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU - -#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) -#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) -#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) -#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) - -#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) -#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (1U) // This comes from the Electrical Characteristics in the hardware manual. Rounding up to nearest microsecond. +#define BSP_FEATURE_ACMPHS_VREF (ACMPHS_REFERENCE_IVREF2) + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (1U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x1F00FF) // 0 to 7, 16 to 20 in unit 0 and 0 to 3, 5 to 7, 16 to 19 in unit 1 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0xF00EF) +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (1U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (0) +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) +#define BSP_FEATURE_BSP_HAS_SP_MON (1U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x407FB19C) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00FFFFFFU) +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (7U) // Largest channel number associated with lower MSTP bit for GPT on this MCU. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (0U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (60000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (40000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (800000000U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x14) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER ((*(uint32_t *) BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION) + \ + BSP_FEATURE_BSP_UNIQUE_ID_OFFSET) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M3 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x40100000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (1) +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (1) + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFF) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFF) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, {2, 5}} +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (1U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (1U) // 2 (2^1) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x90000000U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (3U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (0U) #endif diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h index b9899ea04..e4e6b94ef 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h @@ -35,8 +35,8 @@ **********************************************************************************************************************/ /* BSP MCU Specific Includes. */ -#include "../../src/bsp/mcu/ra6m3/bsp_elc.h" -#include "../../src/bsp/mcu/ra6m3/bsp_feature.h" +#include "bsp_elc.h" +#include "bsp_feature.h" /*********************************************************************************************************************** * Macro definitions diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h new file mode 100644 index 000000000..37cfbe4df --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h @@ -0,0 +1,310 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/******************************************************************************************************************* + * @addtogroup BSP_MCU_RA6M4 + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra6m4 +{ + ELC_EVENT_NONE = (0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC transfer end 0 + ELC_EVENT_DMAC1_INT = (0x021), // DMAC transfer end 1 + ELC_EVENT_DMAC2_INT = (0x022), // DMAC transfer end 2 + ELC_EVENT_DMAC3_INT = (0x023), // DMAC transfer end 3 + ELC_EVENT_DMAC4_INT = (0x024), // DMAC transfer end 4 + ELC_EVENT_DMAC5_INT = (0x025), // DMAC transfer end 5 + ELC_EVENT_DMAC6_INT = (0x026), // DMAC transfer end 6 + ELC_EVENT_DMAC7_INT = (0x027), // DMAC transfer end 7 + ELC_EVENT_DTC_TRANSFER = (0x028), // DTC transfer + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Slave address match + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CAN0_ERROR = (0x0A1), // Error interrupt + ELC_EVENT_CAN0_FIFO_RX = (0x0A2), // Receive FIFO interrupt + ELC_EVENT_CAN0_FIFO_TX = (0x0A3), // Transmit FIFO interrupt + ELC_EVENT_CAN0_MAILBOX_RX = (0x0A4), // Reception complete interrupt + ELC_EVENT_CAN0_MAILBOX_TX = (0x0A5), // Transmission complete interrupt + ELC_EVENT_CAN1_ERROR = (0x0A6), // Error interrupt + ELC_EVENT_CAN1_FIFO_RX = (0x0A7), // Receive FIFO interrupt + ELC_EVENT_CAN1_FIFO_TX = (0x0A8), // Transmit FIFO interrupt + ELC_EVENT_CAN1_MAILBOX_RX = (0x0A9), // Reception complete interrupt + ELC_EVENT_CAN1_MAILBOX_TX = (0x0AA), // Transmission complete interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable interrupt B + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable interrupt C + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable interrupt D + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_ADC0_SCAN_END = (0x160), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // A/D scan end interrupt + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (0x186), // Received data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Received data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Received data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Received data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Received data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Received data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Received data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Received data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Received data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA6M4) */ + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h new file mode 100644 index 000000000..3f5d731b5 --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -0,0 +1,269 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (19999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x01U) +#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x02U) +#else + #define CGC_MAINCLOCK_DRIVE (0x03U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x33FF) // 0 to 9, 12, 13 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F0007) // 0 to 2, 16 to 22 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) +#define BSP_FEATURE_BSP_HAS_SP_MON (0U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M4 there are specific registers for configuring the USB clock. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFU) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) +#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (1U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + +#endif diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h new file mode 100644 index 000000000..494d2161e --- /dev/null +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h @@ -0,0 +1,40 @@ +/* ${REA_DISCLAIMER_PLACEHOLDER} */ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA6M4 RA6M4 + * @includedoc config_bsp_ra6m4_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA6M4) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/ra/fsp/src/r_adc/r_adc.c b/ra/fsp/src/r_adc/r_adc.c index 0d239692b..eab37b810 100644 --- a/ra/fsp/src/r_adc/r_adc.c +++ b/ra/fsp/src/r_adc/r_adc.c @@ -78,8 +78,6 @@ #define ADC_PRV_TSCR_TSN_ENABLE (R_TSN_CTRL_TSCR_TSEN_Msk | R_TSN_CTRL_TSCR_TSOE_Msk) -#define ADC_PRV_TSN_CALIBRATION_TSCDR_BITS (0x00000FFFU) - /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -94,6 +92,12 @@ typedef enum e_adc_elc_trigger ADC_ELC_TRIGGER_DISABLED = (0x3FU) } adc_elc_trigger_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile adc_prv_ns_callback)(adc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile adc_prv_ns_callback)(adc_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private global variables and functions **********************************************************************************************************************/ @@ -179,6 +183,7 @@ const adc_api_t g_adc_on_adc = .versionGet = R_ADC_VersionGet, .calibrate = R_ADC_Calibrate, .offsetSet = R_ADC_OffsetSet, + .callbackSet = R_ADC_CallbackSet, }; /*******************************************************************************************************************//** @@ -236,6 +241,15 @@ fsp_err_t R_ADC_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg) /* Save configurations. */ p_instance_ctrl->p_cfg = p_cfg; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_instance_ctrl->callback_is_secure = true; +#endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + /* Calculate the register base address. */ uint32_t address_gap = (uint32_t) R_ADC1 - (uint32_t) R_ADC0; p_instance_ctrl->p_reg = (R_ADC0_Type *) ((uint32_t) R_ADC0 + (address_gap * p_cfg->unit)); @@ -299,6 +313,42 @@ fsp_err_t R_ADC_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_extend) return err; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements adc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_ADC_CallbackSet (adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void const * const p_context, + adc_callback_args_t * const p_callback_memory) +{ + adc_instance_ctrl_t * p_ctrl = (adc_instance_ctrl_t *) p_api_ctrl; + +#if (ADC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(ADC_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Starts a software scan or enables the hardware trigger for a scan depending on how the triggers were configured in * the R_ADC_Open call. If the unit was configured for ELC or external hardware triggering, then this function allows @@ -575,14 +625,14 @@ fsp_err_t R_ADC_InfoGet (adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info) p_adc_info->calibration_data = UINT32_MAX; /* If calibration register is available, retrieve it from the MCU */ -#if BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE - #if BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE +#if 1U == BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE + #if 1U == BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE /* Read into memory. */ uint32_t data = R_TSN_CAL->TSCDR; - /* Read the calibration data from ROM and AND it to mask off 12bit of calibration data. */ - p_adc_info->calibration_data = (data & ADC_PRV_TSN_CALIBRATION_TSCDR_BITS); + /* Read the temperature calibration data from ROM. */ + p_adc_info->calibration_data = (data & BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK); #else /* Read into memory to prevent compiler warning when performing "|" on volatile register data. */ @@ -1406,16 +1456,30 @@ static void r_adc_scan_end_common_isr (adc_event_t event) adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet()); adc_callback_args_t args; + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + adc_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + /* Clear the BSP IRQ Flag */ R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); - args.event = event; + p_args->event = event; #if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE /* Store the correct event into the callback argument */ if (ADC_ADICR_CALIBRATION_INTERRUPT_DISABLED != p_instance_ctrl->p_reg->ADICR) { - args.event = ADC_EVENT_CALIBRATION_COMPLETE; + p_args->event = ADC_EVENT_CALIBRATION_COMPLETE; /* Restore the interrupt source to disable interrupts after calibration is done. */ p_instance_ctrl->p_reg->ADICR = 0U; @@ -1423,18 +1487,43 @@ static void r_adc_scan_end_common_isr (adc_event_t event) #endif /* Store the unit number into the callback argument */ - args.unit = p_instance_ctrl->p_cfg->unit; + p_args->unit = p_instance_ctrl->p_cfg->unit; /* Initialize the channel to 0. It is not used in this implementation. */ - args.channel = ADC_CHANNEL_0; + p_args->channel = ADC_CHANNEL_0; /* Populate the context field. */ - args.p_context = p_instance_ctrl->p_cfg->p_context; + p_args->p_context = p_instance_ctrl->p_context; /* If a callback was provided, call it with the argument */ - if (NULL != p_instance_ctrl->p_cfg->p_callback) + if (NULL != p_instance_ctrl->p_callback) + { +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_instance_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + adc_prv_ns_callback p_callback = (adc_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + } + + if (NULL != p_instance_ctrl->p_callback_memory) { - p_instance_ctrl->p_cfg->p_callback(&args); + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; } /* Restore context if RTOS is used */ diff --git a/ra/fsp/src/r_agt/r_agt.c b/ra/fsp/src/r_agt/r_agt.c index 353bd0247..a7862559c 100644 --- a/ra/fsp/src/r_agt/r_agt.c +++ b/ra/fsp/src/r_agt/r_agt.c @@ -30,8 +30,6 @@ /** "AGT" in ASCII, used to determine if channel is open. */ #define AGT_OPEN (0x00414754ULL) -#define AGT_PRV_VALID_CHANNEL_MASK (0x3U) - #define AGT_COMPARE_MATCH_A_OUTPUT (0x03U) ///< Enabling AGTOAn pin #define AGT_COMPARE_MATCH_B_OUTPUT (0x30U) ///< Enabling AGTOBn pin @@ -57,6 +55,11 @@ /********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile agt_prv_ns_callback)(timer_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile agt_prv_ns_callback)(timer_callback_args_t * p_args); +#endif /*********************************************************************************************************************** * Private function prototypes @@ -111,6 +114,7 @@ const timer_api_t g_timer_on_agt = .dutyCycleSet = R_AGT_DutyCycleSet, .infoGet = R_AGT_InfoGet, .statusGet = R_AGT_StatusGet, + .callbackSet = R_AGT_CallbackSet, .close = R_AGT_Close, .versionGet = R_AGT_VersionGet }; @@ -178,6 +182,17 @@ fsp_err_t R_AGT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_c R_BSP_IrqCfgEnable(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl); } + /* Set callback and context pointers */ + +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_instance_ctrl->callback_is_secure = true; +#endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + p_instance_ctrl->open = AGT_OPEN; /* All done. */ @@ -474,6 +489,58 @@ fsp_err_t R_AGT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_AGT_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + agt_instance_ctrl_t * p_ctrl = (agt_instance_ctrl_t *) p_api_ctrl; + +#if AGT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(AGT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if AGT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Stops counter, disables interrupts, disables output pins, and clears internal driver data. Implements * @ref timer_api_t::close. @@ -572,7 +639,7 @@ static fsp_err_t r_agt_open_param_checking (agt_instance_ctrl_t * p_instance_ctr FSP_ASSERT(p_cfg->period_counts <= AGT_MAX_PERIOD); /* Validate channel number. */ - FSP_ERROR_RETURN(((1U << p_cfg->channel) & AGT_PRV_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(((1U << p_cfg->channel) & BSP_FEATURE_AGT_VALID_CHANNEL_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); /* AGT_CLOCK_AGT0_UNDERFLOW is not allowed on AGT channel 0. */ agt_extended_cfg_t const * p_extend = (agt_extended_cfg_t const *) p_cfg->p_extend; @@ -871,21 +938,36 @@ void agt_int_isr (void) } /* Invoke the callback function if it is set. */ - if (NULL != p_instance_ctrl->p_cfg->p_callback) + if (NULL != p_instance_ctrl->p_callback) { /* Setup parameters for the user-supplied callback function. */ timer_callback_args_t callback_args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + timer_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &callback_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + callback_args = *p_args; + } + if (agtcr & R_AGT0_AGTCR_TUNDF_Msk) { - callback_args.event = TIMER_EVENT_CYCLE_END; + p_args->event = TIMER_EVENT_CYCLE_END; } #if AGT_CFG_INPUT_SUPPORT_ENABLE else { - callback_args.event = TIMER_EVENT_CAPTURE_A; + p_args->event = TIMER_EVENT_CAPTURE_A; uint32_t reload_value = p_instance_ctrl->period - 1U; - callback_args.capture = reload_value - p_instance_ctrl->p_reg->AGT; + p_args->capture = reload_value - p_instance_ctrl->p_reg->AGT; /* The AGT counter is not reset in pulse width measurement mode. Reset it by software. Note that this * will restart the counter if a new capture has already started. Application writers must ensure that @@ -898,13 +980,39 @@ void agt_int_isr (void) { /* Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1 * Reference section 25.4.5 of the RA6M3 manual R01UH0886EJ0100. */ - callback_args.capture++; + p_args->capture++; } } #endif - callback_args.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&callback_args); + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_instance_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + agt_prv_ns_callback p_callback = (agt_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = callback_args; + } } /* Clear flags in AGTCR. */ diff --git a/ra/fsp/src/r_cac/r_cac.c b/ra/fsp/src/r_cac/r_cac.c index c095f9a34..29affd41b 100644 --- a/ra/fsp/src/r_cac/r_cac.c +++ b/ra/fsp/src/r_cac/r_cac.c @@ -79,6 +79,11 @@ /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile cac_prv_ns_callback)(cac_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile cac_prv_ns_callback)(cac_callback_args_t * p_args); +#endif /*********************************************************************************************************************** * Private global variables and functions @@ -115,6 +120,7 @@ const cac_api_t g_cac_on_cac = .startMeasurement = R_CAC_StartMeasurement, .stopMeasurement = R_CAC_StopMeasurement, .read = R_CAC_Read, + .callbackSet = R_CAC_CallbackSet, .close = R_CAC_Close, .versionGet = R_CAC_VersionGet }; @@ -155,6 +161,14 @@ fsp_err_t R_CAC_Open (cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg) p_instance_ctrl->p_cfg = p_cfg; + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->callback_is_secure = true; +#endif + /* Configure the CAC per the configuration. */ r_cac_hw_configure(p_instance_ctrl); @@ -242,6 +256,52 @@ fsp_err_t R_CAC_Read (cac_ctrl_t * const p_ctrl, uint16_t * const p_counter) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref cac_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CAC_CallbackSet (cac_ctrl_t * const p_ctrl, + void ( * p_callback)(cac_callback_args_t *), + void const * const p_context, + cac_callback_args_t * const p_callback_memory) +{ + cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) p_ctrl; + +#if CAC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CAC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_instance_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CAC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + cac_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_instance_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), + FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Release any resources that were allocated by the Open() or any subsequent CAC operations. * @@ -318,7 +378,7 @@ static void r_cac_hw_configure (cac_instance_ctrl_t * const p_instance_ctrl) R_BSP_MODULE_START(FSP_IP_CAC, 0); /* Disable measurements. */ - R_CAC->CACR0 = 0U; + R_CAC->CACR0 = 0; /* Read CFME bit to confirm the bit value has changed. See section 10.2.1 CAC Control Register 0 of the RA6M3 * manual R01UH0886EJ0100. */ @@ -391,20 +451,63 @@ static void r_cac_hw_configure (cac_instance_ctrl_t * const p_instance_ctrl) **********************************************************************************************************************/ static void r_cac_isr_handler (cac_event_t event, uint32_t clear_mask) { - IRQn_Type irq = R_FSP_CurrentIrqGet(); - cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + IRQn_Type irq = R_FSP_CurrentIrqGet(); + volatile cac_instance_ctrl_t * p_instance_ctrl = (cac_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - if (NULL != p_instance_ctrl->p_cfg->p_callback) + if (NULL != p_instance_ctrl->p_callback) { - /* Call the user defined callback. */ - cac_callback_args_t cb_data; - cb_data.event = event; - cb_data.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&cb_data); + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + cac_callback_args_t args; + cac_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_instance_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_instance_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + cac_prv_ns_callback p_callback = (cac_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } } /* Clear the status flag. */ R_CAC->CAICR |= (uint8_t) clear_mask; + + /* Depending on MPU and cache settings, the register may need to be read back to ensure the write happens before + * clearing the IRQ in the ICU. */ + R_CAC->CAICR; + R_BSP_IrqStatusClear(irq); } diff --git a/ra/fsp/src/r_can/r_can.c b/ra/fsp/src/r_can/r_can.c index 9bda7bf57..ca4559aa7 100644 --- a/ra/fsp/src/r_can/r_can.c +++ b/ra/fsp/src/r_can/r_can.c @@ -102,9 +102,16 @@ typedef union } int_status_b; } can_error_interrrupt_status_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile can_prv_ns_callback)(can_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile can_prv_ns_callback)(can_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ +static void r_can_call_callback(can_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args); static void r_can_switch_to_operation_mode(can_instance_ctrl_t * p_ctrl, can_operation_mode_t canm_mode_setting); static void r_can_mode_transition(can_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode, @@ -143,6 +150,7 @@ const can_api_t g_can_on_can = .write = R_CAN_Write, .modeTransition = R_CAN_ModeTransition, .infoGet = R_CAN_InfoGet, + .callbackSet = R_CAN_CallbackSet, .versionGet = R_CAN_VersionGet }; @@ -275,6 +283,15 @@ fsp_err_t R_CAN_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p_c /* Initialize the control block */ p_ctrl->p_cfg = p_cfg; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif + + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + /* Set the clock source to the user configured source. */ p_ctrl->clock_source = extended_cfg->clock_source; @@ -578,6 +595,51 @@ fsp_err_t R_CAN_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_inf return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref can_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_CAN_CallbackSet (can_ctrl_t * const p_api_ctrl, + void ( * p_callback)(can_callback_args_t *), + void const * const p_context, + can_callback_args_t * const p_callback_memory) +{ + can_instance_ctrl_t * p_ctrl = (can_instance_ctrl_t *) p_api_ctrl; + +#if CAN_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CAN_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if CAN_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + can_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Get CAN module code and API versions. * @retval FSP_SUCCESS Operation succeeded. @@ -606,6 +668,61 @@ fsp_err_t R_CAN_VersionGet (fsp_version_t * const p_version) * Private Functions **********************************************************************************************************************/ +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to CAN instance control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void r_can_call_callback (can_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args) +{ + can_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + can_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + can_prv_ns_callback p_callback = (can_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * Error ISR. * @@ -646,9 +763,9 @@ void can_error_isr (void) args.p_frame = NULL; args.channel = p_ctrl->p_cfg->channel; - args.p_context = p_ctrl->p_cfg->p_context; + args.p_context = p_ctrl->p_context; args.mailbox = mailbox; - p_ctrl->p_cfg->p_callback(&args); + r_can_call_callback(p_ctrl, &args); /* Check for mailboxes with data loss due to overrun, * if true, fire this interrupt again. @@ -739,8 +856,8 @@ void can_mailbox_rx_isr (void) args.mailbox = mailbox; args.channel = p_ctrl->p_cfg->channel; - args.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&args); + args.p_context = p_ctrl->p_context; + r_can_call_callback(p_ctrl, &args); /* Check for mailboxes with receive data, if true, fire this interrupt again */ if ((p_ctrl->p_reg->STR_b.NDST)) @@ -792,9 +909,9 @@ void can_mailbox_tx_isr (void) /* Set event argument to transmit complete. */ args.event = CAN_EVENT_TX_COMPLETE; args.channel = p_ctrl->p_cfg->channel; - args.p_context = p_ctrl->p_cfg->p_context; + args.p_context = p_ctrl->p_context; args.p_frame = NULL; - p_ctrl->p_cfg->p_callback(&args); + r_can_call_callback(p_ctrl, &args); /* Check for other mailboxes with pending transmit complete flags. */ if ((p_ctrl->p_reg->STR_b.SDST)) diff --git a/ra/fsp/src/r_cgc/r_cgc.c b/ra/fsp/src/r_cgc/r_cgc.c index 0fbe5cbe9..d409f080f 100644 --- a/ra/fsp/src/r_cgc/r_cgc.c +++ b/ra/fsp/src/r_cgc/r_cgc.c @@ -28,6 +28,12 @@ * Macro definitions **********************************************************************************************************************/ +#if BSP_TZ_NONSECURE_BUILD + #if defined(BSP_CFG_CLOCKS_SECURE) && BSP_CFG_CLOCKS_SECURE + #error "The CGC registers are only accessible in the TrustZone Secure Project." + #endif +#endif + /* "CGC" in ASCII, used to determine if the module is open. */ #define CGC_OPEN (0x00434743U) @@ -54,7 +60,11 @@ #define CGC_PRV_CKOCR_CKODIV_BIT (4) #if BSP_PRV_PLL_SUPPORTED - #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_PLL + 1U) + #if BSP_PRV_PLL2_SUPPORTED + #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_PLL2 + 1U) + #else + #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_PLL + 1U) + #endif #else #define CGC_PRV_NUM_CLOCKS ((uint8_t) CGC_CLOCK_SUBCLOCK + 1U) #endif @@ -68,6 +78,7 @@ #define CGC_PRV_MOSCCR ((uint8_t *) 0x4001E032U) #define CGC_PRV_SOSCCR ((uint8_t *) 0x4001E480U) #define CGC_PRV_PLLCR ((uint8_t *) 0x4001E02AU) +#define CGC_PRV_PLL2CR ((uint8_t *) 0x4001E04AU) /* The closest supported power mode to use when exiting low speed or low voltage mode. */ #if BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ > 0U @@ -84,7 +95,6 @@ /* Specifications for PLL on MCUs with PLLCCR. */ #define CGC_PRV_PLLCCR_PLL_MIN_HZ (120000000U) -#define CGC_PRV_PLLCCR_PLL_MAX_HZ (240000000U) /* Specifications for PLL on MCUs with PLLCCR2. */ #define CGC_PRV_PLLCCR2_PLL_MIN_HZ (24000000U) @@ -110,6 +120,12 @@ typedef enum e_cgc_prv_change CGC_PRV_CHANGE_LPM_CGC = 1, } cgc_prv_change_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile cgc_prv_ns_callback)(cgc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile cgc_prv_ns_callback)(cgc_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -138,14 +154,27 @@ static fsp_err_t r_cgc_pll_parameter_check(cgc_pll_cfg_t const * const p_pll_cfg #endif #endif -#if BSP_PRV_PLL_SUPPORTED -static uint32_t r_cgc_pllccr_calculate(cgc_pll_cfg_t const * const p_pll_cfg); +#if BSP_PRV_PLL_SUPPORTED || BSP_PRV_PLL2_SUPPORTED +static uint32_t r_cgc_pllccr_calculate(cgc_pll_cfg_t const * const p_pll_cfg); + + #if BSP_PRV_PLL_SUPPORTED + static inline cgc_clock_t r_cgc_pll_clocksource_get(void); -static fsp_err_t r_cgc_pll_hz_calculate(cgc_pll_cfg_t const * const p_pll_cfg, uint32_t * const p_pll_hz); -static void r_cgc_pll_cfg(uint32_t pll_hz, uint32_t pllccr); -static fsp_err_t r_cgc_pllccr_pll_hz_calculate(cgc_pll_cfg_t const * const p_pll_cfg, - uint32_t * const p_pll_hz, - uint32_t * const p_pllccr); + + #endif + + #if BSP_PRV_PLL2_SUPPORTED && CGC_CFG_PARAM_CHECKING_ENABLE + +static inline cgc_clock_t r_cgc_pll2_clocksource_get(void); + + #endif + +static fsp_err_t r_cgc_pll_hz_calculate(cgc_pll_cfg_t const * const p_pll_cfg, uint32_t * const p_pll_hz); +static void r_cgc_pll_cfg(uint32_t pll_hz, uint32_t pllccr); +static fsp_err_t r_cgc_pllccr_pll_hz_calculate(cgc_pll_cfg_t const * const p_pll_cfg, + uint32_t * const p_pll_hz, + uint32_t * const p_pllccr, + cgc_clock_t pll); #endif @@ -179,6 +208,9 @@ static uint8_t volatile * const gp_cgc_clock_stp_registers[CGC_PRV_NUM_CLOCKS] = #if BSP_PRV_PLL_SUPPORTED [CGC_CLOCK_PLL] = CGC_PRV_PLLCR, #endif +#if BSP_PRV_PLL2_SUPPORTED + [CGC_CLOCK_PLL2] = CGC_PRV_PLL2CR, +#endif }; /* How long of a software delay is required after starting each clock before activating it as the system clock. */ @@ -192,6 +224,9 @@ static const uint8_t g_cgc_software_wait_us[CGC_PRV_NUM_CLOCKS] = #if BSP_PRV_PLL_SUPPORTED [CGC_CLOCK_PLL] = 0U, // PLL has a stabilization wait flag #endif +#if BSP_PRV_PLL2_SUPPORTED + [CGC_CLOCK_PLL2] = 0U, // PLL2 has a stabilization wait flag +#endif }; /* Create a mask of the uppermost bits of all valid clock dividers in SCKDIVCR. */ @@ -215,6 +250,7 @@ const cgc_api_t g_cgc_on_cgc = .oscStopDetectEnable = R_CGC_OscStopDetectEnable, .oscStopDetectDisable = R_CGC_OscStopDetectDisable, .oscStopStatusClear = R_CGC_OscStopStatusClear, + .callbackSet = R_CGC_CallbackSet, .close = R_CGC_Close, .versionGet = R_CGC_VersionGet, }; @@ -248,10 +284,16 @@ fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) FSP_ERROR_RETURN(CGC_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); #endif +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->callback_is_secure = true; +#endif + /* Store the control structure in a private global variable so the oscillation stop detection function can be * called from the NMI callback. */ - gp_cgc_ctrl = p_instance_ctrl; - p_instance_ctrl->p_callback = p_cfg->p_callback; + gp_cgc_ctrl = p_instance_ctrl; + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; /* Mark the module as open so other APIs can be used. */ p_instance_ctrl->open = CGC_OPEN; @@ -263,7 +305,7 @@ fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) * Reconfigures all main system clocks. This API can be used for any of the following purposes: * - start or stop clocks * - change the system clock source - * - configure the PLL multiplication and division ratios when starting the PLL + * - configure the PLL/PLL2 multiplication and division ratios when starting the PLL * - change the system dividers * * If the requested system clock source has a stabilization flag, this function blocks waiting for the stabilization @@ -281,7 +323,7 @@ fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) * - RA2A1: see footnotes of Table 9.2 "Clock generation circuit specifications for the internal clocks" in the RA2A1 * manual R01UH0888EJ0100 * - * Do not attempt to stop the requested clock source or the source of the PLL if the PLL will be running after this + * Do not attempt to stop the requested clock source or the source of a PLL if the PLL will be running after this * operation completes. * * Implements @ref cgc_api_t::clocksCfg. @@ -291,6 +333,7 @@ fsp_err_t R_CGC_Open (cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg) * * @retval FSP_SUCCESS Clock configuration applied successfully. * @retval FSP_ERR_ASSERTION Invalid input argument. + * @retval FSP_ERR_UNSUPPORTED PLL/PLL2 is not available on this MCU. * @retval FSP_ERR_NOT_OPEN Module is not open. * @retval FSP_ERR_IN_USE Attempt to stop the current system clock or the PLL source clock. * @retval FSP_ERR_CLOCK_ACTIVE PLL configuration cannot be changed while PLL is running. @@ -328,7 +371,11 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c options[CGC_CLOCK_SUBCLOCK] = CGC_CLOCK_CHANGE_NONE; #if CGC_CFG_PARAM_CHECKING_ENABLE #if !BSP_PRV_PLL_SUPPORTED - FSP_ASSERT(CGC_CLOCK_CHANGE_START != p_clock_cfg->pll_state); + FSP_ERROR_RETURN(CGC_CLOCK_CHANGE_START != p_clock_cfg->pll_state, FSP_ERR_UNSUPPORTED); + #endif + + #if !BSP_PRV_PLL2_SUPPORTED + FSP_ERROR_RETURN(CGC_CLOCK_CHANGE_START != p_clock_cfg->pll2_state, FSP_ERR_UNSUPPORTED); #endif #if BSP_CFG_USE_LOW_VOLTAGE_MODE @@ -354,7 +401,7 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c uint32_t pllccr = 0U; if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll_state) { - err = r_cgc_pllccr_pll_hz_calculate(&p_clock_cfg->pll_cfg, &pll_hz, &pllccr); + err = r_cgc_pllccr_pll_hz_calculate(&p_clock_cfg->pll_cfg, &pll_hz, &pllccr, CGC_CLOCK_PLL); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } @@ -371,6 +418,30 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c #endif #endif +#if BSP_PRV_PLL2_SUPPORTED + options[CGC_CLOCK_PLL2] = p_clock_cfg->pll2_state; + + uint32_t pll2_hz = 0U; + uint32_t pll2ccr = 0U; + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) + { + err = r_cgc_pllccr_pll_hz_calculate(&p_clock_cfg->pll2_cfg, &pll2_hz, &pll2ccr, CGC_CLOCK_PLL2); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + #if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Check the PLL2 parameters if starting PLL2. */ + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) + { + err = + r_cgc_pll_parameter_check(&p_clock_cfg->pll2_cfg, + (CGC_CLOCK_CHANGE_START != options[p_clock_cfg->pll2_cfg.source_clock])); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif +#endif + #if CGC_CFG_PARAM_CHECKING_ENABLE /* Do not attempt to stop the new system clock. */ @@ -386,6 +457,17 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c } } #endif + #if BSP_PRV_PLL2_SUPPORTED + + /* Do not attempt to stop the source of PLL2 if PLL2 will be running after this operation completes. */ + if (CGC_CLOCK_CHANGE_STOP != options[CGC_CLOCK_PLL2]) + { + if ((CGC_CLOCK_CHANGE_START == options[CGC_CLOCK_PLL2]) || r_cgc_clock_run_state_get(CGC_CLOCK_PLL2)) + { + FSP_ERROR_RETURN(CGC_CLOCK_CHANGE_STOP != options[p_clock_cfg->pll2_cfg.source_clock], FSP_ERR_IN_USE); + } + } + #endif #endif /* Prerequisite to starting clocks or changing the system clock. */ @@ -405,6 +487,20 @@ fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * c } } #endif +#if BSP_PRV_PLL2_SUPPORTED + if (CGC_CLOCK_CHANGE_START == p_clock_cfg->pll2_state) + { + /* Configure PLL2 and store frequency in BSP. */ + R_SYSTEM->PLL2CCR = (uint16_t) pll2ccr; + + if (CGC_CLOCK_CHANGE_START == options[p_clock_cfg->pll_cfg.source_clock]) + { + /* Need to start PLL source clock and let it stabilize before starting PLL. */ + r_cgc_clock_change(p_clock_cfg->pll2_cfg.source_clock, CGC_CLOCK_CHANGE_START); + FSP_HARDWARE_REGISTER_WAIT(r_cgc_clock_check(p_clock_cfg->pll2_cfg.source_clock), FSP_SUCCESS); + } + } +#endif /* Start or stop clocks based on the input configuration. Start with PLL clock, so it can be stopped before trying * to stop the PLL source clock. */ @@ -506,7 +602,7 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, fsp_err_t err = FSP_SUCCESS; FSP_PARAMETER_NOT_USED(err); // unused in some build configurations -#if !BSP_PRV_PLL_SUPPORTED +#if !BSP_PRV_PLL_SUPPORTED && !BSP_PRV_PLL2_SUPPORTED FSP_PARAMETER_NOT_USED(p_pll_cfg); #endif #if CGC_CFG_PARAM_CHECKING_ENABLE @@ -516,8 +612,15 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, #if !BSP_PRV_PLL_SUPPORTED FSP_ASSERT(CGC_CLOCK_PLL != clock_source); #endif + #if !BSP_PRV_PLL2_SUPPORTED + FSP_ASSERT(CGC_CLOCK_PLL2 != clock_source); + #endif #if BSP_PRV_PLL_SUPPORTED - if (CGC_CLOCK_PLL == clock_source) + if ((CGC_CLOCK_PLL == clock_source) + #if BSP_PRV_PLL2_SUPPORTED + || (CGC_CLOCK_PLL2 == clock_source) + #endif + ) { /* p_pll_cfg is required to start PLL. */ FSP_ASSERT(NULL != p_pll_cfg); @@ -533,9 +636,13 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, #if BSP_PRV_PLL_SUPPORTED uint32_t pll_hz; uint32_t pllccr; - if (CGC_CLOCK_PLL == clock_source) + if ((CGC_CLOCK_PLL == clock_source) + #if BSP_PRV_PLL2_SUPPORTED + || (CGC_CLOCK_PLL2 == clock_source) + #endif + ) { - err = r_cgc_pllccr_pll_hz_calculate(p_pll_cfg, &pll_hz, &pllccr); + err = r_cgc_pllccr_pll_hz_calculate(p_pll_cfg, &pll_hz, &pllccr, clock_source); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } @@ -552,6 +659,17 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, { r_cgc_pll_cfg(pll_hz, pllccr); } + + #if BSP_PRV_PLL2_SUPPORTED + else if (CGC_CLOCK_PLL2 == clock_source) + { + R_SYSTEM->PLL2CCR = (uint16_t) pllccr; + } + else + { + /* Do nothing. */ + } + #endif #endif /* Start the clock. */ @@ -567,7 +685,7 @@ fsp_err_t R_CGC_ClockStart (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, /*******************************************************************************************************************//** * Stop the specified clock if it is active. Implements @ref cgc_api_t::clockStop. * - * Do not attempt to stop the current system clock source. Do not attempt to stop the source clock of the PLL if the + * Do not attempt to stop the current system clock source. Do not attempt to stop the source clock of a PLL if the * PLL is running. * * @retval FSP_SUCCESS Clock stopped successfully. @@ -600,7 +718,11 @@ fsp_err_t R_CGC_ClockStop (cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source) #if BSP_PRV_PLL_SUPPORTED /* If PLL is operating, the PLL clock source cannot be stopped. */ - FSP_ERROR_RETURN(!((r_cgc_clock_run_state_get(CGC_CLOCK_PLL) && (r_cgc_pll_clocksource_get() == clock_source))), + FSP_ERROR_RETURN(!((r_cgc_clock_run_state_get(CGC_CLOCK_PLL) && (r_cgc_pll_clocksource_get() == clock_source))) + #if BSP_PRV_PLL2_SUPPORTED + && !((r_cgc_clock_run_state_get(CGC_CLOCK_PLL2) && (r_cgc_pll2_clocksource_get() == clock_source))) + #endif + , FSP_ERR_IN_USE); #endif @@ -792,6 +914,16 @@ fsp_err_t R_CGC_OscStopDetectEnable (cgc_ctrl_t * const p_ctrl) /* Verify p_instance_ctrl is not NULL and the module is open. */ fsp_err_t err = r_cgc_common_parameter_checking(p_instance_ctrl); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + + /* The NMI must be configured to TrustZone Non-secure in order to be used in a Non-secure project. */ + FSP_ASSERT(0U != (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk)); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + + /* The NMI must be configured to TrustZone Secure in order to be used in a Secure project. */ + FSP_ASSERT(0U == (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk)); + #endif #else FSP_PARAMETER_NOT_USED(p_instance_ctrl); #endif @@ -960,6 +1092,56 @@ fsp_err_t R_CGC_OscStopStatusClear (cgc_ctrl_t * const p_ctrl) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements cgc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_CGC_CallbackSet (cgc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(cgc_callback_args_t *), + void const * const p_context, + cgc_callback_args_t * const p_callback_memory) +{ + cgc_instance_ctrl_t * p_ctrl = (cgc_instance_ctrl_t *) p_api_ctrl; + +#if BSP_TZ_SECURE_BUILD + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + +#if CGC_CFG_PARAM_CHECKING_ENABLE + + /* Verify p_ctrl is not NULL and the module is open. */ + fsp_err_t err = r_cgc_common_parameter_checking(p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Verify that the callback is not NULL. */ + FSP_ASSERT(NULL != p_callback); + + #if BSP_TZ_SECURE_BUILD + if (!callback_is_secure) + { + FSP_ASSERT(NULL != p_callback_memory); + } + #endif +#endif + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = callback_is_secure; +#endif + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /******************************************************************************************************************//** * Closes the CGC module. Implements @ref cgc_api_t::close. * @@ -1037,9 +1219,12 @@ static fsp_err_t r_cgc_common_parameter_checking (cgc_instance_ctrl_t * p_instan static void r_cgc_pre_change (cgc_prv_change_t change) { #if !BSP_CFG_USE_LOW_VOLTAGE_MODE + #if BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM /* Disable flash cache. */ - R_FCACHE->FCACHEE = 0U; + R_BSP_FlashCacheDisable(); + #endif + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); #endif if (CGC_PRV_CHANGE_LPM_CGC == change) @@ -1072,13 +1257,9 @@ static void r_cgc_post_change (cgc_prv_change_t change) #if !BSP_CFG_USE_LOW_VOLTAGE_MODE R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); - - /* Invalidate flash cache. */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; + #if BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM + R_BSP_FlashCacheEnable(); + #endif #endif } @@ -1104,6 +1285,9 @@ static bool r_cgc_subosc_mode_possible (uint32_t sckdivcr) if ((((!R_SYSTEM->HOCOCR) || (!R_SYSTEM->MOCOCR)) || (!R_SYSTEM->MOSCCR)) #if BSP_PRV_PLL_SUPPORTED || (!R_SYSTEM->PLLCR) + #endif + #if BSP_PRV_PLL2_SUPPORTED + || (!R_SYSTEM->PLL2CR) #endif ) { @@ -1163,7 +1347,11 @@ static bool r_cgc_low_speed_or_voltage_mode_possible (uint32_t sckdivcr, uint8_t #if BSP_PRV_PLL_SUPPORTED /* Low speed mode is only possible if the PLL is stopped. */ - return (bool) R_SYSTEM->PLLCR; + return (bool) R_SYSTEM->PLLCR + #if BSP_PRV_PLL2_SUPPORTED + || R_SYSTEM->PLL2CR + #endif + ; #else /* BSP_PRV_PLL_SUPPORTED */ return true; #endif @@ -1454,10 +1642,10 @@ static fsp_err_t r_cgc_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, #if CGC_CFG_PARAM_CHECKING_ENABLE - /* The PLL output frequency must be between 120 MHz and 240 MHz on this MCU (see Table 9.1 "Specifications of the + /* The PLL output frequency must be between 120 MHz and 240 MHz on most MCUs (see Table 9.1 "Specifications of the * clock generation circuit for the clock sources" in the RA6M3 manual R01UH0886EJ0100). */ FSP_ASSERT(pll_hz >= CGC_PRV_PLLCCR_PLL_MIN_HZ); - FSP_ASSERT(pll_hz <= CGC_PRV_PLLCCR_PLL_MAX_HZ); + FSP_ASSERT(pll_hz <= BSP_FEATURE_CGC_PLLCCR_MAX_HZ); #endif #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE uint32_t multiplier = (p_pll_cfg->multiplier + 1U) >> 1; @@ -1560,6 +1748,20 @@ static inline cgc_clock_t r_cgc_pll_clocksource_get (void) #endif +#if BSP_PRV_PLL2_SUPPORTED && CGC_CFG_PARAM_CHECKING_ENABLE + +/*******************************************************************************************************************//** + * This function returns the PLL2 clock source. + * + * @return PLL2 clock source + **********************************************************************************************************************/ +static inline cgc_clock_t r_cgc_pll2_clocksource_get (void) +{ + return R_SYSTEM->PLL2CCR_b.PL2SRCSEL == 1U ? CGC_CLOCK_HOCO : CGC_CLOCK_MAIN_OSC; +} + +#endif + #if BSP_PRV_PLL_SUPPORTED /*******************************************************************************************************************//** @@ -1568,6 +1770,7 @@ static inline cgc_clock_t r_cgc_pll_clocksource_get (void) * @param[in] p_pll_cfg Pointer to clock system configuration * @param[out] p_pll_hz Pointer to store calculated PLL frequency * @param[out] p_pllccr Pointer to store calculated PLLCCR value + * @param[out] pll PLL to be configured (if PLL2 is supported) * * @retval FSP_SUCCESS No errors detected in PLL configuration. * @retval FSP_ERR_ASSERTION Invalid input argument. @@ -1575,21 +1778,44 @@ static inline cgc_clock_t r_cgc_pll_clocksource_get (void) **********************************************************************************************************************/ static fsp_err_t r_cgc_pllccr_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, uint32_t * const p_pll_hz, - uint32_t * const p_pllccr) + uint32_t * const p_pllccr, + cgc_clock_t pll) { + #if !BSP_PRV_PLL2_SUPPORTED + FSP_PARAMETER_NOT_USED(pll); + #endif + /* Calculate the PLLCCR register. */ uint32_t pllccr = r_cgc_pllccr_calculate(p_pll_cfg); - /* PLLCCR cannot be changed while PLL is running. Verify requested PLLCCR value is unchanged or the PLL is - * currently stopped. */ - FSP_ERROR_RETURN( #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE - (R_SYSTEM->PLLCCR == pllccr) - #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE - (R_SYSTEM->PLLCCR2 == pllccr) + volatile uint16_t * p_pllccr_reg; + #else + volatile uint8_t * p_pllccr_reg; + #endif + + #if BSP_PRV_PLL2_SUPPORTED + if (CGC_CLOCK_PLL == pll) #endif - || (CGC_PRV_CLOCK_STATE_STOPPED == r_cgc_clock_run_state_get(CGC_CLOCK_PLL)), - FSP_ERR_CLOCK_ACTIVE); + { + #if 1U == BSP_FEATURE_CGC_PLLCCR_TYPE + p_pllccr_reg = &(R_SYSTEM->PLLCCR); + #else + p_pllccr_reg = &(R_SYSTEM->PLLCCR2); + #endif + } + + #if BSP_PRV_PLL2_SUPPORTED + else + { + p_pllccr_reg = &(R_SYSTEM->PLL2CCR); + } + #endif + + /* PLLCCR cannot be changed while PLL is running. Verify requested PLLCCR value is unchanged or the PLL is + * currently stopped. */ + FSP_ERROR_RETURN((*p_pllccr_reg == pllccr) || (CGC_PRV_CLOCK_STATE_STOPPED == r_cgc_clock_run_state_get(pll)), + FSP_ERR_CLOCK_ACTIVE); /* Calculate the new PLL frequency. Parameter checking is performed during this calculation if parameter * checking is enabled, but the calculation is required even if parameter checking is not enabled. */ @@ -1650,9 +1876,46 @@ static void r_cgc_nmi_internal_callback (bsp_grp_irq_t irq) if (NULL != gp_cgc_ctrl->p_callback) { cgc_callback_args_t args; - args.event = CGC_EVENT_OSC_STOP_DETECT; - args.p_context = gp_cgc_ctrl->p_context; + + cgc_callback_args_t * p_args = gp_cgc_ctrl->p_callback_memory; + if (NULL == p_args) + { + p_args = &args; + } + else + { + args = *p_args; + } + + p_args->event = CGC_EVENT_OSC_STOP_DETECT; + p_args->p_context = gp_cgc_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (gp_cgc_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_cgc_ctrl->p_callback(&args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + cgc_prv_ns_callback p_callback = (cgc_prv_ns_callback) (gp_cgc_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ gp_cgc_ctrl->p_callback(&args); +#endif + + if (NULL != gp_cgc_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_cgc_ctrl->p_callback_memory = args; + } } } } diff --git a/ra/fsp/src/r_ctsu/r_ctsu.c b/ra/fsp/src/r_ctsu/r_ctsu.c index 69bcaedcb..433deed0d 100644 --- a/ra/fsp/src/r_ctsu/r_ctsu.c +++ b/ra/fsp/src/r_ctsu/r_ctsu.c @@ -32,105 +32,120 @@ **********************************************************************************************************************/ /** "CTSU" in ASCII, used to determine if device is open. */ -#define CTSU_OPEN (0x43545355U) +#define CTSU_OPEN (0x43545355U) /* Macro definitions for register setting */ -#define CTSU_PON_OFF (0) // CTSU hardware macro power off -#define CTSU_PON_ON (1) // CTSU hardware macro power on -#define CTSU_CSW_OFF (0) // Capacitance switch turned off -#define CTSU_CSW_ON (1) // Capacitance switch turned on - -#define CTSU_CR1_MODIFY_BIT (0xC8) // MD1, MD0, ATUNE1 -#define CTSU_SOVF (0x20) // Overflow bit -#define CTSU_CORRECTION_AVERAGE (32) -#define CTSU_SHIFT_AMOUNT (15) -#define CTSU_COUNT_MAX (0xFFFF) -#define CTSU_PCLKB_FREQ_MHZ (1000000) -#define CTSU_PCLKB_FREQ_RANGE1 (32) -#define CTSU_PCLKB_FREQ_RANGE2 (64) -#define CTSU_PCLKB_FREQ_RANGE3 (128) -#define CTSU_WAIT_TIME (500) +#define CTSU_PON_OFF (0) // CTSU hardware macro power off +#define CTSU_PON_ON (1) // CTSU hardware macro power on +#define CTSU_CSW_OFF (0) // Capacitance switch turned off +#define CTSU_CSW_ON (1) // Capacitance switch turned on + +#define CTSU_CR1_MODIFY_BIT (0xC8) // MD1, MD0, ATUNE1 +#define CTSU_SOVF (0x20) // Overflow bit +#define CTSU_CORRECTION_AVERAGE (32) +#define CTSU_SHIFT_AMOUNT (15) +#define CTSU_COUNT_MAX (0xFFFF) +#define CTSU_PCLKB_FREQ_MHZ (1000000) +#define CTSU_PCLKB_FREQ_RANGE1 (32) +#define CTSU_PCLKB_FREQ_RANGE2 (64) +#define CTSU_PCLKB_FREQ_RANGE3 (128) +#define CTSU_WAIT_TIME (500) /* Macro definitions for initial offset tuning */ -#define CTSU_TUNING_MAX (0x03FF) -#define CTSU_TUNING_MIN (0x0000) -#define CTSU_TUNING_VALUE_SELF (15360) -#define CTSU_TUNING_VALUE_MUTUAL (10240) +#define CTSU_TUNING_MAX (0x03FF) +#define CTSU_TUNING_MIN (0x0000) +#define CTSU_TUNING_VALUE_SELF (15360) +#define CTSU_TUNING_VALUE_MUTUAL (10240) +#define CTSU_TUNING_OT_COUNT (25) #if (BSP_FEATURE_CTSU_VERSION == 2) - #define CTSU_SST_RECOMMEND (0x1F) // The value of SST should be fixed - #define CTSU_SNUM_RECOMMEND (0x07) // The value of SNUM should be fixed - #define CTSU_SNUM_MAX (0xFF) // The maximum value of SNUM - #define CTSU_ICOMP0 (0x80) // ICOMP0 bit - #define CTSU_ICOMP1 (0x40) // ICOMP1 bit - #define CTSU_ICOMPRST (0x20) // ICOMPRST bit - #define CTSU_CR0_MODIFY_BIT (0xC0) // TXVSEL - #define CTSU_CR2_MODIFY_BIT (0x33) // POSEL, ATUNE2, MD2 - #define CTSU_SUADJ_RECOMMEND (0x0080) - #define CTSU_MUTUAL_BUF_SIZE (CTSU_CFG_NUM_SUMULTI * 2) - #define CTSU_REG_TRIMA (*(uint32_t *) 0x407EC3A4) - #define CTSU_REG_TRIMB (*(uint32_t *) 0x407EC3A8) + #define CTSU_SST_RECOMMEND (0x1F) // The recommend value of SST + #define CTSU_SST_RECOMMEND_CURRENT (0x3F) // The recommend value of SST with current + #define CTSU_SNUM_RECOMMEND (0x07) // The value of SNUM should be fixed + #define CTSU_SNUM_MAX (0xFF) // The maximum value of SNUM + #define CTSU_ICOMP0 (0x80) // ICOMP0 bit + #define CTSU_ICOMP1 (0x40) // ICOMP1 bit + #define CTSU_ICOMPRST (0x20) // ICOMPRST bit + #define CTSU_CR0_MODIFY_BIT (0xC0) // TXVSEL + #define CTSU_CR2_MODIFY_BIT (0x33) // POSEL, ATUNE2, MD2 + #define CTSU_SUADJ_MAX (0xFF) // The maximum value of SUADJx + #define CTSU_SUADJ_SSCNT_ADJ (0x20) // The value of Adjusting SCADJx by SSCNT + #define CTSU_MUTUAL_BUF_SIZE (CTSU_CFG_NUM_SUMULTI * 2) + #define CTSU_REG_TRIMA (*(uint32_t *) 0x407EC3A4) + #define CTSU_REG_TRIMB (*(uint32_t *) 0x407EC3A8) /* Macro definitions for correction */ - #define CTSU_CORRECTION_STD_VAL (19200) // 20UC standard value - #define CTSU_CORRECTION_STD_UNIT (1920) // 2UC value - #define CTSU_CORRECTION_SUMULTI (0x20) // SUMULTI step - #define CTSU_CORRECTION_OFFSET_UNIT (120) // (CTSU_CORRECTION_STD_VAL / 256) * 2 - #define CTSU_CORRECTION_TRIMB_MAX (0xFF) - #define CTSU_CORRECTION_TRIMB_SIGN_BIT (0x80) - #define CTSU_CORRECTION_BIT10 (0x0400) - #define CTSU_CORRECTION_BIT9 (0x0200) - #define CTSU_CORRECTION_BIT8 (0x0100) - #define CTSU_CORRECTION_BIT7 (0x0080) + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CORRECTION_STD_VAL (19200) // 20UC standard value + #define CTSU_CORRECTION_STD_UNIT (1920) // 2UC value + #define CTSU_CORRECTION_OFFSET_UNIT (120) // (7680 / 64) + #else + #define CTSU_CORRECTION_STD_VAL (15360) // 20UC standard value * 0.8 + #define CTSU_CORRECTION_STD_UNIT (1536) // 2UC value * 0.8 + #define CTSU_CORRECTION_OFFSET_UNIT (96) // (7680 / 64) * 0.8 + #endif + #define CTSU_CORRECTION_SUMULTI (0x20) // SUMULTI step + #define CTSU_CORRECTION_TRIMB_MAX (0xFF) + #define CTSU_CORRECTION_TRIMB_SIGN_BIT (0x80) + #define CTSU_CORRECTION_RTRIM_THRESHOLD1 (0xA0) + #define CTSU_CORRECTION_RTRIM_THRESHOLD2 (0x50) + #define CTSU_CORRECTION_TRIMB_THRESHOLD1 (0xC0) + #define CTSU_CORRECTION_TRIMB_THRESHOLD2 (0x3F) + #define CTSU_CORRECTION_BIT10 (0x0400) + #define CTSU_CORRECTION_BIT9 (0x0200) + #define CTSU_CORRECTION_BIT8 (0x0100) + #define CTSU_CORRECTION_BIT7 (0x0080) #if (CTSU_CFG_NUM_CFC != 0) - #define CTSU_CORRCFC_POINT_NUM (5) // number of table - #define CTSU_CORRCFC_CENTER_POINT ((CTSU_CORRCFC_POINT_NUM - 1) / 2) // number of center point - #define CTSU_CORRCFC_TS_MAX (36) // Maximum number of TS terminal - #define CTSU_CORRCFC_SHIFT8 (8) // Definition of 8bit shift + #define CTSU_CORRCFC_POINT_NUM (5) // number of table + #define CTSU_CORRCFC_CENTER_POINT ((CTSU_CORRCFC_POINT_NUM - 1) / 2) // number of center point + #define CTSU_CORRCFC_TS_MAX (36) // Maximum number of TS terminal + #define CTSU_CORRCFC_SHIFT8 (8) // Definition of 8bit shift #endif #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - #define CTSU_REG_ADCTDR (*(uint16_t *) 0x4005C040) // ADCTDR address - #define CTSU_CALIB_REF (6140000 / CTSU_CFG_VCC_MV) // 1.5V Reference value (4096 * 1500) - #define CTSU_CALIB_AVERAGE_TIME (64) // ADC average time - #define CTSU_CALIB_THRESHOLD ((0x1000 * 4) / CTSU_CFG_VCC_MV) // RTRIM calib threshold - #define CTSU_CALIB_CTSUSO (0x3C0) // 150uA offset - #define CTSU_CALIB_ADSSTRL (0x3F) // Sampling time + #define CTSU_REG_ADCTDR (*(uint16_t *) 0x4005C040) // ADCTDR address + #if (CTSU_CFG_LOW_VOLTAGE_MODE == 0) + #define CTSU_CALIB_REF ((6144000 * 10) / CTSU_CFG_VCC_MV) // 1.5V Reference value (4096 * 1500 * 10) + #else + #define CTSU_CALIB_REF ((4915200 * 10) / CTSU_CFG_VCC_MV) // 1.2V Reference value (4096 * 1200 * 10) + #endif + #define CTSU_CALIB_AVERAGE_TIME (64) // ADC average time + #define CTSU_CALIB_THRESHOLD ((0x1000 * 4) / CTSU_CFG_VCC_MV) // RTRIM calib threshold + #define CTSU_CALIB_CTSUSO (0x3C0) // 150uA offset + #define CTSU_CALIB_ADSSTRL (0x3F) // Sampling time #endif #endif #if (BSP_FEATURE_CTSU_VERSION == 1) - #define CTSU_TXVSEL (0x80) // TXVSEL bit - #define CTSU_SST_RECOMMEND (0x10) // The value of SST should be fixed to 00010000b - #define CTSU_SNUM_MAX (0x3F) // The maximum value of SNUM - #define CTSU_SDPA_MAX (0x1F) // The maximum value of SDPA - #define CTSU_PRRATIO_RECOMMEND (3) // Recommended setting value - #define CTSU_PRMODE_62_PULSES (2) // 62 pulses (recommended setting value) - #define CTSU_SOFF_ON (0) // High-pass noise reduction function turned on - #define CTSU_SSMOD (0) // The value of SSMOD should be fixed to 00b - #define CTSU_SSCNT (3) // The value of SSCNT should be fixed to 11b - #define CTSU_RICOA_RECOMMEND (0x0F) // Recommended setting value - #define CTSU_ICOG_100 (0) // ICOG = 100% - #define CTSU_ICOG_66 (1) // ICOG = 66% - #define CTSU_ICOG_50 (2) // ICOG = 50% - #define CTSU_ICOG_40 (3) // ICOG = 40% - #define CTSU_MUTUAL_BUF_SIZE (1) + #define CTSU_TXVSEL (0x80) // TXVSEL bit + #define CTSU_SST_RECOMMEND (0x10) // The value of SST should be fixed to 00010000b + #define CTSU_SNUM_MAX (0x3F) // The maximum value of SNUM + #define CTSU_SDPA_MAX (0x1F) // The maximum value of SDPA + #define CTSU_PRRATIO_RECOMMEND (3) // Recommended setting value + #define CTSU_PRMODE_62_PULSES (2) // 62 pulses (recommended setting value) + #define CTSU_SOFF_ON (0) // High-pass noise reduction function turned on + #define CTSU_SSMOD (0) // The value of SSMOD should be fixed to 00b + #define CTSU_SSCNT (3) // The value of SSCNT should be fixed to 11b + #define CTSU_RICOA_RECOMMEND (0x0F) // Recommended setting value + #define CTSU_ICOG_100 (0) // ICOG = 100% + #define CTSU_ICOG_66 (1) // ICOG = 66% + #define CTSU_ICOG_50 (2) // ICOG = 50% + #define CTSU_ICOG_40 (3) // ICOG = 40% + #define CTSU_MUTUAL_BUF_SIZE (1) /* Macro definitions for correction */ - #define CTSU_REGISTER_CTSUERRS (*(uint16_t *) 0x4008101c) - #define CTSU_CTSUERRS_VALUE (0x0082) #if (BSP_CFG_MCU_PART_SERIES == 2) || (BSP_CFG_MCU_PART_SERIES == 4) - #define CTSU_CORRECTION_1ST_STD_VAL (40960UL) // ICOG = 66% - #define CTSU_CORRECTION_2ND_STD_VAL (24824) // ICOG = 40%, (x = 40960 * 40 / 66) - #define CTSU_WAFER_PARAMETER (0.96523525) - #define CTSU_ICOG_RECOMMEND (CTSU_ICOG_66) // Recommended setting value + #define CTSU_CORRECTION_1ST_STD_VAL (40960UL) // ICOG = 66% + #define CTSU_CORRECTION_2ND_STD_VAL (24824) // ICOG = 40%, (x = 40960 * 40 / 66) + #define CTSU_WAFER_PARAMETER (0.96523525) + #define CTSU_ICOG_RECOMMEND (CTSU_ICOG_66) // Recommended setting value #endif #if (BSP_CFG_MCU_PART_SERIES == 6) - #define CTSU_CORRECTION_1ST_STD_VAL (27306UL) // ICOG = 66%, (x = 40960 * 66 / 100) - #define CTSU_CORRECTION_2ND_STD_VAL (16384) // ICOG = 40%, (x = 40960 * 40 / 100) - #define CTSU_WAFER_PARAMETER (1) - #define CTSU_ICOG_RECOMMEND (CTSU_ICOG_100) // Recommended setting value + #define CTSU_CORRECTION_1ST_STD_VAL (27306UL) // ICOG = 66%, (x = 40960 * 66 / 100) + #define CTSU_CORRECTION_2ND_STD_VAL (16384) // ICOG = 40%, (x = 40960 * 40 / 100) + #define CTSU_WAFER_PARAMETER (1) + #define CTSU_ICOG_RECOMMEND (CTSU_ICOG_100) // Recommended setting value #endif #endif @@ -148,14 +163,19 @@ typedef struct st_ctsu_correction_calc typedef struct st_ctsu_correction_multi { - ctsu_range_t range; - uint16_t snum; uint16_t pri[CTSU_CFG_NUM_SUMULTI]; uint16_t snd[CTSU_CFG_NUM_SUMULTI]; uint32_t offset[CTSU_CFG_NUM_SUMULTI]; + int32_t offset_error[CTSU_CFG_NUM_SUMULTI]; ctsu_correction_calc_t calc; } ctsu_correction_multi_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile ctsu_prv_ns_callback)(ctsu_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile ctsu_prv_ns_callback)(ctsu_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -185,6 +205,7 @@ static void ctsu_correction_data_get(ctsu_instance_ctrl_t * const p_instance_ctr #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) static void ctsu_correction_calib_rtrim(ctsu_instance_ctrl_t * const p_instance_ctrl); +static void ctsu_correction_offset_adjust(uint16_t * p_adj_data, uint16_t raw_data, int32_t offset_error); #endif #endif @@ -208,7 +229,7 @@ static const fsp_version_t g_ctsu_version = .code_version_minor = CTSU_CODE_VERSION_MINOR }; static uint16_t g_ctsu_element_index = 0; -static uint8_t g_ctsu_tuning_complete[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +static uint8_t g_ctsu_tuning_count[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; static int32_t g_ctsu_tuning_diff[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; static ctsu_ctsuwr_t g_ctsu_ctsuwr[(CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS) * CTSU_CFG_NUM_SUMULTI]; #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) @@ -246,11 +267,12 @@ static const ioport_cfg_t g_ctsu_tscap_pin_cfg = **********************************************************************************************************************/ const ctsu_api_t g_ctsu_on_ctsu = { - .open = R_CTSU_Open, - .scanStart = R_CTSU_ScanStart, - .dataGet = R_CTSU_DataGet, - .close = R_CTSU_Close, - .versionGet = R_CTSU_VersionGet, + .open = R_CTSU_Open, + .scanStart = R_CTSU_ScanStart, + .dataGet = R_CTSU_DataGet, + .close = R_CTSU_Close, + .callbackSet = R_CTSU_CallbackSet, + .versionGet = R_CTSU_VersionGet, }; /*******************************************************************************************************************//** @@ -284,6 +306,7 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf #if (BSP_FEATURE_CTSU_VERSION == 2) uint16_t i; uint32_t pclkb_mhz; + uint16_t suadj[3]; #endif #if (CTSU_CFG_PARAM_CHECKING_ENABLE == 1) @@ -311,6 +334,7 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf #endif p_instance_ctrl->state = CTSU_STATE_INIT; + /* Save configurations. */ p_instance_ctrl->p_ctsu_cfg = p_cfg; /* Initialize driver control structure (address setting) */ @@ -336,10 +360,10 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf g_ctsu_mutual_element_index = (uint8_t) (g_ctsu_mutual_element_index + p_instance_ctrl->num_elements); } #endif - p_instance_ctrl->p_tuning_complete = &g_ctsu_tuning_complete[g_ctsu_element_index]; - p_instance_ctrl->p_tuning_diff = &g_ctsu_tuning_diff[g_ctsu_element_index]; - p_instance_ctrl->p_ctsuwr = &g_ctsu_ctsuwr[g_ctsu_element_index * CTSU_CFG_NUM_SUMULTI]; - g_ctsu_element_index = (uint8_t) (g_ctsu_element_index + p_instance_ctrl->num_elements); + p_instance_ctrl->p_tuning_count = &g_ctsu_tuning_count[g_ctsu_element_index]; + p_instance_ctrl->p_tuning_diff = &g_ctsu_tuning_diff[g_ctsu_element_index]; + p_instance_ctrl->p_ctsuwr = &g_ctsu_ctsuwr[g_ctsu_element_index * CTSU_CFG_NUM_SUMULTI]; + g_ctsu_element_index = (uint8_t) (g_ctsu_element_index + p_instance_ctrl->num_elements); /* Set Value */ p_instance_ctrl->num_moving_average = p_cfg->num_moving_average; @@ -401,8 +425,8 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf #endif for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) { - p_instance_ctrl->p_tuning_complete[element_id] = 0; - p_instance_ctrl->p_tuning_diff[element_id] = 0; + p_instance_ctrl->p_tuning_count[element_id] = 0; + p_instance_ctrl->p_tuning_diff[element_id] = 0; element_cfgs = (p_cfg->p_elements + element_id); #if (BSP_FEATURE_CTSU_VERSION == 2) if (CTSU_MODE_CURRENT_SCAN == p_cfg->md) @@ -544,6 +568,7 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf /* High resolution pulse mode */ R_CTSU->CTSUCRA_b.SDPSEL = 1; + R_CTSU->CTSUCRA_b.FCMODE = 1; R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; R_CTSU->CTSUCALIB_b.CCOCLK = 0; R_CTSU->CTSUCALIB_b.SUCLKEN = 0; @@ -576,23 +601,48 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf p_instance_ctrl->p_corrcfc_info = &g_ctsu_corrcfc_info; #endif - R_CTSU->CTSUCRA_b.LOAD = 1; - R_CTSU->CTSUCALIB_b.CCOCLK = 1; - R_CTSU->CTSUCALIB_b.SUCLKEN = 1; + R_CTSU->CTSUCRA_b.LOAD = 1; + R_CTSU->CTSUCRB_b.SSCNT = 1; + R_CTSU->CTSUCALIB_b.SUCARRY = 0; + R_CTSU->CTSUCALIB_b.CCOCALIB = 0; + R_CTSU->CTSUCALIB_b.CCOCLK = 1; + R_CTSU->CTSUCALIB_b.TSOC = 0; + R_CTSU->CTSUCALIB_b.SUCLKEN = 1; + + /* Read SUADJD byte */ + suadj[0] = (uint16_t) ((CTSU_REG_TRIMA >> 16) & CTSU_SUADJ_MAX); + + /* Adjust multi freq */ + suadj[1] = (uint16_t) ((suadj[0] * (CTSU_CFG_SUMULTI1 + 1)) / (CTSU_CFG_SUMULTI0 + 1)); + suadj[2] = (uint16_t) ((suadj[0] * (CTSU_CFG_SUMULTI2 + 1)) / (CTSU_CFG_SUMULTI0 + 1)); - R_CTSU->CTSUCRA_b.FCMODE = 0; - R_CTSU->CTSUSUCLK0 = (uint16_t) (CTSU_CFG_SUMULTI0 << 8) | CTSU_SUADJ_RECOMMEND; - R_CTSU->CTSUSUCLK1 = (uint16_t) (CTSU_CFG_SUMULTI1 << 8) | CTSU_SUADJ_RECOMMEND; - R_CTSU->CTSUSUCLK2 = (uint16_t) (CTSU_CFG_SUMULTI2 << 8) | CTSU_SUADJ_RECOMMEND; - R_CTSU->CTSUCRA_b.FCMODE = 1; + /* Adjust SSCNT setting */ + suadj[0] = (uint16_t) (suadj[0] - (CTSU_SUADJ_SSCNT_ADJ * R_CTSU->CTSUCRB_b.SSCNT)); + suadj[1] = (uint16_t) (suadj[1] - (CTSU_SUADJ_SSCNT_ADJ * R_CTSU->CTSUCRB_b.SSCNT)); + suadj[2] = (uint16_t) (suadj[2] - (CTSU_SUADJ_SSCNT_ADJ * R_CTSU->CTSUCRB_b.SSCNT)); + + /* Set CTSUSUCLK register */ + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLK0 = (uint16_t) (CTSU_CFG_SUMULTI0 << 8) | suadj[0]; + R_CTSU->CTSUSUCLK1 = (uint16_t) (CTSU_CFG_SUMULTI1 << 8) | suadj[1]; + R_CTSU->CTSUSUCLK2 = (uint16_t) (CTSU_CFG_SUMULTI2 << 8) | suadj[2]; + R_CTSU->CTSUCRA_b.SDPSEL = 1; #endif p_instance_ctrl->p_correction_info = &g_ctsu_correction_info; p_instance_ctrl->rd_index = 0; p_instance_ctrl->wr_index = 0; - p_instance_ctrl->p_callback = p_cfg->p_callback; p_instance_ctrl->state = CTSU_STATE_IDLE; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_instance_ctrl->callback_is_secure = true; +#endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + /* Mark driver as open */ p_instance_ctrl->open = CTSU_OPEN; @@ -672,6 +722,7 @@ fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) R_CTSU->CTSUCR2 = (uint8_t) (temp | (p_instance_ctrl->ctsucr2 & CTSU_CR2_MODIFY_BIT)); // POSEL, ATUNE2, MD2 if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND_CURRENT; R_CTSU->CTSUCRA_b.DCMODE = 1; R_CTSU->CTSUCRA_b.DCBACK = 1; R_CTSU->CTSUMCH_b.MCA0 = 1; @@ -681,6 +732,7 @@ fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) } else { + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; R_CTSU->CTSUCRA_b.DCMODE = 0; R_CTSU->CTSUCRA_b.DCBACK = 0; R_CTSU->CTSUMCH_b.MCA0 = 1; @@ -708,6 +760,7 @@ fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) else { + R_CTSU->CTSUSST = CTSU_SST_RECOMMEND; ctsu_correction_scan_start(); } #endif @@ -749,14 +802,11 @@ fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) #endif #endif - /* Initialize CTSU hardware control block */ - R_CTSU->CTSUCR0 |= 0x10; + p_instance_ctrl->state = CTSU_STATE_SCANNING; - /* CTSU scan start */ + /* Set CTSU_STRT bit to start scan */ R_CTSU->CTSUCR0 |= 0x01; ///< CTSU_STRT - p_instance_ctrl->state = CTSU_STATE_SCANNING; - return err; } @@ -847,6 +897,42 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) return err; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements ctsu_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_CTSU_CallbackSet (ctsu_ctrl_t * const p_api_ctrl, + void ( * p_callback)(ctsu_callback_args_t *), + void const * const p_context, + ctsu_callback_args_t * const p_callback_memory) +{ + ctsu_instance_ctrl_t * p_ctrl = (ctsu_instance_ctrl_t *) p_api_ctrl; + +#if (CTSU_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(CTSU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * @brief Disables specified CTSU control block. Implements @ref ctsu_api_t::close. * @@ -941,9 +1027,9 @@ fsp_err_t ctsu_transfer_open (ctsu_instance_ctrl_t * const p_instance_ctrl) p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; p_info->size = TRANSFER_SIZE_4_BYTE; p_info->p_dest = (void *) &R_CTSU->CTSUSO; - p_info->mode = TRANSFER_MODE_REPEAT; - p_info->repeat_area = TRANSFER_REPEAT_AREA_SOURCE; - p_info->length = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); + p_info->mode = TRANSFER_MODE_BLOCK; + p_info->repeat_area = TRANSFER_REPEAT_AREA_DESTINATION; + p_info->length = 1; #endif #if (BSP_FEATURE_CTSU_VERSION == 1) p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; @@ -972,9 +1058,9 @@ fsp_err_t ctsu_transfer_open (ctsu_instance_ctrl_t * const p_instance_ctrl) p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED; p_info->size = TRANSFER_SIZE_2_BYTE; p_info->p_dest = p_instance_ctrl->p_mutual_raw; - p_info->mode = TRANSFER_MODE_REPEAT; - p_info->repeat_area = TRANSFER_REPEAT_AREA_DESTINATION; - p_info->length = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); + p_info->mode = TRANSFER_MODE_BLOCK; + p_info->repeat_area = TRANSFER_REPEAT_AREA_SOURCE; + p_info->length = 1; #endif #if (BSP_FEATURE_CTSU_VERSION == 1) p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; @@ -1034,44 +1120,44 @@ fsp_err_t ctsu_transfer_configure (ctsu_instance_ctrl_t * const p_instance_ctrl) p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_tx; p_info = p_transfer->p_cfg->p_info; #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info->length = 1; if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) { - p_info->length = 1; - p_info->p_src = (void *) &(g_ctsu_correction_info.ctsuwr); + p_info->num_blocks = 1; + p_info->p_src = (void *) &(g_ctsu_correction_info.ctsuwr); } #if (CTSU_CFG_NUM_CFC != 0) else if (CTSU_CORRECTION_RUN == g_ctsu_corrcfc_info.status) { - p_info->length = 1; - p_info->p_src = (void *) &(g_ctsu_corrcfc_info.ctsuwr); + p_info->num_blocks = 1; + p_info->p_src = (void *) &(g_ctsu_corrcfc_info.ctsuwr); } #endif else { if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { - p_info->length = p_instance_ctrl->num_elements; + p_info->num_blocks = p_instance_ctrl->num_elements; } else { - p_info->length = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); + p_info->num_blocks = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); } p_info->p_src = p_instance_ctrl->p_ctsuwr; } #endif #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info->length = 3; if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) { p_info->num_blocks = 1; - p_info->length = 3; p_info->p_src = (void *) &(g_ctsu_correction_info.ctsuwr); } else { p_info->num_blocks = p_instance_ctrl->num_elements; - p_info->length = 3; p_info->p_src = p_instance_ctrl->p_ctsuwr; } #endif @@ -1082,30 +1168,31 @@ fsp_err_t ctsu_transfer_configure (ctsu_instance_ctrl_t * const p_instance_ctrl) p_transfer = p_instance_ctrl->p_ctsu_cfg->p_transfer_rx; p_info = p_transfer->p_cfg->p_info; #if (BSP_FEATURE_CTSU_VERSION == 2) + p_info->length = 1; if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) { - p_info->length = 1; - p_info->p_dest = (void *) &g_ctsu_correction_info.scanbuf; - p_info->p_src = (void *) &R_CTSU->CTSUSC; + p_info->num_blocks = 1; + p_info->p_dest = (void *) &g_ctsu_correction_info.scanbuf; + p_info->p_src = (void *) &R_CTSU->CTSUSC; } #if (CTSU_CFG_NUM_CFC != 0) else if (CTSU_CORRECTION_RUN == g_ctsu_corrcfc_info.status) { - p_info->length = g_ctsu_corrcfc_info.num_ts; - p_info->p_dest = (void *) g_ctsu_corrcfc_info.scanbuf; - p_info->p_src = (void *) &R_CTSU->CTSUCFCCNT; + p_info->num_blocks = g_ctsu_corrcfc_info.num_ts; + p_info->p_dest = (void *) g_ctsu_corrcfc_info.scanbuf; + p_info->p_src = (void *) &R_CTSU->CTSUCFCCNT; } #endif else { if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { - p_info->length = p_instance_ctrl->num_elements; + p_info->num_blocks = p_instance_ctrl->num_elements; } else { - p_info->length = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); + p_info->num_blocks = (uint16_t) (p_instance_ctrl->num_elements * CTSU_CFG_NUM_SUMULTI); } p_info->p_dest = p_instance_ctrl->p_self_raw; @@ -1113,8 +1200,8 @@ fsp_err_t ctsu_transfer_configure (ctsu_instance_ctrl_t * const p_instance_ctrl) #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->p_ctsu_cfg->md)) { - p_info->p_dest = p_instance_ctrl->p_mutual_raw; - p_info->length = (uint16_t) (p_info->length * 2); ///< Primary and Secondary + p_info->p_dest = p_instance_ctrl->p_mutual_raw; + p_info->num_blocks = (uint16_t) (p_info->num_blocks * 2); ///< Primary and Secondary } #if (CTSU_CFG_NUM_CFC != 0) @@ -1127,16 +1214,15 @@ fsp_err_t ctsu_transfer_configure (ctsu_instance_ctrl_t * const p_instance_ctrl) } #endif #if (BSP_FEATURE_CTSU_VERSION == 1) + p_info->length = 2; if (CTSU_CORRECTION_RUN == g_ctsu_correction_info.status) { p_info->num_blocks = 1; - p_info->length = 2; p_info->p_dest = (void *) &g_ctsu_correction_info.scanbuf; } else { p_info->num_blocks = p_instance_ctrl->num_elements; - p_info->length = 2; p_info->p_dest = p_instance_ctrl->p_self_raw; #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) if (CTSU_MODE_MUTUAL_FULL_SCAN == (CTSU_MODE_MUTUAL_FULL_SCAN & p_instance_ctrl->p_ctsu_cfg->md)) @@ -1173,6 +1259,7 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) uint16_t corr_data[CTSU_CFG_NUM_SUMULTI]; uint16_t target_val; int32_t ctsuso; + uint32_t snum; #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->p_ctsu_cfg->md) @@ -1191,7 +1278,7 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) /* element_id through each element for control block */ for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) { - if (0 == *(p_instance_ctrl->p_tuning_complete + element_id)) + if (CTSU_TUNING_OT_COUNT != *(p_instance_ctrl->p_tuning_count + element_id)) { #if (BSP_FEATURE_CTSU_VERSION == 1) #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) @@ -1264,8 +1351,7 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) p_instance_ctrl->p_ctsuwr[element_id].ctsuso0 |= ctsuso; #endif #if (BSP_FEATURE_CTSU_VERSION == 2) - element_top = (uint16_t) (element_id * CTSU_CFG_NUM_SUMULTI); - complete_flag = 1; + element_top = (uint16_t) (element_id * CTSU_CFG_NUM_SUMULTI); for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) @@ -1281,15 +1367,13 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) } #endif + snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & + CTSU_SNUM_MAX; + corr_data[i] = (uint16_t) ((uint32_t) (corr_data[i] * (CTSU_SNUM_RECOMMEND + 1)) / (snum + 1)); + /* Calculate CTSUSO equivalent difference between current value and target value */ diff = (int32_t) (corr_data[i] - target_val) / (CTSU_CORRECTION_OFFSET_UNIT >> p_instance_ctrl->range); - /* If the difference is large, tuning value may not be able to match, so create the next opportunity */ - if ((diff > 10) || (diff < -10)) - { - complete_flag = 0; - } - ctsuso = (int32_t) (p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso & CTSU_TUNING_MAX); ctsuso += diff; @@ -1297,15 +1381,24 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) if (ctsuso < 0) { ctsuso = 0; - *(p_instance_ctrl->p_tuning_complete + element_id) = 1; + complete_flag++; } else if (ctsuso > CTSU_TUNING_MAX) { ctsuso = CTSU_TUNING_MAX; - *(p_instance_ctrl->p_tuning_complete + element_id) = 1; + complete_flag++; } else { + /* If the difference is large, tuning value may not be able to match, so create the next opportunity */ + if (0 == diff) + { + complete_flag++; + } + else + { + (*(p_instance_ctrl->p_tuning_count + element_id))++; + } } /* Set the result of the calculated CTSUSO */ @@ -1316,14 +1409,14 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) } else { - num_complete++; + complete_flag = CTSU_CFG_NUM_SUMULTI; } - if (complete_flag) + if (CTSU_CFG_NUM_SUMULTI == complete_flag) { complete_flag = 0; num_complete++; - *(p_instance_ctrl->p_tuning_complete + element_id) = 1; + *(p_instance_ctrl->p_tuning_count + element_id) = CTSU_TUNING_OT_COUNT; } } @@ -1592,14 +1685,28 @@ void ctsu_end_isr (void) ctsu_instance_ctrl_t * p_instance_ctrl = (ctsu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); ctsu_callback_args_t args; + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + ctsu_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + /** Clear the BSP IRQ Flag */ R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet()); - args.event = CTSU_EVENT_SCAN_COMPLETE; + p_args->event = CTSU_EVENT_SCAN_COMPLETE; if (R_CTSU->CTSUST & CTSU_SOVF) { - args.event |= CTSU_EVENT_OVERFLOW; + p_args->event |= CTSU_EVENT_OVERFLOW; R_CTSU->CTSUST &= (uint8_t) (~CTSU_SOVF); } @@ -1608,12 +1715,12 @@ void ctsu_end_isr (void) { if (R_CTSU->CTSUSR0 & CTSU_ICOMP0) { - args.event |= CTSU_EVENT_ICOMP; + p_args->event |= CTSU_EVENT_ICOMP; } if (R_CTSU->CTSUSR0 & CTSU_ICOMP1) { - args.event |= CTSU_EVENT_ICOMP1; + p_args->event |= CTSU_EVENT_ICOMP1; } R_CTSU->CTSUSR0 |= CTSU_ICOMPRST; @@ -1626,31 +1733,60 @@ void ctsu_end_isr (void) __NOP(); __NOP(); R_CTSU->CTSUCR1 |= 0x01; - args.event |= CTSU_EVENT_ICOMP; + p_args->event |= CTSU_EVENT_ICOMP; } #endif #if (BSP_FEATURE_CTSU_VERSION == 2) + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) if (CTSU_CORRECTION_RUN != g_ctsu_correction_info.status) { if (CTSU_MODE_CORRECTION_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { - R_CTSU->CTSUCRA_b.FCMODE = 0; - R_CTSU->CTSUSUCLK0 = (uint16_t) (CTSU_CFG_SUMULTI0 << 8) | CTSU_SUADJ_RECOMMEND; - R_CTSU->CTSUCRB_b.SSCNT = 0; + R_CTSU->CTSUCRA_b.SDPSEL = 0; + R_CTSU->CTSUSUCLK0 = (uint16_t) ((CTSU_CFG_SUMULTI0 << 8) | g_ctsu_correction_info.suadj0); + R_CTSU->CTSUCRB_b.SSCNT = 1; R_CTSU->CTSUCALIB_b.SUCARRY = 0; R_CTSU->CTSUCALIB_b.CCOCALIB = 0; R_CTSU->CTSUCALIB_b.CCOCLK = 1; R_CTSU->CTSUCALIB_b.TSOC = 0; - R_CTSU->CTSUCRA_b.FCMODE = 1; + R_CTSU->CTSUCRA_b.SDPSEL = 1; } } + #endif #endif + p_instance_ctrl->state = CTSU_STATE_SCANNED; + p_args->p_context = p_instance_ctrl->p_context; + + /* If a callback was provided, call it with the argument */ + if (NULL != p_instance_ctrl->p_callback) + { +#if BSP_TZ_SECURE_BUILD - /* if callback present, check for error and do callback */ - if (p_instance_ctrl->p_callback != NULL) + /* p_callback can point to a secure function or a non-secure function. */ + if (p_instance_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + ctsu_prv_ns_callback p_callback = (ctsu_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + } + + if (NULL != p_instance_ctrl->p_callback_memory) { - p_instance_ctrl->p_callback(&args); + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; } /* reset indexes */ @@ -1688,20 +1824,36 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) trimb = CTSU_REG_TRIMB; for (i = 0; i < CTSU_RANGE_NUM; i++) { - trimb_byte = (trimb >> (i * 8)) & CTSU_CORRECTION_TRIMB_MAX; + trimb_byte = (trimb >> (i * 8)) & CTSU_CORRECTION_TRIMB_MAX; + error_registance[i] = (uint16_t) (trimb_byte & (uint8_t) (~CTSU_CORRECTION_TRIMB_SIGN_BIT)); if (trimb_byte & CTSU_CORRECTION_TRIMB_SIGN_BIT) { - /* Plus : bit8(0.50) and bit7(0.25) set 0, bit9(1.00) set 1 */ - error_registance[i] = - (uint16_t) ((trimb_byte & (uint8_t) (~CTSU_CORRECTION_TRIMB_SIGN_BIT)) | CTSU_CORRECTION_BIT9); + if ((CTSU_REG_TRIMA > CTSU_CORRECTION_RTRIM_THRESHOLD1) && (trimb_byte >= CTSU_CORRECTION_TRIMB_THRESHOLD1)) + { + /* Minus2 : bit8(0.50) set 1 */ + error_registance[i] = (error_registance[i] | CTSU_CORRECTION_BIT8); + } + else + { + /* Plus : bit9(1.00) set 1 */ + error_registance[i] = (error_registance[i] | CTSU_CORRECTION_BIT9); + } } else { - /* Minus : bit8(0.50) and bit7(0.25) set 1 */ - error_registance[i] = (uint16_t) (trimb_byte | CTSU_CORRECTION_BIT7 | CTSU_CORRECTION_BIT8); + if ((CTSU_REG_TRIMA < CTSU_CORRECTION_RTRIM_THRESHOLD2) && (trimb_byte <= CTSU_CORRECTION_TRIMB_THRESHOLD2)) + { + /* Plus2 : bit7(0.25) and bit9(1.00) set 1 */ + error_registance[i] = (error_registance[i] | CTSU_CORRECTION_BIT7 | CTSU_CORRECTION_BIT9); + } + else + { + /* Minus : bit8(0.50) and bit7(0.25) set 1 */ + error_registance[i] = (error_registance[i] | CTSU_CORRECTION_BIT7 | CTSU_CORRECTION_BIT8); + } } - /* Reverse sign, and 6-bit left shift, 512 to 32768 */ + /* 6-bit left shift, 512 to 32768 */ error_registance[i] = (uint16_t) (error_registance[i] << (CTSU_SHIFT_AMOUNT - 9)); } @@ -1744,7 +1896,7 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) /* 1.25uA * (j + 1), SUCARRY is required for greater than 10uA */ for (j = 0; j < CTSU_CORRECTION_POINT_NUM; j++) { - R_CTSU->CTSUCRA_b.FCMODE = 0; + R_CTSU->CTSUCRA_b.SDPSEL = 0; if (8 > j) { R_CTSU->CTSUSUCLK0 = (uint16_t) (((j + 1) * CTSU_CORRECTION_SUMULTI) - 1); @@ -1756,16 +1908,10 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) R_CTSU->CTSUSUCLK0 = (uint16_t) (((j - 3) * CTSU_CORRECTION_SUMULTI) - 1); } - R_CTSU->CTSUCRA_b.FCMODE = 1; + R_CTSU->CTSUCRA_b.SDPSEL = 1; ctsu_correction_measurement(p_instance_ctrl, &g_ctsu_correction_info.dac_value[j]); } - R_CTSU->CTSUCRB_b.SSCNT = 0; - R_CTSU->CTSUCALIB_b.SUCARRY = 0; - R_CTSU->CTSUCALIB_b.CCOCALIB = 0; - R_CTSU->CTSUCALIB_b.CCOCLK = 1; - R_CTSU->CTSUCALIB_b.TSOC = 0; - /* Step4 : Calculate the coefficient between step2 and step3. */ for (i = 0; i < CTSU_RANGE_NUM; i++) { @@ -1825,9 +1971,6 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) R_CTSU->CTSUCR1 |= (CTSU_MODE_SELF_MULTI_SCAN << 6); R_CTSU->CTSUCHAC[0] = 0x01; - /* Initialize CTSU hardware control block */ - R_CTSU->CTSUCR0 |= 0x10; - g_ctsu_correction_info.ctsuwr.ctsussc = (CTSU_SSDIV_0500 << 8); g_ctsu_correction_info.ctsuwr.ctsuso0 = 0x0000; @@ -1835,7 +1978,8 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) g_ctsu_correction_info.ctsuwr.ctsuso1 = (uint16_t) ((CTSU_ICOG_66 << 13) | (ctsu_sdpa << 8) | CTSU_RICOA_RECOMMEND); /* Correction measurement setting */ - CTSU_REGISTER_CTSUERRS |= (uint16_t) CTSU_CTSUERRS_VALUE; + R_CTSU->CTSUERRS_b.CTSUSPMD = 2; + R_CTSU->CTSUERRS_b.CTSUTSOC = 1; R_BSP_SoftwareDelay(CTSU_WAIT_TIME, BSP_DELAY_UNITS_MICROSECONDS); /* First value measurement */ @@ -1871,7 +2015,9 @@ void ctsu_correction_process (ctsu_instance_ctrl_t * const p_instance_ctrl) #endif /* Normal measurement setting */ - CTSU_REGISTER_CTSUERRS = (uint16_t) 0x0000; + R_CTSU->CTSUERRS_b.CTSUTSOC = 0; + R_CTSU->CTSUERRS_b.CTSUSPMD = 0; + R_BSP_SoftwareDelay(CTSU_WAIT_TIME, BSP_DELAY_UNITS_MICROSECONDS); if ((0 != g_ctsu_correction_info.first_val) && (0 != g_ctsu_correction_info.second_val)) @@ -1949,6 +2095,7 @@ void ctsu_correction_scan_start (void) /* Setting time of measurement */ g_ctsu_correction_info.ctsuwr.ctsuso = (CTSU_SNUM_RECOMMEND << 10); + g_ctsu_correction_info.suadj0 = (uint8_t) (R_CTSU->CTSUSUCLK0 & CTSU_SUADJ_MAX); if (g_ctsu_correction_info.scan_index < CTSU_CORRECTION_POINT_NUM) { @@ -1957,7 +2104,7 @@ void ctsu_correction_scan_start (void) R_CTSU->CTSUCALIB_b.CCOCALIB = 1; R_CTSU->CTSUCALIB_b.TSOC = 1; - R_CTSU->CTSUCRA_b.FCMODE = 0; + R_CTSU->CTSUCRA_b.SDPSEL = 0; if (8 > g_ctsu_correction_info.scan_index) { R_CTSU->CTSUSUCLK0 = (uint16_t) (((g_ctsu_correction_info.scan_index + 1) * CTSU_CORRECTION_SUMULTI) - 1); @@ -1971,7 +2118,11 @@ void ctsu_correction_scan_start (void) (uint16_t) (((g_ctsu_correction_info.scan_index - 3) * CTSU_CORRECTION_SUMULTI) - 1); } - R_CTSU->CTSUCRA_b.FCMODE = 1; + R_CTSU->CTSUCRA_b.SDPSEL = 1; + + /* Dummy setting */ + R_CTSU->CTSUCHACA = 1; + R_CTSU->CTSUCHACB = 0; } else { @@ -2067,6 +2218,26 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) int16_t dir = 0; uint16_t comp = 0; + adctdr_sum = 0; + for (i = 0; i < CTSU_CALIB_AVERAGE_TIME; i++) + { + p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_api->scanStart( + p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_ctrl); + + /* Wait for conversion to complete. */ + status.state = ADC_STATE_SCAN_IN_PROGRESS; + while (ADC_STATE_SCAN_IN_PROGRESS == status.state) + { + p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_api->scanStatusGet( + p_instance_ctrl->p_ctsu_cfg->p_adc_instance->p_ctrl, + &status); + } + + adctdr_sum += (uint32_t) (CTSU_REG_ADCTDR); + } + + g_ctsu_correction_info.tscap_voltage = (uint16_t) ((adctdr_sum * 10) / CTSU_CALIB_AVERAGE_TIME); + /* Self single scan mode */ R_CTSU->CTSUCRA_b.LOAD = 1; R_CTSU->CTSUCRA_b.MD0 = 0; @@ -2111,7 +2282,7 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) adctdr_sum += (uint32_t) (CTSU_REG_ADCTDR); } - adctdr_ave = (uint16_t) (adctdr_sum / CTSU_CALIB_AVERAGE_TIME); + adctdr_ave = (uint16_t) ((adctdr_sum * 10) / CTSU_CALIB_AVERAGE_TIME); diff = (int16_t) (adctdr_ave - CTSU_CALIB_REF); /* The change unit of the voltage by the RTRIM register is about 4mV (4096 * 4) = 16.384 */ @@ -2151,6 +2322,35 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl) R_CTSU->CTSUCRA_b.DCBACK = 0; } +/*********************************************************************************************************************** + * ctsu_correction_offset_adjust + ***********************************************************************************************************************/ +void ctsu_correction_offset_adjust (uint16_t * p_adj_data, uint16_t raw_data, int32_t offset_error) +{ + if (offset_error > 0) + { + if (0 > (int32_t) (raw_data - offset_error)) + { + *p_adj_data = (uint16_t) (raw_data - offset_error); + } + else + { + *p_adj_data = 0; + } + } + else + { + if (CTSU_COUNT_MAX < (int32_t) (raw_data - offset_error)) + { + *p_adj_data = CTSU_COUNT_MAX; + } + else + { + *p_adj_data = (uint16_t) (raw_data - offset_error); + } + } +} + #endif #endif #endif @@ -2185,6 +2385,7 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c { calc_flag = 1; } + #else if (CTSU_CORRECTION_COMPLETE == g_ctsu_correction_info.status) { @@ -2220,7 +2421,7 @@ void ctsu_correction_calc (uint16_t * correction_data, uint16_t raw_data, ctsu_c /* Get difference of Correction coefficient */ diff_coefficient = - (int32_t) (g_ctsu_correction_info.second_coefficient - g_ctsu_correction_info.first_coefficient); + (int32_t) (g_ctsu_correction_info.first_coefficient - g_ctsu_correction_info.second_coefficient); /* Get multiplication of g_diff_cofficient and (g_ctsu_correction_info.first_val - raw_data_coff) */ mul_diffcoff_diff1valsval = (diff_coefficient * (int32_t) (g_ctsu_correction_info.first_val - cmp_data)); @@ -2370,6 +2571,18 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) ctsuso = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI) + i].ctsuso & CTSU_TUNING_MAX); multi.offset[i] = (ctsuso * (uint32_t) (CTSU_CORRECTION_OFFSET_UNIT >> multi.calc.range)); + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + + /* Correction offset current by TSCAP voltage error */ + multi.offset_error[i] = + (int32_t) ((g_ctsu_correction_info.tscap_voltage << CTSU_SHIFT_AMOUNT) / CTSU_CALIB_REF); + multi.offset_error[i] = + (int32_t) (((multi.offset[i] * (uint32_t) multi.offset_error[i]) >> CTSU_SHIFT_AMOUNT) - + multi.offset[i]); + multi.offset[i] = (multi.offset[i] + (uint32_t) multi.offset_error[i]); + #endif + #endif } #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) @@ -2379,6 +2592,13 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { multi.pri[i] = p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i]; + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + ctsu_correction_offset_adjust(&multi.pri[i], + p_instance_ctrl->p_self_raw[(element_id * CTSU_CFG_NUM_SUMULTI) + i], + multi.offset_error[i]); + #endif + #endif multi.snd[i] = 0; } @@ -2399,7 +2619,14 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) if (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->p_ctsu_cfg->md) { - ctsu_correction_calc(p_self_work, *(p_instance_ctrl->p_self_raw + element_id), &multi.calc); + multi.pri[0] = p_instance_ctrl->p_self_raw[element_id]; + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + ctsu_correction_offset_adjust(&multi.pri[0], p_instance_ctrl->p_self_raw[element_id], + multi.offset_error[0]); + #endif + #endif + ctsu_correction_calc(p_self_work, multi.pri[0], &multi.calc); } #endif #if (CTSU_CFG_NUM_MUTUAL_ELEMENTS != 0) @@ -2411,6 +2638,18 @@ void ctsu_correction_exec (ctsu_instance_ctrl_t * const p_instance_ctrl) { multi.pri[i] = p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2)]; multi.snd[i] = p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + (i * 2) + 1]; + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + ctsu_correction_offset_adjust(&multi.pri[i], + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + + (i * 2)], + multi.offset_error[i]); + ctsu_correction_offset_adjust(&multi.snd[i], + p_instance_ctrl->p_mutual_raw[(element_id * CTSU_MUTUAL_BUF_SIZE) + + (i * 2) + 1], + multi.offset_error[i]); + #endif + #endif } if (CTSU_TUNING_COMPLETE == p_instance_ctrl->tuning) @@ -2663,9 +2902,9 @@ void ctsu_corrcfc_process (ctsu_instance_ctrl_t * const p_instance_ctrl) for (j = 0; j < CTSU_CORRCFC_POINT_NUM; j++) { - R_CTSU->CTSUCRA_b.FCMODE = 0; + R_CTSU->CTSUCRA_b.SDPSEL = 0; R_CTSU->CTSUSUCLK0 = (uint16_t) (((j + CTSU_CORRCFC_CENTER_POINT) * CTSU_CORRECTION_SUMULTI) - 1); - R_CTSU->CTSUCRA_b.FCMODE = 1; + R_CTSU->CTSUCRA_b.SDPSEL = 1; ctsu_corrcfc_measurement(p_instance_ctrl, &g_ctsu_corrcfc_info.value[index][j], CTSU_CORRCFC_POINT_NUM); } diff --git a/ra/fsp/src/r_dmac/r_dmac.c b/ra/fsp/src/r_dmac/r_dmac.c index 7c933528e..62eb45b24 100644 --- a/ra/fsp/src/r_dmac/r_dmac.c +++ b/ra/fsp/src/r_dmac/r_dmac.c @@ -40,7 +40,8 @@ /* Calculate the mask bits for byte alignment from the transfer_size_t. */ #define DMAC_PRV_MASK_ALIGN_N_BYTES(x) ((1U << (x)) - 1U) -#define DMAC_PRV_REG(ch) ((R_DMAC0_Type *) ((R_DMAC1 - R_DMAC0) * ch + R_DMAC0)) +#define DMAC_PRV_REG(ch) ((R_DMAC0_Type *) (((uint32_t) R_DMAC1 - (uint32_t) R_DMAC0) * ch + \ + (uint32_t) R_DMAC0)) /* Transfer Count Register A Bit Field Definitions */ #define DMAC_PRV_DMCRA_LOW_OFFSET (0U) @@ -182,6 +183,7 @@ fsp_err_t R_DMAC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const /* Enable DMAC Operation. */ R_BSP_MODULE_START(FSP_IP_DMAC, p_extend->channel); + R_DMA->DMAST = 1; /* Configure the transfer settings. */ diff --git a/ra/fsp/src/r_doc/r_doc.c b/ra/fsp/src/r_doc/r_doc.c index 4ba0c4271..6cd3715cb 100644 --- a/ra/fsp/src/r_doc/r_doc.c +++ b/ra/fsp/src/r_doc/r_doc.c @@ -37,6 +37,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile doc_prv_ns_callback)(doc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile doc_prv_ns_callback)(doc_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -63,11 +69,12 @@ static const fsp_version_t g_doc_version = const doc_api_t g_doc_on_doc = { - .open = R_DOC_Open, - .close = R_DOC_Close, - .statusGet = R_DOC_StatusGet, - .write = R_DOC_Write, - .versionGet = R_DOC_VersionGet, + .open = R_DOC_Open, + .close = R_DOC_Close, + .statusGet = R_DOC_StatusGet, + .write = R_DOC_Write, + .versionGet = R_DOC_VersionGet, + .callbackSet = R_DOC_CallbackSet, }; /*********************************************************************************************************************** @@ -107,6 +114,14 @@ fsp_err_t R_DOC_Open (doc_ctrl_t * const p_api_ctrl, doc_cfg_t const * const p_c /* save pointers for later use */ p_ctrl->p_cfg = p_cfg; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_ctrl->callback_is_secure = true; +#endif + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; /* Power on the DOC module. */ R_BSP_MODULE_START(FSP_IP_DOC, 0); @@ -239,6 +254,44 @@ fsp_err_t R_DOC_VersionGet (fsp_version_t * const p_version) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements doc_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_DOC_CallbackSet (doc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(doc_callback_args_t *), + void const * const p_context, + doc_callback_args_t * const p_callback_memory) +{ + doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) p_api_ctrl; + +#if (DOC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(DOC_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * @} (end addtogroup DOC) **********************************************************************************************************************/ @@ -262,14 +315,51 @@ void doc_int_isr (void) doc_instance_ctrl_t * p_ctrl = (doc_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - /* Call the callback */ - doc_callback_args_t cb_data; + /* Call callback */ + doc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + doc_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD - /* Set data to identify callback to the user. */ - cb_data.p_context = p_ctrl->p_cfg->p_context; + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + doc_prv_ns_callback p_callback = (doc_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else - /* Call the callback. */ - p_ctrl->p_cfg->p_callback(&cb_data); + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } /* clear DOPCF flag */ R_DOC->DOCR = (uint8_t) (R_DOC_DOCR_DOPCFCL_Msk | (p_ctrl->p_cfg->event)); diff --git a/ra/fsp/src/r_dtc/r_dtc.c b/ra/fsp/src/r_dtc/r_dtc.c index e7770a337..c02b0b1d5 100644 --- a/ra/fsp/src/r_dtc/r_dtc.c +++ b/ra/fsp/src/r_dtc/r_dtc.c @@ -264,7 +264,11 @@ fsp_err_t R_DTC_Reset (transfer_ctrl_t * const p_api_ctrl, /* Disable read skip prior to modifying settings. It will be enabled later * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE; +#else R_DTC->DTCCR = DTC_PRV_RRS_DISABLE; +#endif /* Reset transfer based on input parameters. */ if (NULL != p_src) @@ -291,7 +295,11 @@ fsp_err_t R_DTC_Reset (transfer_ctrl_t * const p_api_ctrl, } /* Enable read skip after all settings are written. */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE; +#else R_DTC->DTCCR = DTC_PRV_RRS_ENABLE; +#endif /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */ /* Enable transfers on this activation source. */ @@ -518,7 +526,11 @@ static void r_dtc_state_initialize (void) memset(&gp_dtc_vector_table, 0U, DTC_VECTOR_TABLE_ENTRIES * sizeof(transfer_info_t *)); /* Set DTC vector table. */ - R_DTC->DTCVBR = (uint32_t) &gp_dtc_vector_table; +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCVBR_SEC = (uint32_t) gp_dtc_vector_table; +#else + R_DTC->DTCVBR = (uint32_t) gp_dtc_vector_table; +#endif /* Enable the DTC Peripheral */ R_DTC->DTCST = 1U; @@ -535,13 +547,21 @@ static void r_dtc_set_info (dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_in /* Disable read skip prior to modifying settings. It will be enabled later * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE; +#else R_DTC->DTCCR = DTC_PRV_RRS_DISABLE; +#endif /* Update the entry in the DTC Vector table. */ gp_dtc_vector_table[p_ctrl->irq] = p_info; /* Enable read skip after all settings are written. */ +#if DTC_PRV_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE; +#else R_DTC->DTCCR = DTC_PRV_RRS_ENABLE; +#endif } /*******************************************************************************************************************//** diff --git a/ra/fsp/src/r_ether/r_ether.c b/ra/fsp/src/r_ether/r_ether.c index cdec7b6b9..b4d865aaf 100644 --- a/ra/fsp/src/r_ether/r_ether.c +++ b/ra/fsp/src/r_ether/r_ether.c @@ -309,7 +309,8 @@ fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p i < (p_instance_ctrl->p_ether_cfg->num_tx_descriptors + p_instance_ctrl->p_ether_cfg->num_rx_descriptors); i++) { - memset(p_instance_ctrl->p_ether_cfg->pp_ether_buffers[i], 0x00, + memset(p_instance_ctrl->p_ether_cfg->pp_ether_buffers[i], + 0x00, p_instance_ctrl->p_ether_cfg->ether_buffer_size); } @@ -1530,7 +1531,9 @@ static fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, c * Enable PAUSE for full duplex link depending on * the pause resolution results */ - ether_pause_resolution(local_pause_bits, partner_pause_bits, &transmit_pause_set, + ether_pause_resolution(local_pause_bits, + partner_pause_bits, + &transmit_pause_set, &receive_pause_set); if (ETHER_PAUSE_XMIT_ON == transmit_pause_set) diff --git a/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c b/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c index 1f554677b..4d3192033 100644 --- a/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c +++ b/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c @@ -37,8 +37,13 @@ ***********************************************************************************************************************/ /* Vendor Specific PHY Registers */ - #define ETHER_PHY_REG_INTERRUPT_CONTROL (0x1B) - #define ETHER_PHY_REG_PHY_CONTROL2 (0x1F) + #define ETHER_PHY_REG_INTERRUPT_CONTROL (0x1B) + #define ETHER_PHY_REG_PHY_CONTROL2 (0x1F) + + #define ETHER_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET (0x8) + #define ETHER_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET (0xA) + #define ETHER_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET (0x7) + #define ETHER_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET (0x9) /*********************************************************************************************************************** * Exported global variables (to be accessed by other files) @@ -75,17 +80,20 @@ void ether_phy_targets_initialize (ether_phy_instance_ctrl_t * p_instance_ctrl) * b10=1:Enable link-down interrupt * b8=1 :Enable link-up interrupt */ - ether_phy_write(p_instance_ctrl, ETHER_PHY_REG_INTERRUPT_CONTROL, 0x0500); + ether_phy_write(p_instance_ctrl, + ETHER_PHY_REG_INTERRUPT_CONTROL, + (0x1 << ETHER_PHY_REG_INTERRUPT_CONTROL_LUIE_OFFSET | 0x1 << + ETHER_PHY_REG_INTERRUPT_CONTROL_LDIE_OFFSET)); ether_phy_read(p_instance_ctrl, ETHER_PHY_REG_INTERRUPT_CONTROL); reg = ether_phy_read(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL2); /* b7=1:RMII 50MHz clock mode; clock input to XI(pin 9) is 50MHz */ #if (ETHER_PHY_CFG_USE_REF_CLK == 0) - reg |= 0x0080; + reg |= (0x1 << ETHER_PHY_REG_PHY_CONTROL2_RMII_RCS_OFFSET); #endif /* b9=0:Interrupt pin active low */ - reg &= 0xfdff; + reg &= (uint16_t) ~ETHER_PHY_REG_PHY_CONTROL2_RMII_IL_OFFSET; ether_phy_write(p_instance_ctrl, ETHER_PHY_REG_PHY_CONTROL2, reg); } /* End of function ether_phy_targets_initialize() */ diff --git a/ra/fsp/src/r_flash_hp/r_flash_hp.c b/ra/fsp/src/r_flash_hp/r_flash_hp.c index 2d5c68e2b..e5db8e648 100644 --- a/ra/fsp/src/r_flash_hp/r_flash_hp.c +++ b/ra/fsp/src/r_flash_hp/r_flash_hp.c @@ -32,6 +32,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile flash_hp_prv_ns_callback)(flash_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile flash_hp_prv_ns_callback)(flash_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Macro definitions **********************************************************************************************************************/ @@ -95,7 +101,11 @@ /** Configuration set Command offset*/ #define FLASH_HP_FCU_CONFIG_SET_ID_BYTE (0x0000A150U) -#define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP (0x0000A160U) +#if !(defined(BSP_MCU_GROUP_RA6M4) || defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA4M2)) + #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP (0x0000A160U) +#else + #define FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP (0x0100A130U) +#endif /* Zero based offset into g_configuration_area_data[] for FAWS */ #define FLASH_HP_FCU_CONFIG_SET_FAWS_OFFSET (2U) @@ -126,6 +136,11 @@ #define FLASH_HP_FENTRYR_READ_MODE (0xAA00U) +#define FLASH_HP_FMEPROT_LOCK (0xD901) +#define FLASH_HP_FMEPROT_UNLOCK (0xD900) + +#define FLASH_HP_OFS_SAS_MASK (0x7FFFU) + #define FLASH_HP_FAEINT_DFAEIE (0x08) #define FLASH_HP_FAEINT_CMDLKIE (0x10) #define FLASH_HP_FAEINT_CFAEIE (0x80) @@ -173,7 +188,8 @@ #if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) static uint16_t g_configuration_area_data[FLASH_HP_CONFIG_SET_ACCESS_WORD_CNT] = {UINT16_MAX}; #endif -#define FLASH_LP_DF_START_ADDRESS (0x40100000) + +#define FLASH_HP_DF_START_ADDRESS (BSP_FEATURE_FLASH_DATA_FLASH_START) static const flash_block_info_t g_code_flash_macro_info[] = { @@ -199,8 +215,8 @@ static const flash_regions_t g_flash_code_region = const flash_block_info_t g_data_flash_macro_info = { - .block_section_st_addr = FLASH_LP_DF_START_ADDRESS, - .block_section_end_addr = FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES - 1, + .block_section_st_addr = FLASH_HP_DF_START_ADDRESS, + .block_section_end_addr = FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES - 1, .block_size = FLASH_HP_DATA_BLOCK_SIZE, .block_size_write = BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE }; @@ -240,6 +256,8 @@ static fsp_err_t flash_hp_write_data(flash_hp_instance_ctrl_t * const p_ctrl, ui static fsp_err_t flash_hp_check_errors(fsp_err_t previous_error, uint32_t error_bits, fsp_err_t return_error) PLACE_IN_RAM_SECTION; +static void r_flash_hp_call_callback(flash_hp_instance_ctrl_t * p_ctrl, flash_event_t event); + #if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) static fsp_err_t flash_hp_df_blank_check(flash_hp_instance_ctrl_t * const p_ctrl, @@ -286,10 +304,10 @@ static fsp_err_t flash_hp_set_id_code(flash_hp_instance_ctrl_t * p_ctrl, static fsp_err_t r_flash_hp_common_parameter_checking(flash_hp_instance_ctrl_t * const p_ctrl); -static fsp_err_t r_flash_hp_write_read_bc_parameter_checking(flash_hp_instance_ctrl_t * const p_ctrl, - uint32_t flash_address, - uint32_t const num_bytes, - bool check_write); +static fsp_err_t r_flash_hp_write_bc_parameter_checking(flash_hp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write); #endif @@ -312,6 +330,7 @@ const flash_api_t g_flash_on_flash_hp = .reset = R_FLASH_HP_Reset, .startupAreaSelect = R_FLASH_HP_StartUpAreaSelect, .updateFlashClockFreq = R_FLASH_HP_UpdateFlashClockFreq, + .callbackSet = R_FLASH_HP_CallbackSet, .versionGet = R_FLASH_HP_VersionGet }; @@ -366,15 +385,24 @@ fsp_err_t R_FLASH_HP_Open (flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * { FSP_ERROR_RETURN(p_cfg->irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); FSP_ERROR_RETURN(p_cfg->err_irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); - FSP_ASSERT(p_cfg->p_callback); } #endif /* Set the parameters struct based on the user supplied settings */ p_ctrl->p_cfg = p_cfg; - if (p_cfg->data_flash_bgo) + if (true == p_cfg->data_flash_bgo) { + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + +#if BSP_TZ_SECURE_BUILD + + /* If a callback is not supplied this will get set during callbackSet */ + p_ctrl->callback_is_secure = true; +#endif + /* Enable FCU interrupts. */ R_FACI_HP->FRDYIE = 1U; R_BSP_IrqCfgEnable(p_cfg->irq, p_cfg->ipl, p_ctrl); @@ -434,7 +462,7 @@ fsp_err_t R_FLASH_HP_Write (flash_ctrl_t * const p_api_ctrl, #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) /* Verify write parameters. If failure return error. */ - err = r_flash_hp_write_read_bc_parameter_checking(p_ctrl, flash_address, num_bytes, true); + err = r_flash_hp_write_bc_parameter_checking(p_ctrl, flash_address, num_bytes, true); FSP_ERROR_RETURN((err == FSP_SUCCESS), err); #endif @@ -501,6 +529,11 @@ fsp_err_t R_FLASH_HP_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const addr err = r_flash_hp_common_parameter_checking(p_ctrl); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + if (true == p_ctrl->p_cfg->data_flash_bgo) + { + FSP_ASSERT(NULL != p_ctrl->p_callback); + } + /* If invalid number of blocks return error. */ FSP_ERROR_RETURN(num_blocks != 0U, FSP_ERR_INVALID_BLOCKS); #endif @@ -549,11 +582,11 @@ fsp_err_t R_FLASH_HP_Erase (flash_ctrl_t * const p_api_ctrl, uint32_t const addr #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) uint32_t num_bytes = num_blocks * BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE; - FSP_ERROR_RETURN((start_address >= (FLASH_LP_DF_START_ADDRESS)) && - (start_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERROR_RETURN((start_address >= (FLASH_HP_DF_START_ADDRESS)) && + (start_address < (FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), FSP_ERR_INVALID_ADDRESS); - FSP_ERROR_RETURN(start_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES), + FSP_ERROR_RETURN(start_address + num_bytes <= (FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES), FSP_ERR_INVALID_BLOCKS); #endif @@ -599,7 +632,7 @@ fsp_err_t R_FLASH_HP_BlankCheck (flash_ctrl_t * const p_api_ctrl, #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE == 1) /* Check parameters. If failure return error */ - err = r_flash_hp_write_read_bc_parameter_checking(p_ctrl, address, num_bytes, false); + err = r_flash_hp_write_bc_parameter_checking(p_ctrl, address, num_bytes, false); FSP_ERROR_RETURN((err == FSP_SUCCESS), err); #endif @@ -697,7 +730,7 @@ fsp_err_t R_FLASH_HP_IdCodeSet (flash_ctrl_t * const p_api_ctrl, fsp_err_t err = FSP_SUCCESS; -#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ID_CODE == 1) #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) /* Verify the id bytes are not in code flash. They will not be available in P/E mode. */ @@ -754,7 +787,7 @@ fsp_err_t R_FLASH_HP_AccessWindowSet (flash_ctrl_t * const p_api_ctrl, fsp_err_t err = FSP_SUCCESS; -#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW == 1) #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) /* Verify the control block is not null and is opened. */ @@ -806,7 +839,7 @@ fsp_err_t R_FLASH_HP_AccessWindowClear (flash_ctrl_t * const p_api_ctrl) fsp_err_t err = FSP_SUCCESS; -#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) && (BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW == 1) #if (FLASH_HP_CFG_PARAM_CHECKING_ENABLE) /* Verify the control block is not null and is opened. */ @@ -1019,6 +1052,51 @@ fsp_err_t R_FLASH_HP_Close (flash_ctrl_t * const p_api_ctrl) return err; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref flash_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_HP_CallbackSet (flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void const * const p_context, + flash_callback_args_t * const p_callback_memory) +{ + flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) p_api_ctrl; + +#if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(FLASH_HP_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if FLASH_HP_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + flash_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * This function gets FLASH HAL driver version * @retval FSP_SUCCESS Operation performed successfully @@ -1277,10 +1355,10 @@ static fsp_err_t flash_hp_df_write (flash_hp_instance_ctrl_t * const p_ctrl) * the maximum range. * @retval FSP_ERR_INVALID_ADDRESS Invalid address was input or address not on programming boundary. **********************************************************************************************************************/ -static fsp_err_t r_flash_hp_write_read_bc_parameter_checking (flash_hp_instance_ctrl_t * const p_ctrl, - uint32_t flash_address, - uint32_t const num_bytes, - bool check_write) +static fsp_err_t r_flash_hp_write_bc_parameter_checking (flash_hp_instance_ctrl_t * const p_ctrl, + uint32_t flash_address, + uint32_t const num_bytes, + bool check_write) { /* Verify the control block is not null and is opened. Verify the flash isn't in use. */ fsp_err_t err = r_flash_hp_common_parameter_checking(p_ctrl); @@ -1288,6 +1366,11 @@ static fsp_err_t r_flash_hp_write_read_bc_parameter_checking (flash_hp_instance_ uint32_t write_size; + if (p_ctrl->p_cfg->data_flash_bgo == true) + { + FSP_ASSERT(NULL != p_ctrl->p_callback); + } + /* If invalid address or number of bytes return error. */ #if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) if (flash_address < BSP_ROM_SIZE_BYTES) @@ -1299,10 +1382,10 @@ static fsp_err_t r_flash_hp_write_read_bc_parameter_checking (flash_hp_instance_ #endif { #if (FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE == 1) - FSP_ERROR_RETURN((flash_address >= (FLASH_LP_DF_START_ADDRESS)) && - (flash_address < (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERROR_RETURN((flash_address >= (FLASH_HP_DF_START_ADDRESS)) && + (flash_address < (FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), FSP_ERR_INVALID_ADDRESS); - FSP_ERROR_RETURN((flash_address + num_bytes <= (FLASH_LP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), + FSP_ERROR_RETURN((flash_address + num_bytes <= (FLASH_HP_DF_START_ADDRESS + BSP_DATA_FLASH_SIZE_BYTES)), FSP_ERR_INVALID_SIZE); write_size = BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE; #else @@ -1757,12 +1840,11 @@ static fsp_err_t flash_hp_pe_mode_exit () /* If the device is coming out of code flash p/e mode restore the flash cache state. */ if (FLASH_HP_FENTRYR_CF_PE_MODE == pe_mode) { - /* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash - * Cache in the RA6M3 manual R01UH0878EJ0100). */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); +#if BSP_FEATURE_FLASH_HP_HAS_FMEPROT + R_FACI_HP->FMEPROT = FLASH_HP_FMEPROT_LOCK; +#endif - R_FCACHE->FCACHEE = 1U; + R_BSP_FlashCacheEnable(); } /* If a command locked state was detected earlier, then return that error. */ @@ -2006,10 +2088,6 @@ static fsp_err_t flash_hp_set_startup_area_boot (flash_hp_instance_ctrl_t * p_ct flash_startup_area_swap_t swap_type, bool is_temporary) { - /* Do not call functions with multiple volatile parameters. */ - uint32_t faws = R_FACI_HP->FAWMON_b.FAWS; - uint32_t fawe = R_FACI_HP->FAWMON_b.FAWE; - /* Update Flash state and enter Code Flash P/E mode */ fsp_err_t err = flash_hp_enter_pe_cf_mode(p_ctrl); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); @@ -2020,8 +2098,21 @@ static fsp_err_t flash_hp_set_startup_area_boot (flash_hp_instance_ctrl_t * p_ct } else { + // todo should FSUACR be cleared? + #if BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW + + /* Do not call functions with multiple volatile parameters. */ + uint32_t faws = R_FACI_HP->FAWMON_b.FAWS; + uint32_t fawe = R_FACI_HP->FAWMON_b.FAWE; + /* Configure the configuration area to be written. */ flash_hp_configuration_area_data_setup(~swap_type & 0x1, faws, fawe); + #else + memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data)); + + g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_FAWE_BTFLG_OFFSET] = + (uint16_t) (((((uint16_t) ~swap_type) & 0x1U) << 15U) | FLASH_HP_OFS_SAS_MASK); + #endif /* Write the configuration area to the access/startup region. */ err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_ACCESS_STARTUP); @@ -2164,13 +2255,11 @@ void fcu_fiferr_isr (void) { /* Save context if RTOS is used */ FSP_CONTEXT_SAVE - flash_callback_args_t cb_data; - IRQn_Type irq = R_FSP_CurrentIrqGet(); + flash_event_t event; + IRQn_Type irq = R_FSP_CurrentIrqGet(); flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - cb_data.p_context = p_ctrl->p_cfg->p_context; - uint32_t fastat = R_FACI_HP->FASTAT; uint32_t fstatr_errors = R_FACI_HP->FSTATR & FLASH_HP_FSTATR_ERROR_MASK; @@ -2178,28 +2267,28 @@ void fcu_fiferr_isr (void) /* Check for the data flash memory access violation flag. */ if (fastat & FLASH_HP_FASTAT_DFAE) { - cb_data.event = FLASH_EVENT_ERR_DF_ACCESS; + event = FLASH_EVENT_ERR_DF_ACCESS; } /* Check for the code flash memory access violation flag. */ else if (fastat & FLASH_HP_FASTAT_CFAE) { - cb_data.event = FLASH_EVENT_ERR_CF_ACCESS; + event = FLASH_EVENT_ERR_CF_ACCESS; } /* Check if the command Lock bit is set. */ else if (fastat & FLASH_HP_FASTAT_CMDLK) { if (fstatr_errors & (FLASH_HP_FSTATR_PRGERR | FLASH_HP_FSTATR_ERSERR)) { - cb_data.event = FLASH_EVENT_ERR_FAILURE; + event = FLASH_EVENT_ERR_FAILURE; } else { - cb_data.event = FLASH_EVENT_ERR_CMD_LOCKED; + event = FLASH_EVENT_ERR_CMD_LOCKED; } } else { - cb_data.event = FLASH_EVENT_ERR_FAILURE; + event = FLASH_EVENT_ERR_FAILURE; } /* Reset the FCU: This will stop any existing processes and exit PE mode*/ @@ -2209,7 +2298,7 @@ void fcu_fiferr_isr (void) R_BSP_IrqStatusClear(irq); /* Call the user callback. */ - p_ctrl->p_cfg->p_callback(&cb_data); + r_flash_hp_call_callback(p_ctrl, event); /* Restore context if RTOS is used */ FSP_CONTEXT_RESTORE @@ -2228,14 +2317,12 @@ void fcu_frdyi_isr (void) bool operation_completed = false; /*Wait counter used for DBFULL flag*/ - flash_callback_args_t cb_data; + flash_event_t event; IRQn_Type irq = R_FSP_CurrentIrqGet(); flash_hp_instance_ctrl_t * p_ctrl = (flash_hp_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - cb_data.p_context = p_ctrl->p_cfg->p_context; - /* Clear the Interrupt Request*/ R_BSP_IrqStatusClear(irq); @@ -2253,13 +2340,13 @@ void fcu_frdyi_isr (void) if (FSP_SUCCESS != err) { flash_hp_reset(p_ctrl); - cb_data.event = FLASH_EVENT_ERR_FAILURE; + event = FLASH_EVENT_ERR_FAILURE; } } /*Done writing all bytes*/ else { - cb_data.event = FLASH_EVENT_WRITE_COMPLETE; + event = FLASH_EVENT_WRITE_COMPLETE; operation_completed = true; } } @@ -2272,7 +2359,7 @@ void fcu_frdyi_isr (void) /* If all blocks are erased*/ else { - cb_data.event = FLASH_EVENT_ERASE_COMPLETE; + event = FLASH_EVENT_ERASE_COMPLETE; operation_completed = true; } } @@ -2282,11 +2369,11 @@ void fcu_frdyi_isr (void) operation_completed = true; if (R_FACI_HP->FBCSTAT == 0x01U) { - cb_data.event = FLASH_EVENT_NOT_BLANK; + event = FLASH_EVENT_NOT_BLANK; } else { - cb_data.event = FLASH_EVENT_BLANK; + event = FLASH_EVENT_BLANK; } } @@ -2300,12 +2387,66 @@ void fcu_frdyi_isr (void) p_ctrl->current_operation = FLASH_OPERATION_NON_BGO; /* Set data to identify callback to user, then call user callback. */ - p_ctrl->p_cfg->p_callback(&cb_data); + r_flash_hp_call_callback(p_ctrl, event); } FSP_CONTEXT_RESTORE } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to FLASH_HP instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_flash_hp_call_callback (flash_hp_instance_ctrl_t * p_ctrl, flash_event_t event) +{ + flash_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + flash_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + flash_hp_prv_ns_callback p_callback = (flash_hp_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * This function switches the peripheral to P/E mode for Data Flash. * @param[in] p_ctrl Pointer to the Flash control block. @@ -2367,8 +2508,10 @@ static fsp_err_t flash_hp_enter_pe_cf_mode (flash_hp_instance_ctrl_t * const p_c /* Timeout counter. */ volatile uint32_t wait_count = FLASH_HP_FRDY_CMD_TIMEOUT; - /* While the Flash API is in use we will disable the FLash Cache. */ - R_FCACHE->FCACHEE = 0U; + /* While the Flash API is in use we will disable the flash cache. */ + #if BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM + R_BSP_FlashCacheDisable(); + #endif /* If interrupts are being used then disable interrupts. */ if (p_ctrl->p_cfg->data_flash_bgo == true) @@ -2380,6 +2523,10 @@ static fsp_err_t flash_hp_enter_pe_cf_mode (flash_hp_instance_ctrl_t * const p_c R_BSP_IrqDisable(p_ctrl->p_cfg->err_irq); } + #if BSP_FEATURE_FLASH_HP_HAS_FMEPROT + R_FACI_HP->FMEPROT = FLASH_HP_FMEPROT_UNLOCK; + #endif + /* Enter code flash PE mode */ R_FACI_HP->FENTRYR = FLASH_HP_FENTRYR_TRANSITION_TO_CF_PE; @@ -2390,8 +2537,9 @@ static fsp_err_t flash_hp_enter_pe_cf_mode (flash_hp_instance_ctrl_t * const p_c /* Wait until FENTRYR is 0x0001UL unless timeout occurs. */ if (wait_count == 0U) { + /* if FENTRYR is not set after max timeout, FSP_ERR_PE_FAILURE*/ - err = FSP_ERR_PE_FAILURE; + return FSP_ERR_PE_FAILURE; } wait_count--; diff --git a/ra/fsp/src/r_flash_lp/r_flash_lp.c b/ra/fsp/src/r_flash_lp/r_flash_lp.c index 32fb1387c..c138bd791 100644 --- a/ra/fsp/src/r_flash_lp/r_flash_lp.c +++ b/ra/fsp/src/r_flash_lp/r_flash_lp.c @@ -327,6 +327,7 @@ const flash_api_t g_flash_on_flash_lp = .reset = R_FLASH_LP_Reset, .startupAreaSelect = R_FLASH_LP_StartUpAreaSelect, .updateFlashClockFreq = R_FLASH_LP_UpdateFlashClockFreq, + .callbackSet = R_FLASH_LP_CallbackSet, .versionGet = R_FLASH_LP_VersionGet }; @@ -1035,6 +1036,25 @@ fsp_err_t R_FLASH_LP_Close (flash_ctrl_t * const p_api_ctrl) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Stub function + * Implements @ref flash_api_t::callbackSet. + * + * @retval FSP_ERR_UNSUPPORTED Function has not been implemented. + **********************************************************************************************************************/ +fsp_err_t R_FLASH_LP_CallbackSet (flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void const * const p_context, + flash_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_callback_memory); + FSP_PARAMETER_NOT_USED(p_context); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * Get Flash LP driver version. * @@ -1788,13 +1808,7 @@ static fsp_err_t r_flash_lp_pe_mode_exit (flash_lp_instance_ctrl_t * const p_ctr if (flash_pe_mode == FLASH_LP_FENTRYR_CF_PE_MODE) { #if BSP_FEATURE_BSP_FLASH_CACHE - - /* Invalidate flash cache. */ - R_FCACHE->FCACHEIV = 1U; - FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); - - /* Enable flash cache. */ - R_FCACHE->FCACHEE = 1U; + R_BSP_FlashCacheEnable(); #endif #if BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER R_FACI_LP->PFBER = 1; @@ -2468,7 +2482,7 @@ void r_flash_lp_cf_enter_pe_mode (flash_lp_instance_ctrl_t * const p_ctrl) R_FACI_LP->PFBER = 0; #endif #if BSP_FEATURE_BSP_FLASH_CACHE - R_FCACHE->FCACHEE = 0U; + R_BSP_FlashCacheDisable(); #endif if (p_ctrl->p_cfg->data_flash_bgo) diff --git a/ra/fsp/src/r_gpt/r_gpt.c b/ra/fsp/src/r_gpt/r_gpt.c index 39bc1d9ee..b53ba0af4 100644 --- a/ra/fsp/src/r_gpt/r_gpt.c +++ b/ra/fsp/src/r_gpt/r_gpt.c @@ -90,6 +90,12 @@ typedef enum e_gpt_prv_capture_event GPT_PRV_CAPTURE_EVENT_B, } gpt_prv_capture_event_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile gpt_prv_ns_callback)(timer_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile gpt_prv_ns_callback)(timer_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -119,6 +125,8 @@ static uint32_t gpt_gtior_calculate(timer_cfg_t const * const p_cfg, gpt_pin_lev #endif +static void r_gpt_call_callback(gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture); + /*********************************************************************************************************************** * ISR prototypes **********************************************************************************************************************/ @@ -157,6 +165,7 @@ const timer_api_t g_timer_on_gpt = .dutyCycleSet = R_GPT_DutyCycleSet, .infoGet = R_GPT_InfoGet, .statusGet = R_GPT_StatusGet, + .callbackSet = R_GPT_CallbackSet, .close = R_GPT_Close, .versionGet = R_GPT_VersionGet }; @@ -725,6 +734,51 @@ fsp_err_t R_GPT_AdcTriggerSet (timer_ctrl_t * const p_ctrl, return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref timer_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_GPT_CallbackSet (timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + gpt_instance_ctrl_t * p_ctrl = (gpt_instance_ctrl_t *) p_api_ctrl; + +#if GPT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(GPT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if GPT_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close. * @@ -848,6 +902,15 @@ static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_ /* Save register base address. */ uint32_t base_address = (uint32_t) R_GPT0 + (p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0)); p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address; + +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->callback_is_secure = true; +#endif + + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; } /*******************************************************************************************************************//** @@ -879,7 +942,7 @@ static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl * RA6M3 manual R01UH0886EJ0100) and other registers required by the driver. */ /* Dividers for GPT are half the enum value. */ - uint32_t gtcr_tpcs = p_cfg->source_div >> 1; + uint32_t gtcr_tpcs = p_cfg->source_div; uint32_t gtcr = gtcr_tpcs << R_GPT0_GTCR_TPCS_Pos; /* Store period register setting. The actual period and is one cycle longer than the register value for saw waves @@ -1114,8 +1177,19 @@ static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctr uint32_t const duty_cycle_counts, gpt_prv_duty_registers_t * p_duty_reg) { - /* 0% and 100% duty cycle are supported in OADTY/OBDTY. */ + /* Determine the current period. The actual period is one cycle longer than the register value for saw waves + * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting + * Register (GTPR)". The setting passed to the configuration is expected to be half the desired duty cycle for + * triangle waves. */ uint32_t current_period = p_instance_ctrl->p_reg->GTPR; + #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE + if (p_instance_ctrl->p_cfg->mode < TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) + #endif + { + current_period++; + } + + /* 0% and 100% duty cycle are supported in OADTY/OBDTY. */ if (0U == duty_cycle_counts) { p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_0_PERCENT; @@ -1128,13 +1202,6 @@ static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctr { uint32_t temp_duty_cycle = duty_cycle_counts; - /* When the GPT_SHORTEST_LEVEL_ON is set, the high part of the PWM wave is at the end of the cycle. */ - gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend; - if (GPT_SHORTEST_LEVEL_ON == p_extend->shortest_pwm_signal) - { - temp_duty_cycle = current_period - temp_duty_cycle; - } - #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM) { @@ -1163,7 +1230,7 @@ static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctr static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ctrl) { /* Look up PCLKD frequency and divide it by GPT PCLKD divider. */ - timer_source_div_t pclk_divisor = (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS << 1); + timer_source_div_t pclk_divisor = (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS); uint32_t pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD); return pclk_freq_hz >> pclk_divisor; @@ -1181,20 +1248,14 @@ static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level) { /* The stop level is used as both the initial level and the stop level. */ - uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t) stop_level << GPT_PRV_GTIOR_STOP_LEVEL_BIT) | + uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t) stop_level << R_GPT0_GTIOR_OADFLT_Pos) | ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT); - uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END; - gpt_pin_level_t compare_match = GPT_PIN_LEVEL_LOW; + uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END; if (TIMER_MODE_PWM == p_cfg->mode) { - gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend; - if (GPT_SHORTEST_LEVEL_ON == p_extend->shortest_pwm_signal) - { - /* Output high after compare match when GPT_SHORTEST_LEVEL_ON is used to generate the shortest PWM duty cycle. */ - compare_match = GPT_PIN_LEVEL_HIGH; - } + /* Use default: GTIOn is high at cycle end, then low at compare match. */ } #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE @@ -1208,15 +1269,10 @@ static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_le /* In one-shot mode, the output pin goes high after the first compare match (one cycle after the timer starts counting). */ if (GPT_PIN_LEVEL_LOW == stop_level) { - compare_match = GPT_PIN_LEVEL_HIGH; + gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END; } } - if (compare_match == GPT_PIN_LEVEL_HIGH) - { - gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END; - } - gtior |= gtion; return gtior; @@ -1224,6 +1280,63 @@ static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_le #endif +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to GPT instance control block + * @param[in] event Event code + * @param[in] capture Event capture counts (if applicable) + **********************************************************************************************************************/ +static void r_gpt_call_callback (gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture) +{ + timer_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + timer_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->capture = capture; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + gpt_prv_ns_callback p_callback = (gpt_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * Common processing for input capture interrupt. * @@ -1256,13 +1369,11 @@ static void r_gpt_capture_common_isr (gpt_prv_capture_event_t event) } /* If a callback is provided, then call it with the captured counter value. */ - if (NULL != p_instance_ctrl->p_cfg->p_callback) + if (NULL != p_instance_ctrl->p_callback) { - timer_callback_args_t callback_args; - callback_args.event = (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event); - callback_args.capture = counter; - callback_args.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&callback_args); + r_gpt_call_callback(p_instance_ctrl, + (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event), + counter); } /* Restore context if RTOS is used */ @@ -1303,13 +1414,9 @@ void gpt_counter_overflow_isr (void) R_BSP_IrqClearPending(irq); } - if (NULL != p_instance_ctrl->p_cfg->p_callback) + if (NULL != p_instance_ctrl->p_callback) { - /* Set data to identify callback to user, then call user callback. */ - timer_callback_args_t callback_args; - callback_args.p_context = p_instance_ctrl->p_cfg->p_context; - callback_args.event = TIMER_EVENT_CYCLE_END; - p_instance_ctrl->p_cfg->p_callback(&callback_args); + r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_CYCLE_END, 0); } /* Restore context if RTOS is used */ @@ -1334,11 +1441,8 @@ void gpt_counter_underflow_isr (void) /* Recover ISR context saved in open. */ gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - /* Set data to identify callback to user, then call user callback. */ - timer_callback_args_t callback_args; - callback_args.p_context = p_instance_ctrl->p_cfg->p_context; - callback_args.event = TIMER_EVENT_TROUGH; - p_instance_ctrl->p_cfg->p_callback(&callback_args); + /* Call user callback. */ + r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_TROUGH, 0); /* Restore context if RTOS is used */ FSP_CONTEXT_RESTORE; diff --git a/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c b/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c index b9a033ded..d0be1682a 100644 --- a/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c +++ b/ra/fsp/src/r_gpt_three_phase/r_gpt_three_phase.c @@ -91,6 +91,7 @@ const three_phase_api_t g_gpt_three_phase_on_gpt_three_phase = .start = R_GPT_THREE_PHASE_Start, .reset = R_GPT_THREE_PHASE_Reset, .dutyCycleSet = R_GPT_THREE_PHASE_DutyCycleSet, + .callbackSet = R_GPT_THREE_PHASE_CallbackSet, .close = R_GPT_THREE_PHASE_Close, .versionGet = R_GPT_THREE_PHASE_VersionGet }; @@ -258,6 +259,9 @@ fsp_err_t R_GPT_THREE_PHASE_Reset (three_phase_ctrl_t * const p_ctrl) * In asymmetric PWM mode this enables both count-up and count-down PWM values to be set at trough (or crest) * exclusively. * + * @note It is recommended to call this function in a high-priority callback to ensure that it is not interrupted and + * that no GPT events occur during setting that would result in a duty cycle buffer load operation. + * * Example: * @snippet r_gpt_three_phase_example.c R_GPT_THREE_PHASE_DutyCycleSet * @@ -311,6 +315,37 @@ fsp_err_t R_GPT_THREE_PHASE_DutyCycleSet (three_phase_ctrl_t * const p_ctr return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback for the GPT U-channel with the option to provide memory for the callback argument + * structure. + * Implements @ref three_phase_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_GPT_THREE_PHASE_CallbackSet (three_phase_ctrl_t * const p_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory) +{ + gpt_three_phase_instance_ctrl_t * p_instance_ctrl = (gpt_three_phase_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if GPT_THREE_PHASE_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_callback); + FSP_ERROR_RETURN(GPT_THREE_PHASE_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + err = R_GPT_CallbackSet(p_instance_ctrl->p_cfg->p_timer_instance[p_instance_ctrl->p_cfg->callback_ch]->p_ctrl, + p_callback, + p_context, + p_callback_memory); + + return err; +} + /*******************************************************************************************************************//** * Stops counters, disables output pins, and clears internal driver data. Implements @ref three_phase_api_t::close. * diff --git a/ra/fsp/src/r_icu/r_icu.c b/ra/fsp/src/r_icu/r_icu.c index c23457f41..ed1d207a3 100644 --- a/ra/fsp/src/r_icu/r_icu.c +++ b/ra/fsp/src/r_icu/r_icu.c @@ -39,6 +39,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -64,11 +70,12 @@ static const fsp_version_t g_icu_version = /* ICU implementation of External IRQ API. */ const external_irq_api_t g_external_irq_on_icu = { - .open = R_ICU_ExternalIrqOpen, - .enable = R_ICU_ExternalIrqEnable, - .disable = R_ICU_ExternalIrqDisable, - .close = R_ICU_ExternalIrqClose, - .versionGet = R_ICU_ExternalIrqVersionGet + .open = R_ICU_ExternalIrqOpen, + .enable = R_ICU_ExternalIrqEnable, + .disable = R_ICU_ExternalIrqDisable, + .callbackSet = R_ICU_ExternalIrqCallbackSet, + .close = R_ICU_ExternalIrqClose, + .versionGet = R_ICU_ExternalIrqVersionGet }; /*******************************************************************************************************************//** @@ -121,6 +128,13 @@ fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, externa uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq]; R_ICU->IELSR[p_ctrl->irq] = 0; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_ctrl->p_callback_memory = NULL; + p_ctrl->callback_is_secure = true; +#endif + /* Initialize control block. */ p_ctrl->p_callback = p_cfg->p_callback; p_ctrl->p_context = p_cfg->p_context; @@ -207,6 +221,55 @@ fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements external_irq_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)( + external_irq_callback_args_t *), + void const * const p_context, + external_irq_callback_args_t * const p_callback_memory) +{ + icu_instance_ctrl_t * p_ctrl = p_api_ctrl; + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#else + FSP_PARAMETER_NOT_USED(p_callback_memory); +#endif + +#if ICU_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_callback); + + #if BSP_TZ_SECURE_BUILD + if (!callback_is_secure) + { + FSP_ASSERT(NULL != p_callback_memory); + } + #endif +#endif + +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = callback_is_secure; + p_ctrl->p_callback_memory = p_callback_memory; +#endif + + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Close the external interrupt channel. Implements @ref external_irq_api_t::close. * @@ -282,11 +345,43 @@ void r_icu_isr (void) if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback)) { +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + + external_irq_callback_args_t args; + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + args.channel = p_ctrl->channel; + args.p_context = p_ctrl->p_context; + p_ctrl->p_callback(&args); + } + else + { + /* Save current state of p_callback_args so that it can be shared between interrupts. */ + args = *p_ctrl->p_callback_memory; + + /* Set the callback args passed to the Non-secure calback. */ + p_ctrl->p_callback_memory->channel = p_ctrl->channel; + p_ctrl->p_callback_memory->p_context = p_ctrl->p_context; + + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + icu_prv_ns_callback p_callback = (icu_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_ctrl->p_callback_memory); + + /* Restore the state of p_callback_args. */ + *p_ctrl->p_callback_memory = args; + } + +#else + /* Set data to identify callback to user, then call user callback. */ external_irq_callback_args_t args; args.channel = p_ctrl->channel; args.p_context = p_ctrl->p_context; p_ctrl->p_callback(&args); +#endif } if (level_irq) diff --git a/ra/fsp/src/r_iic_master/r_iic_master.c b/ra/fsp/src/r_iic_master/r_iic_master.c index 2eb7b2a32..53903d916 100644 --- a/ra/fsp/src/r_iic_master/r_iic_master.c +++ b/ra/fsp/src/r_iic_master/r_iic_master.c @@ -133,6 +133,12 @@ typedef enum e_iic_master_transfer_dir_option IIC_MASTER_TRANSFER_DIR_READ = 0x1 } iic_master_transfer_dir_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile iic_master_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iic_master_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -195,7 +201,8 @@ i2c_master_api_t const g_i2c_master_on_iic = .abort = R_IIC_MASTER_Abort, .slaveAddressSet = R_IIC_MASTER_SlaveAddressSet, .close = R_IIC_MASTER_Close, - .versionGet = R_IIC_MASTER_VersionGet + .versionGet = R_IIC_MASTER_VersionGet, + .callbackSet = R_IIC_MASTER_CallbackSet }; /*******************************************************************************************************************//** @@ -210,14 +217,15 @@ i2c_master_api_t const g_i2c_master_on_iic = /*******************************************************************************************************************//** * Opens the I2C device. * - * @retval FSP_SUCCESS Requested clock rate was set exactly. - * @retval FSP_ERR_ALREADY_OPEN Module is already open. - * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: - * 1. p_api_ctrl or p_cfg is NULL. - * 2. extended parameter is NULL. - * 3. Callback parameter is NULL. - * 4. Set the rate to fast mode plus on a channel which does not support it. - * 5. Invalid IRQ number assigned + * @retval FSP_SUCCESS Requested clock rate was set exactly. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Set the rate to fast mode plus on a channel which does not support it. + * 5. Invalid IRQ number assigned **********************************************************************************************************************/ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg) { @@ -226,13 +234,14 @@ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cf FSP_ASSERT(p_api_ctrl != NULL); FSP_ASSERT(p_cfg != NULL); FSP_ASSERT(p_cfg->p_extend != NULL); - FSP_ASSERT(p_cfg->p_callback != NULL); FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->eri_irq >= (IRQn_Type) 0); FSP_ERROR_RETURN(IIC_MASTER_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ERROR_RETURN(BSP_FEATURE_IIC_VALID_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + /* If rate is configured as Fast mode plus, check whether the channel supports it */ if (I2C_MASTER_RATE_FASTPLUS == p_cfg->rate) { @@ -248,9 +257,15 @@ fsp_err_t R_IIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cf p_ctrl->timeout_mode = ((iic_master_extended_cfg_t *) p_cfg->p_extend)->timeout_mode; /* Record the pointer to the configuration structure for later use */ - p_ctrl->p_cfg = p_cfg; - p_ctrl->slave = p_cfg->slave; - p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = p_cfg->slave; + p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); @@ -408,6 +423,48 @@ fsp_err_t R_IIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, return err; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_master_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void const * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl; + +#if (IIC_MASTER_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE + if (!p_ctrl->callback_is_secure) + { + FSP_ASSERT(p_callback_memory); + } + #endif +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Closes the I2C device. May power down IIC peripheral. * This function will safely terminate any in-progress I2C transfers. @@ -511,6 +568,7 @@ static fsp_err_t iic_master_read_write (i2c_master_ctrl_t * const p_api_ctrl, #if IIC_MASTER_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_buffer != NULL); FSP_ERROR_RETURN((p_ctrl->open == IIC_MASTER_OPEN), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((iic_master_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); #if IIC_MASTER_CFG_DTC_ENABLE /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. @@ -566,11 +624,25 @@ static fsp_err_t iic_master_read_write (i2c_master_ctrl_t * const p_api_ctrl, **********************************************************************************************************************/ static void iic_master_notify (iic_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event) { - i2c_master_callback_args_t args = + i2c_master_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else { - .p_context = p_ctrl->p_cfg->p_context, - .event = event - }; + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + p_args->event = event; + #if IIC_MASTER_CFG_DTC_ENABLE /* Stop any DTC assisted transfer for tx */ @@ -589,7 +661,32 @@ static void iic_master_notify (iic_master_instance_ctrl_t * const p_ctrl, i2c_ma #endif /* Now do the callback here */ - p_ctrl->p_cfg->p_callback(&args); +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iic_master_prv_ns_callback p_callback = (iic_master_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } /* Clear the err flags */ p_ctrl->err = false; diff --git a/ra/fsp/src/r_iic_slave/r_iic_slave.c b/ra/fsp/src/r_iic_slave/r_iic_slave.c index 60c76a7c3..c1dbc322d 100644 --- a/ra/fsp/src/r_iic_slave/r_iic_slave.c +++ b/ra/fsp/src/r_iic_slave/r_iic_slave.c @@ -114,6 +114,11 @@ /********************************************************************************************************************** * Typedef definitions *********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile iic_slave_prv_ns_callback)(i2c_slave_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iic_slave_prv_ns_callback)(i2c_slave_callback_args_t * p_args); +#endif /********************************************************************************************************************** * Private function prototypes @@ -127,6 +132,9 @@ static fsp_err_t iic_slave_read_write(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_buffer, uint32_t const bytes, iic_slave_transfer_dir_t direction); +static void r_iic_slave_call_callback(iic_slave_instance_ctrl_t * p_ctrl, + i2c_slave_event_t event, + uint32_t transaction_count); /* Functions that manipulate hardware */ static void iic_open_hw_slave(iic_slave_instance_ctrl_t * const p_ctrl); @@ -157,11 +165,12 @@ static fsp_version_t const g_iic_slave_version = /* IIC Implementation of I2C device slave interface */ i2c_slave_api_t const g_i2c_slave_on_iic = { - .open = R_IIC_SLAVE_Open, - .read = R_IIC_SLAVE_Read, - .write = R_IIC_SLAVE_Write, - .close = R_IIC_SLAVE_Close, - .versionGet = R_IIC_SLAVE_VersionGet + .open = R_IIC_SLAVE_Open, + .read = R_IIC_SLAVE_Read, + .write = R_IIC_SLAVE_Write, + .close = R_IIC_SLAVE_Close, + .versionGet = R_IIC_SLAVE_VersionGet, + .callbackSet = R_IIC_SLAVE_CallbackSet }; /*******************************************************************************************************************//** @@ -176,14 +185,15 @@ i2c_slave_api_t const g_i2c_slave_on_iic = /******************************************************************************************************************//** * Opens the I2C slave device. * - * @retval FSP_SUCCESS I2C slave device opened successfully. - * @retval FSP_ERR_ALREADY_OPEN Module is already open. - * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: - * 1. p_api_ctrl or p_cfg is NULL. - * 2. extended parameter is NULL. - * 3. Callback parameter is NULL. - * 4. Set the rate to fast mode plus on a channel which does not support it. - * 5. Invalid IRQ number assigned + * @retval FSP_SUCCESS I2C slave device opened successfully. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MCU. + * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below: + * 1. p_api_ctrl or p_cfg is NULL. + * 2. extended parameter is NULL. + * 3. Callback parameter is NULL. + * 4. Set the rate to fast mode plus on a channel which does not support it. + * 5. Invalid IRQ number assigned *********************************************************************************************************************/ fsp_err_t R_IIC_SLAVE_Open (i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t const * const p_cfg) { @@ -193,12 +203,13 @@ fsp_err_t R_IIC_SLAVE_Open (i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t FSP_ASSERT(p_ctrl != NULL); FSP_ASSERT(p_cfg != NULL); FSP_ASSERT(p_cfg->p_extend != NULL); - FSP_ASSERT(p_cfg->p_callback != NULL); FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->eri_irq >= (IRQn_Type) 0); + FSP_ERROR_RETURN(BSP_FEATURE_IIC_VALID_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(IIC_SLAVE_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); /* If rate is configured as Fast mode plus, check whether the channel supports it */ @@ -210,7 +221,14 @@ fsp_err_t R_IIC_SLAVE_Open (i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t p_ctrl->p_reg = (R_IIC0_Type *) ((uint32_t) R_IIC0 + (p_cfg->channel * ((uint32_t) R_IIC1 - (uint32_t) R_IIC0))); /* Record the configuration on the device for use later */ - p_ctrl->p_cfg = p_cfg; + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif + R_BSP_MODULE_START(FSP_IP_IIC, p_cfg->channel); /* Indicate that restart and stop condition detection yet to be enabled */ @@ -286,6 +304,48 @@ fsp_err_t R_IIC_SLAVE_Write (i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * cons return err; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_slave_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_IIC_SLAVE_CallbackSet (i2c_slave_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_slave_callback_args_t *), + void const * const p_context, + i2c_slave_callback_args_t * const p_callback_memory) +{ + iic_slave_instance_ctrl_t * p_ctrl = (iic_slave_instance_ctrl_t *) p_api_ctrl; + +#if (IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IIC_SLAVE_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE + if (!p_ctrl->callback_is_secure) + { + FSP_ASSERT(p_callback_memory); + } + #endif +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /******************************************************************************************************************//** * Closes the I2C device. * @@ -376,6 +436,8 @@ static fsp_err_t iic_slave_read_write (i2c_slave_ctrl_t * const p_api_ctrl, /* Fail if there is already a transfer in progress */ FSP_ERROR_RETURN(IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED == p_ctrl->direction, FSP_ERR_IN_USE); + + FSP_ASSERT(((iic_slave_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); #endif /* Record the new information about this transfer */ @@ -448,15 +510,8 @@ static void iic_slave_notify (iic_slave_instance_ctrl_t * const p_ctrl, i2c_slav p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_SLAVE_ICCR1_ICE_BIT_MASK | IIC_SLAVE_PRV_SCL_SDA_NOT_DRIVEN); } - /* Invoke callback */ - /* Fill in the argument to the callback */ - - i2c_slave_callback_args_t args = - { - .p_context = p_ctrl->p_cfg->p_context, - .bytes = p_ctrl->transaction_count, - .event = slave_event - }; + /* Save transaction count */ + uint32_t transaction_count = p_ctrl->transaction_count; /* Reset the transaction count here */ p_ctrl->transaction_count = 0U; @@ -464,7 +519,7 @@ static void iic_slave_notify (iic_slave_instance_ctrl_t * const p_ctrl, i2c_slav p_ctrl->direction = IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED; /* Invoke the callback */ - p_ctrl->p_cfg->p_callback(&args); + r_iic_slave_call_callback(p_ctrl, slave_event, transaction_count); } /*******************************************************************************************************************//** @@ -475,14 +530,6 @@ static void iic_slave_notify (iic_slave_instance_ctrl_t * const p_ctrl, i2c_slav **********************************************************************************************************************/ static void iic_slave_callback_request (iic_slave_instance_ctrl_t * const p_ctrl, i2c_slave_event_t slave_event) { - /* Fill in the argument to the callback */ - i2c_slave_callback_args_t args = - { - .p_context = p_ctrl->p_cfg->p_context, - .event = slave_event, - .bytes = p_ctrl->transaction_count - }; - p_ctrl->direction = IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED; /* Disable timeout function */ @@ -490,7 +537,7 @@ static void iic_slave_callback_request (iic_slave_instance_ctrl_t * const p_ctrl /* Invoke the callback to notify the read request. * The application must call MasterWriteSlaveRead API in the callback.*/ - p_ctrl->p_cfg->p_callback(&args); + r_iic_slave_call_callback(p_ctrl, slave_event, p_ctrl->transaction_count); /* Allow timeouts to be generated on the low value of SCL using long count mode */ p_ctrl->p_reg->ICMR2 = IIC_SLAVE_BUS_MODE_REGISTER_2_MASK; @@ -655,6 +702,64 @@ static void iic_slave_initiate_transaction (iic_slave_instance_ctrl_t * p_ctrl, } } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to iic slave instance control block + * @param[in] event Event code + * @param[in] transaction_count Transaction count for iic slave + **********************************************************************************************************************/ +static void r_iic_slave_call_callback (iic_slave_instance_ctrl_t * p_ctrl, + i2c_slave_event_t event, + uint32_t transaction_count) +{ + i2c_slave_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_slave_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->bytes = transaction_count; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iic_slave_prv_ns_callback p_callback = (iic_slave_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /******************************************************************************************************************//** * Handles the receive data full interrupt when operating as a slave. * diff --git a/ra/fsp/src/r_iwdt/r_iwdt.c b/ra/fsp/src/r_iwdt/r_iwdt.c index 253c417a1..7bd281901 100644 --- a/ra/fsp/src/r_iwdt/r_iwdt.c +++ b/ra/fsp/src/r_iwdt/r_iwdt.c @@ -67,6 +67,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile iwdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile iwdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -125,7 +131,7 @@ static const uint8_t g_wdt_division_lookup[] = }; /* Global pointer to control structure for use by the NMI callback. */ -static iwdt_instance_ctrl_t * gp_iwdt_ctrl = NULL; +static volatile iwdt_instance_ctrl_t * gp_iwdt_ctrl = NULL; /* Watchdog implementation of IWDT Driver */ const wdt_api_t g_wdt_on_iwdt = @@ -136,6 +142,7 @@ const wdt_api_t g_wdt_on_iwdt = .statusClear = R_IWDT_StatusClear, .counterGet = R_IWDT_CounterGet, .timeoutGet = R_IWDT_TimeoutGet, + .callbackSet = R_IWDT_CallbackSet, .versionGet = R_IWDT_VersionGet, }; @@ -159,6 +166,7 @@ const wdt_api_t g_wdt_on_iwdt = * @retval FSP_ERR_NOT_ENABLED An attempt to open the IWDT when the OFS0 register is not * configured for auto-start mode. * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. **********************************************************************************************************************/ fsp_err_t R_IWDT_Open (wdt_ctrl_t * const p_api_ctrl, wdt_cfg_t const * const p_cfg) { @@ -173,6 +181,13 @@ fsp_err_t R_IWDT_Open (wdt_ctrl_t * const p_api_ctrl, wdt_cfg_t const * const p_ FSP_ASSERT(NULL != p_cfg->p_callback); #endif + /* Ensure this module is in the same security state as the NMI */ + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + FSP_ERROR_RETURN(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk, FSP_ERR_INVALID_STATE); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + FSP_ERROR_RETURN(!(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk), FSP_ERR_INVALID_STATE); + #endif + /* Enum checking is done here because some enums in wdt_timeout_t are not supported by the IWDT peripheral (they are * included for other implementations of the watchdog interface). */ FSP_ASSERT((p_cfg->timeout == WDT_TIMEOUT_128) || (p_cfg->timeout == WDT_TIMEOUT_512) || \ @@ -371,6 +386,42 @@ fsp_err_t R_IWDT_TimeoutGet (wdt_ctrl_t * const p_api_ctrl, wdt_timeout_values_t return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements wdt_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_IWDT_CallbackSet (wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void const * const p_context, + wdt_callback_args_t * const p_callback_memory) +{ + iwdt_instance_ctrl_t * p_instance_ctrl = (iwdt_instance_ctrl_t *) p_ctrl; + +#if IWDT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(IWDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_instance_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Return IWDT HAL driver version. Implements @ref wdt_api_t::versionGet. * @@ -406,10 +457,49 @@ static void iwdt_nmi_internal_callback (bsp_grp_irq_t irq) { FSP_PARAMETER_NOT_USED(irq); - /* Call user registered callback */ - wdt_callback_args_t p_args; - p_args.p_context = gp_iwdt_ctrl->p_context; - gp_iwdt_ctrl->p_callback(&p_args); + wdt_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + wdt_callback_args_t * p_args = gp_iwdt_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = gp_iwdt_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (gp_iwdt_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_iwdt_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + iwdt_prv_ns_callback p_callback = (iwdt_prv_ns_callback) (gp_iwdt_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + gp_iwdt_ctrl->p_callback(p_args); +#endif + if (NULL != gp_iwdt_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_iwdt_ctrl->p_callback_memory = args; + } } /*******************************************************************************************************************//** diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c index 2670463ed..eaeacddf6 100644 --- a/ra/fsp/src/r_lpm/r_lpm.c +++ b/ra/fsp/src/r_lpm/r_lpm.c @@ -53,6 +53,9 @@ #define LPM_SW_STANDBY_STCONR (0x0U) #define LPM_SW_STANDBY_WAKE_STCONR (0x3U) +#define LPM_SNZREQCR1_OFFSET (0x32ULL) +#define LPM_WUPEN1_OFFSET (0x32ULL) + #define LPM_OPEN (0x524c504d) /*********************************************************************************************************************** @@ -345,7 +348,7 @@ fsp_err_t r_lpm_mcu_specific_low_power_check (lpm_cfg_t const * const p_cfg) { if (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode) { - FSP_ERROR_RETURN(0U == ((uint32_t) p_cfg->snooze_request_source & (~BSP_FEATURE_LPM_SNZREQCR_MASK)), + FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->snooze_request_source & (~BSP_FEATURE_LPM_SNZREQCR_MASK)), FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(0U == ((uint32_t) p_cfg->snooze_end_sources & (~BSP_FEATURE_LPM_SNZEDCR_MASK)), FSP_ERR_INVALID_ARGUMENT); @@ -377,7 +380,7 @@ fsp_err_t r_lpm_mcu_specific_low_power_check (lpm_cfg_t const * const p_cfg) /* Do nothing. */ } - FSP_ERROR_RETURN(0U == ((uint32_t) p_cfg->standby_wake_sources & ~BSP_FEATURE_ICU_WUPEN_MASK), + FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->standby_wake_sources & ~BSP_FEATURE_ICU_WUPEN_MASK), FSP_ERR_INVALID_MODE); } @@ -465,7 +468,11 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) } /* Set the request condition that can trigger entry in to snooze mode */ - R_SYSTEM->SNZREQCR = (uint32_t) p_cfg->snooze_request_source; + R_SYSTEM->SNZREQCR = (uint32_t) p_cfg->snooze_request_source & UINT32_MAX; + +#if BSP_FEATURE_LPM_HAS_SNZREQCR1 == 1 + R_SYSTEM->SNZREQCR1 = (uint32_t) (p_cfg->snooze_request_source >> LPM_SNZREQCR1_OFFSET) & UINT32_MAX; +#endif /* Enable/disable DTC operation */ snzcr |= (uint32_t) (p_cfg->dtc_state_in_snooze << R_SYSTEM_SNZCR_SNZDTCEN_Pos); @@ -474,7 +481,11 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) R_ICU->SELSR0_b.SELS = (uint8_t) p_cfg->snooze_cancel_sources; /* Set all sources that can cause an exit from snooze mode to software standby. */ - R_SYSTEM->SNZEDCR = (uint8_t) p_cfg->snooze_end_sources; + R_SYSTEM->SNZEDCR = (uint8_t) p_cfg->snooze_end_sources & UINT8_MAX; + +#if BSP_FEATURE_LPM_HAS_SNZEDCR1 == 1 + R_SYSTEM->SNZEDCR1 = (uint8_t) (p_cfg->snooze_end_sources >> 8U) & UINT8_MAX; +#endif } /* Set SBYCR to Standby/Deep Standby. */ @@ -486,7 +497,10 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) sbycr = (1U << R_SYSTEM_SBYCR_SSBY_Pos); #endif - R_ICU->WUPEN = p_cfg->standby_wake_sources; + R_ICU->WUPEN = (uint32_t) p_cfg->standby_wake_sources & UINT32_MAX; +#if BSP_FEATURE_ICU_HAS_WUPEN1 == 1 + R_ICU->WUPEN1 = (uint32_t) (p_cfg->standby_wake_sources >> LPM_WUPEN1_OFFSET) & UINT32_MAX; +#endif } else { @@ -558,9 +572,13 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) uint32_t saved_opccr = 0U; uint32_t saved_sopccr = 0U; uint32_t saved_ostdcr_ostde = 0U; - uint32_t saved_hocowtcr = 0U; - uint32_t new_hocowtcr = 0U; - uint32_t stopped_modules = 0; + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 + uint32_t saved_hocowtcr = 0U; + uint32_t new_hocowtcr = 0U; + #endif + #if BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED + uint32_t stopped_modules = 0; + #endif #endif if (1U == R_SYSTEM->SBYCR_b.SSBY) @@ -577,6 +595,9 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) FSP_ERROR_RETURN(FSP_SUCCESS == r_lpm_check_clocks(clock_source), FSP_ERR_INVALID_MODE); } + /* Enable writing to CGC and Low Power Mode registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); #else /* RA6 Series Only: @@ -586,8 +607,11 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) saved_opccr = R_SYSTEM->OPCCR_b.OPCM; saved_sopccr = R_SYSTEM->SOPCCR_b.SOPCM; + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 + /* Save HOCOWTCR_b.HSTS */ saved_hocowtcr = R_SYSTEM->HOCOWTCR_b.HSTS; + #endif /* Enable writing to CGC and Low Power Mode registers. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); @@ -602,18 +626,25 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) { /* Verify clock settings. */ FSP_ERROR_RETURN(FSP_SUCCESS == r_lpm_check_clocks(clock_source), FSP_ERR_INVALID_MODE); + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 new_hocowtcr = LPM_SW_STANDBY_HOCOWTCR_SCI0_HSTS; } else { new_hocowtcr = LPM_SW_STANDBY_HOCOWTCR_HSTS; + #endif } + #if BSP_FEATURE_LPM_HAS_STCONR == 1 + /* Set STCONR based on the current system clock. */ if (LPM_CLOCK_HOCO == clock_source) { + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 + /* Set HOCOWTCR_b.HSTS when using HOCO as the system clock */ R_SYSTEM->HOCOWTCR_b.HSTS = R_SYSTEM_HOCOWTCR_HSTS_Msk & (new_hocowtcr << R_SYSTEM_HOCOWTCR_HSTS_Pos); + #endif R_SYSTEM->STCONR = LPM_SW_STANDBY_STCONR; } @@ -621,6 +652,7 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) { R_SYSTEM->STCONR = LPM_SW_STANDBY_WAKE_STCONR; } + #endif } else { @@ -671,6 +703,10 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) /* Enable Snooze mode (SNZCR.SNZE = 1) immediately before entering to Software Standby mode. * See Section 11.8.2 "Canceling Snooze Mode" in the RA6M3 manual R01UM0004EU0110 */ R_SYSTEM->SNZCR_b.SNZE = 1; + + /* Dummy read required. + * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html */ + R_SYSTEM->SNZCR; } /* DSB should be last instruction executed before WFI @@ -690,10 +726,12 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) r_lpm_wait_for_operating_mode_flags(); /* Restore system registers to the values prior to entering standby. */ - R_SYSTEM->OPCCR = saved_opccr & R_SYSTEM_OPCCR_OPCM_Msk; - R_SYSTEM->SOPCCR = saved_sopccr & R_SYSTEM_SOPCCR_SOPCM_Msk; - R_SYSTEM->OSTDCR_b.OSTDE = 0x1U & saved_ostdcr_ostde; + R_SYSTEM->OPCCR = saved_opccr & R_SYSTEM_OPCCR_OPCM_Msk; + R_SYSTEM->SOPCCR = saved_sopccr & R_SYSTEM_SOPCCR_SOPCM_Msk; + R_SYSTEM->OSTDCR_b.OSTDE = 0x1U & saved_ostdcr_ostde; + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 R_SYSTEM->HOCOWTCR_b.HSTS = R_SYSTEM_HOCOWTCR_HSTS_Msk & (saved_hocowtcr << R_SYSTEM_HOCOWTCR_HSTS_Pos); + #endif /* Disable writing to CGC and Low Power Mode registers. */ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); diff --git a/ra/fsp/src/r_lvd/r_lvd.c b/ra/fsp/src/r_lvd/r_lvd.c index 8e353f8a1..1cc383a1d 100644 --- a/ra/fsp/src/r_lvd/r_lvd.c +++ b/ra/fsp/src/r_lvd/r_lvd.c @@ -76,6 +76,11 @@ /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile lvd_prv_ns_callback)(lvd_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile lvd_prv_ns_callback)(lvd_callback_args_t * p_args); +#endif /*********************************************************************************************************************** * Private function prototypes @@ -115,14 +120,19 @@ static const fsp_version_t g_lvd_version = }; /* Look-up tables for writing to monitor 1 and monitor 2 registers. */ -static uint8_t volatile * const g_lvdncr0_lut[] = {&(R_SYSTEM->LVD1CR0), &(R_SYSTEM->LVD2CR0)}; -static uint8_t volatile * const g_lvdncr1_lut[] = {&(R_SYSTEM->LVD1CR1), &(R_SYSTEM->LVD2CR1)}; -static uint8_t volatile * const g_lvdnsr_lut[] = {&(R_SYSTEM->LVD1SR), &(R_SYSTEM->LVD2SR)}; -static uint32_t const g_lvdlvlr_offset_lut[] = +static uint8_t volatile * const g_lvdncr0_lut[] = {&(R_SYSTEM->LVD1CR0), &(R_SYSTEM->LVD2CR0)}; +static uint8_t volatile * const g_lvdncr1_lut[] = {&(R_SYSTEM->LVD1CR1), &(R_SYSTEM->LVD2CR1)}; +static uint8_t volatile * const g_lvdnsr_lut[] = {&(R_SYSTEM->LVD1SR), &(R_SYSTEM->LVD2SR)}; +#if (BSP_FEATURE_LVD_HAS_LVDLVLR == 1) +static uint32_t const g_lvdlvlr_offset_lut[] = { LVD_PRV_LVDLVLR_LVD1LVL_OFFSET, LVD_PRV_LVDLVLR_LVD2LVL_OFFSET }; static uint32_t const g_lvdlvlr_mask_lut[] = {LVD_PRV_LVDLVLR_LVD1LVL_MASK, LVD_PRV_LVDLVLR_LVD2LVL_MASK}; +#else +static uint8_t volatile * const g_lvdncmpcr_lut[] = {&(R_SYSTEM->LVD1CMPCR), &(R_SYSTEM->LVD2CMPCR)}; +static uint32_t const g_lvdnlvl_mask_lut[] = {R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk, R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk}; +#endif /*********************************************************************************************************************** * Global Variables @@ -136,6 +146,7 @@ const lvd_api_t g_lvd_on_lvd = .statusClear = R_LVD_StatusClear, .close = R_LVD_Close, .versionGet = R_LVD_VersionGet, + .callbackSet = R_LVD_CallbackSet }; /*******************************************************************************************************************//** @@ -174,6 +185,15 @@ fsp_err_t R_LVD_Open (lvd_ctrl_t * const p_api_ctrl, lvd_cfg_t const * const p_c /* Store the user configuration. */ p_ctrl->p_cfg = p_cfg; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_ctrl->callback_is_secure = true; +#endif + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + /* Store control structure so it can be accessed from NMI handler. */ gp_ctrls[p_ctrl->p_cfg->monitor_number - 1] = p_ctrl; @@ -256,6 +276,42 @@ fsp_err_t R_LVD_StatusClear (lvd_ctrl_t * const p_api_ctrl) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements lvd_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_LVD_CallbackSet (lvd_ctrl_t * const p_api_ctrl, + void ( * p_callback)(lvd_callback_args_t *), + void const * const p_context, + lvd_callback_args_t * const p_callback_memory) +{ + lvd_instance_ctrl_t * p_ctrl = (lvd_instance_ctrl_t *) p_api_ctrl; + +#if (LVD_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(LVD_OPENED == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Disables the LVD peripheral. Closes the driver instance. * @@ -275,7 +331,9 @@ fsp_err_t R_LVD_Close (lvd_ctrl_t * const p_api_ctrl) FSP_ERROR_RETURN(LVD_OPENED == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif +#if BSP_FEATURE_LVD_HAS_LVDLVLR == 1 FSP_CRITICAL_SECTION_DEFINE; +#endif uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 1; @@ -314,6 +372,8 @@ fsp_err_t R_LVD_Close (lvd_ctrl_t * const p_api_ctrl) *(g_lvdncr0_lut[monitor_index]) = lvdncr0; +#if BSP_FEATURE_LVD_HAS_LVDLVLR == 1 + /* Critical section required because LVCMPCR register is shared with other instances. */ FSP_CRITICAL_SECTION_ENTER; @@ -321,6 +381,9 @@ fsp_err_t R_LVD_Close (lvd_ctrl_t * const p_api_ctrl) R_SYSTEM->LVCMPCR &= (uint8_t) ~(p_ctrl->p_cfg->monitor_number << LVD_PRV_LVCMPCR_LVD1E_OFFSET); FSP_CRITICAL_SECTION_EXIT; +#else + *(g_lvdncmpcr_lut[monitor_index]) &= (uint8_t) ~R_SYSTEM_LVD1CMPCR_LVD1E_Msk; +#endif R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LVD); @@ -435,6 +498,7 @@ static void r_lvd_hw_configure (lvd_instance_ctrl_t * p_ctrl) /* Enable access to LVD registers. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); +#if (BSP_FEATURE_LVD_HAS_LVDLVLR == 1) uint32_t lvdne_mask = p_ctrl->p_cfg->monitor_number << LVD_PRV_LVCMPCR_LVD1E_OFFSET; uint32_t lvdlvr_offset = g_lvdlvlr_offset_lut[monitor_index]; @@ -456,6 +520,44 @@ static void r_lvd_hw_configure (lvd_instance_ctrl_t * p_ctrl) R_SYSTEM->LVCMPCR |= (uint8_t) lvdne_mask; FSP_CRITICAL_SECTION_EXIT; +#else + uint8_t lvdne[LVD_PRV_NUMBER_OF_MONITORS]; + uint8_t i; + + /* Critical section required because LVCMPCR and LVDLVLR registers are shared with other instances. */ + FSP_CRITICAL_SECTION_ENTER; + + /* To change a LVDNLVL register both voltage detection circuits must be disabled. + * Disable the voltage detection circuit for all monitors before writing the LVDLVLR register. + * See section 7.2.2 "LVD1CMPCR : Voltage Monitoring 1 Comparator Control Register" in the RA6M4 manual R01HUM0890EJ0050.*/ + for (i = 0; i < LVD_PRV_NUMBER_OF_MONITORS; i++) + { + lvdne[i] = *(g_lvdncmpcr_lut[i]) & R_SYSTEM_LVD1CMPCR_LVD1E_Msk; // Preserve enable values for other monitors + *(g_lvdncmpcr_lut[i]) &= (uint8_t) ~R_SYSTEM_LVD1CMPCR_LVD1E_Msk; + } + + /* Configure the voltage threshold setting. */ + uint8_t lvdncmpcr = *(g_lvdncmpcr_lut[monitor_index]); + lvdncmpcr &= (uint8_t) ~(g_lvdnlvl_mask_lut[monitor_index]); + lvdncmpcr |= p_ctrl->p_cfg->voltage_threshold; + + /* Write the voltage level setting. */ + *(g_lvdncmpcr_lut[monitor_index]) = lvdncmpcr; + + /* Enable the voltage detection circuits. */ + for (i = 0; i < LVD_PRV_NUMBER_OF_MONITORS; i++) + { + if (monitor_index == i) + { + *(g_lvdncmpcr_lut[monitor_index]) |= R_SYSTEM_LVD1CMPCR_LVD1E_Msk; + } + else + { + *(g_lvdncmpcr_lut[i]) |= lvdne[i]; + } + } + FSP_CRITICAL_SECTION_EXIT; +#endif /* Write settings to control registers. */ *(g_lvdncr0_lut[monitor_index]) = (uint8_t) lvdncr0; @@ -575,10 +677,52 @@ static void lvd_common_isr_handler (lvd_instance_ctrl_t * p_ctrl) uint32_t monitor_index = p_ctrl->p_cfg->monitor_number - 1; lvd_callback_args_t callback_args; - callback_args.current_state = + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + lvd_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &callback_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + callback_args = *p_args; + } + + p_args->current_state = (lvd_current_state_t) ((*(g_lvdnsr_lut[monitor_index]) & LVD_PRV_LVDNSR_MON_MASK) > 0); - callback_args.monitor_number = p_ctrl->p_cfg->monitor_number; - p_ctrl->p_cfg->p_callback(&callback_args); + p_args->monitor_number = p_ctrl->p_cfg->monitor_number; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + lvd_prv_ns_callback p_callback = (lvd_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = callback_args; + } R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LVD); @@ -619,7 +763,6 @@ static void lvd_nmi_handler (bsp_grp_irq_t irq) { /* Save context if RTOS is used */ FSP_CONTEXT_SAVE - /* Call common isr handler. */ lvd_common_isr_handler(gp_ctrls[irq - BSP_GRP_IRQ_LVD1]); diff --git a/ra/fsp/src/r_ospi/r_ospi.c b/ra/fsp/src/r_ospi/r_ospi.c new file mode 100644 index 000000000..44072e5e0 --- /dev/null +++ b/ra/fsp/src/r_ospi/r_ospi.c @@ -0,0 +1,800 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_ospi.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define OSPI_PRV_OPEN (0x4F535049U) +#define OSPI_PRV_SHIFT(device_0_settings, device) \ + (device_0_settings << (device * 16U)) +#define OSPI_PRV_RMW(reg, device_0_settings, device) \ + ((reg & ~(uint32_t) OSPI_PRV_SHIFT(UINT16_MAX, device)) | (OSPI_PRV_SHIFT(device_0_settings, device))) +#define OSPI_PRV_RMW_MASKED(reg, mask, device_0_settings, device) \ + ((reg & ~(uint32_t) OSPI_PRV_SHIFT(mask, device)) | (OSPI_PRV_SHIFT(device_0_settings, device))) +#define OSPI_PRV_AUTOMATIC_CALIBRATION_NORMAL_END (3U) +#define OSPI_PRV_DIRECT_COMMAND_MASK (3U) +#define OSPI_PRV_DIRECT_ADDR_AND_DATA_MASK (7U) +#define OSPI_PRV_PAGE_SIZE_BYTES (256U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static fsp_err_t r_ospi_automatic_calibration_seq(ospi_instance_ctrl_t * p_instance_ctrl); +static bool r_ospi_status_sub(ospi_instance_ctrl_t * p_instance_ctrl, uint8_t bit_pos); +static fsp_err_t r_ospi_spi_protocol_specific_settings(ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_protocol_t spi_protocol); +static void r_ospi_wen(ospi_instance_ctrl_t * p_instance_ctrl); +static void r_ospi_direct_transfer(ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Version data structure used by error logger macro. */ +static const fsp_version_t g_ospi_version = +{ + .api_version_minor = SPI_FLASH_API_VERSION_MINOR, + .api_version_major = SPI_FLASH_API_VERSION_MAJOR, + .code_version_major = OSPI_CODE_VERSION_MAJOR, + .code_version_minor = OSPI_CODE_VERSION_MINOR +}; + +/*******************************************************************************************************************//** + * @addtogroup OSPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +const spi_flash_api_t g_ospi_on_spi_flash = +{ + .open = R_OSPI_Open, + .directWrite = R_OSPI_DirectWrite, + .directRead = R_OSPI_DirectRead, + .directTransfer = R_OSPI_DirectTransfer, + .spiProtocolSet = R_OSPI_SpiProtocolSet, + .write = R_OSPI_Write, + .erase = R_OSPI_Erase, + .statusGet = R_OSPI_StatusGet, + .xipEnter = R_OSPI_XipEnter, + .xipExit = R_OSPI_XipExit, + .bankSet = R_OSPI_BankSet, + .close = R_OSPI_Close, + .versionGet = R_OSPI_VersionGet, +}; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Open the OSPI driver module. After the driver is open, the OSPI can be accessed like internal flash memory. + * + * Implements @ref spi_flash_api_t::open. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_Open + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION The parameter p_ctrl or p_cfg is NULL. + * @retval FSP_ERR_ALREADY_OPEN Driver has already been opened with the same p_ctrl. + * @retval FSP_ERR_CALIBRATE_FAILED Failed to perform auto-calibrate. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Open (spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(OSPI_PRV_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Enable clock to the OSPI block */ + R_BSP_MODULE_START(FSP_IP_OSPI, 0U); + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + + /* Initialize control block. */ + p_instance_ctrl->p_cfg = p_cfg; + p_instance_ctrl->spi_protocol = p_cfg->spi_protocol; + p_instance_ctrl->channel = p_cfg_extend->channel; + + /* Perform OSPI initial setup as described in hardware manual (see Section 34.3.6.1 + * 'Initial Settings' of the RA6M4 manual R01UH0890EJ0100). */ + + /* Set the device type as OctaFlash and storage capacity */ + R_OSPI->DSR[p_instance_ctrl->channel] = p_cfg_extend->memory_size & R_OSPI_DSR_DVSZ_Msk; + + /* DCSTR and DRCSTR values are designed to not change at the time of changing the SPI protocol. + * Minimum latencies are same for SPI and SOPI. + * In case the SPI protocol is intended to be changed to DOPI, these should be configured with latencies required for DOPI. + */ + ospi_timing_setting_t const * p_timing = p_cfg_extend->p_timing_settings; + R_OSPI->DCSTR = (uint32_t) (p_timing->cs_pulldown_lead << R_OSPI_DCSTR_DVSELLO_Pos) | + (uint32_t) (p_timing->cs_pullup_lag << R_OSPI_DCSTR_DVSELHI_Pos) | + (uint32_t) (p_timing->command_to_command_interval << + R_OSPI_DCSTR_DVSELCMD_Pos); + p_timing = p_cfg_extend->p_mem_mapped_read_timing_settings; + R_OSPI->DRCSTR = OSPI_PRV_RMW(R_OSPI->DRCSTR, + ((uint32_t) (p_cfg_extend->single_continuous_mode_read_idle_time << + R_OSPI_DRCSTR_CTRW0_Pos) | + (uint32_t) (p_timing->cs_pullup_lag << R_OSPI_DRCSTR_DVRDHI0_Pos) | + (uint32_t) (p_timing->cs_pulldown_lead << R_OSPI_DRCSTR_DVRDLO0_Pos) | + (uint32_t) (p_timing->command_to_command_interval << R_OSPI_DRCSTR_DVRDCMD0_Pos)), + p_instance_ctrl->channel); + + p_timing = p_cfg_extend->p_mem_mapped_write_timing_settings; + + /* Always keep single continuous write mode enabled with appropriate settings */ + R_OSPI->DWCSTR = OSPI_PRV_RMW(R_OSPI->DWCSTR, + ((uint32_t) (1U << R_OSPI_DWCSTR_CTW0_Pos) | + (uint32_t) (p_cfg_extend->single_continuous_mode_write_idle_time << + R_OSPI_DWCSTR_CTWW0_Pos) | + (uint32_t) (p_timing->cs_pullup_lag << R_OSPI_DWCSTR_DVWHI0_Pos) | + (uint32_t) (p_timing->cs_pulldown_lead << R_OSPI_DWCSTR_DVWLO0_Pos) | + (uint32_t) (p_timing->command_to_command_interval << R_OSPI_DWCSTR_DVWCMD0_Pos)), + p_instance_ctrl->channel); + + /* Max = 256 bytes, i.e., Page size */ + R_OSPI->DWSCTSR = OSPI_PRV_SHIFT(OSPI_PRV_PAGE_SIZE_BYTES << R_OSPI_DWSCTSR_CTSN0_Pos, p_instance_ctrl->channel); + + /* Read back to ensure value has been written */ + FSP_HARDWARE_REGISTER_WAIT(R_OSPI->DWSCTSR, + OSPI_PRV_SHIFT(OSPI_PRV_PAGE_SIZE_BYTES << R_OSPI_DWSCTSR_CTSN0_Pos, + p_instance_ctrl->channel)); + + /* Setup SPI protocol specific registers */ + fsp_err_t ret = r_ospi_spi_protocol_specific_settings(p_instance_ctrl, p_cfg->spi_protocol); + if (FSP_SUCCESS == ret) + { + p_instance_ctrl->open = OSPI_PRV_OPEN; + } + + return ret; +} + +/*******************************************************************************************************************//** + * Writes raw data directly to the OctaFlash. API not supported. Use R_OSPI_DirectTransfer + * + * Implements @ref spi_flash_api_t::directWrite. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_DirectWrite (spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + FSP_PARAMETER_NOT_USED(read_after_write); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Reads raw data directly from the OctaFlash. API not supported. Use R_OSPI_DirectTransfer. + * + * Implements @ref spi_flash_api_t::directRead. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_DirectRead (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Read/Write raw data directly with the OctaFlash. + * + * Implements @ref spi_flash_api_t::directTransfer. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_DirectTransfer + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_DirectTransfer (spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_transfer); + FSP_ASSERT(0 != p_transfer->command_length); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + r_ospi_direct_transfer(p_instance_ctrl, p_transfer, direction); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Enters Single Continuous Read/Write mode. + * + * Implements @ref spi_flash_api_t::xipEnter. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_XipEnter (spi_flash_ctrl_t * p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Single continuous read mode (CTR0/1) is enabled. Other values are set during Open */ + R_OSPI->DRCSTR = + OSPI_PRV_RMW_MASKED(R_OSPI->DRCSTR, + R_OSPI_DRCSTR_CTR0_Msk, + ((uint32_t) (1U << R_OSPI_DRCSTR_CTR0_Pos)), + p_instance_ctrl->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Exits XIP (execute in place) mode. + * + * Implements @ref spi_flash_api_t::xipExit. + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_XipExit (spi_flash_ctrl_t * p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Single continuous read mode (CTR0/1) is disabled. Other values are set during Open */ + R_OSPI->DRCSTR = OSPI_PRV_RMW_MASKED(R_OSPI->DRCSTR, R_OSPI_DRCSTR_CTR0_Msk, 0U, p_instance_ctrl->channel); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Program a page of data to the flash. + * + * Implements @ref spi_flash_api_t::write. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_Write + * + * @retval FSP_SUCCESS The flash was programmed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY Another Write/Erase transaction is in progress. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Write (spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_src); + FSP_ASSERT(NULL != p_dest); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(OSPI_PRV_PAGE_SIZE_BYTES >= byte_count); + FSP_ASSERT(0 != byte_count); +#endif + + FSP_ERROR_RETURN(false == r_ospi_status_sub(p_instance_ctrl, p_instance_ctrl->p_cfg->write_status_bit), + FSP_ERR_DEVICE_BUSY); + + r_ospi_wen(p_instance_ctrl); + + uint32_t i = 0; + + /* Perform entire write opetation keeping the same access width to remain in single continuous write mode (see Section 34.5.1, point#3 + * 'Single continuous write operation' of the RA6M4 manual R01UH0890EJ0100). + * + * A change in access width will reissue the write command only when the access width change happens at a 128-bit boundary. + * This is not handled by the code code below. + * Moreover, a blocking wait (until WIP = 0) needs to be introduced in order to change the access width within this API. + * Below is a conservative approach to perform the entire transfer with a fixed access width. + * Also, memcpy should not be used here to take advantage of larger access widths. + * + * *//* Word access */ + if (0 == byte_count % 4U) + { + uint32_t * p_word_aligned_dest = (uint32_t *) p_dest; + uint32_t * p_word_aligned_src = (uint32_t *) p_src; + for (i = 0; i < byte_count / 4U; i++) + { + *p_word_aligned_dest = *p_word_aligned_src; + p_word_aligned_dest++; + p_word_aligned_src++; + } + } + /* Half Word access */ + else if (0 == byte_count % 2U) + { + uint16_t * p_half_word_aligned_dest = (uint16_t *) p_dest; + uint16_t * p_half_word_aligned_src = (uint16_t *) p_src; + for (i = 0; i < byte_count / 2U; i++) + { + *p_half_word_aligned_dest = *p_half_word_aligned_src; + p_half_word_aligned_dest++; + p_half_word_aligned_src++; + } + } + /* Byte access */ + else + { + for (i = 0; i < byte_count; i++) + { + p_dest[i] = p_src[i]; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. + * For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE. + * + * Implements @ref spi_flash_api_t::erase. + * + * @retval FSP_SUCCESS The command to erase the flash was executed successfully. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase + * size defined in spi_flash_cfg_t, or byte_count is set to 0. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_DEVICE_BUSY The device is busy. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Erase (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_device_address); + FSP_ASSERT(0 != byte_count); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + uint16_t erase_command = 0; + uint32_t chip_address = (uint32_t) p_device_address - BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS; + bool send_address = true; + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + FSP_ERROR_RETURN(false == r_ospi_status_sub(p_instance_ctrl, p_cfg->write_status_bit), FSP_ERR_DEVICE_BUSY); + + for (uint32_t index = 0; index < p_cfg->erase_command_list_length; index++) + { + /* If requested byte_count is supported by underlying flash, store the command. */ + if (byte_count == p_cfg->p_erase_command_list[index].size) + { + if (p_cfg_extend->memory_size == byte_count) + { + /* Don't send address for chip erase. */ + send_address = false; + } + + erase_command = p_cfg->p_erase_command_list[index].command; + break; + } + } + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(0U != erase_command); +#endif + r_ospi_wen(p_instance_ctrl); + + spi_flash_direct_transfer_t direct_command = {0}; + direct_command.command = erase_command; + direct_command.address = chip_address; + direct_command.address_length = (true == send_address) ? + (OSPI_PRV_DIRECT_ADDR_AND_DATA_MASK & (p_cfg->address_bytes + 1U)) : 0U; + direct_command.command_length = (SPI_FLASH_PROTOCOL_EXTENDED_SPI == p_instance_ctrl->spi_protocol) ? + 1U : (p_cfg_extend->p_opi_commands->command_bytes & OSPI_PRV_DIRECT_COMMAND_MASK); + + r_ospi_direct_transfer(p_instance_ctrl, &direct_command, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Gets the write or erase status of the flash. + * + * Implements @ref spi_flash_api_t::statusGet. + * + * Example: + * @snippet r_ospi_example.c R_OSPI_StatusGet + * + * @retval FSP_SUCCESS The write status is in p_status. + * @retval FSP_ERR_ASSERTION p_instance_ctrl or p_status is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_StatusGet (spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Read device status. */ + p_status->write_in_progress = r_ospi_status_sub(p_instance_ctrl, p_instance_ctrl->p_cfg->write_status_bit); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Selects the bank to access. + * + * Implements @ref spi_flash_api_t::bankSet. + * + * @retval FSP_ERR_UNSUPPORTED API not supported by OSPI. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_BankSet (spi_flash_ctrl_t * p_ctrl, uint32_t bank) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(bank); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Sets the SPI protocol. + * + * Implements @ref spi_flash_api_t::spiProtocolSet. + * + * @retval FSP_SUCCESS SPI protocol updated on MCU peripheral. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_CALIBRATE_FAILED Failed to perform auto-calibrate. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_SpiProtocolSet (spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + p_instance_ctrl->spi_protocol = spi_protocol; + + /* Update the SPI protocol and its associated registers. */ + return r_ospi_spi_protocol_specific_settings(p_instance_ctrl, spi_protocol); +} + +/*******************************************************************************************************************//** + * Close the OSPI driver module. + * + * Implements @ref spi_flash_api_t::close. + * + * @retval FSP_SUCCESS Configuration was successful. + * @retval FSP_ERR_ASSERTION p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN Driver is not opened. + **********************************************************************************************************************/ +fsp_err_t R_OSPI_Close (spi_flash_ctrl_t * p_ctrl) +{ + ospi_instance_ctrl_t * p_instance_ctrl = (ospi_instance_ctrl_t *) p_ctrl; + +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(OSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_instance_ctrl->open = 0U; + + /* Disable clock to the OSPI block */ + R_BSP_MODULE_STOP(FSP_IP_OSPI, 0U); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Get the driver version based on compile time macros. + * + * Implements @ref spi_flash_api_t::versionGet. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION p_version is NULL. + * + **********************************************************************************************************************/ +fsp_err_t R_OSPI_VersionGet (fsp_version_t * const p_version) +{ +#if OSPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_version); +#endif + + p_version->version_id = g_ospi_version.version_id; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup OSPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Perform initialization based on SPI/OPI protocol + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * @param[in] spi_protocol SPI/OPI protocol request + * + * @retval FSP_SUCCESS Protocol based settings completed successfully. + * @retval FSP_ERR_CALIBRATE_FAILED Auto-Calibration failed. + **********************************************************************************************************************/ +static fsp_err_t r_ospi_spi_protocol_specific_settings (ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_protocol_t spi_protocol) +{ + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + ospi_extended_cfg_t * p_cfg_extend = (ospi_extended_cfg_t *) p_cfg->p_extend; + fsp_err_t ret = FSP_SUCCESS; + ospi_device_number_t channel = p_instance_ctrl->channel; + + /* In case of SOPI mode enable pre-cycle as described in hardware manual (see Section 34.2.12 + * 'CDSR : Controller and Device Setting Register' Note 1 of the RA6M4 manual R01UH0890EJ0100). */ + uint32_t cdsr = R_OSPI->CDSR; + cdsr &= ~((uint32_t) (R_OSPI_CDSR_DV0TTYP_Msk << (channel * R_OSPI_CDSR_DV1TTYP_Pos)) | + (uint32_t) (R_OSPI_CDSR_DV0PC_Msk << channel)); + + /* Right shifted to match enum to register value */ + cdsr |= ((((uint32_t) spi_protocol) >> 1U) << (channel * R_OSPI_CDSR_DV1TTYP_Pos)); + + /* Enable pre-cycle setting in case of SOPI. ANDed to filter out SOPI enum from other mode enums. */ + cdsr |= ((((uint32_t) spi_protocol) & 1U) << (R_OSPI_CDSR_DV0PC_Pos + channel)); + + /* Keep DLFT disabled. No easy recovery from deadlock */ + cdsr |= 1U << R_OSPI_CDSR_DLFT_Pos; + R_OSPI->CDSR = cdsr; + + /* OPI mode */ + if (SPI_FLASH_PROTOCOL_EXTENDED_SPI != spi_protocol) + { + ospi_opi_command_set_t const * p_opi_commands = p_cfg_extend->p_opi_commands; + R_OSPI->MRWCSR = OSPI_PRV_RMW(R_OSPI->MRWCSR, + ((uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MRAL0_Pos) | + (uint32_t) (p_opi_commands->command_bytes << R_OSPI_MRWCSR_MRCL0_Pos) | + (uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MWAL0_Pos) | + (uint32_t) (p_opi_commands->command_bytes << R_OSPI_MRWCSR_MWCL0_Pos)), + channel); + + /* Set MDLR (Memory Map Dummy Length Reg) with Read dummy length setting */ + R_OSPI->MDLR = + OSPI_PRV_RMW(R_OSPI->MDLR, + ((uint32_t) (p_cfg_extend->opi_mem_read_dummy_cycles << R_OSPI_MDLR_DV0RDL_Pos)), + channel); + + /* Specifies the read and write commands for Device */ + uint32_t read_command = (uint32_t) ((SPI_FLASH_PROTOCOL_SOPI == spi_protocol) ? + p_opi_commands->read_command : p_opi_commands->dual_read_command); + R_OSPI->MRWCR[channel] = (uint32_t) p_opi_commands->page_program_command << R_OSPI_MRWCR_DMWCMD0_Pos | + read_command; + + /* Perform auto-calibration to appropriately update MDTR DVnDEL field */ + if (0 == p_cfg_extend->data_latch_delay_clocks) + { + ret = r_ospi_automatic_calibration_seq(p_instance_ctrl); + } + else + { + /* The OctalFlash is pre-calibrated with the existing clock settings. Do not auto-calibrate. */ + R_OSPI->MDTR = + OSPI_PRV_RMW_MASKED(R_OSPI->MDTR, + R_OSPI_MDTR_DV0DEL_Msk, + ((uint32_t) (p_cfg_extend->data_latch_delay_clocks << R_OSPI_MDTR_DV0DEL_Pos)), + channel); + } + } + else + { + /* Command length is forced to 1 byte for SPI mode */ + R_OSPI->MRWCSR = OSPI_PRV_RMW(R_OSPI->MRWCSR, + ((uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MRAL0_Pos) | + (uint32_t) (1U << R_OSPI_MRWCSR_MRCL0_Pos) | + (uint32_t) (((uint32_t) p_cfg->address_bytes + 1U) << R_OSPI_MRWCSR_MWAL0_Pos) | + (uint32_t) (1U << R_OSPI_MRWCSR_MWCL0_Pos)), + channel); + + /* Specifies the read and write commands for Device 0 */ + R_OSPI->MRWCR[channel] = (uint32_t) p_cfg->page_program_command << R_OSPI_MRWCR_DMWCMD0_Pos | + (uint32_t) p_cfg->read_command << R_OSPI_MRWCR_DMRCMD0_Pos; + + /* Single continuous read mode (CTR) must be disabled for SPI mode */ + R_OSPI->DRCSTR = OSPI_PRV_RMW_MASKED(R_OSPI->DRCSTR, R_OSPI_DRCSTR_CTR0_Msk, 0U, channel); + + /* Clear auto-calibration value */ + R_OSPI->MDTR = OSPI_PRV_RMW_MASKED(R_OSPI->MDTR, R_OSPI_MDTR_DV0DEL_Msk, 0U, channel); + } + + return ret; +} + +/*******************************************************************************************************************//** + * Gets device status. + * + * @param[in] p_instance_ctrl Pointer to a driver handle + * @param[in] bit_pos Write-in-progress bit position + * + * @return True if busy, false if not. + **********************************************************************************************************************/ +static bool r_ospi_status_sub (ospi_instance_ctrl_t * p_instance_ctrl, uint8_t bit_pos) +{ + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + spi_flash_direct_transfer_t direct_command = {0}; + if (SPI_FLASH_PROTOCOL_EXTENDED_SPI == p_instance_ctrl->spi_protocol) + { + direct_command.command = p_cfg->status_command; + direct_command.command_length = 1U; + } + else + { + ospi_opi_command_set_t const * p_opi_commands = ((ospi_extended_cfg_t *) p_cfg->p_extend)->p_opi_commands; + direct_command.command = p_opi_commands->status_command; + direct_command.command_length = p_opi_commands->command_bytes & OSPI_PRV_DIRECT_COMMAND_MASK; + direct_command.address_length = (p_cfg->address_bytes + 1U) & + OSPI_PRV_DIRECT_ADDR_AND_DATA_MASK; + direct_command.dummy_cycles = 4U; + } + + direct_command.data_length = 1U; + r_ospi_direct_transfer(p_instance_ctrl, &direct_command, SPI_FLASH_DIRECT_TRANSFER_DIR_READ); + + return (direct_command.data >> bit_pos) & 1U; +} + +/*******************************************************************************************************************//** + * Send Write enable command to the OctaFlash + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + **********************************************************************************************************************/ +static void r_ospi_wen (ospi_instance_ctrl_t * p_instance_ctrl) +{ + spi_flash_direct_transfer_t direct_command = {0}; + spi_flash_cfg_t const * p_cfg = p_instance_ctrl->p_cfg; + if (SPI_FLASH_PROTOCOL_EXTENDED_SPI == p_instance_ctrl->spi_protocol) + { + direct_command.command = p_cfg->write_enable_command; + direct_command.command_length = 1U; + } + else + { + ospi_opi_command_set_t const * p_opi_commands = ((ospi_extended_cfg_t *) p_cfg->p_extend)->p_opi_commands; + direct_command.command = p_opi_commands->write_enable_command; + direct_command.command_length = p_opi_commands->command_bytes & OSPI_PRV_DIRECT_COMMAND_MASK; + } + + r_ospi_direct_transfer(p_instance_ctrl, &direct_command, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE); +} + +/*******************************************************************************************************************//** + * Perform Automatic Calibration + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * + * @retval FSP_SUCCESS Auto-Calibration completed successfully. + * @retval FSP_ERR_CALIBRATE_FAILED Auto-Calibration failed. + **********************************************************************************************************************/ +static fsp_err_t r_ospi_automatic_calibration_seq (ospi_instance_ctrl_t * p_instance_ctrl) +{ + fsp_err_t ret = FSP_SUCCESS; + ospi_device_number_t channel = p_instance_ctrl->channel; + + /* Default ACTR value is long enough for stable environment */ + R_OSPI->ACAR[channel] = + (uint32_t) ((ospi_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend)->p_autocalibration_preamble_pattern_addr; + uint32_t cdsr = R_OSPI->CDSR; + + /* Enable auto-calibration and allow MDTR update */ + R_OSPI->CDSR = cdsr | (uint32_t) ((1U << (R_OSPI_CDSR_ACMEME0_Pos + channel))) | + (uint32_t) (1U << R_OSPI_CDSR_ACMODE_Pos); + + /* Using default values for DQSSOPI nad DQSDOPI counter */ + /* MDTR.DVnDEL: Typical value(VCC=3.3, 25 degree C, typical sample) is around 0x80 */ + while (0 == (R_OSPI->ACSR & (uint32_t) (R_OSPI_ACSR_ACSR0_Msk << (channel * R_OSPI_ACSR_ACSR1_Pos)))) + { + /* TODO: Add timeout */ + } + + /* Disable automatic calibration */ + R_OSPI->CDSR = cdsr; + if ((OSPI_PRV_AUTOMATIC_CALIBRATION_NORMAL_END << (channel * R_OSPI_ACSR_ACSR1_Pos)) != + (R_OSPI->ACSR & (uint32_t) (R_OSPI_ACSR_ACSR0_Msk << (channel * R_OSPI_ACSR_ACSR1_Pos)))) + { + ret = FSP_ERR_CALIBRATE_FAILED; + } + + /* Clear automatic calibration status */ + R_OSPI->ACSR = + (uint32_t) (R_OSPI->ACSR & + ~(uint32_t) (R_OSPI_ACSR_ACSR0_Msk << (channel * R_OSPI_ACSR_ACSR1_Pos))); + + return ret; +} + +/*******************************************************************************************************************//** + * Performs direct data transfer with the OctaFlash + * + * @param[in] p_instance_ctrl Pointer to OSPI specific control structure + * @param[in] p_transfer Pointer to transfer parameters + * @param[in] direction Read/Write + **********************************************************************************************************************/ +static void r_ospi_direct_transfer (ospi_instance_ctrl_t * p_instance_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction) +{ + R_OSPI->DCR = p_transfer->command; /* Write OSPI command. */ + R_OSPI->DAR = p_transfer->address; /* Write OSPI address */ + /* Direct Read/Write settings */ + R_OSPI->DCSR = (uint32_t) (p_transfer->command_length << R_OSPI_DCSR_CMDLEN_Pos) | + (uint32_t) (p_transfer->address_length << R_OSPI_DCSR_ADLEN_Pos) | + (uint32_t) (p_transfer->dummy_cycles << R_OSPI_DCSR_DMLEN_Pos) | + + /* Right shifted to match enum to register value */ + (uint32_t) ((p_instance_ctrl->spi_protocol >> 2U) << R_OSPI_DCSR_DOPI_Pos) | + (uint32_t) (p_instance_ctrl->channel << R_OSPI_DCSR_ACDV_Pos) | + (uint32_t) (p_transfer->data_length << R_OSPI_DCSR_DALEN_Pos); + if (SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE == direction) + { + if (0 == p_transfer->data_length) + { + /* Write any data. This will only send out command or command & address based on the settings above */ + R_OSPI->CWNDR = (uint32_t) OSPI_PRV_OPEN; + } + else + { + R_OSPI->CWDR = p_transfer->data; + } + } + else + { + p_transfer->data = R_OSPI->CRR; + } +} diff --git a/ra/fsp/src/r_poeg/r_poeg.c b/ra/fsp/src/r_poeg/r_poeg.c index a9427cfca..375137c6c 100644 --- a/ra/fsp/src/r_poeg/r_poeg.c +++ b/ra/fsp/src/r_poeg/r_poeg.c @@ -41,6 +41,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile poeg_prv_ns_callback)(poeg_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile poeg_prv_ns_callback)(poeg_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -74,6 +80,7 @@ const poeg_api_t g_poeg_on_poeg = .reset = R_POEG_Reset, .outputDisable = R_POEG_OutputDisable, .statusGet = R_POEG_StatusGet, + .callbackSet = R_POEG_CallbackSet, .close = R_POEG_Close, .versionGet = R_POEG_VersionGet }; @@ -136,6 +143,14 @@ fsp_err_t R_POEG_Open (poeg_ctrl_t * const p_ctrl, poeg_cfg_t const * const p_cf ((uint32_t) p_cfg->polarity << R_GPT_POEG0_POEGG_INV_Pos) | ((uint32_t) p_cfg->noise_filter << R_GPT_POEG0_POEGG_NFEN_Pos); + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->callback_is_secure = true; +#endif + /* Make sure the module is marked open before enabling the interrupt since the interrupt could fire immediately. */ p_instance_ctrl->open = POEG_OPEN; @@ -221,6 +236,52 @@ fsp_err_t R_POEG_StatusGet (poeg_ctrl_t * const p_ctrl, poeg_status_t * const p_ return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref poeg_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_POEG_CallbackSet (poeg_ctrl_t * const p_ctrl, + void ( * p_callback)(poeg_callback_args_t *), + void const * const p_context, + poeg_callback_args_t * const p_callback_memory) +{ + poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) p_ctrl; + +#if POEG_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(POEG_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_instance_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if POEG_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + poeg_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_instance_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), + FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Disables POEG interrupt. Implements @ref poeg_api_t::close. * @@ -283,15 +344,54 @@ void poeg_event_isr (void) /* Save context if RTOS is used */ FSP_CONTEXT_SAVE; + poeg_callback_args_t args; + IRQn_Type irq = R_FSP_CurrentIrqGet(); /* Recover ISR context saved in open. */ - poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + volatile poeg_instance_ctrl_t * p_instance_ctrl = (poeg_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + poeg_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_instance_ctrl->p_context; - /* Set data to identify callback to user, then call user callback. */ - poeg_callback_args_t callback_args; - callback_args.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&callback_args); +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_instance_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + poeg_prv_ns_callback p_callback = (poeg_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } /* Clear pending IRQ to make sure it doesn't fire again after exiting. This is a level interrupt, so it must be * cleared at the end of the ISR. */ diff --git a/ra/fsp/src/r_qspi/r_qspi.c b/ra/fsp/src/r_qspi/r_qspi.c index 481bf8918..6da0443d2 100644 --- a/ra/fsp/src/r_qspi/r_qspi.c +++ b/ra/fsp/src/r_qspi/r_qspi.c @@ -433,7 +433,7 @@ fsp_err_t R_QSPI_Erase (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_addr FSP_ASSERT(NULL != p_device_address); #endif - uint8_t erase_command = 0; + uint16_t erase_command = 0; uint32_t chip_address = (uint32_t) p_device_address - QSPI_DEVICE_START_ADDRESS + R_QSPI->SFMCNT1; bool send_address = true; @@ -561,6 +561,7 @@ fsp_err_t R_QSPI_BankSet (spi_flash_ctrl_t * p_ctrl, uint32_t bank) * @retval FSP_SUCCESS SPI protocol updated on MCU peripheral. * @retval FSP_ERR_ASSERTION A required pointer is NULL. * @retval FSP_ERR_NOT_OPEN Driver is not opened. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid SPI protocol requested. **********************************************************************************************************************/ fsp_err_t R_QSPI_SpiProtocolSet (spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol) { @@ -569,6 +570,7 @@ fsp_err_t R_QSPI_SpiProtocolSet (spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t #if QSPI_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(SPI_FLASH_PROTOCOL_QPI >= spi_protocol, FSP_ERR_INVALID_ARGUMENT); #else FSP_PARAMETER_NOT_USED(p_instance_ctrl); #endif diff --git a/ra/fsp/src/r_rtc/r_rtc.c b/ra/fsp/src/r_rtc/r_rtc.c index 852f798f7..f8a2c6b64 100644 --- a/ra/fsp/src/r_rtc/r_rtc.c +++ b/ra/fsp/src/r_rtc/r_rtc.c @@ -86,6 +86,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile rtc_prv_ns_callback)(rtc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile rtc_prv_ns_callback)(rtc_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -123,6 +129,7 @@ const rtc_api_t g_rtc_on_rtc = .periodicIrqRateSet = R_RTC_PeriodicIrqRateSet, .infoGet = R_RTC_InfoGet, .errorAdjustmentSet = R_RTC_ErrorAdjustmentSet, + .callbackSet = R_RTC_CallbackSet, .versionGet = R_RTC_VersionGet, }; @@ -146,6 +153,8 @@ static void r_rtc_config_rtc_interrupts(rtc_instance_ctrl_t * const p_ctrl, rtc_ static void r_rtc_irq_set(bool irq_enable_flag, uint8_t mask); +static void r_rtc_call_callback(rtc_instance_ctrl_t * p_ctrl, rtc_event_t event); + #if RTC_CFG_PARAM_CHECKING_ENABLE static fsp_err_t r_rtc_rfrl_validate(uint32_t value); @@ -205,6 +214,15 @@ fsp_err_t R_RTC_Open (rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg) /* Save the configuration */ p_instance_ctrl->p_cfg = p_cfg; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_instance_ctrl->callback_is_secure = true; +#endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + #if RTC_CFG_PARAM_CHECKING_ENABLE /* Verify the frequency comparison value for RFRL when using LOCO */ @@ -699,6 +717,43 @@ fsp_err_t R_RTC_VersionGet (fsp_version_t * p_version) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements rtc_api_t::callbackSet + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to RTC control block is NULL or the RTC is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_RTC_CallbackSet (rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void const * const p_context, + rtc_callback_args_t * const p_callback_memory) +{ + rtc_instance_ctrl_t * p_instance_ctrl = (rtc_instance_ctrl_t *) p_ctrl; + +#if (RTC_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(RTC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_instance_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * @} (end addtpgroup RTC) **********************************************************************************************************************/ @@ -838,6 +893,60 @@ static void r_rtc_irq_set (bool irq_enable_flag, uint8_t mask) } } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to RTC instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_rtc_call_callback (rtc_instance_ctrl_t * p_ctrl, rtc_event_t event) +{ + rtc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + rtc_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + rtc_prv_ns_callback p_callback = (rtc_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + #if RTC_CFG_PARAM_CHECKING_ENABLE /*******************************************************************************************************************//** @@ -1243,18 +1352,18 @@ void rtc_alarm_periodic_isr (void) if (NULL != p_ctrl->p_cfg->p_callback) { /* Set data to identify callback to user, then call user callback. */ - rtc_callback_args_t rtc_context_data; + rtc_event_t event; if (irq == p_ctrl->p_cfg->alarm_irq) { - rtc_context_data.event = RTC_EVENT_ALARM_IRQ; + event = RTC_EVENT_ALARM_IRQ; } else { - rtc_context_data.event = RTC_EVENT_PERIODIC_IRQ; + event = RTC_EVENT_PERIODIC_IRQ; } - rtc_context_data.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&rtc_context_data); + /* Call callback */ + r_rtc_call_callback(p_ctrl, event); } /* Clear the IR flag in the ICU */ diff --git a/ra/fsp/src/r_sce/SCE_ProcCommon.h b/ra/fsp/src/r_sce/SCE_ProcCommon.h index 72d97b5e5..b2da7a549 100644 --- a/ra/fsp/src/r_sce/SCE_ProcCommon.h +++ b/ra/fsp/src/r_sce/SCE_ProcCommon.h @@ -24,6 +24,8 @@ #include #include "bsp_api.h" /* For Crypto Error codes */ +#include "SCE_module.h" + /* ================================================================================ */ /* ================ SCE ================ */ /* ================================================================================ */ @@ -31,137 +33,5000 @@ /** * @brief Trusted Security IP (SCE) */ - -typedef struct /*!< SCE Structure */ +typedef struct { - volatile uint32_t REG_00H; /*!< SCE register */ - volatile uint32_t REG_04H; /*!< SCE register */ - volatile uint32_t REG_08H; /*!< SCE register */ - volatile uint32_t REG_0CH; /*!< SCE register */ - volatile uint32_t REG_10H; /*!< SCE register */ - volatile uint32_t REG_14H; /*!< SCE register */ - volatile uint32_t REG_18H; /*!< SCE register */ - volatile uint32_t REG_1CH; /*!< SCE register */ - volatile uint32_t REG_20H; /*!< SCE register */ - volatile uint32_t REG_24H; /*!< SCE register */ - volatile uint32_t REG_28H; /*!< SCE register */ - volatile uint32_t REG_2CH; /*!< SCE register */ - volatile uint32_t REG_30H; /*!< SCE register */ - volatile uint32_t REG_34H; /*!< SCE register */ - volatile uint32_t REG_38H; /*!< SCE register */ - volatile uint32_t REG_3CH; /*!< SCE register */ - volatile uint32_t REG_40H; /*!< SCE register */ - volatile uint32_t REG_44H; /*!< SCE register */ - volatile uint32_t REG_48H; /*!< SCE register */ - volatile uint32_t REG_4CH; /*!< SCE register */ - volatile uint32_t REG_50H; /*!< SCE register */ - volatile uint32_t REG_54H; /*!< SCE register */ - volatile uint32_t REG_58H; /*!< SCE register */ - volatile uint32_t REG_5CH; /*!< SCE register */ - volatile uint32_t REG_60H; /*!< SCE register */ - volatile uint32_t REG_64H; /*!< SCE register */ - volatile uint32_t REG_68H; /*!< SCE register */ - volatile uint32_t REG_6CH; /*!< SCE register */ - volatile uint32_t REG_70H; /*!< SCE register */ - volatile uint32_t REG_74H; /*!< SCE register */ - volatile uint32_t REG_78H; /*!< SCE register */ - volatile uint32_t REG_7CH; /*!< SCE register */ - volatile uint32_t REG_80H; /*!< SCE register */ - volatile uint32_t REG_84H; /*!< SCE register */ - volatile uint32_t REG_88H; /*!< SCE register */ - volatile uint32_t REG_8CH; /*!< SCE register */ - volatile uint32_t REG_90H; /*!< SCE register */ - volatile uint32_t REG_94H; /*!< SCE register */ - volatile uint32_t REG_98H; /*!< SCE register */ - volatile uint32_t REG_9CH; /*!< SCE register */ - volatile uint32_t REG_A0H; /*!< SCE register */ - volatile uint32_t REG_A4H; /*!< SCE register */ - volatile uint32_t REG_A8H; /*!< SCE register */ - volatile uint32_t REG_ACH; /*!< SCE register */ - volatile uint32_t REG_B0H; /*!< SCE register */ - volatile uint32_t REG_B4H; /*!< SCE register */ - volatile uint32_t REG_B8H; /*!< SCE register */ - volatile uint32_t REG_BCH; /*!< SCE register */ - volatile uint32_t REG_C0H; /*!< SCE register */ - volatile uint32_t REG_C4H; /*!< SCE register */ - volatile uint32_t REG_C8H; /*!< SCE register */ - volatile uint32_t REG_CCH; /*!< SCE register */ - volatile uint32_t REG_D0H; /*!< SCE register */ - volatile uint32_t REG_D4H; /*!< SCE register */ - volatile uint32_t REG_D8H; /*!< SCE register */ - volatile uint32_t REG_DCH; /*!< SCE register */ - volatile uint32_t REG_E0H; /*!< SCE register */ - volatile uint32_t REG_E4H; /*!< SCE register */ - volatile uint32_t REG_E8H; /*!< SCE register */ - volatile uint32_t REG_ECH; /*!< SCE register */ - volatile uint32_t REG_F0H; /*!< SCE register */ - volatile uint32_t REG_F4H; /*!< SCE register */ - volatile uint32_t REG_F8H; /*!< SCE register */ - volatile uint32_t REG_FCH; /*!< SCE register */ - volatile uint32_t REG_100H; /*!< SCE register */ - volatile uint32_t REG_104H; /*!< SCE register */ - volatile uint32_t REG_108H; /*!< SCE register */ - volatile uint32_t REG_10CH; /*!< SCE register */ - volatile uint32_t REG_110H; /*!< SCE register */ - volatile uint32_t REG_114H; /*!< SCE register */ - volatile uint32_t REG_118H; /*!< SCE register */ - volatile uint32_t REG_11CH; /*!< SCE register */ - volatile uint32_t REG_120H; /*!< SCE register */ - volatile uint32_t REG_124H; /*!< SCE register */ - volatile uint32_t REG_128H; /*!< SCE register */ - volatile uint32_t REG_12CH; /*!< SCE register */ - volatile uint32_t REG_130H; /*!< SCE register */ - volatile uint32_t REG_134H; /*!< SCE register */ - volatile uint32_t REG_138H; /*!< SCE register */ - volatile uint32_t REG_13CH; /*!< SCE register */ - volatile uint32_t REG_140H; /*!< SCE register */ - volatile uint32_t REG_144H; /*!< SCE register */ - volatile uint32_t REG_148H; /*!< SCE register */ - volatile uint32_t REG_14CH; /*!< SCE register */ - volatile uint32_t REG_150H; /*!< SCE register */ - volatile uint32_t REG_154H; /*!< SCE register */ - volatile uint32_t REG_158H; /*!< SCE register */ - volatile uint32_t REG_15CH; /*!< SCE register */ - volatile uint32_t REG_160H; /*!< SCE register */ - volatile uint32_t REG_164H; /*!< SCE register */ - volatile uint32_t REG_168H; /*!< SCE register */ - volatile uint32_t REG_16CH; /*!< SCE register */ - volatile uint32_t REG_170H; /*!< SCE register */ - volatile uint32_t REG_174H; /*!< SCE register */ - volatile uint32_t REG_178H; /*!< SCE register */ - volatile uint32_t REG_17CH; /*!< SCE register */ - volatile uint32_t REG_180H; /*!< SCE register */ - volatile uint32_t REG_184H; /*!< SCE register */ - volatile uint32_t REG_188H; /*!< SCE register */ - volatile uint32_t REG_18CH; /*!< SCE register */ - volatile uint32_t REG_190H; /*!< SCE register */ - volatile uint32_t REG_194H; /*!< SCE register */ - volatile uint32_t REG_198H; /*!< SCE register */ - volatile uint32_t REG_19CH; /*!< SCE register */ - volatile uint32_t REG_1A0H; /*!< SCE register */ - volatile uint32_t REG_1A4H; /*!< SCE register */ - volatile uint32_t REG_1A8H; /*!< SCE register */ - volatile uint32_t REG_1ACH; /*!< SCE register */ - volatile uint32_t REG_1B0H; /*!< SCE register */ - volatile uint32_t REG_1B4H; /*!< SCE register */ - volatile uint32_t REG_1B8H; /*!< SCE register */ - volatile uint32_t REG_1BCH; /*!< SCE register */ - volatile uint32_t REG_1C0H; /*!< SCE register */ - volatile uint32_t REG_1C4H; /*!< SCE register */ - volatile uint32_t REG_1C8H; /*!< SCE register */ - volatile uint32_t REG_1CCH; /*!< SCE register */ - volatile uint32_t REG_1D0H; /*!< SCE register */ - volatile uint32_t REG_1D4H; /*!< SCE register */ - volatile uint32_t REG_1D8H; /*!< SCE register */ - volatile uint32_t REG_1DCH; /*!< SCE register */ - volatile uint32_t REG_1E0H; /*!< SCE register */ - volatile uint32_t REG_1E4H; /*!< SCE register */ - volatile uint32_t REG_1E8H; /*!< SCE register */ - volatile uint32_t REG_1ECH; /*!< SCE register */ - volatile uint32_t REG_1F0H; /*!< SCE register */ - volatile uint32_t REG_1F4H; /*!< SCE register */ - volatile uint32_t REG_1F8H; /*!< SCE register */ - volatile uint32_t REG_1FCH; /*!< SCE register */ + union + { + __IOM uint32_t REG_00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_00H_b; + }; + union + { + __IOM uint32_t REG_04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_04H_b; + }; + union + { + __IOM uint32_t REG_08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_08H_b; + }; + union + { + __IOM uint32_t REG_0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_0CH_b; + }; + union + { + __IOM uint32_t REG_10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10H_b; + }; + union + { + __IOM uint32_t REG_14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14H_b; + }; + union + { + __IOM uint32_t REG_18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18H_b; + }; + union + { + __IOM uint32_t REG_1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CH_b; + }; + union + { + __IOM uint32_t REG_20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20H_b; + }; + union + { + __IOM uint32_t REG_24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24H_b; + }; + union + { + __IOM uint32_t REG_28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_28H_b; + }; + union + { + __IOM uint32_t REG_2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2CH_b; + }; + union + { + __IOM uint32_t REG_30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_30H_b; + }; + union + { + __IOM uint32_t REG_34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_34H_b; + }; + union + { + __IOM uint32_t REG_38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_38H_b; + }; + union + { + __IOM uint32_t REG_3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3CH_b; + }; + union + { + __IOM uint32_t REG_40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_40H_b; + }; + union + { + __IOM uint32_t REG_44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_44H_b; + }; + union + { + __IOM uint32_t REG_48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_48H_b; + }; + union + { + __IOM uint32_t REG_4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4CH_b; + }; + union + { + __IOM uint32_t REG_50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_50H_b; + }; + union + { + __IOM uint32_t REG_54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_54H_b; + }; + union + { + __IOM uint32_t REG_58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_58H_b; + }; + union + { + __IOM uint32_t REG_5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5CH_b; + }; + union + { + __IOM uint32_t REG_60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_60H_b; + }; + union + { + __IOM uint32_t REG_64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_64H_b; + }; + union + { + __IOM uint32_t REG_68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_68H_b; + }; + union + { + __IOM uint32_t REG_6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6CH_b; + }; + union + { + __IOM uint32_t REG_70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_70H_b; + }; + union + { + __IOM uint32_t REG_74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_74H_b; + }; + union + { + __IOM uint32_t REG_78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_78H_b; + }; + union + { + __IOM uint32_t REG_7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7CH_b; + }; + union + { + __IOM uint32_t REG_80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_80H_b; + }; + union + { + __IOM uint32_t REG_84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_84H_b; + }; + union + { + __IOM uint32_t REG_88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_88H_b; + }; + union + { + __IOM uint32_t REG_8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8CH_b; + }; + union + { + __IOM uint32_t REG_90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_90H_b; + }; + union + { + __IOM uint32_t REG_94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_94H_b; + }; + union + { + __IOM uint32_t REG_98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_98H_b; + }; + union + { + __IOM uint32_t REG_9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9CH_b; + }; + union + { + __IOM uint32_t REG_A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A0H_b; + }; + union + { + __IOM uint32_t REG_A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A4H_b; + }; + union + { + __IOM uint32_t REG_A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A8H_b; + }; + union + { + __IOM uint32_t REG_ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ACH_b; + }; + union + { + __IOM uint32_t REG_B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B0H_b; + }; + union + { + __IOM uint32_t REG_B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B4H_b; + }; + union + { + __IOM uint32_t REG_B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B8H_b; + }; + union + { + __IOM uint32_t REG_BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BCH_b; + }; + union + { + __IOM uint32_t REG_C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C0H_b; + }; + union + { + __IOM uint32_t REG_C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C4H_b; + }; + union + { + __IOM uint32_t REG_C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C8H_b; + }; + union + { + __IOM uint32_t REG_CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CCH_b; + }; + union + { + __IOM uint32_t REG_D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D0H_b; + }; + union + { + __IOM uint32_t REG_D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D4H_b; + }; + union + { + __IOM uint32_t REG_D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D8H_b; + }; + union + { + __IOM uint32_t REG_DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DCH_b; + }; + union + { + __IOM uint32_t REG_E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E0H_b; + }; + union + { + __IOM uint32_t REG_E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E4H_b; + }; + union + { + __IOM uint32_t REG_E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E8H_b; + }; + union + { + __IOM uint32_t REG_ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ECH_b; + }; + union + { + __IOM uint32_t REG_F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F0H_b; + }; + union + { + __IOM uint32_t REG_F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F4H_b; + }; + union + { + __IOM uint32_t REG_F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F8H_b; + }; + union + { + __IOM uint32_t REG_FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FCH_b; + }; + union + { + __IOM uint32_t REG_100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_100H_b; + }; + union + { + __IOM uint32_t REG_104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_104H_b; + }; + union + { + __IOM uint32_t REG_108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_108H_b; + }; + union + { + __IOM uint32_t REG_10CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10CH_b; + }; + union + { + __IOM uint32_t REG_110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_110H_b; + }; + union + { + __IOM uint32_t REG_114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_114H_b; + }; + union + { + __IOM uint32_t REG_118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_118H_b; + }; + union + { + __IOM uint32_t REG_11CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11CH_b; + }; + union + { + __IOM uint32_t REG_120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_120H_b; + }; + union + { + __IOM uint32_t REG_124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_124H_b; + }; + union + { + __IOM uint32_t REG_128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_128H_b; + }; + union + { + __IOM uint32_t REG_12CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12CH_b; + }; + union + { + __IOM uint32_t REG_130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_130H_b; + }; + union + { + __IOM uint32_t REG_134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_134H_b; + }; + union + { + __IOM uint32_t REG_138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_138H_b; + }; + union + { + __IOM uint32_t REG_13CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13CH_b; + }; + union + { + __IOM uint32_t REG_140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_140H_b; + }; + union + { + __IOM uint32_t REG_144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_144H_b; + }; + union + { + __IOM uint32_t REG_148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_148H_b; + }; + union + { + __IOM uint32_t REG_14CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14CH_b; + }; + union + { + __IOM uint32_t REG_150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_150H_b; + }; + union + { + __IOM uint32_t REG_154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_154H_b; + }; + union + { + __IOM uint32_t REG_158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_158H_b; + }; + union + { + __IOM uint32_t REG_15CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15CH_b; + }; + union + { + __IOM uint32_t REG_160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_160H_b; + }; + union + { + __IOM uint32_t REG_164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_164H_b; + }; + union + { + __IOM uint32_t REG_168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_168H_b; + }; + union + { + __IOM uint32_t REG_16CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16CH_b; + }; + union + { + __IOM uint32_t REG_170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_170H_b; + }; + union + { + __IOM uint32_t REG_174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_174H_b; + }; + union + { + __IOM uint32_t REG_178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_178H_b; + }; + union + { + __IOM uint32_t REG_17CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17CH_b; + }; + union + { + __IOM uint32_t REG_180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_180H_b; + }; + union + { + __IOM uint32_t REG_184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_184H_b; + }; + union + { + __IOM uint32_t REG_188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_188H_b; + }; + union + { + __IOM uint32_t REG_18CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18CH_b; + }; + union + { + __IOM uint32_t REG_190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_190H_b; + }; + union + { + __IOM uint32_t REG_194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_194H_b; + }; + union + { + __IOM uint32_t REG_198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_198H_b; + }; + union + { + __IOM uint32_t REG_19CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19CH_b; + }; + union + { + __IOM uint32_t REG_1A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A0H_b; + }; + union + { + __IOM uint32_t REG_1A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A4H_b; + }; + union + { + __IOM uint32_t REG_1A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A8H_b; + }; + union + { + __IOM uint32_t REG_1ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ACH_b; + }; + union + { + __IOM uint32_t REG_1B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B0H_b; + }; + union + { + __IOM uint32_t REG_1B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B4H_b; + }; + union + { + __IOM uint32_t REG_1B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B8H_b; + }; + union + { + __IOM uint32_t REG_1BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BCH_b; + }; + union + { + __IOM uint32_t REG_1C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C0H_b; + }; + union + { + __IOM uint32_t REG_1C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C4H_b; + }; + union + { + __IOM uint32_t REG_1C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C8H_b; + }; + union + { + __IOM uint32_t REG_1CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CCH_b; + }; + union + { + __IOM uint32_t REG_1D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D0H_b; + }; + union + { + __IOM uint32_t REG_1D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D4H_b; + }; + union + { + __IOM uint32_t REG_1D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D8H_b; + }; + union + { + __IOM uint32_t REG_1DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DCH_b; + }; + union + { + __IOM uint32_t REG_1E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E0H_b; + }; + union + { + __IOM uint32_t REG_1E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E4H_b; + }; + union + { + __IOM uint32_t REG_1E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E8H_b; + }; + union + { + __IOM uint32_t REG_1ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ECH_b; + }; + union + { + __IOM uint32_t REG_1F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F0H_b; + }; + union + { + __IOM uint32_t REG_1F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F4H_b; + }; + union + { + __IOM uint32_t REG_1F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F8H_b; + }; + union + { + __IOM uint32_t REG_1FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FCH_b; + }; } SCE_Type; // for bit access @@ -232,17 +5097,11 @@ typedef struct /*!< SCE Structure #define SCE_REG_31_Pos 31 /*!< SCE REG_xxxH: bit 31 Position */ #define SCE_REG_31_Msk (0x01UL << SCE_REG_31_Pos) /*!< SCE REG_xxxH: bit 31 Mask */ -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define SCE_BASE 0x400C0000UL // should be changed for TAHOE - /* ================================================================================ */ /* ================ Peripheral declaration ================ */ /* ================================================================================ */ -#define SCE ((volatile SCE_Type *) SCE_BASE) +#define SCE ((SCE_Type *) SCE_BASE) // macro definishion diff --git a/ra/fsp/src/r_sce/common/hw_sce_common.h b/ra/fsp/src/r_sce/common/hw_sce_common.h index 777030ab2..463ac24d9 100644 --- a/ra/fsp/src/r_sce/common/hw_sce_common.h +++ b/ra/fsp/src/r_sce/common/hw_sce_common.h @@ -31,9 +31,6 @@ ***********************************************************************************************************************/ #include "bsp_api.h" -/* TODO_SCE RELEASE Remove mock reference */ -#if !BSP_MCU_MOCKED - /*********************************************************************************************************************** * Macro definitions ***********************************************************************************************************************/ @@ -59,11 +56,11 @@ **********************************************************************************************************************/ __STATIC_INLINE void HW_SCE_PowerOn (void) { - #if (defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA2L1)) +#if (defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA2L1)) // S1 MCU series has separate power control for RNG R_MSTP->MSTPCRC_b.MSTPC28 = 0; - #endif +#endif // power on the SCE module R_MSTP->MSTPCRC_b.MSTPC31 = 0; @@ -71,18 +68,16 @@ __STATIC_INLINE void HW_SCE_PowerOn (void) __STATIC_INLINE void HW_SCE_PowerOff (void) { - #if (defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA2L1)) +#if (defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA2L1)) // S1 MCU series has separate power control for RNG R_MSTP->MSTPCRC_b.MSTPC28 = 1; - #endif +#endif // power off the SCE module R_MSTP->MSTPCRC_b.MSTPC31 = 1; } -#endif /* BSP_MCU_MOCKED */ - #endif /* HW_SCE_COMMON_H */ /*******************************************************************************************************************//** diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c new file mode 100644 index 000000000..60e54cff7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_AES_adapt.c @@ -0,0 +1,204 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" + +typedef enum e_sce_aes_key_size +{ + SCE_AES_KEY_SIZE_128 = 0, + SCE_AES_KEY_SIZE_256 +} sce_aes_key_size_t; + +fsp_err_t (* init[])(const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, const uint32_t * InData_IV) = +{ + [SCE_AES_KEY_SIZE_128] = HW_SCE_Aes128EncryptDecryptInitSub, + [SCE_AES_KEY_SIZE_256] = HW_SCE_Aes256EncryptDecryptInitSub, +}; + +void (* update[])(const uint32_t * InData_Text, uint32_t * OutData_Text, const uint32_t MAX_CNT) = +{ + [SCE_AES_KEY_SIZE_128] = HW_SCE_Aes128EncryptDecryptUpdateSub, + [SCE_AES_KEY_SIZE_256] = HW_SCE_Aes256EncryptDecryptUpdateSub, +}; + +fsp_err_t (* final[])(void) = +{ + [SCE_AES_KEY_SIZE_128] = HW_SCE_Aes128EncryptDecryptFinalSub, + [SCE_AES_KEY_SIZE_256] = HW_SCE_Aes256EncryptDecryptFinalSub, +}; + +static fsp_err_t hw_sce_aes_encrypt_decrypt(sce_aes_key_size_t key_size, + uint32_t command, + const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +static fsp_err_t hw_sce_aes_encrypt_decrypt (sce_aes_key_size_t key_size, + uint32_t command, + const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + fsp_err_t status = FSP_ERR_CRYPTO_SCE_FAIL; + uint32_t indata_cmd = change_endian_long(command); /* ECB-Encrypt */ + uint32_t Dummy_IV[4] = {0}; + status = init[key_size](&indata_cmd, InData_KeyIndex, Dummy_IV); + if (FSP_SUCCESS == status) + { + update[key_size](InData_Text, OutData_Text, num_words); + status = final[key_size](); + } + + if (FSP_SUCCESS != status) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + return FSP_SUCCESS; + } +} + +fsp_err_t HW_SCE_AES_128EcbEncryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_128, + 0x00000000u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_128EcbDecryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_128, + 0x00000001u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_128EcbEncrypt (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_128, + 0x00000000u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_128EcbDecrypt (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_128, + 0x00000001u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_256EcbEncryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_256, + 0x00000000u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_256EcbDecryptUsingEncryptedKey (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_256, + 0x00000001u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_256EcbEncrypt (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_256, + 0x00000000u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_256EcbDecrypt (const uint32_t * InData_KeyIndex, + const uint32_t num_words, + const uint32_t * InData_Text, + uint32_t * OutData_Text) +{ + return hw_sce_aes_encrypt_decrypt(SCE_AES_KEY_SIZE_256, + 0x00000001u, + InData_KeyIndex, + num_words, + InData_Text, + OutData_Text); +} + +fsp_err_t HW_SCE_AES_128CreateEncryptedKey (uint32_t * OutData_KeyIndex) +{ + if (FSP_SUCCESS != HW_SCE_GenerateAes128RandomKeyIndexSub(OutData_KeyIndex)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_AES_256CreateEncryptedKey (uint32_t * OutData_KeyIndex) +{ + if (FSP_SUCCESS != HW_SCE_GenerateAes256RandomKeyIndexSub(OutData_KeyIndex)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c new file mode 100644 index 000000000..3f37a966b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_ECC_adapt.c @@ -0,0 +1,305 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" + +fsp_err_t HW_SCE_ECC_256HrkGenerateKey (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_KeyIndex, + uint32_t * OutData_PubKey) +{ + return HW_SCE_GenerateEccRandomKeyIndexSub(InData_DomainParam, InData_G, OutData_PubKey, OutData_KeyIndex); +} + +fsp_err_t HW_SCE_ECC_256GenerateKey (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_PrivKey, + uint32_t * OutData_PubKey) +{ + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(InData_G); + FSP_PARAMETER_NOT_USED(OutData_PrivKey); + FSP_PARAMETER_NOT_USED(OutData_PubKey); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_ECC_384GenerateKey (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_PrivKey, + uint32_t * OutData_PubKey) +{ + FSP_PARAMETER_NOT_USED(InData_DomainParam); + FSP_PARAMETER_NOT_USED(InData_G); + FSP_PARAMETER_NOT_USED(OutData_PrivKey); + FSP_PARAMETER_NOT_USED(OutData_PubKey); + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_ECC_384HrkGenerateKey (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + uint32_t * OutData_KeyIndex, + uint32_t * OutData_PubKey) +{ + FSP_PARAMETER_NOT_USED(InData_G); + + return HW_SCE_GenerateEccP384RandomKeyIndexSub(InData_DomainParam, OutData_PubKey, OutData_KeyIndex); +} + +fsp_err_t HW_SCE_ECC_256WrappedScalarMultiplication (const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + uint32_t * OutData_R) +{ + return HW_SCE_Ecc256ScalarMultiplicationSub(InData_CurveType, InData_Cmd, InData_KeyIndex, InData_P, OutData_R); +} + +fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication (const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + uint32_t * OutData_R) +{ + FSP_PARAMETER_NOT_USED(InData_Cmd); + return HW_SCE_Ecc384ScalarMultiplicationSub(InData_CurveType, InData_KeyIndex, InData_P, OutData_R); +} + +fsp_err_t HW_SCE_ECC_256GenerateSign (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S) +{ + uint32_t signature[HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U] = {0}; + uint32_t wrapped_private_key[13U]; + sce_oem_cmd_t key_command; + + /* NIST curve */ + if (0U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P256_PRIVATE; + } + /* Brainpool Curve */ + else if (1U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P256R1_PRIVATE; + } + /* Koblitz curve */ + else + { + key_command = SCE_OEM_CMD_ECC_SECP256K1_PRIVATE; + } + + /* Install the plaintext private key to get the wrapped key */ + fsp_err_t err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + key_command, + NULL, + NULL, + (const uint8_t *)InData_PrivKey, + wrapped_private_key); + if (FSP_SUCCESS == err) + { + err = HW_SCE_EcdsaSigunatureGenerateSub(InData_DomainParam, + InData_G, + wrapped_private_key, + InData_MsgDgst, + signature); + } + if (FSP_SUCCESS == err) + { + memcpy(OutData_R, signature, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + memcpy(OutData_S, &signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + } + + return err; +} + +fsp_err_t HW_SCE_ECC_256HrkGenerateSign (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S) +{ + uint32_t signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U)] = {0}; + fsp_err_t err = HW_SCE_EcdsaSigunatureGenerateSub(InData_DomainParam, + InData_G, + InData_KeyIndex, + InData_MsgDgst, + signature); + if (FSP_SUCCESS == err) + { + memcpy(OutData_R, signature, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + memcpy(OutData_S, &signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + } + + return err; +} + +fsp_err_t HW_SCE_ECC_384GenerateSign (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PrivKey, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S) +{ + uint32_t signature[HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U] = {0}; + uint32_t wrapped_private_key[17U]; + sce_oem_cmd_t key_command; + /* NIST curve */ + if (0U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P384_PRIVATE; + } + /* Brainpool Curve */ + else if (1U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P384R1_PRIVATE; + } + /* Koblitz curve unsupported */ + else + { + return FSP_ERR_UNSUPPORTED; + } + /* Install the plaintext private key to get the wrapped key */ + fsp_err_t err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + key_command, + NULL, + NULL, + (const uint8_t *)InData_PrivKey, + wrapped_private_key); + if (FSP_SUCCESS == err) + { + err = + HW_SCE_EcdsaP384SigunatureGenerateSub(InData_DomainParam, wrapped_private_key, InData_MsgDgst, signature); + } + if (FSP_SUCCESS == err) + { + memcpy(OutData_R, signature, (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); + memcpy(OutData_S, &signature[(HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U) / 2U], (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); + } + + return err; +} + +fsp_err_t HW_SCE_ECC_384HrkGenerateSign (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_MsgDgst, + uint32_t * OutData_R, + uint32_t * OutData_S) +{ + uint32_t signature[HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U] = {0}; + fsp_err_t err = HW_SCE_EcdsaP384SigunatureGenerateSub(InData_DomainParam, InData_KeyIndex, InData_MsgDgst, signature); + if (FSP_SUCCESS == err) + { + memcpy(OutData_R, signature, (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); + memcpy(OutData_S, &signature[(HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U) / 2U], (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); + } + + return err; +} + +fsp_err_t HW_SCE_ECC_256VerifySign (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PubKey, + const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, + const uint32_t * InData_S) +{ + uint32_t signature[HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U] = {0}; + uint32_t formatted_public_key[21U]; + memcpy(signature, InData_R, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + memcpy(&signature[(HW_SCE_ECDSA_DATA_BYTE_SIZE / 4U) / 2U], InData_S, (HW_SCE_ECDSA_DATA_BYTE_SIZE / 2U)); + sce_oem_cmd_t key_command; + /* NIST curve */ + if (0U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P256_PUBLIC; + } + /* Brainpool Curve */ + else if (1U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P256R1_PUBLIC; + } + /* Koblitz curve */ + else + { + key_command = SCE_OEM_CMD_ECC_SECP256K1_PUBLIC; + } + /* Install the plaintext public key to get the formatted public key */ + fsp_err_t err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + key_command, + NULL, + NULL, + (const uint8_t *)InData_PubKey, + formatted_public_key); + if (FSP_SUCCESS == err) + { + /* InData_DomainParam = curve type; InData_G = command */ + err = HW_SCE_EcdsaSigunatureVerificationSub(InData_DomainParam, InData_G, formatted_public_key, InData_MsgDgst, + signature); + } + return err; +} + +fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_DomainParam, + const uint32_t * InData_G, + const uint32_t * InData_PubKey, + const uint32_t * InData_MsgDgst, + const uint32_t * InData_R, + const uint32_t * InData_S) +{ + uint32_t signature[HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U] = {0}; + uint32_t formatted_public_key[29U]; + memcpy(signature, InData_R, (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); + memcpy(&signature[(HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U) / 2U], InData_S, (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); + + sce_oem_cmd_t key_command; + /* NIST curve */ + if (0U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P384_PUBLIC; + } + /* Brainpool Curve */ + else if (1U == *InData_DomainParam) + { + key_command = SCE_OEM_CMD_ECC_P384R1_PUBLIC; + } + /* Koblitz curve unsupported */ + else + { + return FSP_ERR_UNSUPPORTED; + } + /* Install the plaintext public key to get the formatted public key */ + fsp_err_t err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + key_command, + NULL, + NULL, + (const uint8_t *)InData_PubKey, + formatted_public_key); + if (FSP_SUCCESS == err) + { + err = HW_SCE_EcdsaP384SigunatureVerificationSub(InData_DomainParam, formatted_public_key, InData_MsgDgst, signature); + } + + return err; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c new file mode 100644 index 000000000..8af494886 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_HASH_adapt.c @@ -0,0 +1,31 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" + +fsp_err_t HW_SCE_SHA256_UpdateHash (const uint32_t * p_source, uint32_t num_words, uint32_t * p_digest) +{ + uint32_t out_data[8] = {0}; + fsp_err_t err = HW_SCE_Sha224256GenerateMessageDigestSub(p_digest, p_source, num_words, out_data); + memcpy(p_digest, out_data, (4U * num_words)); + + return err; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_RSA_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_RSA_adapt.c new file mode 100644 index 000000000..4cdf1651d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_RSA_adapt.c @@ -0,0 +1,213 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#include "hw_sce_private.h" +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_RSA_4096PublicKeyEncrypt (const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text) + +{ + fsp_err_t err = FSP_SUCCESS; + + /* Create storage to hold the generated OEM key index */ + sce_rsa4096_public_key_index_t formatted_rsa_public_key_output; + uint8_t formatted_rsa_public_key_input[HW_SCE_RSA4096_NE_KEY_BYTE_SIZE] = {0}; + memcpy(&formatted_rsa_public_key_input[0], InData_N, HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE); + memcpy(&formatted_rsa_public_key_input[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE], + InData_PublicKey, + HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE); + + err = + HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_RSA4096_PUBLIC, + NULL, + NULL, + (const uint8_t *) &formatted_rsa_public_key_input, + (uint32_t *) &formatted_rsa_public_key_output.value); + + if (FSP_SUCCESS == err) + { + err = HW_SCE_Rsa4096ModularExponentEncryptSub((uint32_t *) &formatted_rsa_public_key_output.value, + InData_Text, + OutData_Text); + } + + return err; +} + +fsp_err_t HW_SCE_RSA_3072PublicKeyEncrypt (const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text) + +{ + fsp_err_t err = FSP_SUCCESS; + + /* Create storage to hold the generated OEM key index */ + sce_rsa3072_public_key_index_t formatted_rsa_public_key_output; + uint8_t formatted_rsa_public_key_input[HW_SCE_RSA3072_NE_KEY_BYTE_SIZE] = {0}; + memcpy(&formatted_rsa_public_key_input[0], InData_N, HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE); + memcpy(&formatted_rsa_public_key_input[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE], + InData_PublicKey, + HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE); + + err = + HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_RSA3072_PUBLIC, + NULL, + NULL, + (const uint8_t *) &formatted_rsa_public_key_input, + (uint32_t *) &formatted_rsa_public_key_output.value); + + if (FSP_SUCCESS == err) + { + err = HW_SCE_Rsa3072ModularExponentEncryptSub((uint32_t *) &formatted_rsa_public_key_output.value, + InData_Text, + OutData_Text); + } + + return err; +} + +fsp_err_t HW_SCE_RSA_2048KeyGenerate (uint32_t num_tries, + uint32_t * OutData_PrivateKey, + uint32_t * OutData_N, + uint32_t * OutData_DomainParam) + +{ + FSP_PARAMETER_NOT_USED(num_tries); + FSP_PARAMETER_NOT_USED(OutData_PrivateKey); + FSP_PARAMETER_NOT_USED(OutData_N); + FSP_PARAMETER_NOT_USED(OutData_DomainParam); + + return FSP_ERR_UNSUPPORTED; +} + +fsp_err_t HW_SCE_RSA_2048PublicKeyEncrypt (const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text) + +{ + fsp_err_t err = FSP_SUCCESS; + + /* Create storage to hold the generated OEM key index */ + sce_rsa2048_public_key_index_t formatted_rsa_public_key_output; + uint8_t formatted_rsa_public_key_input[HW_SCE_RSA2048_NE_KEY_BYTE_SIZE] = {0}; + memcpy(&formatted_rsa_public_key_input[0], InData_N, HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE); + memcpy(&formatted_rsa_public_key_input[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE], + InData_PublicKey, + HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE); + + err = + HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_RSA2048_PUBLIC, + NULL, + NULL, + (const uint8_t *) &formatted_rsa_public_key_input, + (uint32_t *) &formatted_rsa_public_key_output.value); + + if (FSP_SUCCESS == err) + { + err = HW_SCE_Rsa2048ModularExponentEncryptSub((uint32_t *) &formatted_rsa_public_key_output.value, + InData_Text, + OutData_Text); + } + + return err; +} + +fsp_err_t HW_SCE_RSA_2048PrivateKeyDecrypt (const uint32_t * InData_Text, + const uint32_t * InData_PrivateKey, + const uint32_t * InData_N, + uint32_t * OutData_Text) + +{ + FSP_PARAMETER_NOT_USED(InData_PrivateKey); + fsp_err_t err = FSP_SUCCESS; + + /* Create storage to hold the generated OEM key index */ + sce_rsa2048_private_key_index_t encrypted_rsa_key; + + /*This function requires the plaintext RSA key is provided in a single buffer in the order: + * Public Key (N) of size RSA_MODULUS_SIZE_BYTES(x) + * Private Key (D) of size private_key_size_bytes + * The buffer in mbedtls_rsa_private() already contains the data in that format, so InData_N + * is directly provided to this function. + */ + err = + HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, SCE_OEM_CMD_RSA2048_PRIVATE, NULL, NULL, + (const uint8_t *) InData_N, (uint32_t *) &encrypted_rsa_key.value); + + if (FSP_SUCCESS == err) + { + err = HW_SCE_Rsa2048ModularExponentDecryptSub((uint32_t *) &encrypted_rsa_key.value, InData_Text, OutData_Text); + } + + return err; +} + +fsp_err_t HW_SCE_HRK_RSA_2048KeyGenerate (uint32_t num_tries, + uint32_t * OutData_KeyIndex, + uint32_t * OutData_N, + uint32_t * OutData_DomainParam) + +{ + sce_rsa2048_key_pair_index_t key_pair_index = {0}; + fsp_err_t err = FSP_SUCCESS; + + /* P.Q are the prime 1 and 2 fields that are in some cases generated when the private key is generated. + * This was the case with W1D; but this information is not provided on the RA6M4. + * There is no functional issue since the procedures do not require it for operation, + * however mbedCrypto requires these fields to be non-zero in order for the private key_export to work. + * These dummy values are placed into those fields to get past the non-zero check. */ + uint8_t dummy_P_Q[20] = {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; + + err = + HW_SCE_GenerateRsa2048RandomKeyIndexSub(num_tries, + (uint32_t *) &key_pair_index.public.value, + (uint32_t *) &key_pair_index.private.value); + + if (FSP_SUCCESS == err) + { + memcpy(OutData_KeyIndex, &key_pair_index.private.value, sizeof(key_pair_index.private.value)); + memcpy(OutData_N, &key_pair_index.public.value.key_n, sizeof(key_pair_index.public.value.key_n)); + memcpy(OutData_DomainParam, dummy_P_Q, sizeof(dummy_P_Q)); + } + + return err; +} + +fsp_err_t HW_SCE_HRK_RSA_2048PrivateKeyDecrypt (const uint32_t * InData_Text, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_N, + uint32_t * OutData_Text) + +{ + FSP_PARAMETER_NOT_USED(InData_N); + + fsp_err_t err = FSP_SUCCESS; + + err = HW_SCE_Rsa2048ModularExponentDecryptSub((uint32_t *) InData_KeyIndex, InData_Text, OutData_Text); + + return err; +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c new file mode 100644 index 000000000..862bb493d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/adaptors/r_sce_adapt.c @@ -0,0 +1,184 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "SCE_ProcCommon.h" +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +uint32_t INST_DATA_SIZE; + +/******************************************************* + * The following are valid SCE lifecycle states: + * + * CM1(Lifecycle state) + * + * CM2(Lifecycle state) + * + * SSD(Lifecycle state) + * + * NSECSD(Lifecycle state) + * + * DPL(Lifecycle state) + * + * LCK_DBG(Lifecycle state) + * + * LCK_BOOT(Lifecycle state) + * + * RMA_REQ(Lifecycle state) + * + * RMA_ACK(Lifecycle state) + ****************************************************/ + +#define FSP_SCE_DLMMON_MASK 0x0000000F /* for lcs in stored in R_PSCU->DLMMON */ + +const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM] = +{ + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD, +}; + +/* Find the lifecycle state load the hardware unique key */ +/* returns fsp_err_t */ + +fsp_err_t HW_SCE_HUK_Load_LCS (void) +{ + uint32_t lc_state = R_PSCU->DLMMON & FSP_SCE_DLMMON_MASK; + + return HW_SCE_LoadHukSub(&lc_state); +} + +/* SCE9 specific initialization functions */ +/* returns fsp_err_t */ + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; + + // power on the SCE module + HW_SCE_PowerOn(); + + HW_SCE_SoftwareResetSub(); + iret = HW_SCE_SelfCheck1Sub(); + + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_SelfCheck2Sub(); + + /* Change SCE to little endian mode */ + SCE->REG_1D4H = 0x0000ffff; + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_HUK_Load_LCS(); + + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_FwIntegrityCheck(); + } + } + } + + return iret; +} + +fsp_err_t HW_SCE_RNG_Read (uint32_t * OutData_Text) +{ + if (FSP_SUCCESS != HW_SCE_GenerateRandomNumberSub(OutData_Text)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, + const sce_oem_cmd_t cmd, + const uint8_t * encrypted_provisioning_key, + const uint8_t * iv, + const uint8_t * encrypted_oem_key, + uint32_t * key_index) +{ + uint32_t indata_key_type[1] = {0}; + uint32_t indata_cmd[1] = {0}; + uint32_t install_key_ring_index[1] = {0}; + indata_key_type[0] = key_type; + indata_cmd[0] = (cmd); + install_key_ring_index[0] = 0U; + + INST_DATA_SIZE = sce_oem_key_size[cmd] - 4U; + + /* Casting uint32_t pointer is used for address. */ + return HW_SCE_GenerateOemKeyIndexSub(indata_key_type, + indata_cmd, + install_key_ring_index, + (uint32_t *) encrypted_provisioning_key, + (uint32_t *) iv, + (uint32_t *) encrypted_oem_key, + key_index); +} + +uint32_t change_endian_long (uint32_t a) +{ + return __REV(a); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c new file mode 100644 index 000000000..d11b95dfa --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func000.c @@ -0,0 +1,102 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func000(uint32_t *InData_PaddedMsg, int32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 16) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[iLoop + 0]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 1]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 2]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 3]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 4]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 5]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 6]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 7]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 8]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 9]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 10]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 11]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 12]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 13]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 14]; + SCE->REG_100H = InData_PaddedMsg[iLoop + 15]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_104H = 0x00000000u; + SCE->REG_1CH = 0x00001600u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func000.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c new file mode 100644 index 000000000..a9dc906b2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func001.c @@ -0,0 +1,136 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func001(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040000u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_A4H = 0x00050805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00005143u; + SCE->REG_104H = 0x00000f51u; + SCE->REG_A4H = 0x00000c85u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_A4H = 0x00000cc5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_B0H = 0x00000100u; + SCE->REG_A4H = 0x00008887u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + SCE->REG_100H = change_endian_long(0x36363636u); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func001.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c new file mode 100644 index 000000000..e1fbd0a88 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func002.c @@ -0,0 +1,118 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func002(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_00H = 0x00005143u; + SCE->REG_104H = 0x00000f51u; + SCE->REG_A4H = 0x00000c85u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_A4H = 0x00000cc5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_B0H = 0x00000100u; + SCE->REG_A4H = 0x00008887u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + SCE->REG_100H = change_endian_long(0x5c5c5c5cu); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func002.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c new file mode 100644 index 000000000..3fe52818b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func027.c @@ -0,0 +1,328 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func027_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x01305c44u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0142859du; + SCE->REG_ECH = 0x00000080u; + SCE->REG_C4H = 0x00443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000c3e1cu; + SCE->REG_E0H = 0x810103c0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00003b62u; + SCE->REG_D0H = 0x00000e00u; + SCE->REG_C4H = 0x02f087bfu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+28 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+32 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+36 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x00000015u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+40 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+44 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+48 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x00000013u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+52 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+56 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+60 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x0000001du; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+64 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+68 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+72 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x0000001cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+76 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+80 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+84 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000b62u; + SCE->REG_D0H = 0x00000200u; + SCE->REG_C4H = 0x00f087bfu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+88 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+92 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+96 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x000007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+100 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func027_r2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c new file mode 100644 index 000000000..7e8a40314 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func028.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func028_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x01166403u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x013659ffu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_C4H = 0x00443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000c3e1cu; + SCE->REG_E0H = 0x810103c0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00001762u; + SCE->REG_D0H = 0x00000500u; + SCE->REG_C4H = 0x02f087bfu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+0 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+8 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+12 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+16 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+20 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 3]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x0000001bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x000007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+24 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func028_r2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c new file mode 100644 index 000000000..defeadce4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func043.c @@ -0,0 +1,178 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func043(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x763017c1u, 0xa6e06e5cu, 0x413ee7c5u, 0x8be19d82u); + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x000001d0u; + SCE->REG_E0H = 0x8188000au; + SCE->REG_C4H = 0x00080805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x661813d3u, 0x1f0216ddu, 0xdb1c9067u, 0xe4e2daeeu); + SCE->REG_C4H = 0x00090805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x41d550f1u, 0x3237f543u, 0x559f9bcau, 0x9aceaba9u); + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x000001c0u; + SCE->REG_E0H = 0x8184000au; + SCE->REG_C4H = 0x000c0805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x3778e67fu, 0x59eb9657u, 0x649d9837u, 0x6e6ab952u); + SCE->REG_C4H = 0x00000b8cu; + SCE->REG_E0H = 0x810100e0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x80040140u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00008d40u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x00009140u; + SCE->REG_ECH = 0x01000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00448a04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00008e95u; + SCE->REG_E0H = 0x81040140u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00008d40u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x00009140u; + SCE->REG_ECH = 0x02000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00448a04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00098e15u; + SCE->REG_E0H = 0x81040140u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x1bbad22du, 0xbc25efb7u, 0x0737ee54u, 0x5dcc4009u); + SCE->REG_C4H = 0x00080805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func043.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c new file mode 100644 index 000000000..9b8fb004a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func044.c @@ -0,0 +1,128 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func044(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xcc2b6612u, 0x09aeabefu, 0xf30f09aau, 0xcd0102c9u); + SCE->REG_ECH = 0x00008ce0u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x000090e0u; + SCE->REG_ECH = 0x01000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00448a04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00008e94u; + SCE->REG_E0H = 0x810100e0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00008ce0u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x000090e0u; + SCE->REG_ECH = 0x02000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00448a04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00098e14u; + SCE->REG_E0H = 0x810100e0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x99fe09e3u, 0x8a2aaee4u, 0xdcec14e9u, 0x4d2dcd38u); + SCE->REG_C4H = 0x00080805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func044.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c new file mode 100644 index 000000000..4c7d37735 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func048.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func048(uint32_t* ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1[0]); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func048.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c new file mode 100644 index 000000000..bf8e69012 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func049.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func049(uint32_t* ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1[0]); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func049.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c new file mode 100644 index 000000000..16d2f435f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func050.c @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func050(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806Au; + SCE->REG_F0H = 0x00000000u; + SCE->REG_14H = 0x10000000u; + SCE->REG_10CH = change_endian_long(ARG1); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func050.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c new file mode 100644 index 000000000..04c7c4401 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func051.c @@ -0,0 +1,73 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func051(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806Au; + SCE->REG_F0H = 0x00000000u; + SCE->REG_10CH = 0x00010001u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func051.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c new file mode 100644 index 000000000..882e4850e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func052.c @@ -0,0 +1,82 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func052(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func051(); + SCE->REG_28H = 0x00000001u; + SCE->REG_3CH = change_endian_long(ARG1); + SCE->REG_14H = 0x00003008u; + SCE->REG_14H = 0x00003018u; + SCE->REG_1D0H = 0x00000000u; + SCE->REG_1D0H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func052.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c new file mode 100644 index 000000000..7afa3da9a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func053.c @@ -0,0 +1,82 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func053(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func051(); + SCE->REG_80H = 0x00000001u; + SCE->REG_8CH = change_endian_long(ARG1); + SCE->REG_14H = 0x00003008u; + SCE->REG_14H = 0x00003018u; + SCE->REG_1D0H = 0x00000000u; + SCE->REG_1D0H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func053.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c new file mode 100644 index 000000000..0460a9f27 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func054.c @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func054(uint32_t ARG1, uint32_t ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_14H = change_endian_long(ARG1); + SCE->REG_14H = change_endian_long(ARG2); + SCE->REG_1D0H = 0x00000000u; + SCE->REG_1D0H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func054.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c new file mode 100644 index 000000000..3fbc1c4d2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func057.c @@ -0,0 +1,522 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func057_r1(uint32_t* ARG1, uint32_t* ARG2, uint32_t* ARG3) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xf31fc280u, 0xb1f04b9eu, 0x9454ff9bu, 0x9c90f37eu); + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000ffu); + HW_SCE_p_func101(0xab47b184u, 0xfa6aa1bfu, 0x2f5a393fu, 0x383be959u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x000034e4u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000feu); + HW_SCE_p_func101(0x8579d3eau, 0x0270bbfcu, 0x83222df1u, 0x72d3673du); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x09b4fe19u, 0xcd9e71fau, 0x41f1394cu, 0xd138ac96u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func081(); + SCE->REG_ECH = 0x00007c01u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0xd863f335u, 0x104e1c40u, 0x70842eb1u, 0xa48e0ba2u); + SCE->REG_00H = 0x80002100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00d049a6u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02e087b6u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[0]; + SCE->REG_100H = ARG2[1]; + SCE->REG_100H = ARG2[2]; + SCE->REG_100H = ARG2[3]; + for (iLoop = 0; iLoop < (INST_DATA_SIZE-8) ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[4+iLoop + 0]; + SCE->REG_100H = ARG2[4+iLoop + 1]; + SCE->REG_100H = ARG2[4+iLoop + 2]; + SCE->REG_100H = ARG2[4+iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + iLoop = iLoop + 4; + oLoop = iLoop; + HW_SCE_p_func202();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x4ca67631u, 0xbfe8efa6u, 0x42650b01u, 0x9a59c797u); + } + else if (0x0a000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0xc39300fcu, 0x932823bau, 0xdc7a21f7u, 0x41e8b020u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_00H = 0x00003183u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func061(0,ARG2); + iLoop = 0 + 32; + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_D0H = 0x40000700u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_04H = 0x00000282u; + for(oLoop=0; oLoop<32; oLoop=oLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x4efe8e8au, 0xfeed2dfcu, 0xdadb5c4au, 0x65e1b33du); + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00d049a5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + iLoop = iLoop + 4; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + SCE->REG_00H = 0x00002113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0xa393ce95u, 0x386cc78fu, 0x4a0dde05u, 0x23b90198u); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func062(36,ARG3); + oLoop = 36 + 32; + HW_SCE_p_func101(0xb78e40beu, 0x9a507c58u, 0xa058119cu, 0x4604a55au); + } + else if (0x0b000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x0ec0ae03u, 0xbdb21de0u, 0x33e56e86u, 0x9376b996u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_00H = 0x00003183u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func061(0,ARG2); + iLoop = 0 + 32; + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func062(0,ARG3); + oLoop = 0 + 32; + HW_SCE_p_func100(0x04750e53u, 0x7952bb79u, 0xc5800b7eu, 0x403b9779u); + SCE->REG_00H = 0x00003183u; + SCE->REG_2CH = 0x00000011u; + HW_SCE_p_func061(32,ARG2); + iLoop = 32 + 32; + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000021u; + HW_SCE_p_func062(32,ARG3); + oLoop = 32 + 32; + HW_SCE_p_func100(0xf1f9707fu, 0x25d81b4fu, 0x22350d39u, 0x14f1ca2au); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func062(64,ARG3); + oLoop = 64 + 32; + HW_SCE_p_func101(0x03dad023u, 0xcec3eca2u, 0xaa31e30fu, 0x45a27577u); + } + else if (0x0c000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x40b8f383u, 0xcc74ecfdu, 0xa253bdf2u, 0x5d08ae64u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func063(0,ARG2); + iLoop = 0 + 64; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_04H = 0x00000202u; + for(oLoop=0; oLoop<64; oLoop=oLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xd5560200u, 0x28a09e8eu, 0xdf18a10au, 0xa09ce3bdu); + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00d049a5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + iLoop = iLoop + 4; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + SCE->REG_00H = 0x00002113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0xb55664d8u, 0xdda299b2u, 0xa618943du, 0x763fa4a4u); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func064(68,ARG3); + oLoop = 68 + 64; + HW_SCE_p_func101(0x197c0cd4u, 0x2641e686u, 0xca561b5au, 0x3a15237au); + } + else if (0x0d000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0xbe980790u, 0x643b9dc7u, 0x163962b6u, 0xc3cc6613u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func063(0,ARG2); + iLoop = 0 + 64; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func064(0,ARG3); + oLoop = 0 + 64; + HW_SCE_p_func100(0x7e2b313au, 0xa6926a4du, 0x837b0236u, 0xe47c35d1u); + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func063(64,ARG2); + iLoop = 64 + 64; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func064(64,ARG3); + oLoop = 64 + 64; + HW_SCE_p_func100(0xee7b76e5u, 0xc6116ce8u, 0x9952521eu, 0xf6ef1e2fu); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func064(128,ARG3); + oLoop = 128 + 64; + HW_SCE_p_func101(0x0bbc011eu, 0x8bf07c60u, 0x4ce1e9aau, 0x24601a0cu); + } + else if (0x12000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0xdb02e3c5u, 0x8f35d0d4u, 0xb1fca80fu, 0xd78d93b5u); + SCE->REG_00H = 0x80002100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00d049a6u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02e08886u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[0]; + SCE->REG_100H = ARG2[1]; + SCE->REG_100H = ARG2[2]; + SCE->REG_100H = ARG2[3]; + for (iLoop = 0; iLoop < (INST_DATA_SIZE-8) ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[4+iLoop + 0]; + SCE->REG_100H = ARG2[4+iLoop + 1]; + SCE->REG_100H = ARG2[4+iLoop + 2]; + SCE->REG_100H = ARG2[4+iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+iLoop + 0] = SCE->REG_100H; + ARG3[1+iLoop + 1] = SCE->REG_100H; + ARG3[1+iLoop + 2] = SCE->REG_100H; + ARG3[1+iLoop + 3] = SCE->REG_100H; + iLoop = iLoop + 4; + oLoop = iLoop; + HW_SCE_p_func202();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x0052d385u, 0xd76d9a95u, 0x7739e2c2u, 0x966b5ef3u); + } + HW_SCE_p_func100(0xd3371c6du, 0xd24af252u, 0x239fe0dcu, 0x815b0e6cu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG3[1+oLoop + 0] = SCE->REG_100H; + ARG3[1+oLoop + 1] = SCE->REG_100H; + ARG3[1+oLoop + 2] = SCE->REG_100H; + ARG3[1+oLoop + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x000049a5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + SCE->REG_A4H = 0x00900c45u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00007c1cu; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func057_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c new file mode 100644 index 000000000..6672fd601 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func058.c @@ -0,0 +1,159 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func058(uint32_t* ARG1, uint32_t ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xf09a7897u, 0xa3a7a023u, 0x3b7a61fdu, 0x362e6610u); + SCE->REG_C4H = 0x00443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000c3e1cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0174d08au); + HW_SCE_p_func100(0x884433ccu, 0x9a27dd57u, 0x8cdc7aa3u, 0xbb2d9912u); + SCE->REG_ECH = 0x00009020u; + SCE->REG_ECH = 0x01000000u; + SCE->REG_C4H = 0x00440a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000c0e1cu; + SCE->REG_E0H = 0x81010020u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa363e8a4u, 0x95c20c4fu, 0x7c0172d7u, 0xdab18365u); + SCE->REG_A4H = 0x02fb073du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG2 + 0]; + SCE->REG_100H = S_FLASH2[ARG2 + 1]; + SCE->REG_100H = S_FLASH2[ARG2 + 2]; + SCE->REG_100H = S_FLASH2[ARG2 + 3]; + HW_SCE_p_func100(0xc113d43fu, 0x19520dc7u, 0x0b311f0au, 0x07b8b3c5u); + SCE->REG_A4H = 0x000007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG2+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG2+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG2+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG2+4 + 3]; + SCE->REG_A4H = 0x00800c45u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00087a05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + HW_SCE_p_func100(0x81625709u, 0x8fa95ce2u, 0xa44190b7u, 0xe2458f05u); + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00097a05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[4]; + SCE->REG_100H = ARG1[5]; + SCE->REG_100H = ARG1[6]; + SCE->REG_100H = ARG1[7]; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func058.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c new file mode 100644 index 000000000..bcb573eb0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func059.c @@ -0,0 +1,108 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func059(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xaf5c1169u, 0xccd8bd52u, 0x88a2f82fu, 0xd9406fc9u); + SCE->REG_ECH = 0x00008d40u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x00009140u; + SCE->REG_ECH = 0x01000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00442a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x00082e0du; + SCE->REG_E0H = 0x81040140u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xef23bf66u, 0x10c19a29u, 0x3551f208u, 0xce071e80u); + SCE->REG_ECH = 0x00008d40u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x00009140u; + SCE->REG_ECH = 0x02000000u; + SCE->REG_C4H = 0x00092e0du; + SCE->REG_E0H = 0x81040140u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func059.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c new file mode 100644 index 000000000..43f3cb9ca --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func060.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func060(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_18H = 0x00000004u; + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func060.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c new file mode 100644 index 000000000..6b355eebf --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func061.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func061(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00001f61u; + SCE->REG_B0H = 0x00000700u; + SCE->REG_A4H = 0x00d0c9a7u; + for(iLoop=ARG1; iLoopREG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func061.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c new file mode 100644 index 000000000..164342466 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func062.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func062(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x40000700u; + SCE->REG_C4H = 0x00e087b7u; + SCE->REG_04H = 0x00000282u; + for(oLoop=ARG1; oLoopREG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func062.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c new file mode 100644 index 000000000..5f098fb3e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func063.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func063(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f61u; + SCE->REG_B0H = 0x00000f00u; + SCE->REG_A4H = 0x00d0c9a7u; + for(iLoop=ARG1; iLoopREG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func063.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c new file mode 100644 index 000000000..6f2d9a5f1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func064.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func064(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00e087b7u; + SCE->REG_04H = 0x00000202u; + for(oLoop=ARG1; oLoopREG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func064.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c new file mode 100644 index 000000000..ff3863091 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func065.c @@ -0,0 +1,484 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func065_r1(uint32_t* ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x23a20f43u, 0xb31e013bu, 0x7d30fa57u, 0xddf885eeu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000011u); + HW_SCE_p_func101(0xabc8f62eu, 0xa0b4b4cdu, 0xabed9fedu, 0x55efaa74u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x000034e4u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000011u); + HW_SCE_p_func101(0x79da836fu, 0x01a8f4b7u, 0x4410b933u, 0x7d62b94du); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xfef7fdd1u, 0x5e78f5c3u, 0xd66fdca4u, 0x5b2ab651u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00050804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func081(); + SCE->REG_ECH = 0x00007c01u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x3b31b2c7u, 0xfdedce3fu, 0xf2657d0au, 0x9d2cac16u); + SCE->REG_00H = 0x80002100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000886u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02e087b6u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + for (iLoop = 0; iLoop < (INST_DATA_SIZE-4) ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[4+iLoop + 0]; + SCE->REG_100H = ARG1[4+iLoop + 1]; + SCE->REG_100H = ARG1[4+iLoop + 2]; + SCE->REG_100H = ARG1[4+iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+iLoop + 0] = SCE->REG_100H; + ARG2[1+iLoop + 1] = SCE->REG_100H; + ARG2[1+iLoop + 2] = SCE->REG_100H; + ARG2[1+iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+iLoop + 0] = SCE->REG_100H; + ARG2[1+iLoop + 1] = SCE->REG_100H; + ARG2[1+iLoop + 2] = SCE->REG_100H; + ARG2[1+iLoop + 3] = SCE->REG_100H; + iLoop = iLoop + 4; + oLoop = iLoop; + HW_SCE_p_func202();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x26483003u, 0x4db2d050u, 0x1fb2570au, 0x627d3e3bu); + } + else if (0x0a000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x2be8ca08u, 0xf05b8eaau, 0xeb20462au, 0xc40e8c69u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_00H = 0x00003183u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func066(0,ARG1); + iLoop = 0 + 32; + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_D0H = 0x40000700u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_04H = 0x00000282u; + for(oLoop=0; oLoop<32; oLoop=oLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xc47ff753u, 0x04506ad6u, 0x013e3dd5u, 0xbe1ead25u); + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00000885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[iLoop + 0]; + SCE->REG_100H = ARG1[iLoop + 1]; + SCE->REG_100H = ARG1[iLoop + 2]; + SCE->REG_100H = ARG1[iLoop + 3]; + iLoop = iLoop + 4; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + SCE->REG_00H = 0x00002113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0x3b861e61u, 0xb600ea62u, 0x4bf70f4eu, 0xff3c1866u); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func062(36,ARG2); + oLoop = 36 + 32; + HW_SCE_p_func101(0x23e8fb2eu, 0x74657e4du, 0x076514e5u, 0xb519809cu); + } + else if (0x0b000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x65278693u, 0x04fabe2eu, 0xfc2fa6d5u, 0x9de2decbu); + SCE->REG_28H = 0x009f0001u; + SCE->REG_00H = 0x00003183u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func066(0,ARG1); + iLoop = 0 + 32; + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func062(0,ARG2); + oLoop = 0 + 32; + HW_SCE_p_func100(0x7fa0d5a1u, 0x3517f529u, 0x36e90eafu, 0x91f1dc4bu); + SCE->REG_00H = 0x00003183u; + SCE->REG_2CH = 0x00000011u; + HW_SCE_p_func066(32,ARG1); + iLoop = 32 + 32; + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000021u; + HW_SCE_p_func062(32,ARG2); + oLoop = 32 + 32; + HW_SCE_p_func100(0xcaa3bb50u, 0xd6691c2bu, 0xc5ff2240u, 0x7f7071bdu); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func062(64,ARG2); + oLoop = 64 + 32; + HW_SCE_p_func101(0x8427d069u, 0x71e1837eu, 0x1d040576u, 0x0c34e400u); + } + else if (0x0c000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0xa26076b9u, 0x10e94805u, 0x196f6ef1u, 0xf38da63du); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func067(0,ARG1); + iLoop = 0 + 64; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_04H = 0x00000202u; + for(oLoop=0; oLoop<64; oLoop=oLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa56b7d5du, 0xf4486507u, 0x64d0b38fu, 0x04fb55a5u); + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00000885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[iLoop + 0]; + SCE->REG_100H = ARG1[iLoop + 1]; + SCE->REG_100H = ARG1[iLoop + 2]; + SCE->REG_100H = ARG1[iLoop + 3]; + iLoop = iLoop + 4; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + SCE->REG_00H = 0x00002113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0x4aed1905u, 0xe5d8ff2eu, 0xcee610e7u, 0x2b56f36cu); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func064(68,ARG2); + oLoop = 68 + 64; + HW_SCE_p_func101(0x953dbb7cu, 0x684783a0u, 0xec9db7b7u, 0xeadfcaa6u); + } + else if (0x0d000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x0da69955u, 0x4c58a953u, 0x660176a5u, 0xb9ae0c4eu); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func067(0,ARG1); + iLoop = 0 + 64; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func064(0,ARG2); + oLoop = 0 + 64; + HW_SCE_p_func100(0x58754c97u, 0xd4752e10u, 0x9fa38d8fu, 0xbe29908fu); + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func067(64,ARG1); + iLoop = 64 + 64; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func064(64,ARG2); + oLoop = 64 + 64; + HW_SCE_p_func100(0x3ab34648u, 0x51ed9b48u, 0x476e0a97u, 0x9dd57620u); + HW_SCE_p_func060(); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func064(128,ARG2); + oLoop = 128 + 64; + HW_SCE_p_func101(0x25db8d2cu, 0xd2c88a95u, 0x654191cbu, 0x45fcaca9u); + } + else if (0x12000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func100(0x546d42e4u, 0x4fab67fau, 0x54171dfeu, 0x01b96779u); + SCE->REG_00H = 0x80002100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000886u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02e08886u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[0]; + SCE->REG_100H = ARG1[1]; + SCE->REG_100H = ARG1[2]; + SCE->REG_100H = ARG1[3]; + for (iLoop = 0; iLoop < (INST_DATA_SIZE-4) ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG1[4+iLoop + 0]; + SCE->REG_100H = ARG1[4+iLoop + 1]; + SCE->REG_100H = ARG1[4+iLoop + 2]; + SCE->REG_100H = ARG1[4+iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+iLoop + 0] = SCE->REG_100H; + ARG2[1+iLoop + 1] = SCE->REG_100H; + ARG2[1+iLoop + 2] = SCE->REG_100H; + ARG2[1+iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+iLoop + 0] = SCE->REG_100H; + ARG2[1+iLoop + 1] = SCE->REG_100H; + ARG2[1+iLoop + 2] = SCE->REG_100H; + ARG2[1+iLoop + 3] = SCE->REG_100H; + iLoop = iLoop + 4; + oLoop = iLoop; + HW_SCE_p_func202();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x0afcbf2fu, 0xc4a4aabau, 0x39c6470fu, 0x02417d40u); + } + HW_SCE_p_func100(0xd3371c6du, 0xd24af252u, 0x239fe0dcu, 0x815b0e6cu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + ARG2[1+oLoop + 0] = SCE->REG_100H; + ARG2[1+oLoop + 1] = SCE->REG_100H; + ARG2[1+oLoop + 2] = SCE->REG_100H; + ARG2[1+oLoop + 3] = SCE->REG_100H; + SCE->REG_ECH = 0x00007c1cu; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func065_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c new file mode 100644 index 000000000..55d6be917 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func066.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func066(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00001f61u; + SCE->REG_B0H = 0x00000700u; + SCE->REG_A4H = 0x00008887u; + for(iLoop=ARG1; iLoopREG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func066.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c new file mode 100644 index 000000000..4ea2a87ec --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func067.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func067(uint32_t ARG1, uint32_t* ARG2) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f61u; + SCE->REG_B0H = 0x00000f00u; + SCE->REG_A4H = 0x00008887u; + for(iLoop=ARG1; iLoopREG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = ARG2[iLoop + 0]; + SCE->REG_100H = ARG2[iLoop + 1]; + SCE->REG_100H = ARG2[iLoop + 2]; + SCE->REG_100H = ARG2[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func067.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c new file mode 100644 index 000000000..b45d6cb5e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func068.c @@ -0,0 +1,108 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func068(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xd4a52766u, 0x8a66b39cu, 0x3e9135a1u, 0x2cc5d444u); + SCE->REG_ECH = 0x00008d40u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x00009140u; + SCE->REG_ECH = 0x01000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00442a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x00082e0cu; + SCE->REG_E0H = 0x81010140u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xb473d362u, 0xa92dfd51u, 0x9eb15e5au, 0x0ba44048u); + SCE->REG_ECH = 0x00008d40u; + SCE->REG_ECH = 0x00ffffffu; + SCE->REG_ECH = 0x00009140u; + SCE->REG_ECH = 0x02000000u; + SCE->REG_C4H = 0x00092e0cu; + SCE->REG_E0H = 0x81010140u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func068.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c new file mode 100644 index 000000000..ef42caca4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func070.c @@ -0,0 +1,284 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func070_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0131ec45u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x014bb610u; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x01542614u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x01ba24feu; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x01bb59d6u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00870001u; + SCE->REG_C4H = 0x00443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000c3e1cu; + SCE->REG_E0H = 0x810103c0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00002f62u; + SCE->REG_D0H = 0x00000b00u; + SCE->REG_C4H = 0x02f087bfu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+68 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+68 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+72 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+72 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000015u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+76 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+76 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+80 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+80 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000009au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+84 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+84 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+88 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+88 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000001du; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+92 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+92 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+96 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+96 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000009du; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+100 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+100 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+104 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+104 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+108 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+108 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+112 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+112 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x000007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+116 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+116 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func070_r2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c new file mode 100644 index 000000000..2f650bdc0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func071.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func071_r2(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x017d423au; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0163c737u; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x017c67d8u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0126ddb5u; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x01bcfa36u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00870001u; + SCE->REG_C4H = 0x00443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000c3e1cu; + SCE->REG_E0H = 0x810103c0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00003f62u; + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x02f087bfu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+0 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+0 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+4 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+4 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+8 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+8 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+12 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+12 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000001bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+16 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+16 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+20 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+20 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000098u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+24 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+24 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+28 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+28 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000099u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+32 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+32 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+36 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+36 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000094u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+40 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+40 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+44 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+44 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000095u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+48 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+48 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+52 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+52 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000009cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+56 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+56 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+60 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+60 + 3]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000009du; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x000007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH2[ARG1+64 + 0]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 1]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 2]; + SCE->REG_100H = S_FLASH2[ARG1+64 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func071_r2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c new file mode 100644 index 000000000..7748ee081 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func074.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func074_r1(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000023u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001du; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000017u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000015u; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000013u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func074_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c new file mode 100644 index 000000000..f43962b0a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func075.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func075_r1(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000022u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000016u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000012u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func075_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c new file mode 100644 index 000000000..f98149efd --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func076.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func076(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000019u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x00000080u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func076.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c new file mode 100644 index 000000000..f63b6122b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func077.c @@ -0,0 +1,78 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func077(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001eu; + SCE->REG_ECH = 0x00000080u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func077.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c new file mode 100644 index 000000000..3ecf76770 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func080.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func080(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00440a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x00080e9cu; + SCE->REG_E0H = 0x81010020u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func080.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c new file mode 100644 index 000000000..b918e939f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func081.c @@ -0,0 +1,152 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func081(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x00003424u; + SCE->REG_ECH = 0x3420a880u; + SCE->REG_ECH = 0x0000000au; + SCE->REG_ECH = 0x10000821u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000000du; + SCE->REG_ECH = 0x342028e4u; + SCE->REG_ECH = 0x10000821u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000012u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_104H = 0x00000958u; + SCE->REG_E0H = 0x808a001fu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000012u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000014u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000016u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000018u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000001cu); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000001eu); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000020u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000000eu); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000010u); + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000022u); + for(iLoop=0; iLoop<10; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x00003bdfu; + SCE->REG_ECH = 0x3800089eu; + SCE->REG_ECH = 0x10003427u; + SCE->REG_ECH = 0x000027fdu; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func081.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c new file mode 100644 index 000000000..e7f7eccf1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func100.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x000f3a8du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B16) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func100.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c new file mode 100644 index 000000000..17edf1a06 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func101.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x000e3a8du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B17) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func101.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c new file mode 100644 index 000000000..7e76d7c72 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func102.c @@ -0,0 +1,80 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x000d3a8du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(ARG1); + SCE->REG_100H = change_endian_long(ARG2); + SCE->REG_100H = change_endian_long(ARG3); + SCE->REG_100H = change_endian_long(ARG4); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func102.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c new file mode 100644 index 000000000..daed00e47 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func103.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func103(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000252u; + SCE->REG_C4H = 0x01003774u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x010037f4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x010037f4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x00060805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01073644u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x000b0805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func103.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c new file mode 100644 index 000000000..c6b7ee2e6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func200.c @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func200(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_04H = 0x00000000u; + SCE->REG_104H = 0x00000000u; + SCE->REG_1CH = 0x002c0000u; + SCE->REG_1CH = 0x002d0000u; + SCE->REG_B0H = 0x00000001u; + SCE->REG_A4H = 0x00000000u; + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00000000u; + SCE->REG_1CH = 0x002e0000u; + SCE->REG_1CH = 0x002f0000u; + SCE->REG_D0H = 0x00000001u; + SCE->REG_C4H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func200.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c new file mode 100644 index 000000000..dbeeedecf --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func202.c @@ -0,0 +1,77 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func202(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000u; + SCE->REG_104H = 0x00000000u; + SCE->REG_A4H = 0x00000000u; + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00000000u; + SCE->REG_C4H = 0x00000000u; + SCE->REG_1CH = 0x00000900u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func202.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c new file mode 100644 index 000000000..2aeaf2be2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func206.c @@ -0,0 +1,76 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func206(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_04H = 0x00000000u; + SCE->REG_104H = 0x00000000u; + SCE->REG_1CH = 0x002c0000u; + SCE->REG_1CH = 0x002d0000u; + SCE->REG_B0H = 0x00000001u; + SCE->REG_A4H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func206.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c new file mode 100644 index 000000000..32f931b2f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func300.c @@ -0,0 +1,1180 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func300(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38008fc0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x1000381fu; + SCE->REG_ECH = 0x100027e1u; + SCE->REG_ECH = 0x00002fc0u; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x80000000u; + SCE->REG_ECH = 0x20002c40u; + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000863u; + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_ECH = 0x1000d060u; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x80000000u; + SCE->REG_ECH = 0x2000d061u; + SCE->REG_ECH = 0x38008860u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x7cb9bdc4u, 0xe2ed2e73u, 0x4a5b41a8u, 0x425eb43eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xd0c4c720u, 0x1d3105e5u, 0x59d8a4afu, 0x0aca73a5u); + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000a41u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008860u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x05080e70u, 0x42335a73u, 0xa2816ca7u, 0x60d9a58eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x5439d1d0u, 0xf77edaccu, 0x57b2b29fu, 0xdd61d360u); + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x80000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x6881e9fbu, 0x06aa6fdfu, 0x762ffc17u, 0x0ae7d84au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x1e20aafbu, 0x0da3797bu, 0x1af729a3u, 0x9c0738b4u); + } + else + { + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x646bf0ddu, 0x564d0572u, 0xea3a4866u, 0x1d52fff8u); + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x900019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x80000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x5784ad1eu, 0x63814257u, 0x33a4b910u, 0x1700cf71u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x8b0b83e6u, 0x57999af5u, 0x29955b52u, 0xa5f96b63u); + } + else + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xdd3bb8cau, 0x5d1667a4u, 0x248aebc8u, 0x3a8569d1u); + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x80000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x3a6b9affu, 0x96c744c5u, 0x2ba5e0d7u, 0x473b64d7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x6d4b179bu, 0xd894c624u, 0x41aec014u, 0x3b6a07ccu); + } + else + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x4585ea52u, 0xc7508304u, 0xa730e47du, 0x56bff85au); + } + SCE->REG_ECH = 0x38000bc4u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x19bb82dau, 0x8e4d3bddu, 0x159c1223u, 0x100a1ebfu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002f80u; + HW_SCE_p_func100(0x9496dc85u, 0x5565ff4fu, 0x0e3ae0fcu, 0x5fccf5f2u); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; + } + else + { + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000208u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001141u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800094d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xdc69660au, 0x37cc1f51u, 0x3a646afcu, 0x133dad9du); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xb93c6b4eu, 0xdaa196c9u, 0xf84a2b35u, 0x80f87383u); + } + else + { + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xc769e365u, 0x6330fdfdu, 0x3604efb4u, 0xb017fb9eu); + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800002d1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x8000014au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00016c00u; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func300.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c new file mode 100644 index 000000000..241ef399d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func301.c @@ -0,0 +1,264 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func301(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800016c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func301.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c new file mode 100644 index 000000000..a3bc06bad --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func302.c @@ -0,0 +1,1172 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func302(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x38008fc0u; + SCE->REG_ECH = 0x0000001fu; + SCE->REG_ECH = 0x1000381fu; + SCE->REG_ECH = 0x100027e1u; + SCE->REG_ECH = 0x00002fc0u; + SCE->REG_ECH = 0x38008c00u; + SCE->REG_ECH = 0x80000000u; + SCE->REG_ECH = 0x20002c40u; + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x0be803f1u, 0xaf43b4fbu, 0xc4b808e5u, 0x656569c2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x7e98a73bu, 0xd8a9ce59u, 0xdb79f215u, 0xa333be2cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000863u; + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x97923a72u, 0xf3c1b530u, 0x377b742du, 0x1cfbe97fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x7b388408u, 0x87cdbf3du, 0x2de37e3eu, 0x6980acafu); + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000a41u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x8c171365u, 0x2d85eca3u, 0x2870eac6u, 0x0728f6e1u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xf0b2a5cfu, 0x92e837e0u, 0xc8e075efu, 0x5e47de2eu); + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x2c7196a2u, 0x36fb8304u, 0xafce3eb1u, 0xaeaee9a8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xb5777ab6u, 0x40e740a5u, 0x49575931u, 0xf19d5425u); + } + else + { + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xb2724ea1u, 0x7c74561fu, 0xa0b5d998u, 0x57550da6u); + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x900019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x75ba536du, 0x2e30f36cu, 0xb3324f38u, 0x5968458cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x802b0684u, 0x69264948u, 0x4286494bu, 0x3bdd8e36u); + } + else + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x44ebc595u, 0x10b0e3a3u, 0x777d4c82u, 0xd06d541bu); + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xb09dccf4u, 0x63be4033u, 0x60160e20u, 0xcbb759d4u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x7eb1a8abu, 0xbac3f161u, 0x463f7896u, 0x8c21338au); + } + else + { + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xfc93967bu, 0xa7d222e5u, 0x1a38ceaeu, 0x64f35868u); + } + } + else + { + HW_SCE_p_func101(0x42dbdae1u, 0xd6c90dadu, 0xf0da9152u, 0x4af05ac5u); + } + SCE->REG_ECH = 0x38000bc4u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x04c62050u, 0x85471239u, 0x431e9a1eu, 0x94e9736cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002f80u; + HW_SCE_p_func100(0x0ca11aceu, 0xf756a0aau, 0x85202c6bu, 0xeafbb7edu); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; + } + else + { + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000208u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001141u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800094d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00002c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800002d1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000302cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x8000014au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000282cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func101(0x52430301u, 0x4929e648u, 0xddef7975u, 0x2d2cf120u); + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; + } + } + else + { + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func101(0x2feff25fu, 0xfcd487ebu, 0x6afa67d6u, 0x32960ea4u); + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func302.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c new file mode 100644 index 000000000..45d3a8634 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func304.c @@ -0,0 +1,2173 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func304(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000024u; + SCE->REG_ECH = 0x00003c1eu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d779u; + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x00000b18u; + SCE->REG_E0H = 0x80010300u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x000000adu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000031fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x3800db1fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xe5986152u, 0x77a0ec4cu, 0x96bf2690u, 0x6a2cacffu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x10ff3fe3u, 0x4b460b48u, 0x277e1172u, 0x463feb78u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d379u; + HW_SCE_p_func101(0x969611fbu, 0x4648fd51u, 0x43577ed6u, 0xff05cec7u); + } + HW_SCE_p_func100(0xab8c8692u, 0xebf4f03eu, 0xcca553b8u, 0x62b91c3au); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x017da167u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf2ca2938u, 0xa80f39e9u, 0xc43330dau, 0xf5fde800u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func313(1156); + HW_SCE_p_func100(0xb49d7ef6u, 0x65fe3fafu, 0xcdf2ff51u, 0x40cac15bu); + HW_SCE_p_func314(1156+64); + SCE->REG_ECH = 0x00000b5au; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d77cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x3800db7au; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x01dd3aa3u, 0xe9b30484u, 0xe9ee2277u, 0xf9d02553u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000157u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000110u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xd26d42ffu, 0xc3695e06u, 0x9cf5af99u, 0x9bfeede5u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00003340u; + HW_SCE_p_func101(0xefd40792u, 0x390bb84au, 0x4c63e1c2u, 0x269e897bu); + } + else + { + HW_SCE_p_func101(0x7ea798c1u, 0x39d52927u, 0xb2a79290u, 0xfca05510u); + oLoop1 = 0; + } + } + SCE->REG_ECH = 0x0000d37cu; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x00002b9au; + SCE->REG_ECH = 0x0000375cu; + HW_SCE_p_func101(0xb4818009u, 0x9240b2ceu, 0x392a2156u, 0xedf546aeu); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xcf9e1796u, 0xe867c7f2u, 0x0c8b147au, 0x5844a87eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x64029b2fu, 0x0f0e1921u, 0x574ab5cbu, 0x278bca4bu); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002f40u; + HW_SCE_p_func101(0xe2b49ae6u, 0x659727f9u, 0x3a18be25u, 0x6e781766u); + } + } + HW_SCE_p_func101(0xa170ddb7u, 0x02cde70cu, 0x20f0afa1u, 0x6e9e2b7au); + } + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000b39u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d77du; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x3800db7bu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x3d1e1391u, 0xc39a7bdbu, 0x02df7a57u, 0xa1095da7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000157u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000110u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x9ffb65aau, 0x2cf47374u, 0x960cbf4bu, 0xe0d92891u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00003320u; + HW_SCE_p_func101(0x9f6d4d47u, 0x5a540a97u, 0x90e36ff3u, 0xb3e0c0e5u); + } + else + { + HW_SCE_p_func101(0x428b2571u, 0xa7416f10u, 0x0de2c174u, 0x45a203f0u); + oLoop1 = 0; + } + } + SCE->REG_ECH = 0x0000d37du; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x00002b99u; + SCE->REG_ECH = 0x0000373cu; + HW_SCE_p_func101(0x6acd5fb2u, 0xdf585e2eu, 0x1c716be9u, 0xff0414eau); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xcdb35358u, 0x9476764cu, 0xa8981e90u, 0xdd46be8bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xbd0b86adu, 0x8c871c31u, 0xdfd5d06cu, 0xf4194799u); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002f20u; + HW_SCE_p_func101(0x568a7b8bu, 0x164d8cdeu, 0xdb712a97u, 0xf572288du); + } + } + HW_SCE_p_func101(0xc33dc603u, 0x8a8373acu, 0x372774ccu, 0x978192f9u); + } + HW_SCE_p_func100(0x3461b0c9u, 0xd8ad5898u, 0xe4570345u, 0x8d731553u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcdb27765u, 0x54ad18a7u, 0x2a027349u, 0xaa40ee12u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(1088); + HW_SCE_p_func100(0x6ca37557u, 0xd24a3739u, 0x7c970af6u, 0x200ecc3eu); + HW_SCE_p_func314(1088+64); + HW_SCE_p_func100(0x65e7019au, 0xc524e055u, 0x269764ceu, 0x48b54eefu); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x0000480cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xdbfd0b8cu, 0x55072b70u, 0x2b8d035au, 0xe0f5939au); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(1224); + HW_SCE_p_func100(0xdc20f138u, 0xd0d20635u, 0x62fe940fu, 0x16494aeeu); + HW_SCE_p_func314(1224+64); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00800001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x80010380u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800103a0u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x000000adu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000031fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000012u; + SCE->REG_104H = 0x00000767u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x40000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_34H = 0x00000030u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800dbbeu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x71b9f77bu, 0x15ebca7bu, 0xf7ac0f68u, 0x4f17baf2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d375u; + HW_SCE_p_func101(0x3adaeacau, 0x6e43d4abu, 0x8db7589fu, 0xc4323a0eu); + } + else + { + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d775u; + HW_SCE_p_func101(0x7efebc70u, 0xe8bbac54u, 0x76d54f63u, 0xc908420bu); + } + HW_SCE_p_func100(0xc22d191fu, 0x4585204au, 0xe46132b0u, 0x3b5fcb5au); + SCE->REG_34H = 0x00000c00u; + SCE->REG_24H = 0x8000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013d2cc1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6d3ccc34u, 0xfd034277u, 0xe9f917a1u, 0x4b7fe353u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func313(1428); + HW_SCE_p_func100(0xae117735u, 0x1a2569e6u, 0x41130d87u, 0x42e20119u); + HW_SCE_p_func314(1428+64); + HW_SCE_p_func100(0x0f09dc1bu, 0x0d25ed9bu, 0xc647791bu, 0x2b003f89u); + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c80cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(1224); + SCE->REG_ECH = 0x0000d776u; + SCE->REG_ECH = 0x3800db75u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x5cc64a69u, 0xf2a44982u, 0xc740beb0u, 0x6a2516bdu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x33b90ce4u, 0x5db0e894u, 0x00e112ddu, 0xf58dcd06u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d376u; + SCE->REG_28H = 0x00800001u; + SCE->REG_104H = 0x00000257u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_2CH = 0x00000110u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFu); + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xae9e04cfu, 0xd330fbdeu, 0x30d4edf8u, 0xc9a2ff40u); + } + else + { + SCE->REG_ECH = 0x0000d776u; + SCE->REG_28H = 0x00800001u; + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00000067u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xcd1f90deu, 0x9ac953a4u, 0xfeda1414u, 0xec875363u); + } + } + else + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x5f5687adu, 0xae101c00u, 0x054dc8e3u, 0x12360356u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d376u; + SCE->REG_28H = 0x00800001u; + SCE->REG_104H = 0x00000257u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_2CH = 0x00000110u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFu); + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xffbb0cbcu, 0x0e646d5cu, 0xce376485u, 0x470e965bu); + } + else + { + SCE->REG_ECH = 0x0000d776u; + SCE->REG_28H = 0x00800001u; + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00000067u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xd2c19e49u, 0xe40ff80du, 0x83aeb8a3u, 0xbd0e4c85u); + } + } + HW_SCE_p_func100(0x18b5fb6cu, 0x7d7790ffu, 0x9c25c4f6u, 0x8c05cb7fu); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000189u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000189u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000189u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000189u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016be062u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xda802bb3u, 0x2d8929d6u, 0x76e9e8cfu, 0xdbc5b788u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(1360); + HW_SCE_p_func100(0xe6339cf1u, 0xb532bf6au, 0xa3482974u, 0xd9807aecu); + HW_SCE_p_func314(1360+64); + HW_SCE_p_func100(0x6bc0e5eau, 0x4aedebcau, 0xa9fcf8f6u, 0x785dfbb8u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x000037dcu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016be062u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcb65077au, 0x4d3fa4b8u, 0x1cfe2b93u, 0x8d794d55u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(1360); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x017da167u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x402e7dbfu, 0xfadf9e7eu, 0x4687ad22u, 0x8fe85d29u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(1156); + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x80010380u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x810103c0u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010380u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x800103c0u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00008fc0u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x0000d777u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x3000dbc3u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x00002bddu; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000d377u; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x00002b9eu; + SCE->REG_ECH = 0x000037dcu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013d2cc1u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1428); + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x3800db77u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xc0dff601u, 0xdd161907u, 0x3683b9ecu, 0xfbd124aeu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func100(0x143b4871u, 0xb551f34eu, 0xd21077e6u, 0x930f4960u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002fe0u; + HW_SCE_p_func101(0xe0c3f7d3u, 0x43549f5eu, 0x91d5a220u, 0xc0ccba56u); + } + HW_SCE_p_func101(0x5615313fu, 0x56817861u, 0xebc2c1acu, 0x5531da32u); + } + else + { + HW_SCE_p_func100(0x32226c01u, 0x47382077u, 0x5543d625u, 0x0538b162u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002fe0u; + HW_SCE_p_func101(0xda5dda6eu, 0x33afdb96u, 0x36b203a6u, 0x4450e14au); + } + HW_SCE_p_func101(0x3afc982bu, 0x640862e2u, 0xdee123a1u, 0xca8502c7u); + } + SCE->REG_ECH = 0x38000bdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0x06131c0au, 0x4c7c54f5u, 0x3ab8cdceu, 0xb791ca1cu); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016be062u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1360); + SCE->REG_ECH = 0x3800db76u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x8abe5331u, 0x481743e0u, 0x5b657230u, 0xbf6f27d2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000190u); + HW_SCE_p_func101(0x8f559563u, 0x97af0837u, 0xd313a066u, 0xa2705e73u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xb42e3262u, 0x9859ebaeu, 0x954f236bu, 0x77816924u); + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d378u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d778u; + SCE->REG_ECH = 0x00000080u; + HW_SCE_p_func100(0xc9ed9bb6u, 0x433b0541u, 0xcc23870au, 0x214a676bu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016efbeau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x713e9a08u, 0x75913315u, 0x841cf33du, 0xb3a1c40du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(1292); + HW_SCE_p_func100(0x76276a5du, 0xf64ab6d3u, 0x8e0a61c5u, 0x3355b0fdu); + HW_SCE_p_func314(1292+64); + HW_SCE_p_func100(0xb5d07c20u, 0x8e60825au, 0x1ca4c842u, 0x53189972u); + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x81010320u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x81010340u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x80010300u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000d77eu; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x3000db7cu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x00002fc0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x3000db7du; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x00002fc0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x3000dbc0u; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d77eu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d37eu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1088); + SCE->REG_ECH = 0x3000db7cu; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d76bu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d36bu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x000037dau; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000097u; + HW_SCE_p_func101(0x3f40f3f7u, 0xbcae5503u, 0xa1e66292u, 0x25e9989cu); + HW_SCE_p_func310(); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3000db7du; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d76bu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d36bu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x000037d9u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000098u; + HW_SCE_p_func101(0x2549e4eau, 0xa0d3cc6fu, 0x23a5edaau, 0xd5bffedau); + HW_SCE_p_func310(); + HW_SCE_p_func100(0xe6e2105fu, 0xf966fefeu, 0x430a3701u, 0x6a1b7bcbu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x017da167u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1156); + SCE->REG_ECH = 0x3000db7eu; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d76bu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d36bu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x000037d8u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000099u; + HW_SCE_p_func101(0xfa5ebe91u, 0x608dd2a2u, 0x703e6190u, 0xe345f97au); + HW_SCE_p_func310(); + HW_SCE_p_func100(0x7098f4e1u, 0x755029a7u, 0xcf086487u, 0x3a769432u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016efbeau); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1292); + SCE->REG_ECH = 0x3800db78u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xb5e88869u, 0x47d1e807u, 0x1f8e358du, 0x13c8289fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001u; + SCE->REG_104H = 0x00000257u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_2CH = 0x00000190u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFu); + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x1e90575au, 0x6f9e8914u, 0x56924477u, 0x20dfd07du); + } + else + { + HW_SCE_p_func101(0xee9e77e3u, 0x6eae0791u, 0x4ab75099u, 0x0a8da033u); + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x3800db79u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x6dfc72e1u, 0x4aa97e03u, 0x9fefa641u, 0xb7d6a06au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func100(0xa6fcc1c7u, 0x509bfa42u, 0xd75055a0u, 0x559ad70fu); + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d368u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d768u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1224); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d372u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d772u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000098d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xc3143860u, 0xcb79a6fdu, 0x9bf4bad1u, 0x20e4b647u); + } + else + { + HW_SCE_p_func100(0x8d0528ddu, 0x4e505ffbu, 0xe5a9e4e6u, 0x71567e2eu); + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d368u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d768u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d772u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a2b89bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(1224); + HW_SCE_p_func101(0x5fc4a8f8u, 0x188438f1u, 0x443f6818u, 0xdc8f97a7u); + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000024u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func304.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c new file mode 100644 index 000000000..22d8615f5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func307.c @@ -0,0 +1,521 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func307(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000090u; + SCE->REG_ECH = 0x00003c1eu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000080u; + HW_SCE_p_func101(0x46765f77u, 0x5749f546u, 0xffae0ff7u, 0x8b2d018eu); + HW_SCE_p_func311(); + SCE->REG_ECH = 0x00000a73u; + SCE->REG_ECH = 0x00000a31u; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00002e20u; + SCE->REG_ECH = 0x38002673u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x0efed670u, 0x4c5eb194u, 0xde5be454u, 0x29041d0fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x733f12abu, 0xecc5543eu, 0xc537a171u, 0x48357424u); + } + else + { + HW_SCE_p_func100(0x2d664c4du, 0xd9d9fd9du, 0xe34eae6au, 0x62d43b41u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe804d856u, 0xe4909999u, 0xa52e04fdu, 0xfe75ac58u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(204); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x517c7161u, 0x77c03114u, 0x61d87db2u, 0x4f1c9985u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(136); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x989e30fdu, 0xfb087ef5u, 0xec2e871bu, 0x64eb0658u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(476); + HW_SCE_p_func100(0xbf56fa09u, 0x821175ccu, 0x1891f091u, 0x8f3b024au); + HW_SCE_p_func314(476+64); + HW_SCE_p_func100(0xd2825fcdu, 0xc659f6e8u, 0x10029c48u, 0x47827fb5u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa3c241c7u, 0x45c0ad6bu, 0xe6a7bb38u, 0x84b04d8bu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(612); + HW_SCE_p_func100(0x3f406e95u, 0x13025ff8u, 0xf8b51b24u, 0x4c05351cu); + HW_SCE_p_func314(612+64); + HW_SCE_p_func100(0x0830ae7au, 0x6d43b3e9u, 0xd4ccc5eau, 0xe6dcdce5u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x40901979u, 0xc4600862u, 0x60d83598u, 0xf0d8941fu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(408); + HW_SCE_p_func100(0x2c04ab0bu, 0x0e747ad8u, 0x7eb80229u, 0xf876f457u); + HW_SCE_p_func314(408+64); + HW_SCE_p_func100(0xa016bd2cu, 0x3aa9aa45u, 0x7542dc38u, 0xdcc879c6u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x20c49ee6u, 0x329d4116u, 0xa1fa89feu, 0x0340299cu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(544); + HW_SCE_p_func100(0x6e9c8d98u, 0x6120d3adu, 0x665f0919u, 0x27efb3bau); + HW_SCE_p_func314(544+64); + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000081u; + HW_SCE_p_func101(0xca53192fu, 0x211abfddu, 0xa870386fu, 0xb8e79d3eu); + HW_SCE_p_func309(); + HW_SCE_p_func100(0xcd35d372u, 0x54dbdbceu, 0xb0afbbdbu, 0xf796fc29u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xaee9f5b2u, 0x522163adu, 0x95ef5614u, 0x66787e86u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(204); + HW_SCE_p_func100(0x2e1850f0u, 0x07ff76f0u, 0xce36e13cu, 0x6eea89e8u); + HW_SCE_p_func314(204+64); + HW_SCE_p_func100(0x05d76537u, 0xa64e6099u, 0x19533700u, 0x491094b8u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe6475365u, 0x1fae56fbu, 0x565db664u, 0xa6771660u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(136); + HW_SCE_p_func100(0xfe310ec6u, 0xff3bb340u, 0x3af230a3u, 0xbcedede9u); + HW_SCE_p_func314(136+64); + HW_SCE_p_func101(0x9fa02c96u, 0xfaf805deu, 0x6623feddu, 0xbc1389aeu); + } + SCE->REG_ECH = 0x3800da9fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x3d92f89au, 0xa4b197f4u, 0x583087f9u, 0x353f282du); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x60afc885u, 0xc0ff181bu, 0x12ea81aeu, 0x2804d93eu); + } + else + { + HW_SCE_p_func100(0xb9b491e0u, 0x1463bd81u, 0x8cdca180u, 0x461e2b79u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x909714ffu, 0xd0219bf6u, 0x9f8fbbbdu, 0xd4083fd2u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(204); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(136); + HW_SCE_p_func100(0x5592c700u, 0x5a6eaa8au, 0xd9bf08bdu, 0x69ab981du); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x5925d68du, 0x7a61ecf6u, 0x5bae60ccu, 0x83f7e3a4u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(476); + HW_SCE_p_func100(0xa3ca016bu, 0x8aaf93d3u, 0xbdc90e30u, 0x56d8ac7du); + HW_SCE_p_func314(476+64); + HW_SCE_p_func100(0xb313c752u, 0x5c602865u, 0xec2fe69cu, 0x7be094a4u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa821b521u, 0x461c4e09u, 0x65b8de9cu, 0x3ce623a5u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(408); + HW_SCE_p_func100(0x1360b584u, 0xf686799du, 0xab5b69bfu, 0x19469924u); + HW_SCE_p_func314(408+64); + HW_SCE_p_func100(0x7af0c270u, 0x7ed6ff84u, 0x92765f4fu, 0xc608e17fu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6964e4b4u, 0xe864d305u, 0xc84d8bb4u, 0x07ec5ec8u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(68); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7au); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(0); + HW_SCE_p_func100(0xd7e164c0u, 0x1ecc338bu, 0x510e64e7u, 0x6a2613a5u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4e82d9a2u, 0x40be6e96u, 0x0fe40003u, 0x6ff6e827u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(612); + HW_SCE_p_func100(0xa348c089u, 0x43d0ff84u, 0x778ff6b8u, 0x67521438u); + HW_SCE_p_func314(612+64); + HW_SCE_p_func100(0xdc825e03u, 0x32ed1ec4u, 0x42c88adfu, 0x371b0bc8u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0e29cd80u, 0x38300037u, 0x45986240u, 0x957d7b77u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(544); + HW_SCE_p_func100(0x4e55f63au, 0x2241701bu, 0x4a60cce7u, 0x29c0bbd9u); + HW_SCE_p_func314(544+64); + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000082u; + HW_SCE_p_func101(0x8389d01fu, 0xe6c6ffddu, 0x142d5ccfu, 0x7a0e9c6du); + HW_SCE_p_func309(); + HW_SCE_p_func100(0xdee3518fu, 0xb273ad82u, 0x9fe71ee7u, 0x2edf8f2cu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb9c1509fu, 0xbf54f012u, 0x98c8652au, 0x203d25fcu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(204); + HW_SCE_p_func100(0x8eea8326u, 0x2d4020ceu, 0x4d41424cu, 0xe4982805u); + HW_SCE_p_func314(204+64); + HW_SCE_p_func100(0xbf7df5f8u, 0x324650cau, 0x225fdd08u, 0x90466761u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x45705ce6u, 0xd8eacde4u, 0x3a795df3u, 0xbe5b4797u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(136); + HW_SCE_p_func100(0x1fe6691eu, 0xe9108d9au, 0x57f0bf4cu, 0x6708d01cu); + HW_SCE_p_func314(136+64); + SCE->REG_ECH = 0x0000d260u; + HW_SCE_p_func101(0x6358b604u, 0x6dc2d12bu, 0x6cbb7715u, 0x3eb0ec45u); + } + SCE->REG_ECH = 0x01816e94u; + HW_SCE_p_func101(0xf737726cu, 0x7dc9f6f9u, 0xe1731169u, 0x6df578f1u); + } + SCE->REG_ECH = 0x38008a20u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0x07ff897au, 0x247d24c7u, 0xfbf81f2cu, 0x1baceb97u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x5035ba16u, 0xf255a3adu, 0x1ed0bc13u, 0x92e894d5u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(204); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4a5f6826u, 0xfa67b379u, 0x995c12b3u, 0x2c6cab19u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(136); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9f2effcau, 0xfa8f0918u, 0x75ac2514u, 0xf921ad9fu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(476); + HW_SCE_p_func100(0x932f0373u, 0x17ca4781u, 0x75f63f1du, 0x12347107u); + HW_SCE_p_func314(476+64); + HW_SCE_p_func100(0x5e19c95eu, 0x1bf7f515u, 0xa49b9e82u, 0xdebab01eu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc5a99131u, 0x9797c7d3u, 0xea9c1037u, 0xb9f0451du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(408); + HW_SCE_p_func100(0x95a8001eu, 0x9fb1b0ecu, 0xf62ab0a9u, 0x2b362008u); + HW_SCE_p_func314(408+64); + HW_SCE_p_func100(0x4bcfab8fu, 0x3ffb18cfu, 0x786aa6c9u, 0x3bab7324u); + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4078b7d0u, 0x46f98634u, 0x880c48a1u, 0x7cf1df0du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(612); + HW_SCE_p_func100(0x68145b96u, 0x8dfc7766u, 0xc0a86193u, 0x9d16ea7au); + HW_SCE_p_func314(612+64); + HW_SCE_p_func100(0xb2940826u, 0xa63e577fu, 0x926b6b1eu, 0x16a88b70u); + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x17c2749cu, 0x8d75c162u, 0xfd7d6916u, 0x945b30a9u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(544); + HW_SCE_p_func100(0x5cdf4f3du, 0xc1445dfau, 0x7c2cd0aau, 0x42ffc8a0u); + HW_SCE_p_func314(544+64); + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000083u; + HW_SCE_p_func101(0x24e91976u, 0x418be7b2u, 0x2aeeec01u, 0x65afa0b3u); + HW_SCE_p_func309(); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000090u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func307.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c new file mode 100644 index 000000000..171bf0964 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func308.c @@ -0,0 +1,427 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func308(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x8c2d8cf6u, 0x8d56e617u, 0x4e381155u, 0x0522ae21u); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000024u; + SCE->REG_ECH = 0x00003c1eu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000b5au; + SCE->REG_ECH = 0x0000d77cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x3800db7au; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d37cu; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00002b5du; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x00003b5eu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0161d833u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe9363776u, 0x8ffc645cu, 0x22b826ccu, 0x70a25e76u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(1020); + HW_SCE_p_func100(0x073d446bu, 0xeccd11c7u, 0x5b0e9e5fu, 0x98abb4ccu); + HW_SCE_p_func314(1020+64); + HW_SCE_p_func100(0xfbf01920u, 0xb35ecab2u, 0x10236fdfu, 0xa5cebfeau); + SCE->REG_ECH = 0x00000b39u; + SCE->REG_ECH = 0x0000d77du; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x3800db7bu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d37du; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00002b3du; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x00003b3eu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x659d1915u, 0x355d44e1u, 0x0a383dc2u, 0xfc52da53u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(1088); + HW_SCE_p_func100(0xff1123e5u, 0x5c8c6531u, 0x4477a46du, 0x1d416236u); + HW_SCE_p_func314(1088+64); + HW_SCE_p_func100(0xd336b7c0u, 0xc1d5ac1cu, 0x38833731u, 0x970f8d08u); + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x81010320u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x81010340u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000080au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x80010300u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000d77eu; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x3000db7cu; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x00002fc0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x3000db7du; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x00002fc0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x3000dbc0u; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d77eu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d37eu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000058d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x013fd1d7u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1088); + SCE->REG_ECH = 0x3000db7cu; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d76bu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d36bu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x000037dau; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000097u; + HW_SCE_p_func101(0x2d831169u, 0xf3e9c45fu, 0x86a9a7dbu, 0x48bfc00cu); + HW_SCE_p_func310(); + HW_SCE_p_func100(0x5ba57e89u, 0x2ad0cf5cu, 0xc546cbb0u, 0xdfd6101du); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0161d833u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(1020); + SCE->REG_ECH = 0x3000db7du; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d76bu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d36bu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x000037d9u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000098u; + HW_SCE_p_func101(0xfb0daf22u, 0xfc7f120eu, 0x6e4b02adu, 0x7c564c8au); + HW_SCE_p_func310(); + SCE->REG_ECH = 0x3800db7eu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x6ce6e688u, 0x1ca60eafu, 0x25c7e486u, 0x73068e9au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x81010300u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x80001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x2a06ba12u, 0xe8bfbe05u, 0xfc7ae4e6u, 0x2454e45au); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x81010300u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x80001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xa71d69d5u, 0x3fd3bbc8u, 0xcfd2107au, 0xc1462c2cu); + } + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d372u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d772u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d768u; + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000024u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func308.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c new file mode 100644 index 000000000..2ca462575 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func309.c @@ -0,0 +1,3066 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func309(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x507efdf0u, 0x2d03401au, 0xf5398ec0u, 0x286217ffu); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000028u; + SCE->REG_ECH = 0x00003c1eu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000b7bu; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x230f406fu, 0xda7f5edcu, 0x27c3bebbu, 0x1ca2d98fu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(476); + SCE->REG_ECH = 0x0000d77au; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(612); + SCE->REG_ECH = 0x0000d77bu; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000090u; + HW_SCE_p_func101(0x6cc0e7d9u, 0x458cdd1fu, 0x11511bb6u, 0x77d8e29au); + HW_SCE_p_func308(); + HW_SCE_p_func100(0xb8612113u, 0xf762b28au, 0x1e228883u, 0x606b460fu); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x00003fbeu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x07650df4u, 0x218ae494u, 0x62a374a7u, 0x69f77c6du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(884); + HW_SCE_p_func100(0x3b9e2e17u, 0x00dc30b0u, 0xd4f87fbdu, 0x78cc9f77u); + HW_SCE_p_func314(884+64); + HW_SCE_p_func100(0x34f500c3u, 0x1e7d953du, 0x5a457d14u, 0x1456c4e7u); + SCE->REG_ECH = 0x3000db72u; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d770u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d366u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d766u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x045fd001u, 0x1c068ffcu, 0xf9ad4dc2u, 0x0dc15f12u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func313(816); + HW_SCE_p_func100(0x23ee48a2u, 0x420f6666u, 0x7f916148u, 0xbcaeb32fu); + HW_SCE_p_func314(816+64); + HW_SCE_p_func100(0xedc72e02u, 0x9067ecb0u, 0xbd01da64u, 0x475ec240u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x000000a0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d371u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d771u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa0d2af88u, 0x564963feu, 0xfda15b9fu, 0x0a9b6eb2u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(952); + HW_SCE_p_func100(0x8efeada1u, 0x86c947d3u, 0x97c19f1du, 0xc42b5457u); + HW_SCE_p_func314(952+64); + HW_SCE_p_func100(0x9b785ba7u, 0xca31ebe8u, 0xf0c98a00u, 0x3de02bd5u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbc1763d6u, 0xbaf51d99u, 0x286abac4u, 0x4afbbf25u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(544); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x20f12a95u, 0x2310397au, 0x9acc6944u, 0x9593ac91u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(612); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d77bu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xffceae7au, 0x6ced0145u, 0xa2b22416u, 0x66e29adcu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(408); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(476); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000000cu; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d77au; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000091u; + HW_SCE_p_func101(0x38ac0cdfu, 0x425c549bu, 0x4671434cu, 0xe7db001cu); + HW_SCE_p_func308(); + HW_SCE_p_func100(0xdcd705d9u, 0xc956e1bau, 0x824590e2u, 0xe2a4d2bau); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(816); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x3800db66u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xc5cbb3acu, 0x5a613e5fu, 0xe6719980u, 0xf4de0324u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0x5618de29u, 0x7dbf376bu, 0xdc848924u, 0xc3253b00u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xb8196e42u, 0x78ff726au, 0xcffc4955u, 0x6a8728b9u); + } + HW_SCE_p_func100(0x2f82a82du, 0xbf4bcf6au, 0x553f6038u, 0x8cac813cu); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000d766u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x89e121cdu, 0x93dc5382u, 0x515ddcadu, 0x04b38724u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(816); + HW_SCE_p_func100(0xae198934u, 0x9f1bc69cu, 0x05bffac6u, 0x9ba4919fu); + HW_SCE_p_func314(816+64); + HW_SCE_p_func100(0x8459fdfbu, 0x6264fd2cu, 0x58015355u, 0x6a1a691fu); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(952); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_ECH = 0x3800db71u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x13094415u, 0x7c03e279u, 0x87253dceu, 0x8671997bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0xf526deaau, 0x635f2504u, 0x0c669acau, 0x08b6f407u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xc43db222u, 0xe635f693u, 0xeba2377du, 0xd87d0b4cu); + } + HW_SCE_p_func100(0xabd3f950u, 0x60198146u, 0xadd1361cu, 0xd933adc9u); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d371u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d771u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0737b74fu, 0x953016b6u, 0xb66797cbu, 0x75808618u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(952); + HW_SCE_p_func100(0x78ef5134u, 0x844af139u, 0xd4823d75u, 0xf6f97fd9u); + HW_SCE_p_func314(952+64); + HW_SCE_p_func100(0xe5f9bbbeu, 0x96509cc3u, 0x8318b854u, 0x9bd50be0u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xaa1376c8u, 0x78c0ff2au, 0xbe1af5b8u, 0xda3a88cfu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(408); + SCE->REG_ECH = 0x0000d77au; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9bedacc0u, 0x8f425520u, 0x027f1c14u, 0xc15dde50u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(544); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000d77bu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(680); + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000092u; + HW_SCE_p_func101(0xb3093a43u, 0xac9c9129u, 0x503622eeu, 0x14cdab75u); + HW_SCE_p_func304(); + HW_SCE_p_func100(0xe32e76f5u, 0x11a6942du, 0xdf08bb94u, 0x69570b0du); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(816); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_ECH = 0x3800db72u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x62b11180u, 0x0ee880b8u, 0xc1c11bd2u, 0x15f65922u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000190u); + HW_SCE_p_func101(0x0d868a6au, 0x65052db0u, 0xe774b17au, 0xab134626u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x4507bc11u, 0xdf51099eu, 0x7400ad3bu, 0xadedb23du); + } + HW_SCE_p_func100(0x1db9f65du, 0x7a78d897u, 0xb589b7bau, 0x0d86c3a2u); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d366u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d766u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x90e33230u, 0xd7da6c0cu, 0xabd9d876u, 0x2d38ff3bu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(816); + HW_SCE_p_func100(0x9fd81c3du, 0x58ca1673u, 0xa58d4cbbu, 0x1a9d9068u); + HW_SCE_p_func314(816+64); + HW_SCE_p_func100(0x0d1d631du, 0x1c5ababau, 0xd136b9c0u, 0x6a317f80u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(952); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_ECH = 0x3800db71u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x0e836fc7u, 0x884c03cfu, 0x77ffdf45u, 0x4db53950u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0xe5becc29u, 0x9802628eu, 0xae42ccabu, 0xd07c1c64u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x29b7a504u, 0xc94a398du, 0x66872d1bu, 0x8601d289u); + } + HW_SCE_p_func100(0x0b00de3du, 0x621ec070u, 0xab514fd4u, 0x37132da0u); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d371u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d771u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcc64659cu, 0x8f163d4au, 0x02a5e2a5u, 0x5b33e3c2u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(952); + HW_SCE_p_func100(0x5ca187ebu, 0x6d8317b9u, 0x3a029136u, 0x64db1852u); + HW_SCE_p_func314(952+64); + HW_SCE_p_func100(0xe3b6589cu, 0xab1e9255u, 0x276afe4cu, 0x0aabeb6fu); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_ECH = 0x00003b9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3000db68u; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d77au; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d37au; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(748); + SCE->REG_ECH = 0x0000d77bu; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000093u; + HW_SCE_p_func101(0x297b5087u, 0xb154b2a1u, 0x00f202ecu, 0x33047f78u); + HW_SCE_p_func308(); + HW_SCE_p_func100(0x86e1c646u, 0x99aeac35u, 0x85f6aae8u, 0x98139038u); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(884); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_ECH = 0x3800db72u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xd506cd07u, 0xc57d0308u, 0x73a273d2u, 0x115959dfu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000190u); + HW_SCE_p_func101(0xe51785d3u, 0x16e71b98u, 0x2b674987u, 0xecd2eb45u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xec1d90edu, 0xafea5063u, 0x4014965au, 0xc4644ea5u); + } + HW_SCE_p_func100(0x8212523fu, 0x83dc322du, 0x9e84585du, 0xf22dd763u); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d370u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d770u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcfb1c7c9u, 0xb6df7dcdu, 0x49ba0092u, 0x5d22b17du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(884); + HW_SCE_p_func100(0x1de4b4b9u, 0xab0b62a0u, 0x23a8f5e1u, 0x3cf5363eu); + HW_SCE_p_func314(884+64); + HW_SCE_p_func100(0xd2cfce67u, 0xfb8ed3a2u, 0x08f387fau, 0xda42e922u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(816); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x3800db66u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x6d365454u, 0x4239bc0bu, 0x853c3d8du, 0x207b1244u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0x3945b5a2u, 0x4da29a16u, 0x105b508eu, 0xac563ff4u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x964d6119u, 0x7782c2d7u, 0x7e79dd33u, 0xce9d6cd1u); + } + HW_SCE_p_func100(0xeb4eea4au, 0xadad34cfu, 0x6f717270u, 0xc9e241eeu); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d366u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d766u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xdf42a902u, 0x8d143a96u, 0x81d9c449u, 0x99d9b6a3u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(816); + HW_SCE_p_func100(0x5f571992u, 0x76ecf695u, 0xf56636dfu, 0x4d8743e8u); + HW_SCE_p_func314(816+64); + HW_SCE_p_func100(0x58beab10u, 0x244d3763u, 0x6eea2fb4u, 0x309d7802u); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c90cfu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(952); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_ECH = 0x3800db71u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x933c9b61u, 0x0b68a76bu, 0xf68bd356u, 0x641ef71fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0xf6014c4cu, 0x8056f7b7u, 0x72b2ba3au, 0xa19a3635u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x1764ff9fu, 0x1a8492b3u, 0xc49a1d32u, 0x2dc11287u); + } + HW_SCE_p_func100(0xad074cdcu, 0xea7ae448u, 0x7324e020u, 0xd3129bcbu); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d371u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d771u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000014u; + SCE->REG_ECH = 0x00003b9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_ECH = 0x3000db71u; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d77au; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d37au; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000d77bu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(680); + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000094u; + HW_SCE_p_func101(0x51e65f45u, 0x2cdb1de0u, 0xf57eea4au, 0x2c370be4u); + HW_SCE_p_func304(); + HW_SCE_p_func100(0x725794c2u, 0x871ac300u, 0xac83aff0u, 0xf400d18du); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(816); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x3800db66u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xc31cbbd1u, 0x268d2b25u, 0xe7a62786u, 0x27e369bcu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0x4ca8e691u, 0xd83998fau, 0x26c5f9f2u, 0xe71b8a45u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xf54c3628u, 0x49f01760u, 0xcd33d93du, 0xfeedfa57u); + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_ECH = 0x3800db72u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x239e8ef4u, 0x45342004u, 0x4cd0d273u, 0x246ec09du); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000190u); + HW_SCE_p_func101(0x73401201u, 0xa84dc3b4u, 0x54435447u, 0x3f45b6bdu); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x69bf6174u, 0xbd2a73a4u, 0x831c564bu, 0xc86a28cfu); + } + HW_SCE_p_func100(0xcece2e3du, 0x451a005bu, 0x84c56b5eu, 0x0934d294u); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d366u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d766u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x14512db2u, 0x44a5245au, 0x46a63ddau, 0xe66d64d7u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(816); + HW_SCE_p_func100(0x8e38417cu, 0x84dd6705u, 0x34259ec4u, 0xad64a68du); + HW_SCE_p_func314(816+64); + HW_SCE_p_func100(0x2f4e25f7u, 0x508e0b9au, 0x9d404c48u, 0x813169cdu); + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_ECH = 0x00003b9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3000db68u; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d77au; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d37au; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(748); + SCE->REG_ECH = 0x0000d77bu; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000095u; + HW_SCE_p_func101(0x882fccf7u, 0xa9db782bu, 0x0cb6d375u, 0x49f70d6du); + HW_SCE_p_func308(); + HW_SCE_p_func100(0x023d5574u, 0xd6d309ffu, 0x25ba5b5eu, 0x580371f1u); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000c8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010b238bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(816); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x3800db66u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x7455c717u, 0x6006723au, 0x42eb0f2du, 0x9b272b9du); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0xa1bc46c7u, 0x07125db3u, 0xa32ee9a0u, 0x47f7555cu); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0xc879e5dcu, 0x17888d82u, 0x5f5c4d9bu, 0xc82298aeu); + } + HW_SCE_p_func100(0x0d5b76d6u, 0xb70cd2cfu, 0x3b074b32u, 0xb6516a0fu); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d366u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d766u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f0b809u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(884); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x3800db70u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x5dfa8bb0u, 0xf9addc81u, 0x8a267091u, 0x100b0e96u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000110u); + HW_SCE_p_func101(0x97d49d5cu, 0xb0f0efeau, 0xeee5ba07u, 0x48ea7fe7u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x77cef942u, 0x2ac856acu, 0x6ee1e859u, 0x95e98234u); + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000018u; + SCE->REG_ECH = 0x3800db72u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x0b686405u, 0x878db4bbu, 0xd8c40795u, 0xfe6a6eb6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func315(0x00000190u); + HW_SCE_p_func101(0xdb27deefu, 0xd2f2fcedu, 0x462b8a78u, 0x7eabc0c4u); + } + else + { + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x99186c2fu, 0xd463674bu, 0xa9b83865u, 0xedc5f09du); + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x3800db66u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x7c788bcau, 0xa3bb3c75u, 0xb469bc2fu, 0x85b3a642u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x04000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000030u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x00003b9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000004cu; + SCE->REG_ECH = 0x00003f9eu; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000030u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00800001u; + SCE->REG_104H = 0x00000257u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_2CH = 0x00000190u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xFFFFFFFFu); + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x775d82a9u, 0x6e093bcdu, 0xaee304d3u, 0xd1452d0bu); + } + else + { + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func101(0x68e145aeu, 0xf73293aau, 0x898193e4u, 0x8bab27edu); + } + HW_SCE_p_func100(0x5ec7873du, 0x6d0dd9e3u, 0xeef645ecu, 0xc612a596u); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x02816fdeu; + SCE->REG_ECH = 0x30008bc0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00020020u; + SCE->REG_ECH = 0x0000d37eu; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000d77eu; + SCE->REG_ECH = 0x00000080u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb9165f89u, 0xf87676cau, 0x3bc818f5u, 0x726d1a94u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(748); + SCE->REG_ECH = 0x3800db7eu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x084f91efu, 0xd3cb359bu, 0x5514cb43u, 0xeb853283u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + oLoop1 = 1; + while(oLoop1 == 1) + { + HW_SCE_p_func100(0x053fe767u, 0x7e88b106u, 0x364f0755u, 0x687c7376u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x06001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x000000a0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_104H = 0x00000157u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000110u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xfe9804e6u, 0x12645ab9u, 0xdae649f1u, 0x0ec657c8u); + } + else + { + HW_SCE_p_func101(0x9e0b8c35u, 0xdd07524au, 0x03cc62fau, 0x826984e6u); + oLoop1 = 0; + } + } + HW_SCE_p_func101(0x1f5625b7u, 0xda5863eeu, 0x88bfd0b1u, 0x9cba4d84u); + } + else + { + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x06001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x000000a0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa5d602dcu, 0x83ac45edu, 0x9d872697u, 0x8b1a9561u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0xcad68de3u, 0xaf4e1f11u, 0x82c8a327u, 0x940029c3u); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x06001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x80c0001eu; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8088001eu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x000000a0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00800001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_104H = 0x00000157u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000110u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x8081001eu; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000050u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x8188001eu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000090u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000a0u; + SCE->REG_E0H = 0x81c0001eu; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xe24acd49u, 0x60443dd8u, 0x248474a6u, 0x58cab95eu); + } + } + HW_SCE_p_func101(0xdd2a0b5cu, 0x766c6608u, 0xe17bc4d7u, 0xa3f93441u); + } + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000028u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func309.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c new file mode 100644 index 000000000..3734454db --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func310.c @@ -0,0 +1,197 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func310(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x3800db6bu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x37586798u, 0xceb0a5e6u, 0xd919e7e3u, 0xc7566c27u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func100(0xba3e67acu, 0x77923dc6u, 0xf20f94eeu, 0x8caa5b29u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002fe0u; + HW_SCE_p_func101(0xa399fe47u, 0x7f8396a0u, 0xa5800b1bu, 0xa90e187au); + } + HW_SCE_p_func101(0xfd179c04u, 0x17853e37u, 0xb53c5511u, 0xfa864017u); + } + else + { + HW_SCE_p_func100(0x249f2fc5u, 0x3cc969d5u, 0x8b2fc801u, 0x391bc107u); + SCE->REG_E0H = 0x810103c0u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00800001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x82001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002fe0u; + HW_SCE_p_func101(0xf1d57656u, 0xc866fae8u, 0x1d69570cu, 0xc958fbf8u); + } + HW_SCE_p_func101(0xb4b60db5u, 0x46826080u, 0xe4c9f49du, 0x86683fceu); + } + SCE->REG_ECH = 0x38000bdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func310.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c new file mode 100644 index 000000000..250fb6aea --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func311.c @@ -0,0 +1,660 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func311(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xfd4b176bu, 0xd5a81478u, 0x6420f33du, 0xf5728f32u); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000002cu; + SCE->REG_ECH = 0x00003c1eu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x04000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa9ea96d7u, 0x43b13488u, 0x024e5431u, 0x4c64617bu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(748); + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + oLoop1 = 1; + while(oLoop1 == 1) + { + HW_SCE_p_func100(0xd6e08aa7u, 0xec23e33du, 0x69c55027u, 0xb230fa25u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x6a97a04bu, 0x686aafbau, 0x37cc5886u, 0xf353c266u); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func101(0x7f0eb3ebu, 0x8636ae7eu, 0xa78fc1fau, 0x8247ea08u); + } + } + HW_SCE_p_func100(0xb4873111u, 0xecb38ea8u, 0x15a4ff05u, 0x06e2ba67u); + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x016bcaa1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x089ef4feu, 0x15bbe85fu, 0x80a2f025u, 0x29ff60e2u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(136); + HW_SCE_p_func100(0x99313b51u, 0x88d8f2e1u, 0xdb56f33bu, 0xb6d38a7fu); + HW_SCE_p_func314(136+64); + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0xcfda5444u, 0x2be84e0fu, 0xe0e2bd7bu, 0xa7c355d9u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019c85beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa765abb1u, 0x26cce39du, 0x4b9fdea1u, 0xf6435bdbu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(204); + HW_SCE_p_func100(0x8d279c22u, 0xfc68a162u, 0x2fbd3f61u, 0x61c9e67fu); + HW_SCE_p_func314(204+64); + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52u; + for (iLoop = 0; iLoop < 256; iLoop = iLoop + 1) + { + HW_SCE_p_func100(0x9bdc8e76u, 0xa1c2a576u, 0xf7908ae4u, 0xa3ee9d7fu); + SCE->REG_24H = 0x040049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(680); + SCE->REG_ECH = 0x00002e40u; + HW_SCE_p_func101(0x7d34eb40u, 0x5747f818u, 0x1be65614u, 0xd6ed34b3u); + } + HW_SCE_p_func100(0x142ecffcu, 0x326510a6u, 0x8cbe023bu, 0x026a5df9u); + SCE->REG_ECH = 0x38008a40u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_24H = 0x040049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x040019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x020019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb896da45u, 0x16e2080fu, 0x293b4f68u, 0x9dc078e9u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x718e4ecbu, 0x6d103300u, 0xcb1eb1bbu, 0x52ffc030u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(408); + HW_SCE_p_func100(0xf0047e74u, 0xc38cc552u, 0x8a3454a0u, 0x0dc9fc09u); + HW_SCE_p_func314(408+64); + HW_SCE_p_func100(0xb89c82d1u, 0xca37b6d4u, 0xfebe0198u, 0x2992116au); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8c0b1577u, 0xd80af8b9u, 0x8a28fa6au, 0xb8691f5au); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(544); + HW_SCE_p_func100(0x6a8f8a7bu, 0xea162157u, 0xf8e0b9d6u, 0xb3d9155bu); + HW_SCE_p_func314(544+64); + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0x0cd9debeu, 0x90441b42u, 0x6c48e06du, 0xd5ce096eu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x95056b4fu, 0xa2022506u, 0xd5895c90u, 0xc9016455u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(476); + HW_SCE_p_func100(0x8de7ac54u, 0x2086ac6eu, 0xda5ccc3du, 0x720b13b1u); + HW_SCE_p_func314(476+64); + HW_SCE_p_func100(0xd9c89923u, 0xda6185eeu, 0x520354eau, 0x62d3ec2bu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8c5f3115u, 0x6e3076f9u, 0xc072f381u, 0x3dceb2c9u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(612); + HW_SCE_p_func100(0x0221233fu, 0x3eb2c7f3u, 0x2f53721bu, 0x87b0f538u); + HW_SCE_p_func314(612+64); + SCE->REG_ECH = 0x00000a52u; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000085u; + HW_SCE_p_func101(0x6d1dde65u, 0x27e804aau, 0x0353a48au, 0xc63e1af4u); + HW_SCE_p_func309(); + HW_SCE_p_func100(0x52609d4fu, 0x2847540du, 0xe7fd5f89u, 0xf730b53du); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe6b75748u, 0xf45d1592u, 0xee7bfe91u, 0x326aca9du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(476); + HW_SCE_p_func100(0xe9fe5121u, 0xce726d25u, 0xa83a96a3u, 0xb8b584aau); + HW_SCE_p_func314(476+64); + HW_SCE_p_func100(0xb3bc9911u, 0xf6c18db0u, 0xfc732293u, 0x3cd6f686u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6dd6c2adu, 0x7c99c2a6u, 0x3a7d202du, 0x33864215u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(612); + HW_SCE_p_func100(0x00e68939u, 0x22376fe5u, 0x1dc88c20u, 0x4f16dbfeu); + HW_SCE_p_func314(612+64); + HW_SCE_p_func100(0x225f07a7u, 0xe5c06b6bu, 0xd5ad4e40u, 0x77a94de9u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x161d0285u, 0x582fea60u, 0x8ddb0abfu, 0xf3e3813fu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(408); + HW_SCE_p_func100(0xba986d4au, 0x8c0c05c3u, 0x9106460cu, 0x4fcb22b1u); + HW_SCE_p_func314(408+64); + HW_SCE_p_func100(0xba3a26c5u, 0xab973a6du, 0x113d70d0u, 0x17ceceabu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xed966499u, 0xffbb31adu, 0x0babdc9eu, 0x028e43eau); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(544); + HW_SCE_p_func100(0x70e80bbeu, 0x80e52ebcu, 0xc889fbaeu, 0x908cde5du); + HW_SCE_p_func314(544+64); + SCE->REG_ECH = 0x00002e40u; + HW_SCE_p_func101(0xe79021aau, 0x8e1a3178u, 0x17485e2au, 0x7739cc4au); + } + SCE->REG_ECH = 0x38008a40u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0xa7713f01u, 0xff3d0159u, 0x902c8403u, 0xa6e08877u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01a67f45u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xd79142abu, 0xdda79cd3u, 0xa39e379bu, 0x30387819u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(476); + HW_SCE_p_func100(0x840d4a08u, 0x2d844345u, 0xcafbbf9fu, 0x5f275859u); + HW_SCE_p_func314(476+64); + HW_SCE_p_func100(0xebcced92u, 0x52a220a6u, 0x4b7a4cfbu, 0xe36bc013u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011f5dcdu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf2e9a370u, 0x660aefceu, 0x405fff51u, 0xb7af9bb1u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(408); + HW_SCE_p_func100(0x17c8247cu, 0xa0ddb080u, 0x9e68312cu, 0xef695d8eu); + HW_SCE_p_func314(408+64); + HW_SCE_p_func100(0x8de20e43u, 0x8198b797u, 0x50909c69u, 0xe206fb6eu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8bd2bbe9u, 0x0be9aca0u, 0x6bf6b397u, 0x2b511dbfu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(68); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7au); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8921c32eu, 0x0b09dafau, 0x0a0bda14u, 0x9944d54cu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(0); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019fce91u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x2541ef28u, 0x061e859cu, 0xe88ecdd7u, 0x0f6035d5u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(612); + HW_SCE_p_func100(0x4d51142bu, 0x42fff715u, 0x472627e9u, 0x603bdc70u); + HW_SCE_p_func314(612+64); + HW_SCE_p_func100(0x0efd708cu, 0xcc94585bu, 0xc223494au, 0xc6eb2968u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01e59c3du); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa3fc9c35u, 0x200d7e68u, 0x469464dau, 0x5b9149ecu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(544); + HW_SCE_p_func100(0xcbb87f2cu, 0xcdf462d9u, 0x6ff399b9u, 0x9b315f2du); + HW_SCE_p_func314(544+64); + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000086u; + HW_SCE_p_func101(0x3cbf7cedu, 0x9f0ca8c1u, 0x9fc1b0a7u, 0x1fb8e5cbu); + HW_SCE_p_func309(); + HW_SCE_p_func100(0xd887c518u, 0x5a403aa4u, 0xc6176be4u, 0x5ce2816eu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x33ef899cu, 0x80ff43e7u, 0x24d6eaa4u, 0x1fcd4bb9u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(68); + HW_SCE_p_func100(0x4eb32dd0u, 0x894b3a68u, 0x790aeb44u, 0x83d869b6u); + HW_SCE_p_func314(68+64); + HW_SCE_p_func100(0x6441f351u, 0x8a23ac4eu, 0xaf9adeadu, 0xeae53c32u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7au); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbdf03440u, 0x37792dbcu, 0x58df6b26u, 0x61fffe27u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(0); + HW_SCE_p_func100(0x10098830u, 0x68ef79e5u, 0x8d4399a9u, 0x320f688fu); + HW_SCE_p_func314(0+64); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000002cu; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func311.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c new file mode 100644 index 000000000..40c477e21 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func312.c @@ -0,0 +1,109 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func312(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00003f62u; + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x42f087bfu; + for (iLoop2 = 0; iLoop2 < 64 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x400007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func312.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c new file mode 100644 index 000000000..c3f1b966c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func313.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func313(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x42e087bfu; + SCE->REG_04H = 0x00000202u; + for (iLoop2 = 0; iLoop2 < 64 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1+iLoop2 + 0] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 1] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 2] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func313.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c new file mode 100644 index 000000000..c6653cf11 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func314.c @@ -0,0 +1,96 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func314(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x400009cdu; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000213u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1 + 0] = SCE->REG_100H; + S_HEAP[ARG1 + 1] = SCE->REG_100H; + S_HEAP[ARG1 + 2] = SCE->REG_100H; + S_HEAP[ARG1 + 3] = SCE->REG_100H; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func314.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c new file mode 100644 index 000000000..a32908109 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func315.c @@ -0,0 +1,96 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func315(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_28H = 0x00800001u; + SCE->REG_104H = 0x00000157u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_E0H = 0x8181001eu; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = ARG1; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000050u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func315.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c new file mode 100644 index 000000000..8a23a6b8b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func316.c @@ -0,0 +1,703 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func316(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x00003fbeu; + SCE->REG_28H = 0x009f0001u; + SCE->REG_ECH = 0x0000d779u; + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x80010300u; + SCE->REG_00H = 0x00008307u; + SCE->REG_2CH = 0x000000acu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000031fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000e0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_ECH = 0x3800db1fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x8dd5b077u, 0xd50c776fu, 0x9d162b11u, 0xab952327u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00a70001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x00000682u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000d379u; + HW_SCE_p_func101(0x1eb5c006u, 0x14f8b611u, 0x3c79c58bu, 0x2b91f0c0u); + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x0000001cu; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f0u; + HW_SCE_p_func101(0x2d145c92u, 0x70901d38u, 0x611110efu, 0x988983bfu); + HW_SCE_p_func317(); + SCE->REG_ECH = 0x00003759u; + SCE->REG_24H = 0x000050d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x0000001du; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f1u; + HW_SCE_p_func101(0x82531a33u, 0xa8d87c8fu, 0x6ac862c0u, 0x734e49c8u); + HW_SCE_p_func317(); + SCE->REG_24H = 0x000050d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x0000b0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000c00u; + SCE->REG_24H = 0x8000ecd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00007cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000bcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + for(oLoop2 = 0; oLoop2 < 32; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x00000189u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000030u; + SCE->REG_24H = 0x80007cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000002c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x00001151u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x511e8e8eu, 0xd9e12ddbu, 0xf22bed32u, 0x73de2ff2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x1e68f2e3u, 0xb5e7bbfcu, 0x18236343u, 0xecce8c56u); + } + else + { + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000006c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x040091c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x91b9177bu, 0xc40e686du, 0xce3d3442u, 0x8db507f8u); + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000006c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xffb51ee1u, 0x2551d008u, 0x419923a9u, 0xa6a91ad0u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x8bafbae7u, 0xcc319b8eu, 0x09db8e30u, 0x6719a39au); + } + else + { + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000006c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x040091c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x4ee65c47u, 0x1e802413u, 0xe499d1a8u, 0xdb8fab6au); + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800db20u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x1d570422u, 0xba2e8875u, 0x4417d7b7u, 0x75e2ba4au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000002c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000002c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x00001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x5930a123u, 0xe735b3d5u, 0xc4d172b9u, 0x05e9d5b3u); + } + else + { + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x0000d4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x8000dcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xaa453373u, 0xe70c1f7bu, 0x2794ae86u, 0x1e04ffb8u); + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x00004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + HW_SCE_p_func100(0x1424e022u, 0x37343771u, 0xa0416005u, 0x010b4e36u); + SCE->REG_E0H = 0x81010340u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x3800db7cu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xd4918aa4u, 0x20669ad3u, 0x6d1f6b3fu, 0x6459ad47u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002fe0u; + HW_SCE_p_func101(0xb7698563u, 0x1d329d6bu, 0x968a2dceu, 0xd32a5eadu); + } + HW_SCE_p_func101(0x8cfc7f48u, 0x1596a76du, 0xe304f64au, 0xe359ab67u); + } + else + { + for (oLoop2 = 0; oLoop2 < S_RAM[0]; oLoop2 = oLoop2 + 1) + { + SCE->REG_24H = 0x00001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002fe0u; + HW_SCE_p_func101(0x4e152c24u, 0xe90797beu, 0x172490f0u, 0x260bc8bcu); + } + HW_SCE_p_func101(0xb6fea3f5u, 0x85e41681u, 0xb3f14e96u, 0x5022aeefu); + } + SCE->REG_ECH = 0x38000b5fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800db79u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x40f924e5u, 0xc4f5438du, 0xb74cc091u, 0xf662ab19u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a00001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x0270d572u, 0x600e206bu, 0x72b67275u, 0xfd7bff07u); + } + else + { + HW_SCE_p_func101(0x145e3f7du, 0x4bd25dc4u, 0x94ed56edu, 0x32ddd531u); + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func316.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c new file mode 100644 index 000000000..80eba1cf0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func317.c @@ -0,0 +1,251 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func317(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x00003fbeu; + SCE->REG_28H = 0x00a30001u; + SCE->REG_ECH = 0x00000b39u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800103c0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3800dbdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x54c736d5u, 0x1687cea2u, 0xb9a27aefu, 0x0efb8de2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800103c0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00a30001u; + SCE->REG_ECH = 0x3800dbdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xb050152eu, 0x4b531e69u, 0x106eb6e5u, 0xa55c8f7fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002f20u; + HW_SCE_p_func101(0x53c53629u, 0xc624f94du, 0xcc1a9552u, 0x5b2c6d97u); + } + else + { + HW_SCE_p_func101(0x1279d640u, 0x26ecf237u, 0x637e567bu, 0xdf3efeccu); + oLoop1 = 0; + } + } + SCE->REG_ECH = 0x0000537fu; + HW_SCE_p_func101(0x7cb89078u, 0x36f852b6u, 0xb36ce496u, 0xdd7983beu); + } + else + { + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800103c0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00a30001u; + SCE->REG_ECH = 0x3800dbdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x3b020f6eu, 0xeb260ad7u, 0xa93e0aa8u, 0x95ef9e82u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x8624917eu, 0x91b076eeu, 0x5dbd5e14u, 0x70155193u); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00002f20u; + HW_SCE_p_func101(0x09722fbau, 0xa95ea208u, 0x4ad6f5a0u, 0xeaae6343u); + } + } + SCE->REG_ECH = 0x0000577fu; + HW_SCE_p_func101(0x654a6dd5u, 0x21175d16u, 0x4cab116eu, 0xbfd1f105u); + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func317.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c new file mode 100644 index 000000000..df5accfe2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func318.c @@ -0,0 +1,3214 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func318(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_ECH = 0x00003fbeu; + HW_SCE_p_func100(0x8c693a67u, 0xb13f66fbu, 0xa25ea81bu, 0x560d7c20u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x2074e03cu, 0x98ab4303u, 0xc1cce9b5u, 0xd43ba3ebu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(480); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbf51ada8u, 0x1fc04491u, 0xc988fb18u, 0xfaa5c11du); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(616); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0dfaa529u, 0x282e920du, 0xf64592dfu, 0x9f7c68adu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(444); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9c1a0702u, 0xedb2e972u, 0x22852fd3u, 0x1855837cu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(580); + HW_SCE_p_func323(); + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x38d4cc3du, 0xce4e1aa8u, 0x561920b3u, 0x7adf0eb5u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x452bbfd4u, 0x121cc6aau, 0xbd3daaf0u, 0xedaf7d58u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x45fea76au, 0x2c6eb1dcu, 0xe2b278ceu, 0x6e651334u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa434e2acu, 0x846c8258u, 0x9bafbdf5u, 0xc50a1cf7u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0x451158f5u, 0x81c038e1u, 0x097a63bbu, 0xe2348aedu); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0x65dae8bdu, 0x14d558ceu, 0x16b8aafcu, 0x6bd59a86u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x00005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000098d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x050df3ffu, 0x4aecfa26u, 0x639cc9a9u, 0xc359e623u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(408); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf1362f19u, 0x84c03fcfu, 0xb31f41a3u, 0x709874b2u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(544); + HW_SCE_p_func323(); + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0266126au, 0x5478a930u, 0x489ca55cu, 0x04eecab0u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0xedb8ae49u, 0xbfdb28e5u, 0x05f80921u, 0xc430a4acu); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x8b69697du, 0x2c955d96u, 0x8ceae065u, 0x540a0614u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xea10d2f9u, 0xa280b4beu, 0x3834e872u, 0x0458f807u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x934fc829u, 0x8913448fu, 0x5fda9cfeu, 0x8343d6e1u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x83a90bf3u, 0xb6654be1u, 0xe1dbfccau, 0xf7375c69u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x9536bf06u, 0x9ecd622au, 0xd94cdfbcu, 0xf5391467u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x00005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000098d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x74787d02u, 0x0c72fbacu, 0xd30f6441u, 0x26867c12u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(444); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc61ecfffu, 0xa9953287u, 0xb4500ebfu, 0xd34162e6u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(580); + HW_SCE_p_func323(); + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x51aedde7u, 0x9413ad77u, 0xec2342bbu, 0xa4a9cbecu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func321(952); + HW_SCE_p_func100(0xf03ed4f3u, 0x5745c781u, 0x0b42d870u, 0x0c7db3cbu); + HW_SCE_p_func314(952+36); + HW_SCE_p_func100(0x5674c372u, 0x77e8dea9u, 0x5a55452au, 0xab9bb69du); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x70b5c05cu, 0x8660d602u, 0xd1c971cbu, 0x76e117c1u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x2c5ddd9cu, 0x9b4b818au, 0x1977f83du, 0x1f6e88f4u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0x10413e6au, 0x338ea4acu, 0x559a535au, 0x0e97cb42u); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0xc8d87a13u, 0x28ba25bdu, 0x4ece54ccu, 0x3d697361u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x00005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000098d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x52ffcbfbu, 0x25c68561u, 0x0eeed611u, 0x9cf5088du); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x2114e727u, 0x4d307b50u, 0x94f1eb46u, 0xa38d9ce8u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0x09bae1beu, 0xd3e14145u, 0x7d2ba63fu, 0x23c194deu); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0x05752256u, 0x4096e871u, 0xafb2d8f2u, 0x9810e5c7u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x2ec33011u, 0xbcb2710eu, 0xc81ed862u, 0x457fdff6u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbf2131abu, 0xab0a83eau, 0x7065e26cu, 0xcd6c7bcdu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0x1c4648e5u, 0x3a746a56u, 0x40a6b1c3u, 0x8b198efeu); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x413a569au, 0x477e2227u, 0xcb5e412du, 0x020d1af2u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x5571223au, 0xb8e696adu, 0xa27da0c5u, 0xa0de4e32u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4b3715c5u, 0x62ff3f7bu, 0xc93b1343u, 0x9e7c130au); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x21fecf08u, 0xc8e1e918u, 0x8addf0e1u, 0x930bd727u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0xae7ec822u, 0x07a1ce62u, 0x55ae5ea0u, 0x5cf840acu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xde7eba77u, 0x66ec29ebu, 0x09990687u, 0x799c56eeu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(952); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0b4fe097u, 0xc820684du, 0x02412687u, 0x6e212565u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(952); + HW_SCE_p_func100(0x395026a9u, 0x6c42a3fbu, 0x07b2fd77u, 0x2c39ed94u); + HW_SCE_p_func314(952+36); + HW_SCE_p_func100(0x2cbbbb51u, 0xb5c1b6d5u, 0x83276d22u, 0x0c8a2248u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xaaaa7ac4u, 0xfb5bed0eu, 0x8be2cb55u, 0xe7fd0473u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(480); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x31ff55c9u, 0x8140b0f5u, 0xceb9a311u, 0xf8a6f300u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(616); + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x0000c8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xacaeb6e8u, 0xd069eaffu, 0xfd178003u, 0xc18b9d75u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(896); + HW_SCE_p_func100(0xbf3b464fu, 0x49a9553fu, 0xc387c770u, 0xc7f9b17du); + HW_SCE_p_func314(896+36); + HW_SCE_p_func100(0x1f7f68abu, 0x91a1a4efu, 0x664851deu, 0x26452beeu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x726ceea7u, 0xbde2b6e5u, 0xe19911d3u, 0xecccacfeu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa17ed11eu, 0x2ef17845u, 0x267746bfu, 0xb3fd52dfu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0xfc753a2bu, 0xf34825afu, 0x03876e89u, 0x51b76719u); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0xf3047cc0u, 0x32c7c135u, 0x77bbf376u, 0xe4c5bdcau); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x61da3608u, 0x2332ad99u, 0x3f516d34u, 0xcd2305dfu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc8e8a814u, 0x05a35651u, 0xaca24a7fu, 0x0ea729fau); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x1dde4b25u, 0x530e5bb0u, 0xc5becf97u, 0x35b81685u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x27d54b6du, 0xeefed33fu, 0xc73bc03bu, 0xd427373du); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa900c2c0u, 0x602b64dcu, 0x5d44f94bu, 0x4fe44840u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xaf0d3c1cu, 0x50563233u, 0xe2b291b6u, 0xe0e17dd0u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0xbea9c41cu, 0x79c109f4u, 0xc1a7ff55u, 0xcadfd250u); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x647ca49eu, 0xb06921a5u, 0xe84a252du, 0xc598c5a4u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x91c27ea4u, 0x049f5f5au, 0xc129ce0cu, 0x64a8e27bu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xd55a5390u, 0x35f33131u, 0xd6a62829u, 0x7d2fa738u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(408); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(544); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f0u; + HW_SCE_p_func101(0x5b38f724u, 0xe9aa7946u, 0xa88a1bbfu, 0x4d8a1c23u); + HW_SCE_p_func316(); + HW_SCE_p_func100(0xe81e581cu, 0x1b609ef3u, 0x346419fdu, 0x8a3fe878u); + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa1941a0eu, 0xcdcde287u, 0x1b756ae4u, 0xe9bdb894u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xea1c0bbdu, 0x9ae71488u, 0xfa0a43b3u, 0xa5729ea2u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x066e4ff9u, 0xf8dbab9fu, 0xafc2b53au, 0xf9846ca7u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x692d67d5u, 0xe8de307bu, 0xcb829d7fu, 0x92fe6f5cu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc1fc96f6u, 0x295eac95u, 0x7352e482u, 0x21ae2cb1u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(952); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1b397203u, 0xf394d796u, 0x8b40b8a1u, 0x7c0e538eu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(952); + HW_SCE_p_func100(0x0f0d9326u, 0x089c4bf1u, 0x39dc51eau, 0x3703a5acu); + HW_SCE_p_func314(952+36); + HW_SCE_p_func100(0xa124c08bu, 0xc2ecaa23u, 0x531ca0f3u, 0x40c3e724u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4b859310u, 0x0b9fd51fu, 0xf76e1dc8u, 0xff37911eu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x5372057au, 0xf005e4a0u, 0x4dbb9b05u, 0xa278ffb8u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0x80f4b23du, 0x05c58c40u, 0x4e36b493u, 0xb12e2146u); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x69e11c7fu, 0x60427693u, 0x38ce5d4cu, 0x8be945a7u); + SCE->REG_28H = 0x008f0001u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000408u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000080cu; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00u; + SCE->REG_24H = 0x8000f4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x000050d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb76505f2u, 0xebf3eb95u, 0x4fa359a1u, 0x04a325bbu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(752); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x287e45eeu, 0xeb5626adu, 0x449bc603u, 0xf05aa3fau); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(896); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xeb481312u, 0x27c8327du, 0x7f4519acu, 0xde7645abu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(896); + HW_SCE_p_func100(0x7feadcc7u, 0x4d7648c9u, 0xa9f88d13u, 0xbb0d7a6fu); + HW_SCE_p_func314(896+36); + HW_SCE_p_func100(0xc2684d93u, 0x6d5d6e62u, 0x909d3383u, 0x31c612e1u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe5b4cae5u, 0xbcfc9e35u, 0x66ccaeedu, 0x09b575afu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe7e196efu, 0x8bda93e4u, 0x06cfe5f7u, 0x42a9bdfeu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0xb8a0f1b1u, 0x10d2babbu, 0xe39d0053u, 0xca6a2be4u); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0xc8bff03bu, 0x822949adu, 0x1d0275c3u, 0x66aa2304u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xd088dc87u, 0x1e079d65u, 0x58f71342u, 0xfe73372eu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6a449ba3u, 0x644592a8u, 0xe4c0d031u, 0x0111d512u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x136d4dceu, 0x8829fe81u, 0xe1fdab6cu, 0x90d661c3u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0xdd6d1badu, 0x3f4fd94fu, 0x17bb48e3u, 0x7955ea13u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x47c671eeu, 0xac239171u, 0x21208ac1u, 0x6f45b650u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x89c44f64u, 0xcbc5e25au, 0x5f99f504u, 0x071f488eu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0x79a12141u, 0x224ee8dcu, 0x5ab33560u, 0xc20b192au); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x81c4a87bu, 0xe2676d1du, 0xbac0211au, 0x5ff29039u); + SCE->REG_28H = 0x008f0001u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000810u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030u; + SCE->REG_24H = 0x80007cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe1c00d44u, 0xa3b1d245u, 0x3379eef5u, 0xa7a32ecdu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(716); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x7e4caf6cu, 0xd26d5b9cu, 0x2009e623u, 0xd5135784u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcec6776eu, 0x068afdfbu, 0x5b95a84bu, 0x37dea6cdu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0x5bb04bc7u, 0x40307f33u, 0x4438611cu, 0xce77ef4cu); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0xc23e5bffu, 0x3ff2f682u, 0x86ffb501u, 0x4b33968bu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe6aa096du, 0xd2c44e40u, 0x4bd7380eu, 0x1ee64b02u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x66651932u, 0xdd1276c0u, 0xcb505742u, 0xa96b774au); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0xc92bb4b8u, 0x3ec1b9beu, 0x6e7c1b1fu, 0x55983590u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x96245bd7u, 0x56105797u, 0x13f7872cu, 0xe823d68du); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf5e906f9u, 0x44bb39adu, 0xd0519e29u, 0x7475f442u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(952); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x06aff7d1u, 0x18aea6c8u, 0x86f229c2u, 0xf0e58cddu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(952); + HW_SCE_p_func100(0x68d7ffdbu, 0x48eebde8u, 0x65c5ae8bu, 0xfcd43c74u); + HW_SCE_p_func314(952+36); + HW_SCE_p_func100(0x58880bd1u, 0xa03cce13u, 0x5cb152e7u, 0x54ed01dbu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbeb6df12u, 0xb51f6599u, 0x04dd5c6du, 0xf91a1791u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x25cafafeu, 0x8c3c0489u, 0x66ca83ffu, 0xd6d66e08u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0x1f46ab53u, 0x124cc60cu, 0x8ad45ce5u, 0x7fb59dd1u); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x9b79a0f6u, 0xcb67c0b6u, 0xa3a3e1b3u, 0xd73496bbu); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6e0e8a8au, 0x6b6b1bf9u, 0xb4b8663bu, 0x628bad41u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ff6162u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func322(952); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f1u; + HW_SCE_p_func101(0x95bda937u, 0x8aa1ebf4u, 0x011ebbfbu, 0xc72e05a2u); + HW_SCE_p_func316(); + HW_SCE_p_func100(0xd5706a1cu, 0x9efead44u, 0x8624f1b4u, 0xe4ed91eeu); + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf27d42d7u, 0x9aebe897u, 0xa4bf4ed6u, 0xea904263u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x7b35e1c2u, 0x376987cdu, 0xffea7a71u, 0xfa1ff3f6u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0xcc82736au, 0x582bd5fau, 0x3a5ab3c7u, 0x73c1f935u); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0xc3892749u, 0x72d1a0c4u, 0x4bbe56d8u, 0x16968510u); + SCE->REG_28H = 0x008f0001u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000408u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000080cu; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00u; + SCE->REG_24H = 0x8000f4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_24H = 0x000050d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1e9fc4b4u, 0xa5142e28u, 0x2f8d26a5u, 0xf5e585f3u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(752); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x48326af2u, 0x44f85d94u, 0x71fcc7abu, 0xb1d54290u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1c1d2aacu, 0xee5bfa48u, 0x15543797u, 0xd62be25cu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0xbff66f32u, 0xdeaa2ffau, 0xaeea0bf2u, 0x57221606u); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0x3f4de62au, 0xd4a7763cu, 0x72a2c25du, 0xfee76446u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x408a6332u, 0x70c85823u, 0xba550647u, 0x6c7a0118u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xce068befu, 0x594ede3cu, 0xdd21f885u, 0x161bb234u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x06577a13u, 0x046c382au, 0x87202106u, 0x4aadd486u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x693044b9u, 0xf444e09du, 0x9cd38744u, 0xe79400dfu); + SCE->REG_28H = 0x008f0001u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000810u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030u; + SCE->REG_24H = 0x80007cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x02c0a883u, 0x19bc9bf8u, 0x8a4d98f1u, 0xe96ed903u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(716); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xfa3c622cu, 0xbe404837u, 0xeaf69b97u, 0x06fe547bu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x302b59aau, 0x3c798675u, 0xb2620a09u, 0xabfc9999u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x2caa1a54u, 0x74f01619u, 0x52968b85u, 0xde32ac27u); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0xaf3e4354u, 0xc389c01cu, 0x8632c676u, 0x37f71c4fu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xfa47bbbcu, 0x2186ab9bu, 0x6cbb06aeu, 0x24eec58du); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(992); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbba4691bu, 0xe809e7ecu, 0x87cc4caeu, 0x36e4d9ceu); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(992); + HW_SCE_p_func100(0xc300af1du, 0x00630fe3u, 0x587a44c0u, 0x979fcffdu); + HW_SCE_p_func314(992+36); + HW_SCE_p_func100(0x1add51aau, 0xd1792bb8u, 0x5da32e2du, 0xd9009259u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6533e676u, 0x00320303u, 0x5c57fa97u, 0xcd8f78d4u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x014842beu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func322(992); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f2u; + HW_SCE_p_func101(0x20156d0du, 0x4a6debf6u, 0xcd98c326u, 0xc2592cf4u); + HW_SCE_p_func316(); + HW_SCE_p_func100(0xb2a69fbdu, 0xd54a0102u, 0xa4ae8bc1u, 0xb09ac9cbu); + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x21279ea7u, 0x8885e559u, 0xfee5f26fu, 0xb8e8810eu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc61bc8d8u, 0xa17db7e5u, 0x4cf9ace0u, 0x8f4f62c0u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x3511825fu, 0xa1ad11c6u, 0x31304478u, 0x31441f8au); + HW_SCE_p_func314(816+36); + HW_SCE_p_func100(0x7afc6944u, 0x3665a4b9u, 0xe89d431eu, 0x812626ecu); + SCE->REG_28H = 0x008f0001u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000408u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x0000080cu; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00u; + SCE->REG_24H = 0x8000f4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_24H = 0x000050d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9370c3b9u, 0x1148f325u, 0xe6e883c1u, 0x1554a40eu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(752); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x5de51f5au, 0xd2ab8b57u, 0x5b4abc0au, 0xb66fa0ecu); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(896); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x73ba7d8eu, 0x3ec086e9u, 0xb7f46379u, 0x9bfbb9e7u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(896); + HW_SCE_p_func100(0x98fcf7c7u, 0xdb8e3b77u, 0x6d7956d9u, 0x27e79ea2u); + HW_SCE_p_func314(896+36); + HW_SCE_p_func100(0xf4cbee06u, 0x7c2204a2u, 0x9d9edc3fu, 0xf500a0deu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4327aa73u, 0xc6d287bbu, 0x43f83e20u, 0x2d47933du); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x898cf445u, 0xcd6ecfe9u, 0xb1e7dd5du, 0x3e376e78u); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0xe04ac6d1u, 0xbbd060d9u, 0x5333fbedu, 0xb1c7a350u); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0x78baf84bu, 0xd1b8ce55u, 0x026ec1a4u, 0x85342454u); + SCE->REG_28H = 0x008f0001u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000810u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c20u; + SCE->REG_24H = 0x80005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000030u; + SCE->REG_24H = 0x80007cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8da0cac8u, 0x7f4719efu, 0xdd188136u, 0xc4b4b9c7u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(716); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbf53761fu, 0x094a3437u, 0xe9a062d0u, 0xd6a2d246u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(856); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcc697f8bu, 0x92ad849au, 0xa4431439u, 0x9d2a656du); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x55bcde64u, 0x94f0b7ceu, 0xc4beae7eu, 0x801ee81du); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func321(816); + HW_SCE_p_func100(0x20b7209eu, 0x64136fe8u, 0x7c127365u, 0xde84756bu); + HW_SCE_p_func314(816+36); + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x800103e0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x800103c0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x3800dbffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x0e0631dfu, 0xffba1140u, 0xdb43c976u, 0xa4eb562cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0xffffffffu; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x1d28f437u, 0x93b026e2u, 0xf16d82e8u, 0x9f89524au); + } + else + { + SCE->REG_ECH = 0x00000800u; + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xf946db7du, 0x8ce722a7u, 0xd1bf9f9fu, 0x652119e5u); + } + HW_SCE_p_func100(0xf758d158u, 0x1da3af1cu, 0x8442f130u, 0x481aeb30u); + SCE->REG_ECH = 0x000034ffu; + SCE->REG_ECH = 0x00003420u; + SCE->REG_ECH = 0x00003440u; + SCE->REG_ECH = 0x00003460u; + SCE->REG_ECH = 0x00003480u; + SCE->REG_ECH = 0x000034a0u; + SCE->REG_ECH = 0x000034c0u; + SCE->REG_E0H = 0x81080000u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_34H = 0x00000804u; + SCE->REG_24H = 0x800090d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c04u; + SCE->REG_24H = 0x800090d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x8000b0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8ce9f145u, 0x0583725du, 0x018addc6u, 0x34a422fau); + SCE->REG_00H = 0x00002393u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func321(856); + HW_SCE_p_func100(0xc6b3739cu, 0xd28a9d79u, 0x1a35fa37u, 0xa6242a49u); + HW_SCE_p_func314(856+36); + HW_SCE_p_func100(0x55afc622u, 0xa9d4b88eu, 0x14cfedb9u, 0x2b7144c8u); + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x800090d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d3c420u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func322(896); + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x3800dbdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x1c438645u, 0x94e7987fu, 0xd13e1a83u, 0xe5515679u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0xffffffffu; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x82001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x94647d15u, 0xf787c49eu, 0xef925afeu, 0x6482c67eu); + } + else + { + SCE->REG_ECH = 0x00000800u; + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x2a5c9e0bu, 0x8043cdf5u, 0x8b7f2110u, 0x0d8657c3u); + } + SCE->REG_ECH = 0x000034feu; + SCE->REG_ECH = 0x00003420u; + SCE->REG_ECH = 0x00003440u; + SCE->REG_ECH = 0x00003460u; + SCE->REG_ECH = 0x00003480u; + SCE->REG_ECH = 0x000034a0u; + SCE->REG_ECH = 0x000034c0u; + SCE->REG_E0H = 0x81080000u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_34H = 0x00000804u; + SCE->REG_24H = 0x800090d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c04u; + SCE->REG_24H = 0x800090d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000004u; + SCE->REG_24H = 0x8000b0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0x9a8f5bd4u, 0x7c50c72bu, 0x2584aed1u, 0xbffc5331u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018fa058u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf8a9bcacu, 0xaa6f357fu, 0x644801e7u, 0x96ba6801u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func322(816); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef0d63u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbb149186u, 0x526dc394u, 0xedf700e9u, 0x16c04c42u); + SCE->REG_00H = 0x00003293u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func322(856); + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1a9e726bu, 0xffb2129bu, 0x15e2b7fbu, 0x10575273u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4f21d1bcu, 0xb4adf116u, 0xa072f0c8u, 0x5bc08591u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(716); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(752); + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c00u; + SCE->REG_24H = 0x800060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x800103e0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x3800dbffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xbf8f24dcu, 0xa8611807u, 0xd3d73e92u, 0x917d5611u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800103e0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3800dbffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x16bbe080u, 0x3a58b36du, 0x9c3bd981u, 0x89c7e361u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x74ef9fabu, 0x4f103f45u, 0x28e539d5u, 0x8781be87u); + oLoop1 = 0; + } + else + { + HW_SCE_p_func101(0xa8588d4eu, 0xd6390acau, 0x96539494u, 0x6e8e682fu); + } + } + } + else + { + oLoop1 = 1; + while(oLoop1 == 1) + { + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800103e0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3800dbffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x362dfab8u, 0x92e5f78au, 0x438ce431u, 0xf280d849u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x08586c47u, 0x91f65898u, 0xd0f33d44u, 0x5c1d4285u); + oLoop1 = 0; + } + else + { + HW_SCE_p_func101(0x09a1a341u, 0x90a8d52au, 0x83a061f8u, 0x02856805u); + } + } + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000008u; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func318.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c new file mode 100644 index 000000000..8b5e32cc7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func319.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func319(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x00000700u; + SCE->REG_C4H = 0x42e087bfu; + SCE->REG_04H = 0x00000282u; + for (iLoop2 = 0; iLoop2 < 32 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1+iLoop2 + 0] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 1] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 2] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func319.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c new file mode 100644 index 000000000..7e4e739f2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func320.c @@ -0,0 +1,109 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func320(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00001f62u; + SCE->REG_D0H = 0x00000700u; + SCE->REG_C4H = 0x42f087bfu; + for (iLoop2 = 0; iLoop2 < 32 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x400007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func320.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c new file mode 100644 index 000000000..b211f54fc --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func321.c @@ -0,0 +1,91 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func321(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_D0H = 0x00000800u; + SCE->REG_C4H = 0x42e087bfu; + SCE->REG_04H = 0x00000292u; + for (iLoop2 = 0; iLoop2 < 36 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[ARG1+iLoop2 + 0] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 1] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 2] = SCE->REG_100H; + S_HEAP[ARG1+iLoop2 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func321.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c new file mode 100644 index 000000000..0c8967151 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func322.c @@ -0,0 +1,109 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func322(uint32_t ARG1) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00002362u; + SCE->REG_D0H = 0x00000800u; + SCE->REG_C4H = 0x42f087bfu; + for (iLoop2 = 0; iLoop2 < 36 ; iLoop2 = iLoop2 + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x400007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 0]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 1]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 2]; + SCE->REG_100H = S_HEAP[ARG1+iLoop2 + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func322.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c new file mode 100644 index 000000000..abfb14544 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func323.c @@ -0,0 +1,184 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func323(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x000060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000002c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x00000981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000002c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a30001u; + SCE->REG_24H = 0x00001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00a70001u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000480au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000c02u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000801u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000054d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func323.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c new file mode 100644 index 000000000..b8140d134 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func324.c @@ -0,0 +1,944 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func324(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003fbeu; + HW_SCE_p_func100(0xba800165u, 0x9d0773f6u, 0xc404520bu, 0x64890201u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xd5fc2c48u, 0x3ee36e03u, 0x5d0a4911u, 0x3a0bf64du); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8b104378u, 0x5c4821e6u, 0xd5ad0910u, 0x350a2659u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(716); + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(752); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + oLoop1 = 1; + while(oLoop1 == 1) + { + HW_SCE_p_func100(0xf53e35c6u, 0xd82158c6u, 0xb88968fcu, 0xc7b36f20u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x905bfec7u, 0x34f45708u, 0x8a2c63ffu, 0x0f52cc31u); + oLoop1 = 0; + } + else + { + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func101(0x6fd622f4u, 0xc5c30bdbu, 0x97754975u, 0xabab04e2u); + } + } + HW_SCE_p_func100(0x21bbb393u, 0xcd9f14a3u, 0x26a0865fu, 0x7ab63a5fu); + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001981u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001181u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xfc6ff514u, 0xa79a0df4u, 0x7e3fac51u, 0x4283d461u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(136); + HW_SCE_p_func100(0x94f25a99u, 0xdcf9f94bu, 0xcc235501u, 0x569b42ddu); + HW_SCE_p_func314(136+32); + HW_SCE_p_func100(0xc3c50340u, 0x1fed1a99u, 0xc269950cu, 0xe7766b8eu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8cebb57cu, 0x04b0382fu, 0x60452136u, 0xde3445a7u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(172); + HW_SCE_p_func100(0xf53e25d8u, 0x61d4a5ceu, 0xd3c4952au, 0x9acca047u); + HW_SCE_p_func314(172+32); + HW_SCE_p_func100(0xb8a00ca9u, 0x28cfa0d8u, 0x81dd7ba0u, 0xa28e4d9fu); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6f9aab8fu, 0xabe2fdc1u, 0xd809f527u, 0x5f0cfc44u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(208); + HW_SCE_p_func100(0x85986bc9u, 0xdfec6f9fu, 0xd0187c6du, 0x35b96576u); + HW_SCE_p_func314(208+32); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52u; + for (iLoop = 0; iLoop < 128; iLoop = iLoop + 1) + { + HW_SCE_p_func100(0x676328e0u, 0x613dcc15u, 0xb5174525u, 0x35e75a6fu); + SCE->REG_24H = 0x040049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x23195e77u, 0x97f9f9e3u, 0x3a294c80u, 0x21a31b5fu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(716); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x00002e40u; + HW_SCE_p_func101(0xe6f2fb13u, 0x44ac6782u, 0xacacfa2cu, 0xc6ce06bau); + } + SCE->REG_ECH = 0x38008a40u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0xdff19989u, 0xed86b6e4u, 0x810692d1u, 0x4054ba1fu); + SCE->REG_24H = 0x040049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x040019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0400d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x020019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb252e8f6u, 0xa305ef14u, 0xae64b69au, 0x585821f5u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(680); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe3ac09b8u, 0xed2ade8eu, 0x09e0d6a0u, 0x53c92617u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(716); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4a733c3du, 0x2b978923u, 0xc70ac96au, 0xf892a403u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0x6a895ce5u, 0x6c42347fu, 0x214cfe83u, 0x59e7049eu); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0xdea06f25u, 0x53d8df33u, 0x9c88cf0eu, 0x67a0090au); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xbf3bc416u, 0x136f6b3eu, 0xacf5f90fu, 0x3425f707u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0x1c85df96u, 0x3d70a07du, 0x430218bcu, 0xb738452du); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0x4894e0eau, 0x1ed6fd66u, 0x44c98fa9u, 0x93476849u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x27653520u, 0xaf747027u, 0xdc554257u, 0xf7ab9d4bu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(544); + HW_SCE_p_func100(0x799b94d4u, 0xc20a7cd7u, 0x9cca7baau, 0x7cb589a4u); + HW_SCE_p_func314(544+32); + HW_SCE_p_func100(0x88fb9181u, 0xb55c73deu, 0x7d7588f0u, 0xf5f0778cu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf3a6d287u, 0xc0bae19au, 0x4a678488u, 0x782770a3u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(580); + HW_SCE_p_func100(0x713444a7u, 0xc18c9532u, 0x50c8e298u, 0x48490351u); + HW_SCE_p_func314(580+32); + HW_SCE_p_func100(0xc516255bu, 0xc4f1442cu, 0xe9885d55u, 0xb986eeb2u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x54c6a527u, 0x13c8e927u, 0xb44ce6aau, 0xeb9e9d3fu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0x265120a7u, 0x73fc5c2eu, 0xef24e3f8u, 0x4fbcfaadu); + HW_SCE_p_func314(480+32); + HW_SCE_p_func100(0x61f0fe5eu, 0x0f4cbddfu, 0x1ad3a9e8u, 0x1a0d7668u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x7be00fceu, 0x9aeb3edeu, 0x25026ce9u, 0xc2d0db59u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(616); + HW_SCE_p_func100(0x73a48fa9u, 0x38d334c0u, 0xadf63b4du, 0xf330a5ccu); + HW_SCE_p_func314(616+32); + SCE->REG_ECH = 0x00000a52u; + for (iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f0u; + HW_SCE_p_func101(0x20fa9c73u, 0xbbf1986du, 0x9bfb0b9du, 0x272b4a9eu); + HW_SCE_p_func318(); + HW_SCE_p_func100(0x91e54cabu, 0xdaa2840bu, 0xe523dc34u, 0x667f6b46u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb669ddffu, 0xc3ef8260u, 0x5350ad91u, 0x9fa7b544u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0x147c2639u, 0x9cc02970u, 0x583dd0dbu, 0x528abff7u); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0x1714ce33u, 0x4aad3236u, 0x7b544d55u, 0xd9609333u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1cd470e5u, 0x633c9ff4u, 0x1cdcb115u, 0x26eda65cu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0xb9364cc7u, 0xbefc7673u, 0x0e7a2b28u, 0x2ad0bb86u); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0x51f70bf0u, 0x01fd1d85u, 0x88cd7d7au, 0xc11c13c1u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x859aa5c9u, 0x89c173aeu, 0x7aab7a3eu, 0x4bd05495u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0xa64744e4u, 0xa6a5a5c4u, 0x6f2d5dc6u, 0x2fe1048eu); + HW_SCE_p_func314(480+32); + HW_SCE_p_func100(0xfa4d90b8u, 0x0d966024u, 0x19970766u, 0x2c40f92eu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x7f6a3d31u, 0x15656e45u, 0x8350c92bu, 0xa29a076du); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(544); + HW_SCE_p_func100(0xe8a70fe7u, 0x4d8a9e70u, 0x3f48c23au, 0x89eeb55eu); + HW_SCE_p_func314(544+32); + HW_SCE_p_func100(0x5c04f776u, 0x21f0f81fu, 0x4e3a8a5bu, 0x76098a00u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x472aaf2au, 0xf9d8f81cu, 0x07508940u, 0xd7a49d5au); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(580); + HW_SCE_p_func100(0x05d64b3fu, 0x793b0085u, 0xa705f245u, 0xe95259deu); + HW_SCE_p_func314(580+32); + HW_SCE_p_func100(0xfa3b4138u, 0xbe30de6cu, 0xfc3bd1eau, 0x2e93d150u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa6ec6b8cu, 0xaa9fd90bu, 0x46b98ebeu, 0xfbe37dfcu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(616); + HW_SCE_p_func100(0x0f67fcf6u, 0xd661c9b8u, 0x78b71659u, 0xdc1671e7u); + HW_SCE_p_func314(616+32); + SCE->REG_ECH = 0x00002e40u; + HW_SCE_p_func101(0x61371d76u, 0x8955c0e3u, 0xf57d2ea6u, 0x6b052d94u); + } + SCE->REG_ECH = 0x38008a40u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f1u; + HW_SCE_p_func101(0x8bba8cdbu, 0xa7e18e91u, 0xf71d87c8u, 0x797aa69cu); + HW_SCE_p_func318(); + HW_SCE_p_func100(0x322547acu, 0x9b5539eeu, 0x631909e9u, 0xa317cbbbu); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1759ee18u, 0x3b01deecu, 0x6a8590f4u, 0xf6c5f969u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0x96c47023u, 0x7df6d2ccu, 0xf3632006u, 0x6fe7f4f8u); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0x91a24210u, 0xcbb101b4u, 0xb5ba4705u, 0xfbf14b32u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x2c310da3u, 0x5ea30255u, 0xa29d782eu, 0x0bc1f93eu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0x8b87eef7u, 0x213e09a1u, 0xa69cfedbu, 0xfb9276f3u); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0xd41003bau, 0x105fbe5au, 0x561c8390u, 0x4b945c86u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x48db3531u, 0x94b996bdu, 0x060dbf20u, 0x9520a664u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0xb51fc317u, 0xc794cd92u, 0xb477efbcu, 0x81dce284u); + HW_SCE_p_func314(480+32); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f2u; + HW_SCE_p_func101(0xbf232622u, 0x10d13a51u, 0x848c8464u, 0x5f80635du); + HW_SCE_p_func318(); + HW_SCE_p_func100(0x30a00026u, 0x69802337u, 0x7cd74e4fu, 0x52041efcu); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01d34587u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x553d552eu, 0xb04761ecu, 0x3077aef8u, 0x831743f4u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(272); + HW_SCE_p_func100(0x7432c608u, 0xc9fed9c7u, 0xec726f19u, 0x8d5f8875u); + HW_SCE_p_func314(272+32); + HW_SCE_p_func100(0xaace0e99u, 0x42f2e878u, 0xdd957896u, 0xcd0de241u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01315552u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x5c31900bu, 0x2680183du, 0xe043b5a4u, 0x8db6cf2du); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(308); + HW_SCE_p_func100(0xcdd8331eu, 0xa782fd53u, 0xc031e37eu, 0xf9541b33u); + HW_SCE_p_func314(308+32); + HW_SCE_p_func100(0x36ab5860u, 0x7d1990c3u, 0xd106d439u, 0xd15c9b71u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011a27dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6fc441bdu, 0x7bce0d3bu, 0xe350cbc9u, 0x0d856aceu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(344); + HW_SCE_p_func100(0xe4f910e8u, 0x57082666u, 0x3975f343u, 0xeb5a48a4u); + HW_SCE_p_func314(344+32); + HW_SCE_p_func100(0x8de19a0bu, 0x8f9aed6fu, 0x47fdf7ecu, 0x62fb4c80u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x26831bc6u, 0xcde42f4fu, 0x8b4d5307u, 0xca3cecfeu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0x68d5d8f0u, 0x2d218dd1u, 0xd6eea468u, 0xb35336b8u); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0x021c7250u, 0x492cdf1fu, 0x3a45037fu, 0xefeca1b5u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0cb3fc26u, 0xcb04bc14u, 0xb6de0377u, 0x53ba5f3fu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0x2e642543u, 0x4902544au, 0x51f5ebe8u, 0x72794910u); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0x8f9d782eu, 0x81c16d66u, 0x5e85807eu, 0x6ef1b6d8u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc718fd71u, 0x78b1a7f1u, 0x20b0a1fcu, 0x08efeaa0u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0x1703905fu, 0x2588568cu, 0x62ecbe40u, 0x232f9133u); + HW_SCE_p_func314(480+32); + HW_SCE_p_func100(0x3a1733d4u, 0x86275a46u, 0x6eccc0a1u, 0x33a7dc95u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8e52d68bu, 0x1f5c3894u, 0x691f3877u, 0x2243d7a3u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(0); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x29bf281fu, 0x90730ae8u, 0x5c16ffe4u, 0x9746b752u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000013u; + HW_SCE_p_func320(36); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc6d651f1u, 0xea4e04fbu, 0x1e97b80eu, 0x728f545cu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(72); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4f8d632au, 0xfd956a83u, 0x8a13de73u, 0x6dd74cadu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(544); + HW_SCE_p_func100(0xc1fe21f7u, 0x1494de69u, 0xb4a7584bu, 0x901cd492u); + HW_SCE_p_func314(544+32); + HW_SCE_p_func100(0x0e1dc5d7u, 0x2032e656u, 0x84c0fcffu, 0x1b85a4d7u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x085429ddu, 0x35c43703u, 0x5059446fu, 0x997691b1u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(580); + HW_SCE_p_func100(0x6d916213u, 0xb2da4cceu, 0x367fbab5u, 0x2acea943u); + HW_SCE_p_func314(580+32); + HW_SCE_p_func100(0x18057ff5u, 0x754a8c51u, 0x086a4be3u, 0x90067525u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x325a9a89u, 0x535dc5d9u, 0x1f05a791u, 0xcd2f9884u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(616); + HW_SCE_p_func100(0xc75b4b8fu, 0x620e68b0u, 0xbbebe121u, 0xe12fba81u); + HW_SCE_p_func314(616+32); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f3u; + HW_SCE_p_func101(0x06aa632cu, 0x2c294586u, 0x524b9262u, 0x937064feu); + HW_SCE_p_func318(); + HW_SCE_p_func100(0x7ea795a3u, 0x8915f2cbu, 0xa7c41020u, 0x0f89207eu); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9a6b4727u, 0x19829e58u, 0xb07a6fc7u, 0x1ec71baeu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(0); + HW_SCE_p_func100(0xb85e4c02u, 0x1065c4d4u, 0x565140bcu, 0x9e233683u); + HW_SCE_p_func314(0+32); + HW_SCE_p_func100(0x0f6b1778u, 0xbd59c987u, 0x90211bb5u, 0x109bfbf8u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb356879fu, 0xa9e41716u, 0x28645099u, 0x0bf86938u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(36); + HW_SCE_p_func100(0xb6a059a7u, 0xb27e1a91u, 0xe6575256u, 0x7d8b8dbcu); + HW_SCE_p_func314(36+32); + HW_SCE_p_func100(0xe0209cc9u, 0xc3e5b064u, 0xe233e02bu, 0xb82949e6u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcf7deda8u, 0xb4cb207eu, 0x706bb36cu, 0xd048408eu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(72); + HW_SCE_p_func100(0x39eb6316u, 0x27f38705u, 0x8667e6f3u, 0xf04bff62u); + HW_SCE_p_func314(72+32); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func324.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c new file mode 100644 index 000000000..c904dd279 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_func325.c @@ -0,0 +1,710 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_p_func325(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003fbeu; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f0u; + HW_SCE_p_func101(0x19b9f8aeu, 0x00dc1eecu, 0xf9dd9c29u, 0x487dca94u); + HW_SCE_p_func324(); + SCE->REG_ECH = 0x00000a73u; + SCE->REG_ECH = 0x00000a31u; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x00002e20u; + SCE->REG_ECH = 0x38002673u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x5ff32453u, 0x873c3af2u, 0x1ef0a9f2u, 0xeea1abc8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0xd91c4453u, 0x71906777u, 0x65eb6ac8u, 0x68116537u); + } + else + { + HW_SCE_p_func100(0x6f5b19e9u, 0xdac83bf0u, 0x54111c06u, 0xb860b781u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe22eb519u, 0x6de82dcfu, 0xb8f9baceu, 0xbc0d647du); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(136); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x1cdea842u, 0xb564ce9eu, 0xaf62b09du, 0xa657fcd4u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000013u; + HW_SCE_p_func320(172); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6ae3808fu, 0x31e8aaa5u, 0x83c15ab1u, 0x0e1e2a56u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(208); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xdbf17b2cu, 0x6294819cu, 0x1e63b419u, 0x687af4b1u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0x6cafabccu, 0xab9a7899u, 0x3e4e3a72u, 0x7238056du); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0x2a966046u, 0xe5910a6au, 0xb9af8bc2u, 0x93b2ee87u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf0bb19d3u, 0x6d0a732fu, 0x79edce81u, 0x499d547fu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0xb6c9eb32u, 0xad8b6a5au, 0x5b45535du, 0xdb899e90u); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0xc8542ac7u, 0x35039915u, 0xfe02b565u, 0x41720439u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6977f72au, 0xf0c40367u, 0x67b15bacu, 0x3c1c7ed3u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0x043ee0feu, 0x624f430cu, 0xb8984341u, 0x2e9b0883u); + HW_SCE_p_func314(480+32); + HW_SCE_p_func100(0x990f8d9cu, 0xbae662edu, 0x9243df9fu, 0x70f27c08u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x882daaf8u, 0x19e744beu, 0x796e7434u, 0x58deac8cu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(544); + HW_SCE_p_func100(0xa65ba385u, 0xd358b3d1u, 0x514a28beu, 0xc75e4c3cu); + HW_SCE_p_func314(544+32); + HW_SCE_p_func100(0x8e27c19eu, 0x824b7d7eu, 0xe50f28fdu, 0x7e778871u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x90947f6fu, 0x28cf15d5u, 0xe7bf2d71u, 0xc95bc76cu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(580); + HW_SCE_p_func100(0xd47910a8u, 0x77c0c723u, 0x9458a5c8u, 0xf065fe99u); + HW_SCE_p_func314(580+32); + HW_SCE_p_func100(0x462657d5u, 0xd8ee238bu, 0x244727e6u, 0x5fbb2ec0u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x95cd2f1bu, 0xac924fb3u, 0x07bbac8eu, 0x5868deb3u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(616); + HW_SCE_p_func100(0xb8afe95du, 0xf0a676a8u, 0x278ca2e7u, 0xd432ab29u); + HW_SCE_p_func314(616+32); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f0u; + HW_SCE_p_func101(0x4b583ae7u, 0x56d78152u, 0xd8cd207fu, 0x9097cbb4u); + HW_SCE_p_func318(); + HW_SCE_p_func100(0xa29f08dau, 0x8b21226du, 0xba1aa171u, 0x8c03bd6bu); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x3e09f796u, 0x1f5513bau, 0xf2906a3au, 0xf6a264a1u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(136); + HW_SCE_p_func100(0x83f2f5c5u, 0xdb4b3aa1u, 0xacb5ab71u, 0xe7159fd6u); + HW_SCE_p_func314(136+32); + HW_SCE_p_func100(0xc6cc13adu, 0x22bf318cu, 0xd52ea535u, 0x0bfda6bcu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4434b13au, 0x76d201adu, 0x198d4932u, 0xd9a8e8c6u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(172); + HW_SCE_p_func100(0x2034127au, 0x60179772u, 0x9d4f2692u, 0xf359f550u); + HW_SCE_p_func314(172+32); + HW_SCE_p_func100(0x03be931eu, 0x9b569d30u, 0xf39d0140u, 0x2f929436u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xd22044a4u, 0x1911ee48u, 0x559c468eu, 0x6062e4e5u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(208); + HW_SCE_p_func100(0xf4dc0b69u, 0xee39d2a1u, 0x3638a4f4u, 0x87ad8cf6u); + HW_SCE_p_func314(208+32); + HW_SCE_p_func101(0x48c6011cu, 0x2d1d0c0eu, 0x3ad508d0u, 0x1863f5c7u); + } + SCE->REG_ECH = 0x3800da9fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x06fcfb29u, 0xb5045fefu, 0x87993562u, 0x6e1bce5du); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0xa3dd6937u, 0x1080ea7cu, 0xc0f8663bu, 0x39b34e02u); + } + else + { + HW_SCE_p_func100(0x540eaafeu, 0x60f8d266u, 0x51ba7ec8u, 0x6541c4a3u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xd329fbd9u, 0x86370735u, 0x1cd4c4d4u, 0x1fb5eb99u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(136); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x301cecd5u, 0x4564a991u, 0xbc369ba9u, 0x4a2cf3e1u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000013u; + HW_SCE_p_func320(172); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf8299ab7u, 0x076dd2d1u, 0xc71f95d9u, 0x3f74c2beu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(208); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x955095f2u, 0xd4c1cc44u, 0x0ce404d9u, 0x52d5d7b5u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0xe316b5d0u, 0xdc820713u, 0x5f194abdu, 0xee24561du); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0x9ac19dcdu, 0x11319817u, 0x001f0298u, 0xd44474ddu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf2b7c604u, 0xc4d8ae51u, 0xa1400e6du, 0x4ac2cfe5u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0xc8a82995u, 0x69c2c9d0u, 0xa23c78e5u, 0xa1933962u); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0x3e8777a9u, 0x035aba94u, 0xf0b79fbeu, 0xe1b3f6a2u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xeaa6d560u, 0xabad2c3au, 0xdc290ad1u, 0x39475f8bu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0x2b3c96c7u, 0xb57a384du, 0x2a0d1079u, 0x0b244eddu); + HW_SCE_p_func314(480+32); + HW_SCE_p_func100(0x818d681cu, 0x3c100869u, 0xd540af50u, 0x53b53f03u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x575886ccu, 0x974ffacdu, 0x38c459acu, 0xc330f9f3u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(0); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc1082ebfu, 0xb40fb8aeu, 0x79c8c97cu, 0xed24f889u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000013u; + HW_SCE_p_func320(36); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9fb715ddu, 0xd24805b2u, 0xe75eea3fu, 0x21359476u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(72); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x3d283b5bu, 0xc0006d6eu, 0x5de47c42u, 0x0b5c8f89u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(544); + HW_SCE_p_func100(0x94a39151u, 0xb687a632u, 0x001e36d5u, 0xf6e53aecu); + HW_SCE_p_func314(544+32); + HW_SCE_p_func100(0x244d5b4du, 0xe0528084u, 0xa5561169u, 0x921196d6u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x813a2c73u, 0xc5f64d97u, 0x9fd7d1dbu, 0x38014a6du); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(580); + HW_SCE_p_func100(0xa5186967u, 0xf53547d6u, 0x1f89c868u, 0x20367485u); + HW_SCE_p_func314(580+32); + HW_SCE_p_func100(0x459a5ae0u, 0x3c7dce9du, 0x7515a16eu, 0x531936b7u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf3133da1u, 0x77545f92u, 0x2c13ae9bu, 0x8ab362ebu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(616); + HW_SCE_p_func100(0x58ee5ddbu, 0x9061965bu, 0xfdbfec79u, 0xab87a7f8u); + HW_SCE_p_func314(616+32); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f1u; + HW_SCE_p_func101(0x55a0f782u, 0xc388d766u, 0xc11aff3bu, 0x804653c6u); + HW_SCE_p_func318(); + HW_SCE_p_func100(0x8f95701eu, 0x150383aau, 0x313ca36du, 0x62f31989u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x27b6018du, 0xc2d58137u, 0xdaca4f73u, 0xa52f81c8u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(136); + HW_SCE_p_func100(0x7431f476u, 0x94a93defu, 0x3ba1ad1du, 0x21d00227u); + HW_SCE_p_func314(136+32); + HW_SCE_p_func100(0x25a731a2u, 0x4a77f567u, 0xe605568cu, 0x0e3a4862u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4d9ad891u, 0x883ad05fu, 0x12dd6651u, 0x691f5aafu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(172); + HW_SCE_p_func100(0x0e617478u, 0xaec9a0f7u, 0xab6c622bu, 0xc06428feu); + HW_SCE_p_func314(172+32); + HW_SCE_p_func100(0x8c9380feu, 0x7636013au, 0x4796f2c7u, 0xb9a6e0b0u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe3018af1u, 0x5ca863f5u, 0xc01f235du, 0xd337275fu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(208); + HW_SCE_p_func100(0xb42aa5c7u, 0xde19d9cau, 0x018b5d65u, 0xef529d6fu); + HW_SCE_p_func314(208+32); + SCE->REG_ECH = 0x0000d260u; + HW_SCE_p_func101(0x96bd80abu, 0xe755313eu, 0x61b1ac43u, 0xfe71c8cfu); + } + SCE->REG_ECH = 0x01816e94u; + HW_SCE_p_func101(0xa7c7f7dfu, 0x2e444bafu, 0x34990ba4u, 0x0ce22f12u); + } + SCE->REG_ECH = 0x38008a20u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0x6deb8b57u, 0x94b7124bu, 0x66285537u, 0x5db62f05u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ef2f1cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xaf2a241bu, 0xd409fd47u, 0x4b0764afu, 0xf4628897u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(136); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012e06e6u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xcb93e799u, 0x927f831eu, 0x87824be8u, 0xbd7dd869u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000013u; + HW_SCE_p_func320(172); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0100abe1u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe14b8260u, 0xc2f90836u, 0xa4e4ccfeu, 0xb9181958u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(208); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x011af8f9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc8121ceau, 0x80714d15u, 0x8cef80eeu, 0xb7b9ecb1u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(408); + HW_SCE_p_func100(0x135ecb32u, 0xf40d3d5au, 0x5b75cd89u, 0x555e08a7u); + HW_SCE_p_func314(408+32); + HW_SCE_p_func100(0xd562a946u, 0xb0463152u, 0x1be9639cu, 0xa25bfe98u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0130aeffu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xfb0b81a2u, 0x0475c67eu, 0xb2f3371fu, 0x9c99e5e5u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(444); + HW_SCE_p_func100(0x247abdc4u, 0x8088223au, 0x4c2a3bd3u, 0xf6f4099cu); + HW_SCE_p_func314(444+32); + HW_SCE_p_func100(0x486c7a40u, 0x6761da7eu, 0xf076a48eu, 0x4c49b7bfu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010964eau); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xc1ba29d8u, 0x6b9bded9u, 0xd2a90427u, 0x65629fb1u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(480); + HW_SCE_p_func100(0x22079e19u, 0x70a0624fu, 0xef51c3adu, 0xc38e93d3u); + HW_SCE_p_func314(480+32); + HW_SCE_p_func100(0xa9f9e0a8u, 0x6a85e3a5u, 0x0642606au, 0xdd999e86u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000001c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ac62c9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xb1ebc7b9u, 0x0f36ca8au, 0x8f9b5f56u, 0x44721820u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(616); + HW_SCE_p_func100(0x68433359u, 0x306beee5u, 0x552d671du, 0x7168bbbcu); + HW_SCE_p_func314(616+32); + HW_SCE_p_func100(0xe33d52b8u, 0x809c11a1u, 0xf5117386u, 0xcc37fadcu); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01574730u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x48c37190u, 0x8bbefda8u, 0x978c9cddu, 0x53e45d9bu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(544); + HW_SCE_p_func100(0xa3b1323fu, 0xf6874d14u, 0x8668673bu, 0x7990152fu); + HW_SCE_p_func314(544+32); + HW_SCE_p_func100(0x7daabbc8u, 0x38612bfeu, 0xf86a0b66u, 0x934059b4u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f11123u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x47bab8c1u, 0xafc73bcfu, 0x5e08a50du, 0x30704306u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000023u; + HW_SCE_p_func319(580); + HW_SCE_p_func100(0x6a8a5afdu, 0x62926c28u, 0x8e1be5b5u, 0x89cbfff9u); + HW_SCE_p_func314(580+32); + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f2u; + HW_SCE_p_func101(0xe3857bc5u, 0x0bf35aafu, 0xe3f75101u, 0x83c810b1u); + HW_SCE_p_func318(); + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x00003bbeu; + SCE->REG_ECH = 0x00007c1du; + SCE->REG_1CH = 0x00602000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_func325.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c new file mode 100644 index 000000000..785e7b51a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p00.c @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_SoftwareResetSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0x00000000u; + SCE->REG_1D0H = 0x00000000u; + SCE->REG_1D0H = 0x00000000u; + SCE->REG_1D0H = 0x00000000u; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p00.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c new file mode 100644 index 000000000..f3d439a45 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p01.c @@ -0,0 +1,128 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_SelfCheck1Sub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_SelfCheck1SubSub(); + + SCE->REG_138H = 0xf597806Au; + SCE->REG_F0H = 0x00000000u; + SCE->REG_04H = 0x00000001u; + SCE->REG_10CH = 0x00000701u; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_80H = 0x00000001u; + SCE->REG_28H = 0x00000001u; + SCE->REG_7CH = 0x00000001u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + SCE->REG_84H = 0x00010101u; + SCE->REG_13CH = 0x00000F00u; + SCE->REG_88H = 0x00008002u; + SCE->REG_104H = 0x00000352u; + HW_SCE_p_func101(change_endian_long(0xe1a2a5d8u), change_endian_long(0x821a5428u), change_endian_long(0x7c777ac3u), change_endian_long(0xfd151290u)); + SCE->REG_88H = 0x00000000u; + SCE->REG_104H = 0x00000352u; + SCE->REG_C4H = 0x000f3a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x9ed66559u; + SCE->REG_100H = 0x8e5bcbb9u; + SCE->REG_100H = 0xd2f5d1d3u; + SCE->REG_100H = 0xae209b90u; + HW_SCE_p_func101(change_endian_long(0xf4e6ce80u), change_endian_long(0x39773b0fu), change_endian_long(0x86227f8fu), change_endian_long(0x2b810040u)); + HW_SCE_p_func100(change_endian_long(0x3e5590a5u), change_endian_long(0x96fa7453u), change_endian_long(0x0e213a19u), change_endian_long(0x12498aecu)); + SCE->REG_04H = 0x00001001u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_18H_b.B13)) + { + SCE->REG_1BCH = 0x00000020u; + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_08H = 0x0000FFFFu; + SCE->REG_13CH = 0x00000220u; + HW_SCE_p_func102(change_endian_long(0x62cb9591u), change_endian_long(0x72556c92u), change_endian_long(0x45cac937u), change_endian_long(0x8431be8fu)); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p01.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c new file mode 100644 index 000000000..141b8547a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p02.c @@ -0,0 +1,383 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_SelfCheck2Sub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000201u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00093b8cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x01c7ba56u; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00070804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x00000000u; + SCE->REG_ECH = 0x3000a820u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_ECH = 0x00010020u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_ECH = 0x00000080u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00002008u; + SCE->REG_ECH = 0x00000863u; + SCE->REG_ECH = 0x00000884u; + SCE->REG_ECH = 0x000008a5u; + SCE->REG_ECH = 0x0000b4c0u; + SCE->REG_ECH = 0x00000013u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000348u; + SCE->REG_ECH = 0x0000b500u; + SCE->REG_ECH = 0x000000b7u; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + HW_SCE_p_func100(change_endian_long(0x600eb3f3u), change_endian_long(0x5be54db5u), change_endian_long(0xd957da80u), change_endian_long(0xb7be0bbdu)); + SCE->REG_ECH = 0x00007c01u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901cu; + HW_SCE_p_func101(change_endian_long(0x1cb8f160u), change_endian_long(0x44a42eb9u), change_endian_long(0xb9d9de91u), change_endian_long(0xf7e69233u)); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901eu; + HW_SCE_p_func101(change_endian_long(0x59fb7336u), change_endian_long(0x9c8f2482u), change_endian_long(0xc090f97fu), change_endian_long(0x0dba80dfu)); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0020901du; + HW_SCE_p_func101(change_endian_long(0xed4e6151u), change_endian_long(0xc771e206u), change_endian_long(0x81266996u), change_endian_long(0x2bbee94du)); + } + SCE->REG_C4H = 0x41001e5eu; + SCE->REG_00H = 0x80002401u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001200u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B30) + { + /* waiting */ + } + SCE->REG_00H = 0x00000001u; + SCE->REG_C4H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0010B008u; + SCE->REG_ECH = 0x00000800u; + SCE->REG_E0H = 0x80900000u; + SCE->REG_00H = 0x00008443u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000038a0u; + SCE->REG_ECH = 0x00003405u; + SCE->REG_ECH = 0x00002804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x34202808u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x00003485u; + HW_SCE_p_func101(change_endian_long(0x48b1bfc2u), change_endian_long(0x2f0d98c0u), change_endian_long(0xff07792fu), change_endian_long(0x166d190cu)); + } + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000B50u; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x00000002u; + for(iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x00002440u; + SCE->REG_ECH = 0x00002cc0u; + SCE->REG_ECH = 0x00002485u; + } + SCE->REG_ECH = 0x00002c20u; + SCE->REG_ECH = 0x38008840u; + SCE->REG_ECH = 0x00002000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_1CH = 0x00402000u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000033u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x0000003cu; + SCE->REG_ECH = 0x01003804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x00002cc0u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x0000003eu; + SCE->REG_ECH = 0x01003804u; + SCE->REG_ECH = 0x342028e0u; + SCE->REG_ECH = 0x10005066u; + SCE->REG_ECH = 0x38008860u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(change_endian_long(0xaddf6f7bu), change_endian_long(0xae6de2f8u), change_endian_long(0xf97e7cdau), change_endian_long(0x68b0a447u)); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(change_endian_long(0x2c21e21cu), change_endian_long(0x8f10bb7au), change_endian_long(0x7714e304u), change_endian_long(0x3807136cu)); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x0000001cu; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000cc4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x00000000u; + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x41001eddu; + SCE->REG_00H = 0x00002413u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000000u; + SCE->REG_E0H = 0x80040080u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(change_endian_long(0xcfbe1fc5u), change_endian_long(0xae3c0b75u), change_endian_long(0xfa1b775cu), change_endian_long(0xfccd985au)); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x000b0804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x00000000u; + SCE->REG_104H = 0x00000352u; + SCE->REG_C4H = 0x00070805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x00000000u; + SCE->REG_100H = 0x00000000u; + SCE->REG_100H = 0x00000000u; + SCE->REG_100H = 0x00000001u; + HW_SCE_p_func100(change_endian_long(0xd69c553bu), change_endian_long(0x72e04337u), change_endian_long(0xcf6834e5u), change_endian_long(0x29b2da04u)); + SCE->REG_D0H = 0x00000100u; + SCE->REG_C4H = 0x0100b7f7u; + SCE->REG_E0H = 0x81080000u; + SCE->REG_00H = 0x00002823u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x000b0805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x00070805u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(change_endian_long(0x1c99323fu), change_endian_long(0x6c63dba1u), change_endian_long(0x38229203u), change_endian_long(0x22d91767u)); + HW_SCE_p_func103(); + HW_SCE_p_func100(change_endian_long(0x80b45ab9u), change_endian_long(0x4d97ab5fu), change_endian_long(0x3ef09550u), change_endian_long(0xa94d5b6eu)); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x010d0c04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x00000000u; + HW_SCE_p_func100(change_endian_long(0xe6c8760fu), change_endian_long(0x099c6fc6u), change_endian_long(0x1406eda2u), change_endian_long(0x580bd39cu)); + HW_SCE_p_func103(); + HW_SCE_p_func100(change_endian_long(0xff2b1e8au), change_endian_long(0x3e6453b3u), change_endian_long(0xe33170b8u), change_endian_long(0xe2d6af49u)); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = 0x00000000u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[16] = change_endian_long(SCE->REG_100H); + S_RAM[17] = change_endian_long(SCE->REG_100H); + S_RAM[18] = change_endian_long(SCE->REG_100H); + S_RAM[19] = change_endian_long(SCE->REG_100H); + SCE->REG_13CH = 0x00000221u; + HW_SCE_p_func102(change_endian_long(0xf3939357u), change_endian_long(0x04e0f3c0u), change_endian_long(0x2c7db127u), change_endian_long(0x9914e276u)); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p02.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c new file mode 100644 index 000000000..edf432f31 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p07.c @@ -0,0 +1,201 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000701u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0xf7efeb7eu, 0x5bdda299u, 0xe42a1e4fu, 0x767dea6au); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000007u); + HW_SCE_p_func101(0x513bef76u, 0xa59e0bb3u, 0xcdfad875u, 0x8d637e2eu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000007u); + HW_SCE_p_func101(0x83e1178eu, 0x3dd77044u, 0x3cd5df94u, 0x9ce47099u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xeae16410u, 0x81a2bb97u, 0x822b834eu, 0x1611ebcau); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0xf2419c1cu, 0xefb76c05u, 0x2d1e5187u, 0xe3503335u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02e487b5u; + SCE->REG_E0H = 0x81040000u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x248dcc14u, 0x40944f2bu, 0x3a2a8f3fu, 0x66cf1e3fu); + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000001u); + SCE->REG_04H = 0x00000222u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + HW_SCE_p_func102(0x8728d316u, 0xba08805au, 0x85a1e7e1u, 0xc29c1790u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p07.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c new file mode 100644 index 000000000..c1fd1d731 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p08.c @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00000801u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0xabd3565cu, 0x38ca4728u, 0x0c8efe13u, 0x081a2236u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000008u); + HW_SCE_p_func101(0x10a39676u, 0xc3d8a8a9u, 0xfbeb969eu, 0x182d783du); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000008u); + HW_SCE_p_func101(0x6c226c1bu, 0xb630a761u, 0xa2d8c6f3u, 0x672d12aeu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x6079276cu, 0x59d50fb9u, 0xbd4e561au, 0x86e05366u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0xe69703ebu, 0xba7394ccu, 0x4cb5d6e4u, 0xb4745793u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xbd01dcc1u, 0x16cd31d6u, 0x6634e7beu, 0xff62b791u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x78c9115au, 0xc5dd48b9u, 0x7e7ed9a3u, 0xe62efcacu); + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02e487b7u; + SCE->REG_E0H = 0x81080000u; + SCE->REG_00H = 0x00002823u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000002u); + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + OutData_KeyIndex[2] = SCE->REG_100H; + OutData_KeyIndex[3] = SCE->REG_100H; + OutData_KeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + OutData_KeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + OutData_KeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func102(0x3b696d5fu, 0x686352f3u, 0x37f6ff6fu, 0x9a7c40c2u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p08.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c new file mode 100644 index 000000000..d683ecfc1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p20.c @@ -0,0 +1,105 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002001u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x39474ca5u, 0x2734ab38u, 0xac8a3b6eu, 0xd618ffa1u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x78680554u, 0x7e6bcbf3u, 0x28e0c2d1u, 0x77ed0e82u); + SCE->REG_04H = 0x00000213u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func102(0xabc3a4dbu, 0x2a94f5aeu, 0xd92f7679u, 0x10c3f31bu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p20.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c new file mode 100644 index 000000000..4c464249c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p21.c @@ -0,0 +1,140 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002101u; + SCE->REG_108H = 0x00000000u; + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_74H = 0x00001000u; + SCE->REG_104H = 0x00000364u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_HV[0]; + SCE->REG_100H = InData_HV[1]; + SCE->REG_100H = InData_HV[2]; + SCE->REG_100H = InData_HV[3]; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000364u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_74H = 0x00000002u; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func100(0xa49f2fb4u, 0xcf741bfeu, 0x976976aeu, 0xda8be0abu); + SCE->REG_74H = 0x00000008u; + SCE->REG_04H = 0x00000513u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_p_func102(0xe069ddfdu, 0x5f466981u, 0x494caa8au, 0xc542b9fdu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p21.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c new file mode 100644 index 000000000..8edcbe80e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p26.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_FwIntegrityCheck(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002601u; + SCE->REG_108H = 0x00000000u; + SCE->REG_13CH = 0x00000202u; + HW_SCE_p_func102(0xe8e880e8u, 0xe878ca41u, 0x69b6222du, 0x05286da4u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p26.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c new file mode 100644 index 000000000..90a2fa316 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29a.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func101(0x8088b49eu, 0x287d03e4u, 0x7eb933fau, 0xf28efb78u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29a.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c new file mode 100644 index 000000000..12594caeb --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29f.c @@ -0,0 +1,232 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168u; + SCE->REG_E0H = 0x80020100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580u; + SCE->REG_ECH = 0x0000007Fu; + SCE->REG_ECH = 0x0000b5a0u; + SCE->REG_ECH = 0xFFFFFF00u; + SCE->REG_ECH = 0x0c0029a9u; + SCE->REG_ECH = 0x04a02988u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xfe06d472u, 0x69cf4b13u, 0x7a562175u, 0x8da35523u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x12e1a862u, 0x8ae14d30u, 0x4731fe0bu, 0x84935df2u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409u; + SCE->REG_ECH = 0x00036800u; + SCE->REG_ECH = 0x08008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x6e99cd58u, 0xb62fe0d1u, 0x3716c8d1u, 0x1d656d8eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x6af5fab4u, 0x61f52c93u, 0x79227bf9u, 0xaee63054u); + SCE->REG_A4H = 0x00000885u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00004813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xb0489486u, 0x0908e3b3u, 0x61d62485u, 0x6753ec82u); + } + SCE->REG_104H = 0x00000164u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100u; + SCE->REG_00H = 0x0000580bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000000u; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x50b775adu, 0xb5496f3eu, 0xb8bdee5du, 0x600352ffu); + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x000087b5u; + SCE->REG_00H = 0x00001513u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_p_func102(0x86f4482du, 0x6d4f5eceu, 0x9a8b3afdu, 0xe6b404bbu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c new file mode 100644 index 000000000..97f7765df --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29i.c @@ -0,0 +1,401 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002901u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x14acce85u, 0xe0e82b06u, 0x325e8e2bu, 0x080c3070u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x6632700eu, 0x54bb2b0au, 0x0628c928u, 0x67a53130u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029u); + HW_SCE_p_func101(0x1d5278e5u, 0xa5f75927u, 0xbe17b68bu, 0xe94b042du); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000005u; + HW_SCE_p_func101(0xe901524bu, 0x3472aa7bu, 0xaba040b0u, 0xa105b27bu); + } + else + { + SCE->REG_ECH = 0x00003547u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029u); + HW_SCE_p_func101(0x5de8814fu, 0x0934c569u, 0x807e2b3du, 0x9714458eu); + HW_SCE_p_func068(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x2a46c04bu; + HW_SCE_p_func101(0xc33a264eu, 0x5c158979u, 0xd4fbbf71u, 0xd47008abu); + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029u); + HW_SCE_p_func101(0x41acb932u, 0x1a93d263u, 0x1040891fu, 0x85c5664eu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xd177a4d2u, 0x55fd89a4u, 0x4101c1d1u, 0xdbacd9feu); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x7c240052u, 0x386c9704u, 0xb361b7ffu, 0x1e4f00bfu); + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x00ff0000u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00120000u; + SCE->REG_ECH = 0x1000d3c0u; + SCE->REG_ECH = 0x3800d80fu; + SCE->REG_ECH = 0x2000d3c1u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x000000feu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x1000d3c2u; + SCE->REG_ECH = 0x38008bc0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00003540u; + SCE->REG_ECH = 0x00003561u; + SCE->REG_ECH = 0x00003582u; + SCE->REG_ECH = 0x000035a3u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000029u); + HW_SCE_p_func101(0x068dd838u, 0xf01d1660u, 0x2496a07du, 0x5528979bu); + HW_SCE_p_func059(); + HW_SCE_p_func100(0x85c33db3u, 0xfaf76717u, 0x874d3287u, 0x50161587u); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_E0H = 0x80040080u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x7dac9b7fu, 0x2a43d5c2u, 0x2af22cbeu, 0x0b247357u); + } + HW_SCE_p_func100(0x8bff74d4u, 0x226b6052u, 0x135a49e1u, 0xaf348c2bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x66eabf73u, 0xf41d1e94u, 0xf9a72548u, 0x06165eacu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00005113u; + SCE->REG_74H = 0x00001000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000354u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_74H = 0x00000002u; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29i_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c new file mode 100644 index 000000000..4b72cf1d3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29t.c @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29t.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c new file mode 100644 index 000000000..fc4621970 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p29u.c @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xd135b74du, 0x36d11479u, 0x00318697u, 0xeebc1beeu); + SCE->REG_00H = 0x80007100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x000087b6u; + SCE->REG_C4H = 0x00000886u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_p_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x77860a67u, 0xe59ac361u, 0x8fe185ddu, 0xc14fe253u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p29u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c new file mode 100644 index 000000000..1e2e4a30d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p2b.c @@ -0,0 +1,2301 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002b01u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x8c22ebc6u, 0xbac7b812u, 0x923c6843u, 0xf8ce1439u); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x94583792u, 0x24e30c80u, 0x32f50786u, 0x671c03ecu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01080c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_ECH = 0x00000a31u; + for(kLoop = 0; kLoop < MAX_CNT; kLoop = kLoop + 1) + { + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00003043u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00002f57u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00030005u); + SCE->REG_100H = change_endian_long(0x0007000bu); + SCE->REG_100H = change_endian_long(0x000d0011u); + SCE->REG_100H = change_endian_long(0x00130017u); + SCE->REG_100H = change_endian_long(0x001d001fu); + SCE->REG_100H = change_endian_long(0x00250029u); + SCE->REG_100H = change_endian_long(0x002b002fu); + SCE->REG_100H = change_endian_long(0x003b003du); + SCE->REG_100H = change_endian_long(0x00430047u); + SCE->REG_100H = change_endian_long(0x0049004fu); + SCE->REG_100H = change_endian_long(0x00530059u); + SCE->REG_100H = change_endian_long(0x00610065u); + SCE->REG_100H = change_endian_long(0x0067006bu); + SCE->REG_100H = change_endian_long(0x006d0071u); + SCE->REG_100H = change_endian_long(0x007f0083u); + SCE->REG_100H = change_endian_long(0x0089008bu); + SCE->REG_100H = change_endian_long(0x00950097u); + SCE->REG_100H = change_endian_long(0x009d00a3u); + SCE->REG_100H = change_endian_long(0x00a700adu); + SCE->REG_100H = change_endian_long(0x00b300b5u); + SCE->REG_100H = change_endian_long(0x00bf00c1u); + SCE->REG_100H = change_endian_long(0x00c500c7u); + SCE->REG_100H = change_endian_long(0x00d300dfu); + SCE->REG_100H = change_endian_long(0x00e300e5u); + SCE->REG_100H = change_endian_long(0x00e900efu); + SCE->REG_100H = change_endian_long(0x00f100fbu); + SCE->REG_100H = change_endian_long(0x01010107u); + SCE->REG_100H = change_endian_long(0x010d010fu); + SCE->REG_100H = change_endian_long(0x01150119u); + SCE->REG_100H = change_endian_long(0x011b0125u); + SCE->REG_100H = change_endian_long(0x01330137u); + SCE->REG_100H = change_endian_long(0x0139013du); + SCE->REG_100H = change_endian_long(0x014b0151u); + SCE->REG_100H = change_endian_long(0x015b015du); + SCE->REG_100H = change_endian_long(0x01610167u); + SCE->REG_100H = change_endian_long(0x016f0175u); + SCE->REG_100H = change_endian_long(0x017b017fu); + SCE->REG_100H = change_endian_long(0x0185018du); + SCE->REG_100H = change_endian_long(0x01910199u); + SCE->REG_100H = change_endian_long(0x01a301a5u); + SCE->REG_100H = change_endian_long(0x01af01b1u); + SCE->REG_100H = change_endian_long(0x01b701bbu); + SCE->REG_100H = change_endian_long(0x01c101c9u); + SCE->REG_100H = change_endian_long(0x01cd01cfu); + SCE->REG_100H = change_endian_long(0x01d301dfu); + SCE->REG_100H = change_endian_long(0x01e701ebu); + SCE->REG_100H = change_endian_long(0x01f301f7u); + SCE->REG_100H = change_endian_long(0x01fd0000u); + SCE->REG_ECH = 0x000008c6u; + SCE->REG_00H = 0x00000343u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x80b00006u; + SCE->REG_00H = 0x000083c3u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x009f0001u; + HW_SCE_p_func100(0x7e5acf8bu, 0xd2737edau, 0x4eae0493u, 0x1a30791cu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000d01fu; + SCE->REG_E0H = 0x81040000u; + SCE->REG_00H = 0x00003813u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop = 0; iLoop < 24; iLoop = iLoop + 4) + { + HW_SCE_p_func100(0x07a1fbc9u, 0xe02e1b04u, 0xfe51796bu, 0x3e56e547u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xd2b54d13u, 0xf1bac9dbu, 0x985665fcu, 0x4686ee7du); + } + HW_SCE_p_func100(0x07a1fbc9u, 0xe02e1b04u, 0xfe51796bu, 0x3e56e547u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000d060u; + SCE->REG_E0H = 0x81040000u; + SCE->REG_00H = 0x00003813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000011u; + SCE->REG_104H = 0x00001f57u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xB51EB851u); + SCE->REG_100H = change_endian_long(0xEB851EB8u); + SCE->REG_100H = change_endian_long(0x51EB851Eu); + SCE->REG_100H = change_endian_long(0xB851EB85u); + SCE->REG_100H = change_endian_long(0x1EB851EBu); + SCE->REG_100H = change_endian_long(0x851EB851u); + SCE->REG_100H = change_endian_long(0xEB851EB8u); + SCE->REG_100H = change_endian_long(0x51EB851Eu); + SCE->REG_100H = change_endian_long(0xB851EB85u); + SCE->REG_100H = change_endian_long(0x1EB851EBu); + SCE->REG_100H = change_endian_long(0x851EB851u); + SCE->REG_100H = change_endian_long(0xEB851EB8u); + SCE->REG_100H = change_endian_long(0x51EB851Eu); + SCE->REG_100H = change_endian_long(0xB851EB85u); + SCE->REG_100H = change_endian_long(0x1EB851EBu); + SCE->REG_100H = change_endian_long(0x851EB851u); + SCE->REG_100H = change_endian_long(0xEB851EB8u); + SCE->REG_100H = change_endian_long(0x51EB851Eu); + SCE->REG_100H = change_endian_long(0xB851EB85u); + SCE->REG_100H = change_endian_long(0x1EB851EBu); + SCE->REG_100H = change_endian_long(0x851EB851u); + SCE->REG_100H = change_endian_long(0xEB851EB8u); + SCE->REG_100H = change_endian_long(0x51EB851Eu); + SCE->REG_100H = change_endian_long(0xB851EB85u); + SCE->REG_100H = change_endian_long(0x1EB851EBu); + SCE->REG_100H = change_endian_long(0x851EB851u); + SCE->REG_100H = change_endian_long(0xEB851EB8u); + SCE->REG_100H = change_endian_long(0x51EB851Eu); + SCE->REG_100H = change_endian_long(0xB851EB85u); + SCE->REG_100H = change_endian_long(0x1EB851EBu); + SCE->REG_100H = change_endian_long(0x851EB851u); + SCE->REG_100H = change_endian_long(0xEB851B5Cu); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xf2a4147au, 0x0eab872fu, 0x3dd27a2bu, 0x1960df16u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x2b6e9024u, 0x64c4b8b0u, 0xb11bfcd4u, 0xf8f01459u); + continue; + } + else + { + HW_SCE_p_func101(0xbce884a9u, 0xb4300625u, 0xeb8ed2e5u, 0x145cbbdau); + } + SCE->REG_ECH = 0x38008a20u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x1ff30c58u, 0x2c43ede7u, 0x51891153u, 0xc6f0919au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x491d7813u, 0x9669f2a6u, 0x8ab8a647u, 0xebc5b55fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001d91u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x512c888cu, 0xac3c9b30u, 0x350fde63u, 0xaae062a7u); + } + else + { + HW_SCE_p_func101(0xc1f2ef4fu, 0x557853acu, 0x59b8831bu, 0x4b149043u); + } + SCE->REG_2CH = 0x00000011u; + SCE->REG_104H = 0x00000357u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x10000000u); + SCE->REG_00H = 0x00003073u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x87807a30u, 0x9f5ca829u, 0xe1175f96u, 0x1a9e6e75u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x6e42246au, 0x0051e8dcu, 0x3afb2da8u, 0xfc5b0241u); + continue; + } + else + { + HW_SCE_p_func101(0xc6d10669u, 0x9f4ff89du, 0x8038e04au, 0x9a3e17b0u); + } + } + else + { + HW_SCE_p_func101(0x07901e4cu, 0x0cebe917u, 0x0f834a0eu, 0x9f2d080eu); + } + SCE->REG_ECH = 0x000008c6u; + SCE->REG_ECH = 0x0000094au; + for(iLoop = 0; iLoop < 96; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x01003906u; + SCE->REG_ECH = 0x00002cc0u; + SCE->REG_ECH = 0x00002cc0u; + SCE->REG_E0H = 0x81010100u; + SCE->REG_00H = 0x0000307fu; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00003807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00004006u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x85dde662u, 0xd8fc3123u, 0x89de60c8u, 0x07d5ef2eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x0000d140u; + HW_SCE_p_func101(0x28a65192u, 0xe2a959dbu, 0xd43404eau, 0x7339fd84u); + break; + } + else + { + HW_SCE_p_func101(0x11a06545u, 0x32ad1e6fu, 0xdeb595cdu, 0xe97bc932u); + } + } + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x11867603u, 0x6f83bc5au, 0xaa875c8du, 0x12f9e1ecu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0xa0c54035u, 0xdbc1038cu, 0x6dffe9ffu, 0x22939bb3u); + continue; + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x0000307fu; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000057u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00010001u); + SCE->REG_24H = 0x00004006u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x7c533ae2u, 0x000734a8u, 0x356810bau, 0x487c1ecfu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0xa64df750u, 0x1eacebc9u, 0xa9607bc6u, 0xea154560u); + } + else + { + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000189u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0x79f5b90au, 0xd7922a5au, 0xac0169c2u, 0x03577a52u); + SCE->REG_18H = 0x00000004u; + SCE->REG_38H = 0x00004080u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000044d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x8a4e89beu, 0xad785403u, 0x03489702u, 0x2497f830u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x0c4d57c7u, 0x3f5c6c0fu, 0x0a22b208u, 0xc6301377u); + continue; + } + SCE->REG_24H = 0x000098d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x80a0000au; + SCE->REG_00H = 0x00008383u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b560u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_B0H = 0x00000700u; + SCE->REG_A4H = 0x42e0873fu; + SCE->REG_00H = 0x00001383u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_A4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_A4H = 0x400009cdu; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x38008a20u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xf96cb05eu, 0x7a810f51u, 0x46e8fa5eu, 0x812236d7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_7CH = 0x00000021u; + SCE->REG_00H = 0x00005113u; + SCE->REG_74H = 0x00000004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x87016245u, 0x5e83f673u, 0x602e7aebu, 0xeb5683b0u); + } + else + { + SCE->REG_7CH = 0x00000041u; + SCE->REG_00H = 0x00005113u; + SCE->REG_74H = 0x00000004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x239b33b8u, 0xd6eb409fu, 0x93df7b47u, 0xb35986dcu); + } + HW_SCE_p_func100(0xeaa4de27u, 0x5c6570b3u, 0x23239a44u, 0xb259bd4du); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000929u; + SCE->REG_ECH = 0x0000b4c0u; + SCE->REG_ECH = 0x000000fcu; + SCE->REG_ECH = 0x00003906u; + SCE->REG_ECH = 0x00008d00u; + SCE->REG_ECH = 0xfffffffeu; + SCE->REG_ECH = 0x00003d06u; + SCE->REG_ECH = 0x00000908u; + for(iLoop = 0; iLoop < 32; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x000038e6u; + SCE->REG_ECH = 0x0000a8c0u; + SCE->REG_ECH = 0x00000004u; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 1) + { + SCE->REG_ECH = 0x38008900u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x11816907u; + SCE->REG_ECH = 0x38008900u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x10002d20u; + SCE->REG_ECH = 0x000168e7u; + } + } + SCE->REG_ECH = 0x00003549u; + SCE->REG_ECH = 0x0000a540u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_ECH = 0x0002694au; + SCE->REG_E0H = 0x81010140u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037eau; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_24H = 0x00000185u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000185u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x000033e0u; + HW_SCE_p_func101(0x25f7c21cu, 0xa58e2d37u, 0xc7d2c302u, 0x94a4950cu); + } + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func100(0x3ffbde47u, 0xdf842701u, 0x3ed2ea1fu, 0x92f4b6cdu); + SCE->REG_ECH = 0x00026d4au; + SCE->REG_ECH = 0x00002949u; + SCE->REG_E0H = 0x81010140u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037eau; + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_24H = 0x2000018du; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x000033e0u; + HW_SCE_p_func101(0xf2494d23u, 0x208dc9cfu, 0x9eaacfe5u, 0xe3122179u); + } + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func100(0xb09a35c9u, 0x5d8bb3e6u, 0xfc920928u, 0x6f246efau); + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000a52u; + SCE->REG_24H = 0x00006404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010160u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop = 0; iLoop < S_RAM[0]; iLoop = iLoop + 1) + { + SCE->REG_2CH = 0x00000010u; + for(jLoop = 0; jLoop < 32; jLoop = jLoop + 4) + { + HW_SCE_p_func100(0x80f0c0afu, 0xb016844bu, 0xab5eb905u, 0x9689d197u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x615822e9u, 0xfce99d10u, 0xc52ef231u, 0xd71f309au); + } + HW_SCE_p_func100(0xad8720efu, 0x8c70ba5eu, 0xc306a7e5u, 0x8d3defeeu); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004u; + SCE->REG_38H = 0x00000c40u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x5025e1b2u, 0xe9c90814u, 0x20f9ebb3u, 0x8d9af69eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e40u; + HW_SCE_p_func101(0x400c3652u, 0x19b00af6u, 0x415d810du, 0x6580bbf1u); + } + else + { + HW_SCE_p_func100(0x87f0e1cbu, 0x06afd9adu, 0xc94c17ecu, 0xc9d9cfc0u); + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_E0H = 0x81010120u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0+1 + 0] = change_endian_long(SCE->REG_100H); + SCE->REG_ECH = 0x000037e9u; + for(jLoop = 0; jLoop < S_RAM[0+1]; jLoop = jLoop + 1) + { + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x8ec7a622u, 0xc2ecfd33u, 0x4596d1b1u, 0xdd384955u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (0u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e40u; + HW_SCE_p_func101(0xd4b47306u, 0x947e48e2u, 0xe08a050cu, 0x6baf7466u); + break; + } + else + { + SCE->REG_24H = 0x00004c0cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xe518ad9du, 0x5640af24u, 0x34eac94eu, 0x014d63edu); + } + } + SCE->REG_ECH = 0x38008a40u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x98765488u, 0x67b2035eu, 0x3880187bu, 0x02273ca1u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0xdbe391c8u, 0xe36886d3u, 0x44ecc41bu, 0x542e2e2du); + break; + } + else + { + HW_SCE_p_func101(0x624f8893u, 0xe40b8b49u, 0x8082da1au, 0xc20670a6u); + } + } + } + SCE->REG_ECH = 0x38000a4bu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xd67e7880u, 0xe9c8649eu, 0x28a2b1cau, 0xa1387d95u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_ECH = 0x00002e20u; + SCE->REG_ECH = 0x38008a20u; + SCE->REG_ECH = 0x00000002u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xc0f8142au, 0x43ece9e1u, 0xe5a42c4cu, 0x95e232e0u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x144c6c66u, 0x8a422809u, 0xaca7266eu, 0xcd70f9f0u); + break; + } + else + { + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x817dcc5du, 0x7630144fu, 0x631df7e6u, 0xd908d8c8u); + } + } + else + { + HW_SCE_p_func101(0xdbba2aa6u, 0xbe5543d3u, 0xd39ab5a0u, 0x758fd189u); + } + } + } + SCE->REG_ECH = 0x38008a20u; + SCE->REG_ECH = 0x00000002u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x43009d9cu, 0xb0aaa3a1u, 0x29a32de2u, 0x777a8077u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xdcc9ddc5u, 0x77d8925bu, 0xe4eec2cfu, 0x8a66a099u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + HW_SCE_p_func100(0xc897604bu, 0x7ea24896u, 0x6b2b64f0u, 0x4757ffa2u); + SCE->REG_ECH = 0x0000b5c0u; + SCE->REG_ECH = 0x00010001u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x42e087bfu; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_04H = 0x00000202u; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + HW_SCE_p_func100(0xf04437edu, 0xd2f2aa45u, 0x8905e13bu, 0x87f50a93u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x400009cdu; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + while(1) + { + SCE->REG_24H = 0x00008006u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x02a10e8bu, 0x345b9ec9u, 0x69707df5u, 0xf1d88be4u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func101(0x9493fa8fu, 0xc27e5124u, 0x25f9ca01u, 0x5acd770du); + break; + } + else + { + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000d0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x0c4f97b0u, 0x9a3e48e8u, 0x89031f6bu, 0x5b814724u); + } + } + SCE->REG_24H = 0x000094d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000c002u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000000u; + SCE->REG_24H = 0x0000b80au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x000030ffu; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000057u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00010001u); + SCE->REG_2CH = 0x00000002u; + SCE->REG_24H = 0x0000c002u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_E0H = 0x800100c0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500u; + SCE->REG_ECH = 0x00010001u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + while(1) + { + HW_SCE_p_func100(0x2601c365u, 0x86269c2cu, 0x8bd2d673u, 0x7fd6e24eu); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x628d9e05u, 0xdbb7daa3u, 0xa04bf479u, 0x0ed0c908u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01090c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_ECH = 0x0000094au; + SCE->REG_E0H = 0x80c0000au; + SCE->REG_00H = 0x00018303u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x91cef570u, 0x5ddcb017u, 0x1a28922fu, 0xde55c6f6u); + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x42e097bfu; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + SCE->REG_04H = 0x00000202u; + for (iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + HW_SCE_p_func100(0x85c5fb6eu, 0xd3462e3cu, 0xefde4039u, 0x337f35b6u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x400019cdu; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_00H = 0x0000301fu; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x810100c0u; + SCE->REG_00H = 0x00003807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000301fu; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x81010100u; + SCE->REG_00H = 0x00003807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_2CH = 0x00000000u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c002u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00003506u; + SCE->REG_E0H = 0x800100c0u; + SCE->REG_00H = 0x0000031fu; + SCE->REG_2CH = 0x0000002cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x380088c0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x84072e81u, 0xb4707fe1u, 0x210e80f2u, 0x478f4a77u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00003f61u; + SCE->REG_B0H = 0x00000f00u; + SCE->REG_A4H = 0x42f087bfu; + SCE->REG_00H = 0x00013103u; + SCE->REG_2CH = 0x00000014u; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x4d7de79eu, 0x7aee29b9u, 0xfdb1ad36u, 0xe56bb109u); + break; + } + else + { + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_00H = 0x00003083u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x0000880eu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00003f62u; + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x42f097bfu; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + for (iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x400017bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000094au; + SCE->REG_E0H = 0x81c0000au; + SCE->REG_00H = 0x00013803u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xd78e57d3u, 0x88d3ecf5u, 0x786fbc37u, 0x62fe7edfu); + } + } + SCE->REG_ECH = 0x00007c06u; + SCE->REG_1CH = 0x00602000u; + SCE->REG_A4H = 0x400007bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop + 0]; + SCE->REG_100H = S_HEAP[iLoop + 1]; + SCE->REG_100H = S_HEAP[iLoop + 2]; + SCE->REG_100H = S_HEAP[iLoop + 3]; + SCE->REG_A4H = 0x00800c45u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xe8af30a3u, 0x68c2064eu, 0x712f8903u, 0xf66d4c14u); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0xd6fee8b4u, 0xfeb8e1cfu, 0xec897771u, 0x8805760eu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01090c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x7a264cd4u, 0x63f846bdu, 0x4e808fcau, 0xacfd971fu); + SCE->REG_D0H = 0x00000f00u; + SCE->REG_C4H = 0x42e097bfu; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + SCE->REG_04H = 0x00000202u; + for (iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + } + HW_SCE_p_func100(0x771da7e3u, 0x9729dd62u, 0xae475f17u, 0x8047367cu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x400019cdu; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_HEAP[iLoop + 0] = SCE->REG_100H; + S_HEAP[iLoop + 1] = SCE->REG_100H; + S_HEAP[iLoop + 2] = SCE->REG_100H; + S_HEAP[iLoop + 3] = SCE->REG_100H; + HW_SCE_p_func100(0x34fa079fu, 0x31773c42u, 0xb11338adu, 0x91df1e11u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_24H = 0x0000b8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000002u; + SCE->REG_24H = 0x00007b0au; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0xfcbf0001u; + SCE->REG_24H = 0x0000c8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002bu); + HW_SCE_p_func101(0x04fca964u, 0x90725814u, 0x17b38229u, 0xc9c8f0b5u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000002bu); + HW_SCE_p_func101(0xea8d2962u, 0x23b0c731u, 0x02063f7bu, 0x360e6545u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xfb3eaadcu, 0x1b4c926bu, 0x41d898b5u, 0x5d237607u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0x15b39e7du, 0xbc172d9fu, 0x0dbd45d3u, 0x9d30cd21u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_04H = 0x00000202u; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xea7a2df8u, 0x6d487225u, 0x96637959u, 0xd7948d95u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08884u; + SCE->REG_E0H = 0x810101c0u; + SCE->REG_00H = 0x00002807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[65] = SCE->REG_100H; + OutData_PubKeyIndex[66] = SCE->REG_100H; + OutData_PubKeyIndex[67] = SCE->REG_100H; + OutData_PubKeyIndex[68] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0xf17df3bdu, 0xa237d4c4u, 0x31891948u, 0x398bde44u); + SCE->REG_18H = 0x00000004u; + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00e087b7u; + SCE->REG_04H = 0x00000202u; + for(iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PubKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x77aecc1au, 0xc4e61c3cu, 0x32de60c5u, 0xc40e7285u); + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000010u); + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[133] = SCE->REG_100H; + OutData_PubKeyIndex[134] = SCE->REG_100H; + OutData_PubKeyIndex[135] = SCE->REG_100H; + OutData_PubKeyIndex[136] = SCE->REG_100H; + HW_SCE_p_func100(0xb77e9d11u, 0x739cdbb4u, 0xb03798c4u, 0x99c1079bu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000fdu); + HW_SCE_p_func101(0x394f8441u, 0xfba13dc3u, 0x22815382u, 0xff49cec6u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000000du; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000fdu); + HW_SCE_p_func101(0x66692d56u, 0x5e6c77cau, 0xed7b634fu, 0x905615c9u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x35fa4854u, 0xcef1ec09u, 0xab49a001u, 0x599a6c24u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0x06f73d5fu, 0x532f17d5u, 0x54dc5af0u, 0x6eee362du); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x02e087b7u; + SCE->REG_04H = 0x00000202u; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xbecdb75cu, 0xbca8b94eu, 0x0b91504cu, 0xc1f7fc25u); + SCE->REG_00H = 0x00012103u; + SCE->REG_104H = 0x00000031u; + SCE->REG_B0H = 0x00000f00u; + SCE->REG_A4H = 0x42f097bfu; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00e087b7u; + SCE->REG_04H = 0x00000202u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[68]; + SCE->REG_100H = S_HEAP[69]; + SCE->REG_100H = S_HEAP[70]; + SCE->REG_100H = S_HEAP[71]; + for (iLoop = 64; iLoop < 124 ; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[iLoop+8 + 0]; + SCE->REG_100H = S_HEAP[iLoop+8 + 1]; + SCE->REG_100H = S_HEAP[iLoop+8 + 2]; + SCE->REG_100H = S_HEAP[iLoop+8 + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + SCE->REG_A4H = 0x400017bdu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_HEAP[132]; + SCE->REG_100H = S_HEAP[133]; + SCE->REG_100H = S_HEAP[134]; + SCE->REG_100H = S_HEAP[135]; + SCE->REG_A4H = 0x00800c45u; + SCE->REG_00H = 0x00001113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x9ac4e83au, 0xf48e1713u, 0xe59c8f74u, 0xb22f3529u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00e087b7u; + SCE->REG_04H = 0x00000202u; + for(iLoop=128; iLoop<192; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[iLoop+1 + 0] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 1] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 2] = SCE->REG_100H; + OutData_PrivKeyIndex[iLoop+1 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x36d14ec8u, 0xb8c807a7u, 0x74d82cfdu, 0x7a62a60bu); + SCE->REG_104H = 0x00000352u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000030u); + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[193] = SCE->REG_100H; + OutData_PrivKeyIndex[194] = SCE->REG_100H; + OutData_PrivKeyIndex[195] = SCE->REG_100H; + OutData_PrivKeyIndex[196] = SCE->REG_100H; + HW_SCE_p_func102(0x772f0564u, 0x25d380e3u, 0x92a87dc9u, 0x37b7f321u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p2b_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c new file mode 100644 index 000000000..fbf460a87 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32a.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func101(0xbb74c4ecu, 0xf373c42au, 0xcf167a41u, 0x01ba60d7u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32a.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c new file mode 100644 index 000000000..dfabe2dd2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32f.c @@ -0,0 +1,301 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168u; + SCE->REG_E0H = 0x80020100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580u; + SCE->REG_ECH = 0x0000007Fu; + SCE->REG_ECH = 0x0000b5a0u; + SCE->REG_ECH = 0xFFFFFF00u; + SCE->REG_ECH = 0x0c0029a9u; + SCE->REG_ECH = 0x04a02988u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x34202beau; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xe345fde3u, 0x2356cb88u, 0xa560904eu, 0xdbc1d8feu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf54b1f76u, 0x2f5a2aafu, 0xb19cb855u, 0xc7b45181u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409u; + SCE->REG_ECH = 0x00036800u; + SCE->REG_ECH = 0x08008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x2334eeedu, 0xa7dc4fb9u, 0x14fdd072u, 0x6a73430bu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00000885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_D0H = 0x00000020u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_00H = 0x00007113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0xc455334au, 0xb086101bu, 0x21bdd270u, 0x96aa95c4u); + SCE->REG_C4H = 0x00000885u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000213u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xa64451e5u, 0xd6dfce91u, 0x9ea12341u, 0xdb8910d2u); + } + SCE->REG_104H = 0x00000164u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100u; + SCE->REG_00H = 0x0000580bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000000u; + SCE->REG_C4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x00000020u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_00H = 0x00002513u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beau; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_104H = 0x00000362u; + SCE->REG_C4H = 0x00050805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x00000000u; + HW_SCE_p_func100(0xffff5ca7u, 0x6a8cdc67u, 0x10a7aad0u, 0xbe4102d8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x21114e57u, 0x64bc06a8u, 0x18c1a96eu, 0xf12e134eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x54f55d1cu, 0x159ecbc9u, 0x3f90b5c6u, 0x9629a939u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c new file mode 100644 index 000000000..5b16e3114 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32i.c @@ -0,0 +1,516 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003201u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000002u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x717c7867u, 0x54b3db59u, 0xf733f6adu, 0x08933694u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xb32b9023u, 0x24f2ee1au, 0x9b53c05au, 0x9a3965beu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032u); + HW_SCE_p_func101(0x5ac26175u, 0x3e3950b9u, 0x3a17208du, 0xacd9c2fcu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000005u; + HW_SCE_p_func101(0xfc2e4213u, 0xa406243cu, 0x89b4493cu, 0xd459c7bau); + } + else + { + SCE->REG_ECH = 0x00003547u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032u); + HW_SCE_p_func101(0x3136f03du, 0x13cefeacu, 0x38471846u, 0xb5290306u); + HW_SCE_p_func068(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0146c04bu; + HW_SCE_p_func101(0x5d699af5u, 0x8e5d7ed4u, 0x709a8d2bu, 0x2ee32018u); + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032u); + HW_SCE_p_func101(0x7a5351fdu, 0x60372278u, 0x4f1ff6c5u, 0xa75f4137u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0xd6326ea8u, 0x43f9f29fu, 0xcd13f106u, 0x80e8934bu); + } + else + { + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x34d06864u, 0xfcdeb896u, 0x6bf199cau, 0x8dd419d7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x00ff0000u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00120000u; + SCE->REG_ECH = 0x1000d3c0u; + SCE->REG_ECH = 0x3800d80eu; + SCE->REG_ECH = 0x2000d3c1u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x000000feu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x1000d3c2u; + SCE->REG_ECH = 0x38008bc0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00003540u; + SCE->REG_ECH = 0x00003561u; + SCE->REG_ECH = 0x00003582u; + SCE->REG_ECH = 0x000035a3u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000032u); + HW_SCE_p_func101(0xfdbb289cu, 0xb29b7e31u, 0x8abf765cu, 0x1f97cc5eu); + HW_SCE_p_func059(); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_E0H = 0x80040080u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xa077dacau, 0x4e0be9edu, 0x33810a24u, 0x5b0571bbu); + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000005u); + HW_SCE_p_func101(0x9b614c1au, 0xbb50c8ccu, 0xaed5668du, 0x7f6205dau); + HW_SCE_p_func068(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0195f71du; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000005u); + HW_SCE_p_func101(0xae0bda23u, 0x6d486cb9u, 0x4cd9b7bbu, 0xc741ba11u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80040080u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xa7c07c76u, 0xc417f413u, 0x41723116u, 0x10163c9fu); + } + } + HW_SCE_p_func100(0xf6afb1f0u, 0x49b85b75u, 0x1de05501u, 0x9a451cf9u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xb07a6c46u, 0x392fbf2cu, 0x101414cfu, 0x13d1fd8au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x4bc6b123u, 0x27352405u, 0xd72a388eu, 0x427382d1u); + SCE->REG_E0H = 0x81040000u; + SCE->REG_C4H = 0x00080805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00005213u; + SCE->REG_74H = 0x00001000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000354u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_74H = 0x00000002u; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32i_r2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c new file mode 100644 index 000000000..774787274 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32t.c @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x00000020u; + SCE->REG_C4H = 0x00008734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32t.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c new file mode 100644 index 000000000..e675059bb --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p32u.c @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0xee3369f2u, 0x4cc24009u, 0xa590fb85u, 0x1e4adbfau); + SCE->REG_00H = 0x80007100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000886u; + SCE->REG_D0H = 0x00000020u; + SCE->REG_C4H = 0x000087b6u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_p_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x00387a92u, 0xed4c3d7du, 0x8509db59u, 0x6fa710fbu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p32u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c new file mode 100644 index 000000000..4726e3859 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34a.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func101(0x65222c83u, 0xcd363485u, 0xa00084afu, 0x0097f3ddu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p34a.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c new file mode 100644 index 000000000..fa240ecd4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34f.c @@ -0,0 +1,232 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168u; + SCE->REG_E0H = 0x80020100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580u; + SCE->REG_ECH = 0x0000007Fu; + SCE->REG_ECH = 0x0000b5a0u; + SCE->REG_ECH = 0xFFFFFF00u; + SCE->REG_ECH = 0x0c0029a9u; + SCE->REG_ECH = 0x04a02988u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xa2ab3ccbu, 0x3ea9b7f2u, 0x3b45fa5bu, 0xfac762d6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x777e8592u, 0x90e4b57au, 0x7f2ed30fu, 0x2e356c35u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409u; + SCE->REG_ECH = 0x00036800u; + SCE->REG_ECH = 0x08008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xe4e6cd10u, 0x3d0d8d18u, 0x895d69adu, 0xafeb01eau); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x3352beb1u, 0x697d6205u, 0x55fced5eu, 0x0fa0b58fu); + SCE->REG_A4H = 0x00000885u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00004813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0xa76d4578u, 0x5bffb46eu, 0xd9142159u, 0x21b1a27eu); + } + SCE->REG_104H = 0x00000164u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100u; + SCE->REG_00H = 0x0000580bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000000u; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x49d5260eu, 0x6eabc9cdu, 0x9f44122du, 0x2f7a78a6u); + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x000087b5u; + SCE->REG_00H = 0x00001513u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000113u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_DataT[0] = SCE->REG_100H; + OutData_DataT[1] = SCE->REG_100H; + OutData_DataT[2] = SCE->REG_100H; + OutData_DataT[3] = SCE->REG_100H; + HW_SCE_p_func102(0x213da8b3u, 0x9303aa36u, 0x5b9260beu, 0x4508a912u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p34f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c new file mode 100644 index 000000000..ffb1c05c5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34i.c @@ -0,0 +1,240 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003401u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000034u); + HW_SCE_p_func101(0x4f1e8043u, 0x4502e53fu, 0x43702881u, 0x0158ec3du); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000034u); + HW_SCE_p_func101(0xb24b7cd7u, 0xdafe0b5cu, 0xfc302551u, 0x142780eeu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x3dadf477u, 0xaa79b613u, 0xe024c3e0u, 0x6739d560u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x0dc0d94du, 0x916dcb2au, 0x0abb86a0u, 0x6c1b2403u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x653cab86u, 0x62f0afbeu, 0x0e891ff6u, 0x6f16d588u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x8bbd7bcbu, 0xb89b00efu, 0xa480cd72u, 0xbc8671cfu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00005113u; + SCE->REG_74H = 0x00001000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000354u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_74H = 0x00000002u; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p34i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c new file mode 100644 index 000000000..8d1531a24 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34t.c @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_A4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000051u; + SCE->REG_B0H = 0x00000020u; + SCE->REG_A4H = 0x00008734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p34t.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c new file mode 100644 index 000000000..0a5cb67c1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p34u.c @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x94658c4fu, 0xe13a0b2fu, 0x5b75a986u, 0xebbaa242u); + SCE->REG_00H = 0x80007100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000020u; + SCE->REG_A4H = 0x000087b6u; + SCE->REG_C4H = 0x00000886u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_p_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x5b8ac4aau, 0x7d383cd9u, 0x1d09e873u, 0x3f17373fu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p34u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c new file mode 100644 index 000000000..5d5e1631e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36a.c @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x000000b4u; + for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataA[iLoop + 0]; + SCE->REG_100H = InData_DataA[iLoop + 1]; + SCE->REG_100H = InData_DataA[iLoop + 2]; + SCE->REG_100H = InData_DataA[iLoop + 3]; + } + SCE->REG_104H = 0x00000000u; + HW_SCE_p_func101(0x7b602332u, 0xc4339367u, 0xf9d25d4bu, 0x632c076eu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p36a.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c new file mode 100644 index 000000000..3e3e0609d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36f.c @@ -0,0 +1,301 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_104H = 0x00000168u; + SCE->REG_E0H = 0x80020100u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_TextLen[1]; + SCE->REG_ECH = 0x0000b580u; + SCE->REG_ECH = 0x0000007Fu; + SCE->REG_ECH = 0x0000b5a0u; + SCE->REG_ECH = 0xFFFFFF00u; + SCE->REG_ECH = 0x0c0029a9u; + SCE->REG_ECH = 0x04a02988u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataTLen[0]; + SCE->REG_ECH = 0x38008940u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_ECH = 0x34202beau; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x18cbbc67u, 0xb6f57f2eu, 0xde3361b3u, 0x6adcdf24u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x4f0d908du, 0xf301e51bu, 0xcf69e9efu, 0x651a3635u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003409u; + SCE->REG_ECH = 0x00036800u; + SCE->REG_ECH = 0x08008c00u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x5d383a10u, 0x51e5e005u, 0x791700abu, 0x579427d6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00000885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_D0H = 0x40000020u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_00H = 0x00007113u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be0u; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + HW_SCE_p_func100(0x6c205451u, 0x3598ed83u, 0x6671b2c1u, 0x5e0c223du); + SCE->REG_C4H = 0x00000885u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000213u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + HW_SCE_p_func101(0x21068dd5u, 0xaff8800bu, 0x4dd41e59u, 0x4790d650u); + } + SCE->REG_104H = 0x00000164u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataALen[0]; + SCE->REG_100H = InData_DataALen[1]; + SCE->REG_E0H = 0x81020100u; + SCE->REG_00H = 0x0000580bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000000u; + SCE->REG_C4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x40000020u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_00H = 0x00002513u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bffu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002beau; + SCE->REG_ECH = 0x12003c3fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_104H = 0x00000362u; + SCE->REG_C4H = 0x00050805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_DataT[0]; + SCE->REG_100H = InData_DataT[1]; + SCE->REG_100H = InData_DataT[2]; + SCE->REG_100H = InData_DataT[3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x81840001u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x00000000u; + HW_SCE_p_func100(0xa74fff9au, 0xd3933c3bu, 0x43f4b2ceu, 0x4a7e5283u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x2e4778e7u, 0x1e5f555bu, 0x893c4abfu, 0x7241f880u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x7a084c94u, 0x6fda4b16u, 0xef812686u, 0xb0c16c35u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p36f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c new file mode 100644 index 000000000..ff463a376 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36i.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00003601u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000036u); + HW_SCE_p_func101(0x6e47a7bcu, 0x4d4dda09u, 0xd4fd37e3u, 0x4e9d6be8u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000036u); + HW_SCE_p_func101(0x08681549u, 0x364e6a94u, 0xce358c02u, 0x20f838b3u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008223u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x8e70b58cu, 0xd001ee91u, 0x5ae7a0b3u, 0xf136c4d9u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xa9e6f3aeu, 0xacd0bfaau, 0xe005a0fdu, 0xae5b258au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xb06163bdu, 0x5e4525d5u, 0x8415ba90u, 0x28857abbu); + SCE->REG_E0H = 0x81080000u; + SCE->REG_C4H = 0x00080805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x2ed25b81u, 0x0831d289u, 0xc21be4dfu, 0xbe708663u); + SCE->REG_C4H = 0x00090805u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040080u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[3]; + SCE->REG_7CH = 0x00000001u; + SCE->REG_7CH = 0x00000041u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00008a84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00005213u; + SCE->REG_74H = 0x00001000u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_74H = 0x00000004u; + SCE->REG_104H = 0x00000354u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_74H = 0x00000002u; + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p36i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c new file mode 100644 index 000000000..310b113da --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36t.c @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_C4H = 0x00040805u; + SCE->REG_E0H = 0x81040080u; + SCE->REG_00H = 0x00002813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x00000020u; + SCE->REG_C4H = 0x00008734u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p36t.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c new file mode 100644 index 000000000..ef9b1836f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p36u.c @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func100(0x001e4f2bu, 0x3c22c7bau, 0x4a63c948u, 0x18076020u); + SCE->REG_00H = 0x80007100u; + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000886u; + SCE->REG_D0H = 0x40000020u; + SCE->REG_C4H = 0x000087b6u; + SCE->REG_04H = 0x0000c200u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT; iLoop = iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + HW_SCE_p_func200();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x07698af7u, 0xd862af5au, 0x4e5cb293u, 0x1d825a3fu); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p36u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c new file mode 100644 index 000000000..534b6bc32 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p40.c @@ -0,0 +1,356 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_LoadHukSub(uint32_t *InData_LC) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004001u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + HW_SCE_p_func048(InData_LC); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000009u; + SCE->REG_ECH = 0x34202801u; + SCE->REG_ECH = 0x20003401u; + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00602000u; +if (InData_LC[0] == 0x00000000) + { + SCE->REG_1CH = 0x00b80000u; + HW_SCE_p_func101(0xe83b7e4eu, 0xdb097f27u, 0xb31d59d5u, 0x0daab77bu); + } +else if (InData_LC[0] == 0x00000001) + { + SCE->REG_1CH = 0x00b00000u; + HW_SCE_p_func101(0x78659d26u, 0x860f5f45u, 0x80267e4eu, 0x1f70b510u); + } +else if (InData_LC[0] == 0x00000002) + { + SCE->REG_1CH = 0x00b10000u; + HW_SCE_p_func101(0x2751871bu, 0xe89c2f48u, 0xf573d4cfu, 0x115ecb07u); + } +else if (InData_LC[0] == 0x00000003) + { + SCE->REG_1CH = 0x00b20000u; + HW_SCE_p_func101(0xbba17e71u, 0xbc808154u, 0x1e078979u, 0x86405b9au); + } +else if (InData_LC[0] == 0x00000004) + { + SCE->REG_1CH = 0x00b30000u; + HW_SCE_p_func101(0x4f20b598u, 0xd0dabac4u, 0xc7ad0190u, 0x75198e1cu); + } +else if (InData_LC[0] == 0x00000005) + { + SCE->REG_1CH = 0x00b40000u; + HW_SCE_p_func101(0xf19a5f31u, 0x21feee6au, 0xce2fb686u, 0x6804e1f8u); + } +else if (InData_LC[0] == 0x00000006) + { + SCE->REG_1CH = 0x00b50000u; + HW_SCE_p_func101(0x0524bae4u, 0xa2bdb569u, 0x3882d45bu, 0x0c17e0a9u); + } +else if (InData_LC[0] == 0x00000007) + { + SCE->REG_1CH = 0x00b60000u; + HW_SCE_p_func101(0xa9029f34u, 0x03b9f72cu, 0x0c3dea38u, 0x2168dc2bu); + } +else if (InData_LC[0] == 0x00000008) + { + SCE->REG_1CH = 0x00b70000u; + HW_SCE_p_func101(0x370593d5u, 0xa06496acu, 0x346be3f9u, 0x4ab24229u); + } + else + { + SCE->REG_ECH = 0x38000c00u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func101(0x4ef037fcu, 0x717efbf1u, 0x95329c71u, 0x33958d8du); + } + HW_SCE_p_func100(0xc49e2b89u, 0x3ccaecb7u, 0xa622a807u, 0x78f51bbeu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x0c3811c9u, 0xb8dedefdu, 0xeb431a83u, 0xd5122286u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000352u; + SCE->REG_C4H = 0x000f3a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x7e2fdbffu); + SCE->REG_100H = change_endian_long(0xd4e34e49u); + SCE->REG_100H = change_endian_long(0x86044a47u); + SCE->REG_100H = change_endian_long(0x78ea77fbu); + HW_SCE_p_func100(0x5a22ea97u, 0xb775468eu, 0xc77479b3u, 0xa7c5d2eau); + SCE->REG_C4H = 0x20443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x20083e1cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01ea725du); + HW_SCE_p_func100(0xfbcffc6bu, 0xce9dd311u, 0x605e19c8u, 0xfe10bb07u); + SCE->REG_C4H = 0x20443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x20093e1cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x02ea725du); + SCE->REG_104H = 0x00000352u; + SCE->REG_C4H = 0x000f3a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x1201f0d2u); + SCE->REG_100H = change_endian_long(0x9fc1d562u); + SCE->REG_100H = change_endian_long(0x4f02fc25u); + SCE->REG_100H = change_endian_long(0x6b60ff19u); + HW_SCE_p_func100(0xba5d965cu, 0x54ecb6f4u, 0xf3e2d5bfu, 0xcf8889bcu); + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b5u; + SCE->REG_E8H = 0x80000000u; + SCE->REG_00H = 0x00002613u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00f087b5u; + SCE->REG_E8H = 0x80000004u; + SCE->REG_00H = 0x00002613u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xae1e176eu, 0x880b1b75u, 0x6486a9a3u, 0x9cf0492au); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x000001b0u; + SCE->REG_ECH = 0x00003c01u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + SCE->REG_E8H = 0x80000008u; + SCE->REG_00H = 0x00002613u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_C4H = 0x00800c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000251u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00448a04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019ee295u); + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x029ee295u); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x000001d0u; + SCE->REG_E0H = 0x80880001u; + SCE->REG_00H = 0x00008123u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xf779cdc0u, 0x8979d743u, 0x8cdcd58bu, 0xabca3852u); + SCE->REG_C4H = 0x20443a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x200c3e1cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0152db38u); + SCE->REG_C4H = 0x00440a0cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_C4H = 0x00000e9cu; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01f7370eu); + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x000001c0u; + SCE->REG_E0H = 0x80840001u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_13CH = 0x00000211u; + HW_SCE_p_func102(0xff71be6bu, 0xdfbc00b3u, 0xa5a52bdau, 0x8b9ab0edu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p40_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c new file mode 100644 index 000000000..56c2ffff4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47f.c @@ -0,0 +1,115 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x2567e134u, 0x1c59a254u, 0x33a91a4au, 0x06f2d769u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xaeef1b59u, 0xa2d2eaadu, 0x59797dcdu, 0x3d305810u); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x39200434u, 0x3a9b8bf3u, 0x9bd38d07u, 0xf8813cd9u); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xea6f2734u, 0xa16e75a5u, 0xe73f8298u, 0x686c805bu); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x160ec850u, 0x256044acu, 0x2e147e96u, 0xc4166693u); + } + HW_SCE_p_func100(0x1aee5930u, 0xbae62181u, 0x010b5253u, 0xf8837913u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x456c3ac1u, 0x66da1c4fu, 0xb41b43bcu, 0x951bd5f4u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x8984c019u, 0x50eb8683u, 0x6fdd4b33u, 0xe6447ca1u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c new file mode 100644 index 000000000..f24dcf907 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47i.c @@ -0,0 +1,371 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00004701u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_E0H = 0x80010000u; + SCE->REG_104H = 0x00000068u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x3000a800u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_ECH = 0x00010020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x3420a800u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xb52dabe4u, 0x204b14aau, 0xc2240b7du, 0x23a73aa2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047u); + HW_SCE_p_func101(0xd4e33cfeu, 0xd2687192u, 0x90dacf91u, 0x23025eabu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047u); + HW_SCE_p_func101(0x187b7158u, 0x36068296u, 0xc75b90d8u, 0x3c2e975fu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x5250cc11u, 0xb301ced7u, 0x9817c7a8u, 0x9bd7e48bu); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x50aac0e4u, 0x44f73738u, 0x16915f2fu, 0xb58af45eu); + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040040u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x000037e2u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x00ff0000u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x1000d3c0u; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_ECH = 0x1000b540u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x2000b540u; + SCE->REG_ECH = 0x0000000eu; + SCE->REG_ECH = 0x3800584au; + SCE->REG_ECH = 0x2000d3c1u; + SCE->REG_ECH = 0x000037e2u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x000000feu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x1000d3c2u; + SCE->REG_ECH = 0x38008bc0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x0000a800u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_ECH = 0x00003542u; + SCE->REG_ECH = 0x00003563u; + SCE->REG_ECH = 0x00003584u; + SCE->REG_ECH = 0x000035a5u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000047u); + HW_SCE_p_func101(0x777d2dd1u, 0x6efca390u, 0x2da7d617u, 0x6914cb47u); + HW_SCE_p_func059(); + HW_SCE_p_func100(0x1d35c958u, 0x8ab99b81u, 0x1fab250au, 0xeeb14dabu); + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x02f087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0xe1960594u, 0x2cad8339u, 0xefabb8bbu, 0x59e74638u); + } + HW_SCE_p_func100(0xfc1f2510u, 0xf5be6b44u, 0x98aa6735u, 0xcb95d279u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5e7915ecu, 0xb154b7a3u, 0x2b870eaeu, 0x15ea0d85u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xfcc75883u, 0x8b53d34bu, 0x64cd4158u, 0x2f466f82u); + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x3b9bc948u, 0xecccd80bu, 0x3d091b4fu, 0xc60b0873u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xf1a717d0u, 0x39aef144u, 0xaeaf235cu, 0x114d5fb4u); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0xc3ba43adu, 0xc15afa63u, 0x48f007e8u, 0xda48eeb4u); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x7a684752u, 0x024be5efu, 0x579221adu, 0x47a0a264u); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x0d80a60bu, 0x4b29a5abu, 0x2db3f5b8u, 0xbbdf960eu); + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c new file mode 100644 index 000000000..7e4169b59 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p47u.c @@ -0,0 +1,175 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x9c2bad13u, 0x79b50416u, 0x08b4a371u, 0xa6936ecau); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000a86u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x1f26deedu, 0x56986197u, 0x4d36f8e9u, 0xd2396fe3u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00004a86u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x46890128u, 0xa4bea142u, 0x46108c23u, 0x5eb9e253u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x00000e96u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0xf1e2c1c3u, 0xabc1c083u, 0xb30732a7u, 0x8c59ae8du); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x000049a6u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0xb0e543a4u, 0xa63ab851u, 0xb0bb040bu, 0x54ffef58u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_A4H = 0x000007b6u; + SCE->REG_04H = 0x0000c100u; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x3e045906u, 0x3dab084bu, 0x7f066ce2u, 0xc6491214u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xfb0d3b5cu, 0x665b5756u, 0xf6d445c4u, 0xf1f34104u); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xbee7945au, 0x9846b5c0u, 0x2a31d3d7u, 0xa5080511u); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xe585a470u, 0xf5c70a3au, 0x81d43f35u, 0xe506b30fu); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x115cf208u, 0xb5af7fdeu, 0x2d878176u, 0xb6d311d0u); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p47u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c new file mode 100644 index 000000000..d35655703 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50f.c @@ -0,0 +1,115 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xa53a714eu, 0xce2b3fd6u, 0x3801fd1bu, 0xa2b83ef5u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x82fe7aceu, 0xacd65af6u, 0x959bdef5u, 0x8e151cecu); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x0863ac10u, 0x4a52da44u, 0xd5687f54u, 0x4962b267u); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xcd1f7364u, 0xc1420ba6u, 0x87d65bffu, 0xb3858d7fu); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x39f66ff5u, 0x749d4554u, 0x3bed7a06u, 0xf39940fau); + } + HW_SCE_p_func100(0x2b31b234u, 0x798ccde6u, 0x81ae9de2u, 0x634149d6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x7d67ba6du, 0x40f2ca12u, 0x3fc845eau, 0xccc18a2eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0xda587a2au, 0x27b36189u, 0x2078e407u, 0xeeeb0a36u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c new file mode 100644 index 000000000..761d6f823 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50i.c @@ -0,0 +1,407 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005001u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_E0H = 0x80010000u; + SCE->REG_104H = 0x00000068u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x3000a800u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_ECH = 0x00010020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000006u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x3420a800u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x0e21cf93u, 0x39ff2075u, 0x975fe4d6u, 0xe5002de5u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050u); + HW_SCE_p_func101(0x63a10ee4u, 0x1c9962a7u, 0xc5c75ca8u, 0xa459db17u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050u); + HW_SCE_p_func101(0xf21f08acu, 0xafe1d606u, 0x64a4b8e0u, 0x872de97bu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x66dc5d68u, 0x94d4454cu, 0x572c97f9u, 0xb1ae352du); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa3d98bd6u, 0xde409614u, 0x4865160bu, 0xe2778f91u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x1c335020u, 0x9f787ee6u, 0x3c9df4ebu, 0xfc302bdbu); + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040040u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x000037e2u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x00ff0000u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00010000u; + SCE->REG_ECH = 0x1000d3c0u; + SCE->REG_ECH = 0x38008800u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_ECH = 0x1000b540u; + SCE->REG_ECH = 0x0000000fu; + SCE->REG_ECH = 0x2000b540u; + SCE->REG_ECH = 0x0000000eu; + SCE->REG_ECH = 0x3800584au; + SCE->REG_ECH = 0x2000d3c1u; + SCE->REG_ECH = 0x000037e2u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x000000feu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x1000d3c2u; + SCE->REG_ECH = 0x38008bc0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x0000a800u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_ECH = 0x00003542u; + SCE->REG_ECH = 0x00003563u; + SCE->REG_ECH = 0x00003584u; + SCE->REG_ECH = 0x000035a5u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000050u); + HW_SCE_p_func101(0x328609eau, 0xd57d7798u, 0xfb710b61u, 0xc3f90299u); + HW_SCE_p_func059(); + HW_SCE_p_func100(0xfc41514eu, 0x17da911bu, 0xd1be8b6au, 0xb76ef6c2u); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_A4H = 0x00080805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x0d06633fu, 0x33b5eaf5u, 0xe669c903u, 0xe82117f6u); + SCE->REG_A4H = 0x00090805u; + SCE->REG_00H = 0x00001213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x6477171au, 0x6c3a64ebu, 0x25a1b356u, 0xca8dc5d9u); + } + HW_SCE_p_func100(0x870632e2u, 0xcc4d5f31u, 0xd07aaac5u, 0x05592fc6u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xa0f62086u, 0xb4d95257u, 0x4a8a8cb7u, 0xb3231c7fu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x535d3514u, 0xdabd83b5u, 0x3c1e4e54u, 0xf7550eb2u); + SCE->REG_ECH = 0x00007c00u; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0x5910877eu, 0x9a9688e0u, 0xd01879feu, 0xac44966au); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func101(0xc15c53ebu, 0x5467c50fu, 0x454ecc55u, 0xef61db5eu); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x2a869265u, 0xd7aa0acdu, 0xe047eb03u, 0xa0403e78u); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x612ecac0u, 0x2675bbd3u, 0x23f488dcu, 0x2b4c76a5u); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000361u; + SCE->REG_A4H = 0x00040805u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + HW_SCE_p_func101(0x6882b60du, 0xc5fccc00u, 0x0f996f3eu, 0xf655eecfu); + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c new file mode 100644 index 000000000..32260fa6d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p50u.c @@ -0,0 +1,180 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t * InData_Text, uint32_t * OutData_Text, + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x12fec111u, 0x837686bcu, 0x29da676fu, 0x2a15b6c6u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008a86u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x57bd8fe5u, 0x5a462c45u, 0x9678f8abu, 0x95526c3fu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x0000ca86u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x587a8d69u, 0xa2d8f37eu, 0xc55267b3u, 0x7b67886cu); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x00008e96u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0xb2c8f072u, 0x646e4af5u, 0xa7435e98u, 0x59950484u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x0000c9a6u; + SCE->REG_04H = 0x0000c100u; + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_104H = 0x00000362u; + HW_SCE_p_func100(0x6e63e543u, 0x0b1c2b84u, 0x13059a4fu, 0xe340fb26u); + SCE->REG_104H = 0x000000b1u; + SCE->REG_B0H = 0x40000000u; + SCE->REG_A4H = 0x000087b6u; + SCE->REG_04H = 0x0000c100u; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + for (iLoop = 4; iLoop < MAX_CNT ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[iLoop + 0]; + SCE->REG_100H = InData_Text[iLoop + 1]; + SCE->REG_100H = InData_Text[iLoop + 2]; + SCE->REG_100H = InData_Text[iLoop + 3]; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[iLoop-4 + 0] = SCE->REG_100H; + OutData_Text[iLoop-4 + 1] = SCE->REG_100H; + OutData_Text[iLoop-4 + 2] = SCE->REG_100H; + OutData_Text[iLoop-4 + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[MAX_CNT-4 + 0] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 1] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 2] = SCE->REG_100H; + OutData_Text[MAX_CNT-4 + 3] = SCE->REG_100H; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xb89f76b5u, 0xee125499u, 0x98999e50u, 0x3ea99faau); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xf861eaa0u, 0xb24c5d5du, 0x3e2a924cu, 0x5c7ad83bu); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x279da2a4u, 0x7268bac3u, 0xe5d5d986u, 0xb26c9b0fu); + } + else if (0x03000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0xf1bdb534u, 0x2313da8du, 0x7fd36cd2u, 0x78f418cau); + } + else if (0x04000000u == (SCE->REG_1CH & 0xff000000u)) + { + HW_SCE_p_func206();//DisableINTEGRATE_WRRDYBandINTEGRATE_RDRDYBinthisfunction. + HW_SCE_p_func101(0x2db3fdb1u, 0xe0c0ef7fu, 0x665c0a8du, 0xd752d49eu); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p50u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c new file mode 100644 index 000000000..4fc1512b4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p56.c @@ -0,0 +1,392 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Rsa2048ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005601u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000056u); + HW_SCE_p_func101(0xdc0a590bu, 0x6e3392ffu, 0x97adc5b9u, 0x633171bbu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000000cu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000056u); + HW_SCE_p_func101(0xfc2447fau, 0x9cf0143bu, 0x85110c57u, 0x2b7cbdcfu); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00000001u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + SCE->REG_104H = 0x00008362u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x02e08887u; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[65]; + SCE->REG_100H = InData_KeyIndex[66]; + SCE->REG_100H = InData_KeyIndex[67]; + SCE->REG_100H = InData_KeyIndex[68]; + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00f087b7u; + for(iLoop=68; iLoop<132; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[133]; + SCE->REG_100H = InData_KeyIndex[134]; + SCE->REG_100H = InData_KeyIndex[135]; + SCE->REG_100H = InData_KeyIndex[136]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x0493bf32u, 0x4fd6ac99u, 0x18fd6dbdu, 0x235e32ddu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xe07e4daau, 0x5778972bu, 0xd2cb35fdu, 0x1c09d955u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x30b546ddu, 0x1c282749u, 0xd166b5dfu, 0x5f659d4bu); + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00003f67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_18H = 0x00000004u; + SCE->REG_38H = 0x00000338u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_00H = 0x00003807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + HW_SCE_p_func100(0x305b97ceu, 0x263481e9u, 0x9ae65b13u, 0xb79bccfeu); + SCE->REG_2CH = 0x00000020u; + SCE->REG_04H = 0x00000303u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + HW_SCE_p_func102(0xa498754bu, 0x729577e0u, 0x423a9c49u, 0xbf249dabu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p56.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c new file mode 100644 index 000000000..b6f66de27 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p57.c @@ -0,0 +1,387 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub(uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00005701u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000057u); + HW_SCE_p_func101(0x1d6969f5u, 0x0401b04bu, 0x453404b5u, 0x19622c0cu); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000000du; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000057u); + HW_SCE_p_func101(0xea15afbeu, 0x0eadbcbbu, 0x001b01dbu, 0x7a5e95e1u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00000001u; + SCE->REG_28H = 0x00bf0001u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + SCE->REG_104H = 0x0000bf62u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x02f087b7u; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000821u; + SCE->REG_E0H = 0x80c00001u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00f087b7u; + SCE->REG_00H = 0x00018203u; + for(iLoop=65; iLoop<129; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + SCE->REG_D0H = 0x40000f00u; + SCE->REG_C4H = 0x00f087b7u; + for(iLoop=128; iLoop<192; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[193]; + SCE->REG_100H = InData_KeyIndex[194]; + SCE->REG_100H = InData_KeyIndex[195]; + SCE->REG_100H = InData_KeyIndex[196]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xb1001691u, 0xf4028eb7u, 0x295866f2u, 0x7f84fd00u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x06324a76u, 0x607c42abu, 0x43889fe9u, 0xc012d247u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x2779abe0u, 0x47d803e3u, 0x6a378f2du, 0x69477a0eu); + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00003f67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_E0H = 0x00000100u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x000000fcu; + SCE->REG_18H = 0x00000004u; + SCE->REG_38H = 0x00000248u; + SCE->REG_E0H = 0x81c0001fu; + SCE->REG_00H = 0x00013803u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_E0H = 0x00000000u; + HW_SCE_p_func100(0x3df61758u, 0x0c41d91eu, 0xe9275f9fu, 0x2a583f2bu); + SCE->REG_2CH = 0x00000020u; + SCE->REG_04H = 0x00000303u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + HW_SCE_p_func102(0x2486d860u, 0x24678ef0u, 0x84ba5d03u, 0x0b42a66du); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p57.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c new file mode 100644 index 000000000..b3125580b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p6e.c @@ -0,0 +1,246 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_Cmd, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00006e01u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800103e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x785685e4u, 0x1eb8d70du, 0xe603298au, 0xf0890493u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func049(InData_Cmd); + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_ECH = 0x000037e4u; + SCE->REG_ECH = 0x3420a880u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x3420a880u; + SCE->REG_ECH = 0x00000024u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x3420a820u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x1fc2eb2au, 0xb7a01ddau, 0xe60b956au, 0x2cd96153u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x158158fau, 0xac8c3ed0u, 0xa6fff060u, 0x701fd272u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000349fu; + OFS_ADR = InData_SharedKeyIndex[0] << 3; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006eu); + HW_SCE_p_func101(0x4e05f96fu, 0x9b1167c2u, 0x75157ed6u, 0x55f37badu); + HW_SCE_p_func058(InData_SessionKey,OFS_ADR); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010380u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006eu); + HW_SCE_p_func101(0xe5d19a97u, 0xbbcdd6dau, 0x4233f284u, 0x7d0593bau); + HW_SCE_p_func057_r1(InData_IV,InData_InstData,OutData_KeyIndex); + HW_SCE_p_func100(0x0ab4814bu, 0xb8367889u, 0x271bcf2fu, 0x4feba308u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x9e5039cbu, 0xd69d6c2au, 0xa37c0068u, 0x3994c7b9u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x8daed06bu, 0x2a351c5cu, 0x97281b51u, 0x096a7d03u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func102(0x5d24c640u, 0x65732df6u, 0x707f16f3u, 0x63de5db7u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_p_func049(InData_Cmd); + SCE->REG_ECH = 0x000037e4u; + SCE->REG_ECH = 0x3420a880u; + SCE->REG_ECH = 0x00000005u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x3420a880u; + SCE->REG_ECH = 0x00000024u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x3ddcbafau, 0x68190098u, 0x71aaccc8u, 0x13400e2fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x32392174u, 0x42e93794u, 0xfb704f82u, 0x2fa0736cu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000349fu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010380u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000006eu); + HW_SCE_p_func101(0xf791c673u, 0xdde49f4cu, 0xe3b14380u, 0x967940b2u); + HW_SCE_p_func065_r1(InData_InstData,OutData_KeyIndex); + HW_SCE_p_func100(0x1cf9ac81u, 0x590924eau, 0xd4425eb1u, 0xd5db5292u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func102(0x61423c7fu, 0xf3f4807eu, 0x10a36a81u, 0x6c3dbeadu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p6e_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c new file mode 100644 index 000000000..7b81799e7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p72.c @@ -0,0 +1,150 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Sha224256GenerateMessageDigestSub(const uint32_t *InData_InitVal, const uint32_t *InData_PaddedMsg, const uint32_t MAX_CNT, uint32_t *OutData_MsgDigest) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007201u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x89b55281u, 0x097f6146u, 0xd6a77de8u, 0xec3b48deu); + SCE->REG_7CH = 0x00000011u; + SCE->REG_104H = 0x00000764u; + SCE->REG_74H = 0x00000004u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InitVal[0]; + SCE->REG_100H = InData_InitVal[1]; + SCE->REG_100H = InData_InitVal[2]; + SCE->REG_100H = InData_InitVal[3]; + SCE->REG_100H = InData_InitVal[4]; + SCE->REG_100H = InData_InitVal[5]; + SCE->REG_100H = InData_InitVal[6]; + SCE->REG_100H = InData_InitVal[7]; + SCE->REG_104H = 0x000000b4u; + SCE->REG_74H = 0x08000002u; + for (iLoop = 0; iLoop < MAX_CNT ; iLoop = iLoop + 16) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 0]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 1]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 2]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 3]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 4]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 5]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 6]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 7]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 8]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 9]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 10]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 11]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 12]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 13]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 14]; + SCE->REG_100H = InData_PaddedMsg[0+iLoop + 15]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_74H = 0x00000000u; + SCE->REG_104H = 0x00000000u; + SCE->REG_1CH = 0x00001600u; + SCE->REG_74H = 0x00000008u; + SCE->REG_04H = 0x00000523u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MsgDigest[0] = SCE->REG_100H; + OutData_MsgDigest[1] = SCE->REG_100H; + OutData_MsgDigest[2] = SCE->REG_100H; + OutData_MsgDigest[3] = SCE->REG_100H; + OutData_MsgDigest[4] = SCE->REG_100H; + OutData_MsgDigest[5] = SCE->REG_100H; + OutData_MsgDigest[6] = SCE->REG_100H; + OutData_MsgDigest[7] = SCE->REG_100H; + HW_SCE_p_func102(0x482a4372u, 0x21f251ebu, 0x29dc06a6u, 0x84167a56u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p72.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c new file mode 100644 index 000000000..dc3a74f93 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76f.c @@ -0,0 +1,313 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Sha256HmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_MAC, uint32_t *InData_length, uint32_t *OutData_MAC) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_74H = 0x00000000u; + SCE->REG_28H = 0x00870001u; + SCE->REG_00H = 0x00003523u; + SCE->REG_74H = 0x00000008u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_7CH = 0x00000011u; + SCE->REG_104H = 0x00000754u; + SCE->REG_74H = 0x00000004u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667u); + SCE->REG_100H = change_endian_long(0xbb67ae85u); + SCE->REG_100H = change_endian_long(0x3c6ef372u); + SCE->REG_100H = change_endian_long(0xa54ff53au); + SCE->REG_100H = change_endian_long(0x510e527fu); + SCE->REG_100H = change_endian_long(0x9b05688cu); + SCE->REG_100H = change_endian_long(0x1f83d9abu); + SCE->REG_100H = change_endian_long(0x5be0cd19u); + SCE->REG_74H = 0x00000002u; + HW_SCE_p_func002(); + SCE->REG_00H = 0x00005323u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000054u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x80000000u); + SCE->REG_F8H = 0x00000040u; + SCE->REG_104H = 0x00000154u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_100H = change_endian_long(0x00000300u); + /* WAIT_LOOP */ + while (0u != SCE->REG_74H_b.B18) + { + /* waiting */ + } + SCE->REG_74H = 0x00000000u; + SCE->REG_1CH = 0x00001600u; + SCE->REG_E0H = 0x80010000u; + SCE->REG_104H = 0x00000068u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_ECH = 0x1000b780u; + SCE->REG_ECH = 0x00002000u; + SCE->REG_ECH = 0x2000b780u; + SCE->REG_ECH = 0x00001000u; + SCE->REG_ECH = 0x38000f9bu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x5645d712u, 0xf440c1a2u, 0x355c8516u, 0x48ad4f74u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x9f0753abu, 0x672d8e04u, 0x33faac82u, 0xa4233a9eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x38000c00u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x63745b29u, 0xaebe8cc7u, 0x7085ee73u, 0x8e5d85a1u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func100(0x5b5be3a7u, 0x336987a4u, 0x9aa80c8cu, 0x48f5e12au); + SCE->REG_74H = 0x00000008u; + SCE->REG_04H = 0x00000523u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_MAC[0] = SCE->REG_100H; + OutData_MAC[1] = SCE->REG_100H; + OutData_MAC[2] = SCE->REG_100H; + OutData_MAC[3] = SCE->REG_100H; + OutData_MAC[4] = SCE->REG_100H; + OutData_MAC[5] = SCE->REG_100H; + OutData_MAC[6] = SCE->REG_100H; + OutData_MAC[7] = SCE->REG_100H; + HW_SCE_p_func102(0xf3b0da21u, 0xaa2c1883u, 0x81dcbe92u, 0x1211e78fu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_length[0]; + SCE->REG_ECH = 0x3420a820u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x3420a820u; + SCE->REG_ECH = 0x00000021u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x787f2c3cu, 0x51494157u, 0x8d21dbdau, 0xae4b1106u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x48ebd1e7u, 0x8950bad9u, 0xacd6fb88u, 0x66f4b1edu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008523u; + SCE->REG_74H = 0x00000008u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000800u; + for (iLoop = 0; iLoop < 32; iLoop = iLoop+1) + { + SCE->REG_ECH = 0x3c002be1u; + SCE->REG_ECH = 0x12003c1fu; + SCE->REG_ECH = 0x00002fe0u; + } + SCE->REG_A4H = 0x00040805u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_A4H = 0x00050805u; + SCE->REG_00H = 0x00001813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000761u; + SCE->REG_A4H = 0x00900c05u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[0]; + SCE->REG_100H = InData_MAC[1]; + SCE->REG_100H = InData_MAC[2]; + SCE->REG_100H = InData_MAC[3]; + SCE->REG_A4H = 0x00900c45u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MAC[4]; + SCE->REG_100H = InData_MAC[5]; + SCE->REG_100H = InData_MAC[6]; + SCE->REG_100H = InData_MAC[7]; + HW_SCE_p_func100(0xfcc31f34u, 0x1b5c3390u, 0x9e47672du, 0x93c96d76u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x7db6d140u, 0xac1e40a8u, 0x55d31ba6u, 0xdf750b0bu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x8e622b72u, 0x844d725fu, 0xd2e4a8e7u, 0x6bff87e6u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76f.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c new file mode 100644 index 000000000..87fcaa060 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76i.c @@ -0,0 +1,339 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t LEN) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007601u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_7CH = 0x00000011u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0xf359ed55u, 0xeaf5291fu, 0x95c1799fu, 0x61437f67u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076u); + HW_SCE_p_func101(0x950afab4u, 0xf29174adu, 0x4756ab39u, 0x919653d1u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000001bu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076u); + HW_SCE_p_func101(0x15227eb5u, 0x2c6484bau, 0xec96f901u, 0x9e5bf753u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008223u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b760u; + SCE->REG_ECH = 0x00003000u; + HW_SCE_p_func101(0x2deea867u, 0xb7d5bae0u, 0x3157a392u, 0x9b767470u); + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x00ff0000u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00020000u; + SCE->REG_ECH = 0x1000d3c0u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x38008fe0u; + SCE->REG_ECH = 0x00003000u; + SCE->REG_ECH = 0x2000d3c1u; + SCE->REG_ECH = 0x00003760u; + SCE->REG_ECH = 0x00008f60u; + SCE->REG_ECH = 0x00003000u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x000000feu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_ECH = 0x1000d3c2u; + SCE->REG_ECH = 0x38008bc0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00003540u; + SCE->REG_ECH = 0x00003561u; + SCE->REG_ECH = 0x00003582u; + SCE->REG_ECH = 0x000035a3u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000076u); + HW_SCE_p_func101(0xc893c247u, 0x8ee29456u, 0xf2c5efc8u, 0x848d8db3u); + HW_SCE_p_func059(); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_E0H = 0x80080000u; + SCE->REG_00H = 0x00008223u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func101(0x45ae9272u, 0x79061a99u, 0xea79821du, 0xe5f9bcc5u); + } + HW_SCE_p_func100(0x063a8108u, 0x8c07b7a6u, 0x7e2e826fu, 0xe2a527e9u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x618eda6cu, 0xd48d8015u, 0xaa3ad2fbu, 0xb0d44b36u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_7CH = 0x00000011u; + SCE->REG_104H = 0x00000754u; + SCE->REG_74H = 0x00000004u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x6a09e667u); + SCE->REG_100H = change_endian_long(0xbb67ae85u); + SCE->REG_100H = change_endian_long(0x3c6ef372u); + SCE->REG_100H = change_endian_long(0xa54ff53au); + SCE->REG_100H = change_endian_long(0x510e527fu); + SCE->REG_100H = change_endian_long(0x9b05688cu); + SCE->REG_100H = change_endian_long(0x1f83d9abu); + SCE->REG_100H = change_endian_long(0x5be0cd19u); + SCE->REG_74H = 0x00000002u; + HW_SCE_p_func001(); + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76i.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c new file mode 100644 index 000000000..72cf5ecfc --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p76u.c @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_Sha256HmacUpdateSub(uint32_t *InData_PaddedMsg, uint32_t MAX_CNT) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + HW_SCE_p_func000(InData_PaddedMsg, MAX_CNT); + HW_SCE_p_func101(0x04493113u, 0xd0a36523u, 0x247a2f8fu, 0x9bf01b74u); +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p76u.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c new file mode 100644 index 000000000..f3cbc8773 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p79.c @@ -0,0 +1,831 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007901u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000079u); + HW_SCE_p_func101(0x0fd665fbu, 0x35663e4cu, 0x472c9c29u, 0x480cabf3u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0000000eu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000079u); + HW_SCE_p_func101(0x6b0497cfu, 0x2c4fe92bu, 0x51befe47u, 0xb7bd24b5u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00006362u; + SCE->REG_D0H = 0x40001800u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + for(iLoop=0; iLoop<32; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + for(iLoop=32; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + for(iLoop=64; iLoop<96; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_E0H = 0x80010280u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x7ee8691bu, 0x37b5f60au, 0x87859dc1u, 0x394206a8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x1e94bb70u, 0xd0807b52u, 0xb19b60a0u, 0x875879ffu); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x115bdcb3u, 0x073a2576u, 0xa28bdb20u, 0x2f2d587au); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xa970f4fau, 0xb28af495u, 0x5d28b925u, 0x2ec6dfa3u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x010c0c04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x4350ff0fu, 0x54672d5au, 0x3e9ea952u, 0xed9785dau); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x830263b0u, 0x987f3967u, 0xdd7089eau, 0xfb6164b3u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(752); + HW_SCE_p_func100(0x7d8ff34eu, 0x39614ffau, 0x02d73beeu, 0x32051da9u); + HW_SCE_p_func314(752+32); + HW_SCE_p_func100(0x336798e0u, 0x6d49a1fbu, 0x49bd8f75u, 0x8a0e9fa7u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xa0287871u, 0x20908695u, 0x4fda4e72u, 0x8d0d67a8u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func319(716); + HW_SCE_p_func100(0xe3e3d8acu, 0xa1e30561u, 0x83e21b2eu, 0x7d239563u); + HW_SCE_p_func314(716+32); + HW_SCE_p_func100(0xfa3af305u, 0xdb097dcfu, 0xf809dec6u, 0xfd840cdeu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9fd08737u, 0x4f2d0f36u, 0x1b1a4873u, 0xf3b346f4u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func319(680); + HW_SCE_p_func100(0xe3cbffc7u, 0xa0ff85e1u, 0x18893f9fu, 0xae2c8b0eu); + HW_SCE_p_func314(680+32); + SCE->REG_00H = 0x0000037fu; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x800103e0u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3800dbe0u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00001f67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_2CH = 0x00000014u; + SCE->REG_104H = 0x00003f67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_100H = InData_Text[64]; + SCE->REG_100H = InData_Text[65]; + SCE->REG_100H = InData_Text[66]; + SCE->REG_100H = InData_Text[67]; + SCE->REG_100H = InData_Text[68]; + SCE->REG_100H = InData_Text[69]; + SCE->REG_100H = InData_Text[70]; + SCE->REG_100H = InData_Text[71]; + SCE->REG_100H = InData_Text[72]; + SCE->REG_100H = InData_Text[73]; + SCE->REG_100H = InData_Text[74]; + SCE->REG_100H = InData_Text[75]; + SCE->REG_100H = InData_Text[76]; + SCE->REG_100H = InData_Text[77]; + SCE->REG_100H = InData_Text[78]; + SCE->REG_100H = InData_Text[79]; + SCE->REG_100H = InData_Text[80]; + SCE->REG_100H = InData_Text[81]; + SCE->REG_100H = InData_Text[82]; + SCE->REG_100H = InData_Text[83]; + SCE->REG_100H = InData_Text[84]; + SCE->REG_100H = InData_Text[85]; + SCE->REG_100H = InData_Text[86]; + SCE->REG_100H = InData_Text[87]; + SCE->REG_100H = InData_Text[88]; + SCE->REG_100H = InData_Text[89]; + SCE->REG_100H = InData_Text[90]; + SCE->REG_100H = InData_Text[91]; + SCE->REG_100H = InData_Text[92]; + SCE->REG_100H = InData_Text[93]; + SCE->REG_100H = InData_Text[94]; + SCE->REG_100H = InData_Text[95]; + SCE->REG_28H = 0x009f0001u; + HW_SCE_p_func100(0x3b932c9du, 0xe60b45f9u, 0x4c68dc70u, 0xbab75753u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xf14dc81du, 0x08c983d3u, 0x2ab61a1eu, 0x451526acu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func319(72); + HW_SCE_p_func100(0x2038a22au, 0xb18b5053u, 0xaeaa8fb6u, 0x146a776cu); + HW_SCE_p_func314(72+32); + HW_SCE_p_func100(0x98d4795du, 0xc5730533u, 0x8758a926u, 0x59185715u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x219de09du, 0x3123024fu, 0x16875a12u, 0x75a53b8eu); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000025u; + HW_SCE_p_func319(36); + HW_SCE_p_func100(0x95492014u, 0xb970b606u, 0x4ce340ceu, 0x17ca043au); + HW_SCE_p_func314(36+32); + HW_SCE_p_func100(0x815aba79u, 0x0c7e88ddu, 0xaa881027u, 0x49e7c658u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x50c99eb5u, 0xb362b304u, 0xa260fd0cu, 0xd13b0444u); + SCE->REG_00H = 0x00002383u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func319(0); + HW_SCE_p_func100(0x99efb969u, 0xc88fe10cu, 0x3a83bfc6u, 0xd056ba30u); + HW_SCE_p_func314(0+32); + HW_SCE_p_func100(0x037788a3u, 0x79be5549u, 0xe46f539eu, 0x5aab9302u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000040d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00a10000u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019410dfu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x526c5725u, 0x2b7bafbcu, 0x6f8db96cu, 0xeb735ef5u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(680); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x010273a4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x0865271cu, 0x120ff1a1u, 0x71f5a98au, 0xfccde033u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000011u; + HW_SCE_p_func320(716); + SCE->REG_24H = 0x000016c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x018e0c4cu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xaf4abd00u, 0x732a43fdu, 0xf1b0a12cu, 0x8b129d76u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func320(752); + SCE->REG_24H = 0x000060d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x000080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x009f0001u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01fe1091u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x31290a2bu, 0xbf7356c4u, 0x4d0cccfau, 0x22e1373fu); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func320(0); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019969f4u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x8c99cd47u, 0x2868da89u, 0x91452e8eu, 0x7963c836u); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000015u; + HW_SCE_p_func320(36); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x019de420u); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00003283u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func320(72); + SCE->REG_24H = 0x0000a0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00bf0001u; + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x3578337cu, 0xf2829ff4u, 0xcfc2f8a8u, 0xf4ebc9bau); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xa3c643d5u, 0xbeb0bc69u, 0xc8cb1884u, 0x31c8ab72u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x00000079u; + HW_SCE_p_func101(0xee77e57cu, 0x9533b284u, 0x8d1c3bc5u, 0x7dafdaabu); + HW_SCE_p_func325(); + SCE->REG_28H = 0x009f0001u; + HW_SCE_p_func100(0x89f73d3fu, 0x7ca8dee1u, 0x9173e011u, 0x633d40e3u); + SCE->REG_2CH = 0x00000020u; + SCE->REG_04H = 0x00000382u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func100(0xa42466f5u, 0x57bd3bb3u, 0xb6f415b2u, 0xe32c0359u); + SCE->REG_2CH = 0x00000022u; + SCE->REG_04H = 0x00000302u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + OutData_Text[64] = SCE->REG_100H; + OutData_Text[65] = SCE->REG_100H; + OutData_Text[66] = SCE->REG_100H; + OutData_Text[67] = SCE->REG_100H; + OutData_Text[68] = SCE->REG_100H; + OutData_Text[69] = SCE->REG_100H; + OutData_Text[70] = SCE->REG_100H; + OutData_Text[71] = SCE->REG_100H; + OutData_Text[72] = SCE->REG_100H; + OutData_Text[73] = SCE->REG_100H; + OutData_Text[74] = SCE->REG_100H; + OutData_Text[75] = SCE->REG_100H; + OutData_Text[76] = SCE->REG_100H; + OutData_Text[77] = SCE->REG_100H; + OutData_Text[78] = SCE->REG_100H; + OutData_Text[79] = SCE->REG_100H; + OutData_Text[80] = SCE->REG_100H; + OutData_Text[81] = SCE->REG_100H; + OutData_Text[82] = SCE->REG_100H; + OutData_Text[83] = SCE->REG_100H; + OutData_Text[84] = SCE->REG_100H; + OutData_Text[85] = SCE->REG_100H; + OutData_Text[86] = SCE->REG_100H; + OutData_Text[87] = SCE->REG_100H; + OutData_Text[88] = SCE->REG_100H; + OutData_Text[89] = SCE->REG_100H; + OutData_Text[90] = SCE->REG_100H; + OutData_Text[91] = SCE->REG_100H; + OutData_Text[92] = SCE->REG_100H; + OutData_Text[93] = SCE->REG_100H; + OutData_Text[94] = SCE->REG_100H; + OutData_Text[95] = SCE->REG_100H; + HW_SCE_p_func102(0xfeb44e6eu, 0x7548637du, 0x57cf5ec8u, 0xef21b7b0u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p79_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c new file mode 100644 index 000000000..34168a577 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p7b.c @@ -0,0 +1,787 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, uint32_t *OutData_Text) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00007b01u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000007bu); + HW_SCE_p_func101(0xc0289cc8u, 0x0da9ca5au, 0x10386cecu, 0xb3028594u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x00000010u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000007bu); + HW_SCE_p_func101(0x2309da37u, 0xf0f28872u, 0x6cfd2509u, 0xa7f31384u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_28H = 0x00bf0001u; + SCE->REG_104H = 0x00007f62u; + SCE->REG_D0H = 0x40001f00u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + for(iLoop=0; iLoop<64; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + for(iLoop=64; iLoop<128; iLoop=iLoop+4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_E0H = 0x80010280u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+5 + 3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x903b968eu, 0xad9da53cu, 0xaba0cd07u, 0x97b48c76u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x54d41d5au, 0x06b3a163u, 0x53f979b9u, 0x47bf5286u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x461f3249u, 0x2efadb3eu, 0xbaf07020u, 0xaeeceaecu); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xe5463b0du, 0xcd954697u, 0x740fdb08u, 0xc51bf68cu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x010c0c04u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + HW_SCE_p_func100(0x666934e9u, 0x793e6d91u, 0x0e43c17eu, 0x0616660cu); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xe5642d63u, 0xc3d07339u, 0xa16918beu, 0xa74ae22eu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(748); + HW_SCE_p_func100(0x3839dc3du, 0x00caee54u, 0xce7cc0a9u, 0xc779149fu); + HW_SCE_p_func314(748+64); + HW_SCE_p_func100(0x82eca6bdu, 0xdb97e979u, 0x36f8c5f4u, 0x8f0548a4u); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4fa851eau, 0xfe31e49eu, 0xbf16a61au, 0x411d969cu); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000022u; + HW_SCE_p_func313(680); + HW_SCE_p_func100(0x9810dd6au, 0x2c76d595u, 0xd604ae28u, 0xf8772679u); + HW_SCE_p_func314(680+64); + SCE->REG_00H = 0x000003ffu; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_E0H = 0x800103e0u; + SCE->REG_00H = 0x00008307u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x3800dbe0u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + HW_SCE_p_func100(0x2fd0da4fu, 0xc0180b8eu, 0x9b930e08u, 0x25b04aecu); + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00003f67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[0]; + SCE->REG_100H = InData_Text[1]; + SCE->REG_100H = InData_Text[2]; + SCE->REG_100H = InData_Text[3]; + SCE->REG_100H = InData_Text[4]; + SCE->REG_100H = InData_Text[5]; + SCE->REG_100H = InData_Text[6]; + SCE->REG_100H = InData_Text[7]; + SCE->REG_100H = InData_Text[8]; + SCE->REG_100H = InData_Text[9]; + SCE->REG_100H = InData_Text[10]; + SCE->REG_100H = InData_Text[11]; + SCE->REG_100H = InData_Text[12]; + SCE->REG_100H = InData_Text[13]; + SCE->REG_100H = InData_Text[14]; + SCE->REG_100H = InData_Text[15]; + SCE->REG_100H = InData_Text[16]; + SCE->REG_100H = InData_Text[17]; + SCE->REG_100H = InData_Text[18]; + SCE->REG_100H = InData_Text[19]; + SCE->REG_100H = InData_Text[20]; + SCE->REG_100H = InData_Text[21]; + SCE->REG_100H = InData_Text[22]; + SCE->REG_100H = InData_Text[23]; + SCE->REG_100H = InData_Text[24]; + SCE->REG_100H = InData_Text[25]; + SCE->REG_100H = InData_Text[26]; + SCE->REG_100H = InData_Text[27]; + SCE->REG_100H = InData_Text[28]; + SCE->REG_100H = InData_Text[29]; + SCE->REG_100H = InData_Text[30]; + SCE->REG_100H = InData_Text[31]; + SCE->REG_100H = InData_Text[32]; + SCE->REG_100H = InData_Text[33]; + SCE->REG_100H = InData_Text[34]; + SCE->REG_100H = InData_Text[35]; + SCE->REG_100H = InData_Text[36]; + SCE->REG_100H = InData_Text[37]; + SCE->REG_100H = InData_Text[38]; + SCE->REG_100H = InData_Text[39]; + SCE->REG_100H = InData_Text[40]; + SCE->REG_100H = InData_Text[41]; + SCE->REG_100H = InData_Text[42]; + SCE->REG_100H = InData_Text[43]; + SCE->REG_100H = InData_Text[44]; + SCE->REG_100H = InData_Text[45]; + SCE->REG_100H = InData_Text[46]; + SCE->REG_100H = InData_Text[47]; + SCE->REG_100H = InData_Text[48]; + SCE->REG_100H = InData_Text[49]; + SCE->REG_100H = InData_Text[50]; + SCE->REG_100H = InData_Text[51]; + SCE->REG_100H = InData_Text[52]; + SCE->REG_100H = InData_Text[53]; + SCE->REG_100H = InData_Text[54]; + SCE->REG_100H = InData_Text[55]; + SCE->REG_100H = InData_Text[56]; + SCE->REG_100H = InData_Text[57]; + SCE->REG_100H = InData_Text[58]; + SCE->REG_100H = InData_Text[59]; + SCE->REG_100H = InData_Text[60]; + SCE->REG_100H = InData_Text[61]; + SCE->REG_100H = InData_Text[62]; + SCE->REG_100H = InData_Text[63]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bu); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x3279f1d9u, 0x0f2dfdfbu, 0x0f0ffcb2u, 0x6357c36au); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000020u; + HW_SCE_p_func313(68); + HW_SCE_p_func100(0xf2add757u, 0xfa02b79bu, 0x6c5ffee4u, 0x82be2125u); + HW_SCE_p_func314(68+64); + HW_SCE_p_func100(0x692e1d9fu, 0x0ff2e4d0u, 0x35103c8du, 0x81420ab6u); + SCE->REG_2CH = 0x00000014u; + SCE->REG_104H = 0x00003f67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Text[64]; + SCE->REG_100H = InData_Text[65]; + SCE->REG_100H = InData_Text[66]; + SCE->REG_100H = InData_Text[67]; + SCE->REG_100H = InData_Text[68]; + SCE->REG_100H = InData_Text[69]; + SCE->REG_100H = InData_Text[70]; + SCE->REG_100H = InData_Text[71]; + SCE->REG_100H = InData_Text[72]; + SCE->REG_100H = InData_Text[73]; + SCE->REG_100H = InData_Text[74]; + SCE->REG_100H = InData_Text[75]; + SCE->REG_100H = InData_Text[76]; + SCE->REG_100H = InData_Text[77]; + SCE->REG_100H = InData_Text[78]; + SCE->REG_100H = InData_Text[79]; + SCE->REG_100H = InData_Text[80]; + SCE->REG_100H = InData_Text[81]; + SCE->REG_100H = InData_Text[82]; + SCE->REG_100H = InData_Text[83]; + SCE->REG_100H = InData_Text[84]; + SCE->REG_100H = InData_Text[85]; + SCE->REG_100H = InData_Text[86]; + SCE->REG_100H = InData_Text[87]; + SCE->REG_100H = InData_Text[88]; + SCE->REG_100H = InData_Text[89]; + SCE->REG_100H = InData_Text[90]; + SCE->REG_100H = InData_Text[91]; + SCE->REG_100H = InData_Text[92]; + SCE->REG_100H = InData_Text[93]; + SCE->REG_100H = InData_Text[94]; + SCE->REG_100H = InData_Text[95]; + SCE->REG_100H = InData_Text[96]; + SCE->REG_100H = InData_Text[97]; + SCE->REG_100H = InData_Text[98]; + SCE->REG_100H = InData_Text[99]; + SCE->REG_100H = InData_Text[100]; + SCE->REG_100H = InData_Text[101]; + SCE->REG_100H = InData_Text[102]; + SCE->REG_100H = InData_Text[103]; + SCE->REG_100H = InData_Text[104]; + SCE->REG_100H = InData_Text[105]; + SCE->REG_100H = InData_Text[106]; + SCE->REG_100H = InData_Text[107]; + SCE->REG_100H = InData_Text[108]; + SCE->REG_100H = InData_Text[109]; + SCE->REG_100H = InData_Text[110]; + SCE->REG_100H = InData_Text[111]; + SCE->REG_100H = InData_Text[112]; + SCE->REG_100H = InData_Text[113]; + SCE->REG_100H = InData_Text[114]; + SCE->REG_100H = InData_Text[115]; + SCE->REG_100H = InData_Text[116]; + SCE->REG_100H = InData_Text[117]; + SCE->REG_100H = InData_Text[118]; + SCE->REG_100H = InData_Text[119]; + SCE->REG_100H = InData_Text[120]; + SCE->REG_100H = InData_Text[121]; + SCE->REG_100H = InData_Text[122]; + SCE->REG_100H = InData_Text[123]; + SCE->REG_100H = InData_Text[124]; + SCE->REG_100H = InData_Text[125]; + SCE->REG_100H = InData_Text[126]; + SCE->REG_100H = InData_Text[127]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7au); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x6856f51bu, 0x67c3861bu, 0x0f98564fu, 0x1c2173b6u); + SCE->REG_00H = 0x00012303u; + SCE->REG_2CH = 0x00000024u; + HW_SCE_p_func313(0); + HW_SCE_p_func100(0x2cc7c29fu, 0x55989bb4u, 0xe0885821u, 0x47946e2bu); + HW_SCE_p_func314(0+64); + HW_SCE_p_func100(0x4a70a9f1u, 0x00cbb8f2u, 0xd7e7b87cu, 0xb4b60fccu); + SCE->REG_24H = 0x000040d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00a10000u; + SCE->REG_24H = 0x000005c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000581u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01b9d3a9u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x9ac95ad5u, 0x6a879f56u, 0x923eb619u, 0x26d3747bu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(680); + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x012dc3c7u); + HW_SCE_p_func080(); + HW_SCE_p_func100(0x4f01d2cfu, 0x0d4eb0adu, 0xcaba60efu, 0x3970713cu); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + HW_SCE_p_func312(748); + SCE->REG_24H = 0x000080d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x01432c7au); + HW_SCE_p_func080(); + HW_SCE_p_func100(0xacafc88eu, 0xdbd38fc2u, 0xb6c15c6au, 0x17f023f3u); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + HW_SCE_p_func312(0); + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x80010020u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0132d44bu); + HW_SCE_p_func080(); + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000010u; + HW_SCE_p_func312(68); + SCE->REG_24H = 0x04001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x060049c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x02001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xee4a893eu, 0x61180774u, 0x5f024dfeu, 0x354fe237u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xcbeb2459u, 0x60ad9840u, 0x6aa33f73u, 0xc3e165e4u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000007bu; + HW_SCE_p_func101(0xad1ea16du, 0xf8e9b417u, 0x6e7fb16au, 0x0cb69393u); + HW_SCE_p_func307(); + HW_SCE_p_func100(0x79311285u, 0xe19252e8u, 0x6b8254d5u, 0x5380f50eu); + SCE->REG_2CH = 0x00000020u; + SCE->REG_04H = 0x00000302u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[0] = SCE->REG_100H; + OutData_Text[1] = SCE->REG_100H; + OutData_Text[2] = SCE->REG_100H; + OutData_Text[3] = SCE->REG_100H; + OutData_Text[4] = SCE->REG_100H; + OutData_Text[5] = SCE->REG_100H; + OutData_Text[6] = SCE->REG_100H; + OutData_Text[7] = SCE->REG_100H; + OutData_Text[8] = SCE->REG_100H; + OutData_Text[9] = SCE->REG_100H; + OutData_Text[10] = SCE->REG_100H; + OutData_Text[11] = SCE->REG_100H; + OutData_Text[12] = SCE->REG_100H; + OutData_Text[13] = SCE->REG_100H; + OutData_Text[14] = SCE->REG_100H; + OutData_Text[15] = SCE->REG_100H; + OutData_Text[16] = SCE->REG_100H; + OutData_Text[17] = SCE->REG_100H; + OutData_Text[18] = SCE->REG_100H; + OutData_Text[19] = SCE->REG_100H; + OutData_Text[20] = SCE->REG_100H; + OutData_Text[21] = SCE->REG_100H; + OutData_Text[22] = SCE->REG_100H; + OutData_Text[23] = SCE->REG_100H; + OutData_Text[24] = SCE->REG_100H; + OutData_Text[25] = SCE->REG_100H; + OutData_Text[26] = SCE->REG_100H; + OutData_Text[27] = SCE->REG_100H; + OutData_Text[28] = SCE->REG_100H; + OutData_Text[29] = SCE->REG_100H; + OutData_Text[30] = SCE->REG_100H; + OutData_Text[31] = SCE->REG_100H; + OutData_Text[32] = SCE->REG_100H; + OutData_Text[33] = SCE->REG_100H; + OutData_Text[34] = SCE->REG_100H; + OutData_Text[35] = SCE->REG_100H; + OutData_Text[36] = SCE->REG_100H; + OutData_Text[37] = SCE->REG_100H; + OutData_Text[38] = SCE->REG_100H; + OutData_Text[39] = SCE->REG_100H; + OutData_Text[40] = SCE->REG_100H; + OutData_Text[41] = SCE->REG_100H; + OutData_Text[42] = SCE->REG_100H; + OutData_Text[43] = SCE->REG_100H; + OutData_Text[44] = SCE->REG_100H; + OutData_Text[45] = SCE->REG_100H; + OutData_Text[46] = SCE->REG_100H; + OutData_Text[47] = SCE->REG_100H; + OutData_Text[48] = SCE->REG_100H; + OutData_Text[49] = SCE->REG_100H; + OutData_Text[50] = SCE->REG_100H; + OutData_Text[51] = SCE->REG_100H; + OutData_Text[52] = SCE->REG_100H; + OutData_Text[53] = SCE->REG_100H; + OutData_Text[54] = SCE->REG_100H; + OutData_Text[55] = SCE->REG_100H; + OutData_Text[56] = SCE->REG_100H; + OutData_Text[57] = SCE->REG_100H; + OutData_Text[58] = SCE->REG_100H; + OutData_Text[59] = SCE->REG_100H; + OutData_Text[60] = SCE->REG_100H; + OutData_Text[61] = SCE->REG_100H; + OutData_Text[62] = SCE->REG_100H; + OutData_Text[63] = SCE->REG_100H; + HW_SCE_p_func100(0x05cf816cu, 0xaebbba33u, 0xc92ae771u, 0x1fba7f70u); + SCE->REG_2CH = 0x00000022u; + SCE->REG_04H = 0x00000302u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Text[64] = SCE->REG_100H; + OutData_Text[65] = SCE->REG_100H; + OutData_Text[66] = SCE->REG_100H; + OutData_Text[67] = SCE->REG_100H; + OutData_Text[68] = SCE->REG_100H; + OutData_Text[69] = SCE->REG_100H; + OutData_Text[70] = SCE->REG_100H; + OutData_Text[71] = SCE->REG_100H; + OutData_Text[72] = SCE->REG_100H; + OutData_Text[73] = SCE->REG_100H; + OutData_Text[74] = SCE->REG_100H; + OutData_Text[75] = SCE->REG_100H; + OutData_Text[76] = SCE->REG_100H; + OutData_Text[77] = SCE->REG_100H; + OutData_Text[78] = SCE->REG_100H; + OutData_Text[79] = SCE->REG_100H; + OutData_Text[80] = SCE->REG_100H; + OutData_Text[81] = SCE->REG_100H; + OutData_Text[82] = SCE->REG_100H; + OutData_Text[83] = SCE->REG_100H; + OutData_Text[84] = SCE->REG_100H; + OutData_Text[85] = SCE->REG_100H; + OutData_Text[86] = SCE->REG_100H; + OutData_Text[87] = SCE->REG_100H; + OutData_Text[88] = SCE->REG_100H; + OutData_Text[89] = SCE->REG_100H; + OutData_Text[90] = SCE->REG_100H; + OutData_Text[91] = SCE->REG_100H; + OutData_Text[92] = SCE->REG_100H; + OutData_Text[93] = SCE->REG_100H; + OutData_Text[94] = SCE->REG_100H; + OutData_Text[95] = SCE->REG_100H; + OutData_Text[96] = SCE->REG_100H; + OutData_Text[97] = SCE->REG_100H; + OutData_Text[98] = SCE->REG_100H; + OutData_Text[99] = SCE->REG_100H; + OutData_Text[100] = SCE->REG_100H; + OutData_Text[101] = SCE->REG_100H; + OutData_Text[102] = SCE->REG_100H; + OutData_Text[103] = SCE->REG_100H; + OutData_Text[104] = SCE->REG_100H; + OutData_Text[105] = SCE->REG_100H; + OutData_Text[106] = SCE->REG_100H; + OutData_Text[107] = SCE->REG_100H; + OutData_Text[108] = SCE->REG_100H; + OutData_Text[109] = SCE->REG_100H; + OutData_Text[110] = SCE->REG_100H; + OutData_Text[111] = SCE->REG_100H; + OutData_Text[112] = SCE->REG_100H; + OutData_Text[113] = SCE->REG_100H; + OutData_Text[114] = SCE->REG_100H; + OutData_Text[115] = SCE->REG_100H; + OutData_Text[116] = SCE->REG_100H; + OutData_Text[117] = SCE->REG_100H; + OutData_Text[118] = SCE->REG_100H; + OutData_Text[119] = SCE->REG_100H; + OutData_Text[120] = SCE->REG_100H; + OutData_Text[121] = SCE->REG_100H; + OutData_Text[122] = SCE->REG_100H; + OutData_Text[123] = SCE->REG_100H; + OutData_Text[124] = SCE->REG_100H; + OutData_Text[125] = SCE->REG_100H; + OutData_Text[126] = SCE->REG_100H; + OutData_Text[127] = SCE->REG_100H; + HW_SCE_p_func102(0xd5b1053bu, 0x51915abdu, 0x25d683eeu, 0x9890acd5u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p7b_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c new file mode 100644 index 000000000..7f0c17346 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9a.c @@ -0,0 +1,682 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009a01u; + SCE->REG_108H = 0x00000000u; + SCE->REG_28H = 0x00870001u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010380u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_104H = 0x00000f68u; + SCE->REG_E0H = 0x8090001eu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop + 0]; + } + for (iLoop = 0; iLoop < 2; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000d3e0u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x000037beu; + SCE->REG_ECH = 0x0000a7a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000383du; + SCE->REG_ECH = 0x38001001u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000a7c0u; + SCE->REG_ECH = 0x00000020u; + } + SCE->REG_ECH = 0x30000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d3e1u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x38000f9cu; + SCE->REG_ECH = 0x1000d3e1u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x9f58c96cu, 0x24afabb1u, 0xd7924d6du, 0xffcb5f05u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xe52fe7beu, 0x50ce0297u, 0xd96d5fb9u, 0x734916fbu); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009au); + HW_SCE_p_func101(0x6026ca65u, 0x5c1ca45du, 0x10ae9afcu, 0x9e7b87b4u); + HW_SCE_p_func043(); + HW_SCE_p_func074_r1(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009au); + HW_SCE_p_func101(0x832ab6cbu, 0xf2fc811cu, 0x465c0d18u, 0x085b85d7u); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000011u; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x3d38fe92u, 0x745739efu, 0x96383b59u, 0x1fcc88e9u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x71c33e0du, 0xb021c479u, 0x6b63089eu, 0x571fde41u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x86959a7cu, 0xa4eed527u, 0xeeec7768u, 0xff9ea61bu); + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000004C8u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000031Cu; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000013Cu; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000001F8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x1ed97c6fu, 0x109d0bc2u, 0xfa651f26u, 0xf32e898eu); + HW_SCE_p_func070_r2(OFS_ADR); + HW_SCE_p_func100(0xd1fe94f1u, 0x147cf197u, 0xf1f0ff33u, 0xab3dc8c1u); + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000dcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000820u; + SCE->REG_24H = 0x80009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x0000009au; + SCE->REG_ECH = 0x0000377cu; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xae6f33b4u, 0x064fc23eu, 0x7a4c092bu, 0xd9ff2a9eu); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xf42c3d9eu, 0x179e2b97u, 0xac23a620u, 0xc94db83bu); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xfa0e2dd1u, 0x0d9f7059u, 0xe5c47b66u, 0x1267bf4fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xd1535a62u, 0x712ffe15u, 0x35a7c325u, 0xaec12d1fu); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0xbfa07cbbu, 0x892d135cu, 0x6f39790au, 0x1ebe4fcbu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xcd606843u, 0x98cbb1f5u, 0x4052dda2u, 0x61b8fdd1u); + } + else + { + HW_SCE_p_func101(0x0ce52ca3u, 0x9ceedb58u, 0x5f26d152u, 0x98cc1206u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x84355fe5u, 0xb797abfcu, 0xc5bc5e73u, 0xf3cdaec0u); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func301(); + HW_SCE_p_func100(0x0c5448bdu, 0xe38e6a0du, 0xbc1dc8f3u, 0xc7fa8025u); + SCE->REG_2CH = 0x00000022u; + SCE->REG_04H = 0x00000322u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_R[0] = SCE->REG_100H; + OutData_R[1] = SCE->REG_100H; + OutData_R[2] = SCE->REG_100H; + OutData_R[3] = SCE->REG_100H; + OutData_R[4] = SCE->REG_100H; + OutData_R[5] = SCE->REG_100H; + OutData_R[6] = SCE->REG_100H; + OutData_R[7] = SCE->REG_100H; + HW_SCE_p_func100(0x11f40d9du, 0xc57e5588u, 0x575e1647u, 0x235ad24bu); + SCE->REG_2CH = 0x00000023u; + SCE->REG_04H = 0x00000322u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_R[8] = SCE->REG_100H; + OutData_R[9] = SCE->REG_100H; + OutData_R[10] = SCE->REG_100H; + OutData_R[11] = SCE->REG_100H; + OutData_R[12] = SCE->REG_100H; + OutData_R[13] = SCE->REG_100H; + OutData_R[14] = SCE->REG_100H; + OutData_R[15] = SCE->REG_100H; + HW_SCE_p_func102(0x69e7c53au, 0x0f736cf0u, 0xc4577672u, 0x449008dcu); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p9a_r3.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c new file mode 100644 index 000000000..f59270e1d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_p9b.c @@ -0,0 +1,614 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009b01u; + SCE->REG_108H = 0x00000000u; + SCE->REG_28H = 0x008b0001u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009bu); + HW_SCE_p_func101(0x05ccca86u, 0xc9809ae4u, 0x1b82b071u, 0xab553c28u); + HW_SCE_p_func043(); + HW_SCE_p_func076(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x0000009bu); + HW_SCE_p_func101(0xba343e79u, 0xfe31a1f3u, 0x7dbd0515u, 0xb71fd7bau); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000b62u; + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x02f087b7u; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x00000011u; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xa67b83a2u, 0xc869f5b9u, 0x79ac9b3au, 0x05db1be5u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf1c61cd6u, 0x638a9ff7u, 0x30d2fddfu, 0x66063230u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x4d994ba1u, 0x0e83dd5fu, 0x1ad395aeu, 0xf05795a2u); + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000002B4u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000003D8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x7c3c2b42u, 0x77da4ba5u, 0xdd828a5fu, 0xf0ae4b81u); + HW_SCE_p_func027_r2(OFS_ADR); + HW_SCE_p_func100(0xada38979u, 0x5574dcfbu, 0xcbcebb86u, 0x44cc9663u); + SCE->REG_24H = 0x0000dcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000820u; + SCE->REG_24H = 0x80009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00000b67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + SCE->REG_100H = InData_PubKey[1]; + SCE->REG_100H = InData_PubKey[2]; + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_100H = InData_PubKey[4]; + SCE->REG_100H = InData_PubKey[5]; + SCE->REG_100H = InData_PubKey[6]; + SCE->REG_100H = InData_PubKey[7]; + SCE->REG_100H = InData_PubKey[8]; + SCE->REG_100H = InData_PubKey[9]; + SCE->REG_100H = InData_PubKey[10]; + SCE->REG_100H = InData_PubKey[11]; + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00000b67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[12]; + SCE->REG_100H = InData_PubKey[13]; + SCE->REG_100H = InData_PubKey[14]; + SCE->REG_100H = InData_PubKey[15]; + SCE->REG_100H = InData_PubKey[16]; + SCE->REG_100H = InData_PubKey[17]; + SCE->REG_100H = InData_PubKey[18]; + SCE->REG_100H = InData_PubKey[19]; + SCE->REG_100H = InData_PubKey[20]; + SCE->REG_100H = InData_PubKey[21]; + SCE->REG_100H = InData_PubKey[22]; + SCE->REG_100H = InData_PubKey[23]; + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000180u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x0000009bu; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xd1a20304u, 0x7ec5a832u, 0xfe786d80u, 0x8db0ff21u); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xd89c8381u, 0xd1f4a61cu, 0x434fe417u, 0x7150d01du); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x62b875dcu, 0x77b1bd44u, 0x9da356ddu, 0x268018dbu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x142493c0u, 0x7f78d4e0u, 0xc34d38b2u, 0x5166c60eu); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x6dfda009u, 0xdb9d8c6fu, 0x5f3558dfu, 0x4eeb90f1u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x97eb165fu, 0x003b8d10u, 0xd9f32031u, 0xa635451cu); + } + else + { + HW_SCE_p_func101(0x3775974eu, 0xfd8b4302u, 0x33a3cd37u, 0x5bcc8a49u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0xa93bfadeu, 0x9ae6845au, 0x6ec11109u, 0x707f0125u); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000030u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func301(); + HW_SCE_p_func100(0x036d9c54u, 0xe4a2ebc2u, 0x357cde20u, 0xd1165e27u); + SCE->REG_2CH = 0x00000022u; + SCE->REG_04H = 0x00000332u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_R[0] = SCE->REG_100H; + OutData_R[1] = SCE->REG_100H; + OutData_R[2] = SCE->REG_100H; + OutData_R[3] = SCE->REG_100H; + OutData_R[4] = SCE->REG_100H; + OutData_R[5] = SCE->REG_100H; + OutData_R[6] = SCE->REG_100H; + OutData_R[7] = SCE->REG_100H; + OutData_R[8] = SCE->REG_100H; + OutData_R[9] = SCE->REG_100H; + OutData_R[10] = SCE->REG_100H; + OutData_R[11] = SCE->REG_100H; + HW_SCE_p_func100(0x05a57fffu, 0x0c4047f5u, 0xb8df91a5u, 0x33f572e9u); + SCE->REG_2CH = 0x00000023u; + SCE->REG_04H = 0x00000332u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_R[12] = SCE->REG_100H; + OutData_R[13] = SCE->REG_100H; + OutData_R[14] = SCE->REG_100H; + OutData_R[15] = SCE->REG_100H; + OutData_R[16] = SCE->REG_100H; + OutData_R[17] = SCE->REG_100H; + OutData_R[18] = SCE->REG_100H; + OutData_R[19] = SCE->REG_100H; + OutData_R[20] = SCE->REG_100H; + OutData_R[21] = SCE->REG_100H; + OutData_R[22] = SCE->REG_100H; + OutData_R[23] = SCE->REG_100H; + HW_SCE_p_func102(0xd6535d3fu, 0x32ed02a4u, 0xf2ad998eu, 0x83ac46d5u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_p9b_r2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c new file mode 100644 index 000000000..95c0c992a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pe2.c @@ -0,0 +1,639 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t *InData_PreMasterSecret, uint32_t *OutData_PreMasterSecret) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000e201u; + SCE->REG_108H = 0x00000000u; + SCE->REG_C4H = 0x200e1a0du; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_RAM[16+0 + 0]; + SCE->REG_100H = S_RAM[16+0 + 1]; + SCE->REG_100H = S_RAM[16+0 + 2]; + SCE->REG_100H = S_RAM[16+0 + 3]; + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040000u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x00ff0000u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00050000u; + SCE->REG_ECH = 0x1000d3c0u; + SCE->REG_ECH = 0x3800d80fu; + SCE->REG_ECH = 0x2000d3c1u; + SCE->REG_ECH = 0x000037e0u; + SCE->REG_ECH = 0x00008fe0u; + SCE->REG_ECH = 0x000000ffu; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_ECH = 0x1000d3c2u; + SCE->REG_ECH = 0x38008bc0u; + SCE->REG_ECH = 0x00000007u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xd244310fu, 0x547e382fu, 0xb318a02du, 0x464efc11u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x2b469163u, 0xf6f625a5u, 0xdc4f65eau, 0xba0c2c3bu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_104H = 0x00000368u; + SCE->REG_E0H = 0x80040140u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[0]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[1]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[2]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[3]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e2u); + HW_SCE_p_func101(0xad6085ccu, 0x12c5aee4u, 0x062f76d2u, 0x4b1b7c5cu); + HW_SCE_p_func059(); + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x0154569cu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000e2u); + HW_SCE_p_func101(0x7075c45fu, 0x1a6cd664u, 0x19982f0cu, 0x6ac487efu); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000b62u; + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x02f087b7u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[4]; + SCE->REG_100H = InData_PreMasterSecret[5]; + SCE->REG_100H = InData_PreMasterSecret[6]; + SCE->REG_100H = InData_PreMasterSecret[7]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[8]; + SCE->REG_100H = InData_PreMasterSecret[9]; + SCE->REG_100H = InData_PreMasterSecret[10]; + SCE->REG_100H = InData_PreMasterSecret[11]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[12]; + SCE->REG_100H = InData_PreMasterSecret[13]; + SCE->REG_100H = InData_PreMasterSecret[14]; + SCE->REG_100H = InData_PreMasterSecret[15]; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x808c0004u; + SCE->REG_00H = 0x00008233u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PreMasterSecret[16]; + SCE->REG_100H = InData_PreMasterSecret[17]; + SCE->REG_100H = InData_PreMasterSecret[18]; + SCE->REG_100H = InData_PreMasterSecret[19]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xd487b857u, 0x9f922469u, 0x451b1220u, 0xfcede821u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xfb3a85c0u, 0xa030b5deu, 0x5f5e6b3fu, 0x927f1b5au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x00003540u; + SCE->REG_ECH = 0x00003561u; + SCE->REG_ECH = 0x00003582u; + SCE->REG_ECH = 0x000035a3u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000033u); + HW_SCE_p_func101(0x9713facau, 0x937b3cc7u, 0xbe78ed55u, 0xc139bf30u); + HW_SCE_p_func059(); + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func100(0x5e488b1du, 0xc49fa0bbu, 0x83027809u, 0x516eb597u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00008c00u; + SCE->REG_ECH = 0x0000ffffu; + SCE->REG_ECH = 0x00009000u; + SCE->REG_ECH = 0x00028080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_00H = 0x00003807u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x01020408u; + SCE->REG_ECH = 0x0000b4a0u; + SCE->REG_ECH = 0x10204080u; + SCE->REG_ECH = 0x0000b4c0u; + SCE->REG_ECH = 0x80200802u; + SCE->REG_ECH = 0x0000b4e0u; + SCE->REG_ECH = 0x40100401u; + SCE->REG_ECH = 0x00000bdeu; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 1) + { + HW_SCE_p_func100(0x8b40139du, 0xd6c54d3du, 0x6f325de6u, 0x8d189cc4u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80040000u; + SCE->REG_00H = 0x00008213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00001004u; + SCE->REG_ECH = 0x00001025u; + SCE->REG_ECH = 0x00001046u; + SCE->REG_ECH = 0x00001067u; + SCE->REG_E0H = 0x81040000u; + SCE->REG_00H = 0x00003813u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00002fc0u; + HW_SCE_p_func101(0x2382cdc1u, 0x4eacc78bu, 0x8824b301u, 0xe86064aeu); + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x0000000Cu; + SCE->REG_ECH = 0x38000bdfu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_1CH = 0x00402000u; + HW_SCE_p_func100(0x393cedfbu, 0x2b489645u, 0x0928e755u, 0x1d0d4efeu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80030000u; + SCE->REG_00H = 0x0000820fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00000207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00001004u; + SCE->REG_ECH = 0x00001025u; + SCE->REG_ECH = 0x00001046u; + SCE->REG_E0H = 0x80010140u; + SCE->REG_104H = 0x00000058u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xffffff00u); + SCE->REG_ECH = 0x00000c4au; + SCE->REG_E0H = 0x81030000u; + SCE->REG_00H = 0x0000380fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000070u; + SCE->REG_E0H = 0x818c0001u; + SCE->REG_00H = 0x00003833u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00008362u; + SCE->REG_D0H = 0x40001f00u; + SCE->REG_C4H = 0x02f087b7u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000014u; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+4 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00013203u; + SCE->REG_2CH = 0x00000012u; + for (iLoop = 0; iLoop < 64; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+68 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+68 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00f087b5u; + for (iLoop = 0; iLoop < 4; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[iLoop+132 + 0]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 1]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 2]; + SCE->REG_100H = InData_PubKey[iLoop+132 + 3]; + } + SCE->REG_E0H = 0x800100a0u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[136]; + SCE->REG_100H = InData_PubKey[137]; + SCE->REG_100H = InData_PubKey[138]; + SCE->REG_100H = InData_PubKey[139]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x140b5355u, 0xd93e8fc0u, 0xa2d44b0du, 0x34fee3cdu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5540526au, 0x26f6cb09u, 0x86e149a9u, 0x729f605eu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xe572cffbu, 0xf3bbd0b8u, 0xda874279u, 0x563805dbu); + SCE->REG_18H = 0x00000004u; + SCE->REG_34H = 0x00000000u; + SCE->REG_38H = 0x00000338u; + SCE->REG_E0H = 0x810100a0u; + SCE->REG_00H = 0x00003807u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_28H = 0x00bf0001u; + HW_SCE_p_func100(0x36d94340u, 0x4ed480ffu, 0xb1240401u, 0xfa036355u); + SCE->REG_2CH = 0x00000020u; + SCE->REG_04H = 0x00000302u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PreMasterSecret[0] = SCE->REG_100H; + OutData_PreMasterSecret[1] = SCE->REG_100H; + OutData_PreMasterSecret[2] = SCE->REG_100H; + OutData_PreMasterSecret[3] = SCE->REG_100H; + OutData_PreMasterSecret[4] = SCE->REG_100H; + OutData_PreMasterSecret[5] = SCE->REG_100H; + OutData_PreMasterSecret[6] = SCE->REG_100H; + OutData_PreMasterSecret[7] = SCE->REG_100H; + OutData_PreMasterSecret[8] = SCE->REG_100H; + OutData_PreMasterSecret[9] = SCE->REG_100H; + OutData_PreMasterSecret[10] = SCE->REG_100H; + OutData_PreMasterSecret[11] = SCE->REG_100H; + OutData_PreMasterSecret[12] = SCE->REG_100H; + OutData_PreMasterSecret[13] = SCE->REG_100H; + OutData_PreMasterSecret[14] = SCE->REG_100H; + OutData_PreMasterSecret[15] = SCE->REG_100H; + OutData_PreMasterSecret[16] = SCE->REG_100H; + OutData_PreMasterSecret[17] = SCE->REG_100H; + OutData_PreMasterSecret[18] = SCE->REG_100H; + OutData_PreMasterSecret[19] = SCE->REG_100H; + OutData_PreMasterSecret[20] = SCE->REG_100H; + OutData_PreMasterSecret[21] = SCE->REG_100H; + OutData_PreMasterSecret[22] = SCE->REG_100H; + OutData_PreMasterSecret[23] = SCE->REG_100H; + OutData_PreMasterSecret[24] = SCE->REG_100H; + OutData_PreMasterSecret[25] = SCE->REG_100H; + OutData_PreMasterSecret[26] = SCE->REG_100H; + OutData_PreMasterSecret[27] = SCE->REG_100H; + OutData_PreMasterSecret[28] = SCE->REG_100H; + OutData_PreMasterSecret[29] = SCE->REG_100H; + OutData_PreMasterSecret[30] = SCE->REG_100H; + OutData_PreMasterSecret[31] = SCE->REG_100H; + OutData_PreMasterSecret[32] = SCE->REG_100H; + OutData_PreMasterSecret[33] = SCE->REG_100H; + OutData_PreMasterSecret[34] = SCE->REG_100H; + OutData_PreMasterSecret[35] = SCE->REG_100H; + OutData_PreMasterSecret[36] = SCE->REG_100H; + OutData_PreMasterSecret[37] = SCE->REG_100H; + OutData_PreMasterSecret[38] = SCE->REG_100H; + OutData_PreMasterSecret[39] = SCE->REG_100H; + OutData_PreMasterSecret[40] = SCE->REG_100H; + OutData_PreMasterSecret[41] = SCE->REG_100H; + OutData_PreMasterSecret[42] = SCE->REG_100H; + OutData_PreMasterSecret[43] = SCE->REG_100H; + OutData_PreMasterSecret[44] = SCE->REG_100H; + OutData_PreMasterSecret[45] = SCE->REG_100H; + OutData_PreMasterSecret[46] = SCE->REG_100H; + OutData_PreMasterSecret[47] = SCE->REG_100H; + OutData_PreMasterSecret[48] = SCE->REG_100H; + OutData_PreMasterSecret[49] = SCE->REG_100H; + OutData_PreMasterSecret[50] = SCE->REG_100H; + OutData_PreMasterSecret[51] = SCE->REG_100H; + OutData_PreMasterSecret[52] = SCE->REG_100H; + OutData_PreMasterSecret[53] = SCE->REG_100H; + OutData_PreMasterSecret[54] = SCE->REG_100H; + OutData_PreMasterSecret[55] = SCE->REG_100H; + OutData_PreMasterSecret[56] = SCE->REG_100H; + OutData_PreMasterSecret[57] = SCE->REG_100H; + OutData_PreMasterSecret[58] = SCE->REG_100H; + OutData_PreMasterSecret[59] = SCE->REG_100H; + OutData_PreMasterSecret[60] = SCE->REG_100H; + OutData_PreMasterSecret[61] = SCE->REG_100H; + OutData_PreMasterSecret[62] = SCE->REG_100H; + OutData_PreMasterSecret[63] = SCE->REG_100H; + HW_SCE_p_func102(0x42190fa2u, 0x278edf46u, 0xcf71ae2du, 0x42257106u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pe2.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c new file mode 100644 index 000000000..73c7983cf --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf0.c @@ -0,0 +1,1598 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f001u; + SCE->REG_108H = 0x00000000u; + SCE->REG_28H = 0x00870001u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010380u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x0000b7c0u; + SCE->REG_ECH = 0x000000c0u; + SCE->REG_104H = 0x00000768u; + SCE->REG_E0H = 0x8088001eu; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[iLoop + 0]; + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000d3e0u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x000037beu; + SCE->REG_ECH = 0x0000a7a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000383du; + SCE->REG_ECH = 0x38001001u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x30000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d3e1u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x38000f9cu; + SCE->REG_ECH = 0x1000d3e1u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xf5d8c06eu, 0xc83bb08au, 0xae510efbu, 0x36a7af08u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x8f775961u, 0x0b5a28aau, 0x87943f60u, 0x0f2c8f26u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x405aceaau, 0x2e5e12d4u, 0x11fcc9ccu, 0xf58f11d1u); + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000004C8u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000031Cu; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000013Cu; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000001F8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x45761474u, 0x57cc450bu, 0x5ceb52e5u, 0x6b5c37e2u); + HW_SCE_p_func070_r2(OFS_ADR); + HW_SCE_p_func100(0x00613584u, 0x5c3272c3u, 0x996ad0bdu, 0x304f803du); + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func103(); + HW_SCE_p_func100(0x6805778au, 0x816c6846u, 0x3b6d78aeu, 0x3bcdbe72u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001228u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0xebac350fu, 0x45ec962fu, 0x32c6f830u, 0xe58ac3c3u); + HW_SCE_p_func071_r2(OFS_ADR); + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x8000acd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f0u; + SCE->REG_ECH = 0x0000373cu; + SCE->REG_ECH = 0x00000b9cu; + HW_SCE_p_func100(0xf3ab3173u, 0x27de0948u, 0x5353a013u, 0x2e638bd8u); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + HW_SCE_p_func101(0x3c677163u, 0xea4d3d2eu, 0xafceb4b7u, 0xe2e493feu); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xa7c1a7c6u, 0x18421ea5u, 0x850f9fdbu, 0xfaf97de6u); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xa9085fbeu, 0x25a8489cu, 0xe5f22119u, 0x0e253310u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x85ca9aa5u, 0x59e5f5b6u, 0x4e2034b2u, 0x9a0a1c47u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x32739d60u, 0x0e2671edu, 0x23998dfeu, 0x4f6c4200u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x8258f1e6u, 0x553b5587u, 0x4f1e0975u, 0xd75763f4u); + } + else + { + HW_SCE_p_func101(0x539fd0d3u, 0xea3031bau, 0x97e22ba0u, 0x5000a199u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x5919a370u, 0x0f6d04c5u, 0xce11e96au, 0x4d2ef3fau); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800016c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000ecd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000828u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xc94388e0u, 0x9a7e6cb9u, 0xce5c4ac7u, 0xb132c2d9u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x117e7a37u, 0xe9611638u, 0xe3b97e76u, 0xadd63588u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00000ac0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0xf488209bu, 0x8754f3d9u, 0x9dcac910u, 0x6a315209u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x564da9c0u, 0x175afa15u, 0xdb42594eu, 0x2a5f439fu); + } + else + { + HW_SCE_p_func101(0x707f79d8u, 0xf36e9205u, 0xc8bbbdfcu, 0xa87d56c3u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x4e12ae86u, 0x9ec13781u, 0x54edd46au, 0x1512b2b6u); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x000000c0u; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f0u); + HW_SCE_p_func101(0xf1d0563cu, 0xbbd53440u, 0x9277dcaau, 0xf580df08u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x00003799u; + HW_SCE_p_func074_r1(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f0u); + HW_SCE_p_func101(0xeb59fefbu, 0xc02a6ecbu, 0xdaec63f0u, 0x7971ef3du); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000762u; + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02f087b7u; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000018u; + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x8a7f35bcu, 0x18556ebdu, 0xb1818f43u, 0x312f0c9fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x508e103bu, 0x5176429fu, 0x3455628au, 0x1a3d6475u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x80000c2du; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x8000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x54820b6au, 0x3952524au, 0xa5020e8bu, 0x902155ffu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xca61be04u, 0xf4a62121u, 0x1d40756bu, 0x97a09354u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x64195d93u, 0xee1713e1u, 0x2b8c720bu, 0xb8b83929u); + SCE->REG_2CH = 0x0000002bu; + SCE->REG_04H = 0x00000322u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[0] = SCE->REG_100H; + OutData_Signature[1] = SCE->REG_100H; + OutData_Signature[2] = SCE->REG_100H; + OutData_Signature[3] = SCE->REG_100H; + OutData_Signature[4] = SCE->REG_100H; + OutData_Signature[5] = SCE->REG_100H; + OutData_Signature[6] = SCE->REG_100H; + OutData_Signature[7] = SCE->REG_100H; + HW_SCE_p_func100(0x7f837de5u, 0x2783bdc9u, 0x09f9efa6u, 0xdc30d0abu); + SCE->REG_2CH = 0x0000002au; + SCE->REG_04H = 0x00000322u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[8] = SCE->REG_100H; + OutData_Signature[9] = SCE->REG_100H; + OutData_Signature[10] = SCE->REG_100H; + OutData_Signature[11] = SCE->REG_100H; + OutData_Signature[12] = SCE->REG_100H; + OutData_Signature[13] = SCE->REG_100H; + OutData_Signature[14] = SCE->REG_100H; + OutData_Signature[15] = SCE->REG_100H; + HW_SCE_p_func102(0x582e0cefu, 0x9b53cdceu, 0x3672fe6du, 0x4599d89du); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf0_r4.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c new file mode 100644 index 000000000..5ebc50ca4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf1.c @@ -0,0 +1,2605 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_EcdsaSigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f101u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010380u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_104H = 0x00001768u; + SCE->REG_E0H = 0x8098001eu; + for (iLoop = 0; iLoop < 16; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[iLoop + 0]; + } + for (iLoop = 0; iLoop < 8; iLoop = iLoop + 1) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[iLoop + 0]; + } + for (iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000d3e0u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x38000c00u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000381eu; + SCE->REG_ECH = 0x000037beu; + SCE->REG_ECH = 0x0000a7a0u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000383du; + SCE->REG_ECH = 0x38001001u; + SCE->REG_ECH = 0x1000d3e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38000fffu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00260000u; + SCE->REG_ECH = 0x0000a7c0u; + SCE->REG_ECH = 0x00000020u; + } + SCE->REG_ECH = 0x30000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d3e1u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x38000f9cu; + SCE->REG_ECH = 0x1000d3e1u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0xb3a4bb56u, 0x412a388cu, 0x4f9be231u, 0xe3706b28u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x0ea78a51u, 0xe36bea34u, 0xc54dd04cu, 0xa2ffc22au); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_28H = 0x00870001u; + HW_SCE_p_func100(0x55305e12u, 0x530c0fb5u, 0x1c13599eu, 0x4532a352u); + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000004C8u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000031Cu; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000013Cu; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000001F8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x8f8943c0u, 0x598761b3u, 0xe9847b6eu, 0x8453ab3eu); + HW_SCE_p_func070_r2(OFS_ADR); + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000bcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8190001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000015u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000140u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x590b209bu, 0xc82029c5u, 0x60cf2f49u, 0x6b7025c3u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf6aee8c1u, 0x440d430du, 0x36ee5c4eu, 0x8625dc70u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x2201181cu, 0x9eb62239u, 0x8daf8909u, 0x42c0e057u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xce3c73fbu, 0x286447d7u, 0x58f537c8u, 0xfb51f8bfu); + } + else + { + HW_SCE_p_func101(0xfcf15e4du, 0xa058aa75u, 0x613ad247u, 0x512b85e6u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x3c499c8au, 0x6ea4ec8fu, 0x030ea18cu, 0x70d4f24fu); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000120u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func100(0x7d936becu, 0xe1c658d1u, 0xd42327a8u, 0x9d36429eu); + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000094au; + SCE->REG_E0H = 0x8088000au; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000094d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x8000d4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func071_r2(OFS_ADR); + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x8000acd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x8088000au; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000025u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f1u; + SCE->REG_ECH = 0x0000377cu; + SCE->REG_ECH = 0x00000b9cu; + HW_SCE_p_func100(0x60e62d54u, 0x797b21c9u, 0x1e8cd1c3u, 0xd81aced7u); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xf6ba2066u, 0x71c4054cu, 0x82369773u, 0x52f78ec2u); + HW_SCE_p_func302(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0x3bbc5587u, 0x0ec4b9dfu, 0xfc6d0c6au, 0x4b97b23cu); + } + SCE->REG_ECH = 0x00000a73u; + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x81880013u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x55b2bd60u, 0x788ffd90u, 0x69408616u, 0x9bf25968u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xbc5993a1u, 0x4614565bu, 0x1e1848c2u, 0xbf3b91dfu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x9392224cu, 0x4611f3adu, 0x503f7b17u, 0x7545889cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xa70971feu, 0x5d3a322cu, 0xdd3f98e8u, 0x8d873476u); + } + else + { + HW_SCE_p_func101(0xdd8687b0u, 0xce2201d7u, 0xba53b658u, 0xeab59d81u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x2957d6f7u, 0x2f37a3cdu, 0x94d16a5fu, 0x7d4f21fcu); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000120u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000379bu; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f1u); + HW_SCE_p_func101(0xa2143480u, 0xab721c7du, 0x400794fbu, 0x90b7f286u); + HW_SCE_p_func043(); + HW_SCE_p_func075_r1(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f1u); + HW_SCE_p_func101(0xdfb7aecbu, 0x249b9e49u, 0xbd4f48f9u, 0x09ce82beu); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00000f62u; + SCE->REG_D0H = 0x40000300u; + SCE->REG_C4H = 0x02e08887u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_00H = 0x00003223u; + SCE->REG_2CH = 0x0000001bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xcde594d5u, 0x132b8725u, 0xbc346b76u, 0xb366788au); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x1f11c475u, 0x7cc92153u, 0x52eadf9eu, 0xee64c69bu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x8088000au; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x000000C0u; + SCE->REG_E0H = 0x8088000au; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x00000001u; + SCE->REG_ECH = 0x00000b9cu; + HW_SCE_p_func100(0x26f45b8bu, 0x622dcf12u, 0x37ebeb9au, 0x07bc3f54u); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xfa6fa228u, 0xead297ceu, 0x1fc0b519u, 0x12a298ecu); + HW_SCE_p_func302(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xf284d5a3u, 0x6e54b6ddu, 0x2b8ba9d2u, 0x19948033u); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xfff9e72au, 0x6a9b2259u, 0x9b87326cu, 0x07f21f83u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x7bf8560fu, 0x90b8357bu, 0x986d0b9eu, 0x78964becu); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81880013u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x000000C0u; + SCE->REG_E0H = 0x81880013u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x0000001bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000a41u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x900019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xf8dae94fu, 0x10eb8740u, 0xd99a2a7fu, 0x5994642eu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x3ebc5aabu, 0xb88b7fd2u, 0x30e22266u, 0xd261e34du); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_34H = 0x00000003u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0xa674de4bu, 0x7cfddb14u, 0x04a7a5f9u, 0xe48f30a2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x7073dd36u, 0x2dd6f3acu, 0xc91b5027u, 0xd78a65c5u); + } + else + { + HW_SCE_p_func101(0x92571603u, 0xfcfec157u, 0x36856296u, 0x6a9eb6b0u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x953447d6u, 0x130e6df0u, 0x513a9531u, 0xcf569436u); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000120u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000140u; + SCE->REG_E0H = 0x8188001fu; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x81880013u; + SCE->REG_00H = 0x00003823u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x0407c0bdu, 0x083c771au, 0xf0b7db95u, 0xc265fa8cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x85746d5fu, 0x25b93196u, 0x52b9dc3eu, 0x9cbb1883u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x06dfc759u, 0xb0c6aaa4u, 0x39be31bcu, 0x42fe0748u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf1_r3.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c new file mode 100644 index 000000000..9668b3da8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf4.c @@ -0,0 +1,850 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1BCH & 0x1fu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f401u; + SCE->REG_108H = 0x00000000u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010380u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Cmd[0]; + SCE->REG_ECH = 0x3020ab80u; + SCE->REG_ECH = 0x00000003u; + SCE->REG_ECH = 0x00060020u; + SCE->REG_ECH = 0x0000b780u; + SCE->REG_ECH = 0x00000002u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_ECH = 0x30000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000d3e1u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x38000f9cu; + SCE->REG_ECH = 0x1000d3e1u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x38008be0u; + SCE->REG_ECH = 0x00000002u; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + HW_SCE_p_func100(0x61eee86cu, 0xcb13e52eu, 0x0959472eu, 0x7f912219u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x874384e1u, 0x11b1983eu, 0x04bc55c7u, 0x166a1ad8u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xcee8c68fu, 0xd879df00u, 0x95b02707u, 0x7b8cb6deu); + SCE->REG_28H = 0x00870001u; + SCE->REG_ECH = 0x30003340u; + SCE->REG_ECH = 0x00050020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000004C8u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000031Cu; + SCE->REG_ECH = 0x00070040u; + SCE->REG_ECH = 0x30003380u; + SCE->REG_ECH = 0x00070020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00030040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x0000013Cu; + SCE->REG_ECH = 0x00050040u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000001F8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x46096261u, 0x56f41cd7u, 0x90a6aef4u, 0x6a809daau); + HW_SCE_p_func070_r2(OFS_ADR); + HW_SCE_p_func100(0xb2df82d6u, 0xd8db101eu, 0x46294cb8u, 0xeff1925au); + SCE->REG_34H = 0x00000400u; + SCE->REG_24H = 0x8000c0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00890001u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0x53bc48e0u, 0xf409e715u, 0x3c15c334u, 0x23cadbe8u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0x02dd0676u, 0x9678ebe1u, 0x10c7b8d2u, 0x520bc80fu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0xe1e50ca9u, 0x5e876405u, 0xe9d604d9u, 0xb03217d0u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x0000320bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00007c1cu; + SCE->REG_1CH = 0x00600000u; + SCE->REG_1D0H = 0x00000000u; + if (0x00000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_28H = 0x00890001u; + HW_SCE_p_func101(0x27e9ba0cu, 0xc682106bu, 0x0e239312u, 0x450aa767u); + } + else if (0x01000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_28H = 0x00880001u; + HW_SCE_p_func101(0x8f7dfdc3u, 0x6faa8ac8u, 0x1c6cf5fcu, 0x09387fffu); + } + else if (0x02000000u == (SCE->REG_1CH & 0xff000000u)) + { + SCE->REG_28H = 0x00870001u; + HW_SCE_p_func101(0x19521efau, 0x2f282005u, 0x0ae78c0du, 0x94ed7e6bu); + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004u; + SCE->REG_24H = 0x0000a206u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_24H = 0x000016c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000682u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x00870001u; + SCE->REG_24H = 0x0000dcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000820u; + SCE->REG_24H = 0x80009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0xb0cc8c1au, 0xdabf4f6eu, 0x50ddfd40u, 0x55d7e34fu); + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func071_r2(OFS_ADR); + HW_SCE_p_func100(0x40c0ae57u, 0x29ba04aeu, 0xc761c11eu, 0x1bd201abu); + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x8000acd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f4u; + SCE->REG_ECH = 0x0000377cu; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<256;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xc75067e4u, 0x65f5d835u, 0x270dd151u, 0x1ff8007fu); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0x8e822641u, 0xa560dfdbu, 0xcd8aa6f6u, 0x7ac6e030u); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xe2066680u, 0xf0184b25u, 0xf343846fu, 0xa63764f2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x4356149eu, 0x5afb71ceu, 0xe511df28u, 0xdd8745e2u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000f4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x8088001fu; + SCE->REG_00H = 0x00008323u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<8; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x837faa79u, 0xae805b51u, 0xa4f2c9bfu, 0x7ffc4df8u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xaeabc302u, 0x1b959fdcu, 0xd1c51b83u, 0x95ab024fu); + } + else + { + HW_SCE_p_func101(0xbf206840u, 0x607bab5du, 0x9367a3bfu, 0x193a6d4au); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x4a374666u, 0x52864535u, 0xc339c67cu, 0x34409fbau); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000020u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func301(); + HW_SCE_p_func100(0xab9d9720u, 0xdce394c1u, 0xf00a566cu, 0x266678d5u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f4u); + HW_SCE_p_func101(0xd8882ff8u, 0xb938c560u, 0x5d570822u, 0x3cd2ca54u); + HW_SCE_p_func043(); + SCE->REG_ECH = 0x0000379bu; + HW_SCE_p_func074_r1(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f4u); + HW_SCE_p_func101(0xb255d103u, 0xd13ef5d2u, 0x45974775u, 0xadde338bu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x0e9623e0u, 0xf58c286au, 0xf778486au, 0x4df18dd9u); + SCE->REG_D0H = 0x40000100u; + SCE->REG_C4H = 0x02e087b7u; + SCE->REG_00H = 0x00002323u; + SCE->REG_2CH = 0x0000002du; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000222u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[1] = SCE->REG_100H; + OutData_PrivKeyIndex[2] = SCE->REG_100H; + OutData_PrivKeyIndex[3] = SCE->REG_100H; + OutData_PrivKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[5] = SCE->REG_100H; + OutData_PrivKeyIndex[6] = SCE->REG_100H; + OutData_PrivKeyIndex[7] = SCE->REG_100H; + OutData_PrivKeyIndex[8] = SCE->REG_100H; + HW_SCE_p_func100(0x3019d35cu, 0x645ddc1du, 0x35918009u, 0x199ce470u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[9] = SCE->REG_100H; + OutData_PrivKeyIndex[10] = SCE->REG_100H; + OutData_PrivKeyIndex[11] = SCE->REG_100H; + OutData_PrivKeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func100(0x425dd56du, 0xaab5a89cu, 0x75d7c47fu, 0xdacdb289u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0xec71435au, 0x62d6e866u, 0xaca8918du, 0x3c88529au); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000001u); + HW_SCE_p_func101(0x878f63fdu, 0x1d540d16u, 0x7ec1ac78u, 0xb20bf112u); + HW_SCE_p_func043(); + HW_SCE_p_func075_r1(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000002u); + HW_SCE_p_func101(0xb177a360u, 0xa939f773u, 0x7d142f97u, 0x6344bcedu); + HW_SCE_p_func044(); + HW_SCE_p_func100(0xbb1bd422u, 0xef8c3c92u, 0x4cd047dau, 0x8a62dbe3u); + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_00H = 0x00002323u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x00002313u; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[1] = SCE->REG_100H; + OutData_PubKeyIndex[2] = SCE->REG_100H; + OutData_PubKeyIndex[3] = SCE->REG_100H; + OutData_PubKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[5] = SCE->REG_100H; + OutData_PubKeyIndex[6] = SCE->REG_100H; + OutData_PubKeyIndex[7] = SCE->REG_100H; + OutData_PubKeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[9] = SCE->REG_100H; + OutData_PubKeyIndex[10] = SCE->REG_100H; + OutData_PubKeyIndex[11] = SCE->REG_100H; + OutData_PubKeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func100(0x5ca913fau, 0x6604aba7u, 0x5e907a49u, 0xe6ac5f43u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x00e08885u; + SCE->REG_00H = 0x00002313u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_04H = 0x00000222u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[13] = SCE->REG_100H; + OutData_PubKeyIndex[14] = SCE->REG_100H; + OutData_PubKeyIndex[15] = SCE->REG_100H; + OutData_PubKeyIndex[16] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[17] = SCE->REG_100H; + OutData_PubKeyIndex[18] = SCE->REG_100H; + OutData_PubKeyIndex[19] = SCE->REG_100H; + OutData_PubKeyIndex[20] = SCE->REG_100H; + HW_SCE_p_func100(0xa27751c1u, 0x16ee123cu, 0x8536a299u, 0x3fe25d73u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func102(0xd6c43818u, 0xa89dde83u, 0x15a5cc4au, 0x12255586u); + SCE->REG_1BCH = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf4_r3.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c new file mode 100644 index 000000000..d8c8dfa38 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf5.c @@ -0,0 +1,1543 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f501u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0xa7f12ee1u, 0x27da227du, 0x9461ff19u, 0x6881bdbdu); + SCE->REG_28H = 0x008b0001u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000002B4u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000003D8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0xf46088a1u, 0xf9dbfbbbu, 0xb25ee1f4u, 0x85dd652du); + HW_SCE_p_func027_r2(OFS_ADR); + HW_SCE_p_func100(0xd55c4eb5u, 0x7f198c94u, 0x721f4f41u, 0x1814ae3du); + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func103(); + HW_SCE_p_func100(0xa166c3d1u, 0x63f3e146u, 0x3407e331u, 0x077ac6f2u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xbb59feb0u, 0x4dfb2a9bu, 0x836cc811u, 0x64f2af03u); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001228u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0x41d0bf49u, 0xaa66c69au, 0xf4980677u, 0xfd0c6fa7u); + HW_SCE_p_func028_r2(OFS_ADR); + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x8000acd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000020u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00005cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000180u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f5u; + SCE->REG_ECH = 0x00000b9cu; + HW_SCE_p_func100(0xfc034238u, 0xa16bf6e9u, 0xd5414d16u, 0x07a0874eu); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + HW_SCE_p_func101(0x756940cau, 0x38631cc2u, 0x3a832969u, 0x9de523a9u); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xc2cd7dc5u, 0x4cea4522u, 0xfd87c0a8u, 0x03011e3au); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x39c0dc33u, 0x9bcb18aau, 0x36173556u, 0x886fc9aeu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x11db319au, 0x49dca8d9u, 0x36d85a2fu, 0x6b6d45e6u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x04116ab8u, 0xf01acb4du, 0x8c467b1eu, 0x3d7c1bc3u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x0e9406bfu, 0x21a9c2a2u, 0xf4105826u, 0xfc3f06f7u); + } + else + { + HW_SCE_p_func101(0x72a17c90u, 0x7c36ae1eu, 0xb595c4e4u, 0xae6a585au); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x812e0e4eu, 0x578b4115u, 0x11558fe1u, 0x2dc4c15bu); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000030u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x818c001fu; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800016c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x818c001fu; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c04u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000ecd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000828u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0xcf6556d4u, 0xf5d2420bu, 0xc8dde221u, 0x0d9cb2c7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x7fcc5618u, 0x320d458du, 0x741a2441u, 0x37fd27f7u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00000ac0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0xdb684c16u, 0xad882196u, 0x69ddeeb8u, 0x68182e14u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x09cb3c18u, 0x5022d562u, 0xbc96621fu, 0x02f4e99eu); + } + else + { + HW_SCE_p_func101(0xc154907du, 0x3be52efcu, 0xcaee0c01u, 0x3cc1eca4u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0xc37a8313u, 0x7f7e61f2u, 0xcf184d70u, 0xad35711du); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000030u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000011u; + SCE->REG_104H = 0x00000b67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[0]; + SCE->REG_100H = InData_MsgDgst[1]; + SCE->REG_100H = InData_MsgDgst[2]; + SCE->REG_100H = InData_MsgDgst[3]; + SCE->REG_100H = InData_MsgDgst[4]; + SCE->REG_100H = InData_MsgDgst[5]; + SCE->REG_100H = InData_MsgDgst[6]; + SCE->REG_100H = InData_MsgDgst[7]; + SCE->REG_100H = InData_MsgDgst[8]; + SCE->REG_100H = InData_MsgDgst[9]; + SCE->REG_100H = InData_MsgDgst[10]; + SCE->REG_100H = InData_MsgDgst[11]; + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000020u; + SCE->REG_24H = 0x80001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f5u); + HW_SCE_p_func101(0x596a904bu, 0x3314484cu, 0xcdb16c37u, 0xa8077997u); + HW_SCE_p_func043(); + HW_SCE_p_func076(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f5u); + HW_SCE_p_func101(0xf196b0d1u, 0x2c071f11u, 0xef46062du, 0xe381c81du); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000b62u; + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x02f087b7u; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x00000018u; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + } + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+1 + 3]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0x040820f3u, 0x57958e1eu, 0xf4199077u, 0x88f0a702u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x5d4fa2dcu, 0x09346111u, 0xd90d7c4fu, 0x3877f5dau); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x80000c2du; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x8000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x47e77302u, 0xe077a25cu, 0xdb1110c9u, 0x5aa753c7u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x793d7493u, 0x9ec5b3eau, 0xb0aa4fc7u, 0x0c1c8446u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x146cf125u, 0xea842b6au, 0xe3494589u, 0xda9fcd01u); + SCE->REG_2CH = 0x0000002bu; + SCE->REG_04H = 0x00000332u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[0] = SCE->REG_100H; + OutData_Signature[1] = SCE->REG_100H; + OutData_Signature[2] = SCE->REG_100H; + OutData_Signature[3] = SCE->REG_100H; + OutData_Signature[4] = SCE->REG_100H; + OutData_Signature[5] = SCE->REG_100H; + OutData_Signature[6] = SCE->REG_100H; + OutData_Signature[7] = SCE->REG_100H; + OutData_Signature[8] = SCE->REG_100H; + OutData_Signature[9] = SCE->REG_100H; + OutData_Signature[10] = SCE->REG_100H; + OutData_Signature[11] = SCE->REG_100H; + HW_SCE_p_func100(0xd530f48bu, 0x02e526f6u, 0x375ec265u, 0x6eb53f6fu); + SCE->REG_2CH = 0x0000002au; + SCE->REG_04H = 0x00000332u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[12] = SCE->REG_100H; + OutData_Signature[13] = SCE->REG_100H; + OutData_Signature[14] = SCE->REG_100H; + OutData_Signature[15] = SCE->REG_100H; + OutData_Signature[16] = SCE->REG_100H; + OutData_Signature[17] = SCE->REG_100H; + OutData_Signature[18] = SCE->REG_100H; + OutData_Signature[19] = SCE->REG_100H; + OutData_Signature[20] = SCE->REG_100H; + OutData_Signature[21] = SCE->REG_100H; + OutData_Signature[22] = SCE->REG_100H; + OutData_Signature[23] = SCE->REG_100H; + HW_SCE_p_func102(0x58b223e8u, 0x9262ba2cu, 0x01fed64bu, 0x9da18bd7u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf5_r4.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c new file mode 100644 index 000000000..de7075541 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf6.c @@ -0,0 +1,2581 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_EcdsaP384SigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f601u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0xde86a436u, 0x5028d235u, 0xd797fae2u, 0xe51894ddu); + SCE->REG_28H = 0x008b0001u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000002B4u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000003D8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x50f75db7u, 0x80f401ceu, 0x2b894e39u, 0xb0cb9752u); + HW_SCE_p_func027_r2(OFS_ADR); + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x80006cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000bcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000015u; + SCE->REG_104H = 0x00000b67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[0]; + SCE->REG_100H = InData_Signature[1]; + SCE->REG_100H = InData_Signature[2]; + SCE->REG_100H = InData_Signature[3]; + SCE->REG_100H = InData_Signature[4]; + SCE->REG_100H = InData_Signature[5]; + SCE->REG_100H = InData_Signature[6]; + SCE->REG_100H = InData_Signature[7]; + SCE->REG_100H = InData_Signature[8]; + SCE->REG_100H = InData_Signature[9]; + SCE->REG_100H = InData_Signature[10]; + SCE->REG_100H = InData_Signature[11]; + SCE->REG_2CH = 0x00000010u; + SCE->REG_104H = 0x00000b67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[12]; + SCE->REG_100H = InData_Signature[13]; + SCE->REG_100H = InData_Signature[14]; + SCE->REG_100H = InData_Signature[15]; + SCE->REG_100H = InData_Signature[16]; + SCE->REG_100H = InData_Signature[17]; + SCE->REG_100H = InData_Signature[18]; + SCE->REG_100H = InData_Signature[19]; + SCE->REG_100H = InData_Signature[20]; + SCE->REG_100H = InData_Signature[21]; + SCE->REG_100H = InData_Signature[22]; + SCE->REG_100H = InData_Signature[23]; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000140u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000024u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x00000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x48dc9437u, 0x7d99e59au, 0x359b6d56u, 0x26bc5175u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xb0a214e8u, 0x3ea6e6fdu, 0x18a83f65u, 0x349085f8u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x4f50ce7au, 0x5b245d5du, 0x09650643u, 0x292d4bbfu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0xbfbe8c9cu, 0x3d95ed3cu, 0x3cf22247u, 0xa53ed86cu); + } + else + { + HW_SCE_p_func101(0xc389e42cu, 0x971fe1eau, 0xd116d4fcu, 0x87c07bd4u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x89976506u, 0x0f51be2du, 0x4581d2b3u, 0x31ad08acu); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000130u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func100(0x6e827556u, 0x95f748d3u, 0x599c27e2u, 0x22b78e38u); + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000011u; + SCE->REG_104H = 0x00000b67u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[0]; + SCE->REG_100H = InData_MsgDgst[1]; + SCE->REG_100H = InData_MsgDgst[2]; + SCE->REG_100H = InData_MsgDgst[3]; + SCE->REG_100H = InData_MsgDgst[4]; + SCE->REG_100H = InData_MsgDgst[5]; + SCE->REG_100H = InData_MsgDgst[6]; + SCE->REG_100H = InData_MsgDgst[7]; + SCE->REG_100H = InData_MsgDgst[8]; + SCE->REG_100H = InData_MsgDgst[9]; + SCE->REG_100H = InData_MsgDgst[10]; + SCE->REG_100H = InData_MsgDgst[11]; + SCE->REG_ECH = 0x0000094au; + SCE->REG_E0H = 0x808c000au; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000094d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x8000d4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func028_r2(OFS_ADR); + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x8000acd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x808c000au; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000025u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000180u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f6u; + SCE->REG_ECH = 0x00000b9cu; + HW_SCE_p_func100(0x207fcddau, 0x5d1f4932u, 0x025fe82bu, 0x311610c3u); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + HW_SCE_p_func101(0x343faaa0u, 0xc8a220e1u, 0x9e286aadu, 0x12ebe9cfu); + HW_SCE_p_func302(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xfe611096u, 0xf63529f2u, 0x1bc80c49u, 0xb74546a0u); + } + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x818c0013u; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x77781b31u, 0x7ee34842u, 0x3e67a132u, 0x866f6dffu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x0d2df2eau, 0xcafdcc6du, 0x4b14a008u, 0xeecb2b39u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004804u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x1f9de355u, 0x2cf5dd10u, 0xafc11e8cu, 0x2e0989d4u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x63ed1c79u, 0x60fce20bu, 0xfd1676abu, 0x4b71e169u); + } + else + { + HW_SCE_p_func101(0xf236aa04u, 0xdba8fd83u, 0xf47ee85eu, 0x10f90084u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x09d2c05eu, 0xfc984d92u, 0xe5594ea9u, 0x41078609u); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000130u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000e2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x800100e0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f6u); + HW_SCE_p_func101(0xabde0957u, 0x0fbfdc07u, 0x816885b7u, 0x6864b23eu); + HW_SCE_p_func043(); + HW_SCE_p_func077(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f6u); + HW_SCE_p_func101(0x11952f36u, 0x92fa06b0u, 0xbec6cccfu, 0xdd60618cu); + HW_SCE_p_func044(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00040804u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_104H = 0x00001762u; + SCE->REG_D0H = 0x40000500u; + SCE->REG_C4H = 0x02e08887u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + SCE->REG_100H = InData_KeyIndex[4]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + SCE->REG_100H = InData_KeyIndex[8]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x00000010u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_100H = InData_KeyIndex[16]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_100H = InData_KeyIndex[20]; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[21]; + SCE->REG_100H = InData_KeyIndex[22]; + SCE->REG_100H = InData_KeyIndex[23]; + SCE->REG_100H = InData_KeyIndex[24]; + SCE->REG_00H = 0x00003233u; + SCE->REG_2CH = 0x0000001bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_104H = 0x00000362u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000087b5u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[25]; + SCE->REG_100H = InData_KeyIndex[26]; + SCE->REG_100H = InData_KeyIndex[27]; + SCE->REG_100H = InData_KeyIndex[28]; + SCE->REG_C4H = 0x00900c45u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func100(0xf18601a4u, 0x70bb1760u, 0x318349cbu, 0xff5d1355u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x559c24e4u, 0xf2aa0acdu, 0x8b9b73a1u, 0x3b80136fu); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x808c000au; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b540u; + SCE->REG_ECH = 0x000000C0u; + SCE->REG_E0H = 0x808c000au; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000180u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x00000002u; + SCE->REG_ECH = 0x00000b9cu; + HW_SCE_p_func100(0xf316d8d2u, 0x79929798u, 0x751a3d39u, 0xe14b89b8u); + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + HW_SCE_p_func101(0x67d6accfu, 0x410dac54u, 0xd335e1bfu, 0x3a9b29d0u); + HW_SCE_p_func302(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0x8dc9b62au, 0xea2a3202u, 0x330c3721u, 0xed7351f2u); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x53ca79ecu, 0x8c5fbfbeu, 0x789481f8u, 0x2f64684cu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x17c9dd80u, 0x82da83bfu, 0x0d790543u, 0x50485666u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x818c0013u; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x0000001au; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x000000C0u; + SCE->REG_E0H = 0x818c0013u; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x0000001bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x00009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000070d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x800048d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000a41u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x80000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80004cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x900019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000280u; + SCE->REG_24H = 0x800019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000941u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800015c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800040c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000200u; + SCE->REG_24H = 0x800012c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000951u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000149u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000080u; + SCE->REG_24H = 0x800060c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000c2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d51u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000145u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x5a83c212u, 0x26eaa86eu, 0x1abecd3au, 0xf8dd0538u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x69e5c4abu, 0xbc0d5482u, 0xc110625bu, 0x71573c04u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000040u; + SCE->REG_E0H = 0x818c001fu; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x00000012u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x800068d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000100u; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x1fca6902u, 0xdb92fa7cu, 0x246ef741u, 0x05211b66u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x26c9111fu, 0x476535c1u, 0x13d0b543u, 0xe890e9f3u); + } + else + { + HW_SCE_p_func101(0x03806e32u, 0xa9ed89feu, 0x00e95f20u, 0x5db753ccu); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0xd048889eu, 0x80940a86u, 0x6baaaf20u, 0x544eb0bfu); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000130u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + SCE->REG_34H = 0x00000002u; + SCE->REG_24H = 0x80000dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008u; + SCE->REG_24H = 0x800011c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000a2cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0u; + SCE->REG_ECH = 0x00000140u; + SCE->REG_E0H = 0x818c001fu; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00009004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b660u; + SCE->REG_ECH = 0x00000000u; + SCE->REG_E0H = 0x818c0013u; + SCE->REG_00H = 0x00003833u; + SCE->REG_2CH = 0x00000014u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000009c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x5c2d0ec5u, 0xc2315674u, 0xdcad06ccu, 0x6322755fu); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xdb95f1aau, 0xbf1fe75bu, 0xa804bf04u, 0x7c374249u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x914a2eb8u, 0x0568a5aeu, 0x5d214490u, 0xb78ae4f6u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf6_r3.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c new file mode 100644 index 000000000..576019ec2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_pf9.c @@ -0,0 +1,806 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveType, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0u != (SCE->REG_1B8H & 0x1eu)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f901u; + SCE->REG_108H = 0x00000000u; + HW_SCE_p_func100(0x71955c20u, 0x3ac12303u, 0x15fa1bdau, 0xb60a3db0u); + SCE->REG_28H = 0x008b0001u; + SCE->REG_104H = 0x00000068u; + SCE->REG_E0H = 0x80010340u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5au; + SCE->REG_ECH = 0x00030020u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000002B4u; + SCE->REG_ECH = 0x00000060u; + SCE->REG_ECH = 0x0000b400u; + SCE->REG_ECH = 0x000003D8u; + SCE->REG_ECH = 0x00000080u; + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0x4f0f541eu, 0x1a44960eu, 0x563abdb1u, 0xe3baac79u); + HW_SCE_p_func027_r2(OFS_ADR); + HW_SCE_p_func100(0xc801a728u, 0x47ab14b5u, 0xf9ee4545u, 0xd37aac4fu); + SCE->REG_28H = 0x008d0001u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0x6d82e07fu, 0x8dad4d87u, 0xa9117322u, 0x58cdcce9u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + SCE->REG_2CH = 0x00000011u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0x60a4b8bau, 0x3aa18769u, 0xfaf0117du, 0x2d608defu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + HW_SCE_p_func100(0x11cdcd6cu, 0xa3872140u, 0x68e4fa6au, 0xe51f5637u); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x00003213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_00H = 0x0000320bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020bu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004u; + SCE->REG_24H = 0x0000a206u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000u; + SCE->REG_24H = 0x000016c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000682u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c2u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_28H = 0x008b0001u; + SCE->REG_24H = 0x0000dcd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000820u; + SCE->REG_24H = 0x80009cd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0x60c968fcu, 0x219d0e28u, 0x9436dee9u, 0xcc67ad17u); + SCE->REG_24H = 0x000084d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000c0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e8d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808u; + SCE->REG_24H = 0x8000f0d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func028_r2(OFS_ADR); + HW_SCE_p_func100(0xdfa41c30u, 0xd99f4cfdu, 0xf7a85de6u, 0xa99c9005u); + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x800088d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802u; + SCE->REG_24H = 0x8000acd0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x00000bdeu; + SCE->REG_ECH = 0x00000842u; + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x0000b480u; + SCE->REG_ECH = 0x00000180u; + SCE->REG_ECH = 0x0000b7a0u; + SCE->REG_ECH = 0x000000f9u; + SCE->REG_ECH = 0x00000b9cu; + SCE->REG_E0H = 0x81010380u; + SCE->REG_04H = 0x00000607u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xfbcc0d7fu, 0x36080ac4u, 0xcf7b143cu, 0x6ff21498u); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001) + { + break; + } + HW_SCE_p_func101(0xa45737d5u, 0xb1b23b5au, 0x2de55314u, 0x1d084e61u); + } + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00u; + SCE->REG_1CH = 0x00210000u; + HW_SCE_p_func100(0x1daa4a2du, 0x7ce5aa27u, 0xa5415a80u, 0x914b2f17u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x162e3ccbu, 0x2f9a1e6fu, 0x693474d6u, 0x94d238e3u); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800u; + SCE->REG_24H = 0x8000f4d0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420u; + SCE->REG_ECH = 0x00000004u; + SCE->REG_ECH = 0x00000bffu; + SCE->REG_E0H = 0x808c001fu; + SCE->REG_00H = 0x00008333u; + SCE->REG_2CH = 0x00000021u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fu; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fu; + SCE->REG_E0H = 0x00000080u; + SCE->REG_1CH = 0x00A60000u; + SCE->REG_ECH = 0x00016c00u; + HW_SCE_p_func100(0x8f9c2a77u, 0xf33844d5u, 0x8455d6fdu, 0x13143ad2u); + SCE->REG_1CH = 0x00400000u; + SCE->REG_1D0H = 0x00000000u; + if (1u == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cu; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1u; + /* WAIT_LOOP */ + while (0u != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x86ef67c2u, 0xe8cf24d0u, 0x37804e2au, 0xf098530du); + } + else + { + HW_SCE_p_func101(0xf2132842u, 0x74acefcdu, 0x0c004a87u, 0x08b9d513u); + } + } + SCE->REG_ECH = 0x000027e1u; + HW_SCE_p_func101(0x01c83fafu, 0xef7c4381u, 0x10d53a54u, 0x051e247eu); + } + SCE->REG_ECH = 0x00008be0u; + SCE->REG_ECH = 0x00000030u; + SCE->REG_ECH = 0x00007c1fu; + SCE->REG_1CH = 0x00602000u; + HW_SCE_p_func301(); + HW_SCE_p_func100(0x88354d96u, 0xf9abfe45u, 0xcf2ad333u, 0x5c4b54aau); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f9u); + HW_SCE_p_func101(0xd43c4306u, 0xb91b575bu, 0xded4cef2u, 0x3eedd0dfu); + HW_SCE_p_func043(); + HW_SCE_p_func076(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x000000f9u); + HW_SCE_p_func101(0xa5113cbeu, 0x6d527565u, 0x8445bbf4u, 0xa1034407u); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x6762285cu, 0x0d4cf93du, 0xa3506f40u, 0x1ceecb69u); + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x02e087b7u; + SCE->REG_00H = 0x00002333u; + SCE->REG_2CH = 0x0000002du; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[1] = SCE->REG_100H; + OutData_PrivKeyIndex[2] = SCE->REG_100H; + OutData_PrivKeyIndex[3] = SCE->REG_100H; + OutData_PrivKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[5] = SCE->REG_100H; + OutData_PrivKeyIndex[6] = SCE->REG_100H; + OutData_PrivKeyIndex[7] = SCE->REG_100H; + OutData_PrivKeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[9] = SCE->REG_100H; + OutData_PrivKeyIndex[10] = SCE->REG_100H; + OutData_PrivKeyIndex[11] = SCE->REG_100H; + OutData_PrivKeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func100(0xe81c9889u, 0x67692950u, 0xbe826a22u, 0x2e8a4dbeu); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x00000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c5u; + SCE->REG_00H = 0x00002213u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[13] = SCE->REG_100H; + OutData_PrivKeyIndex[14] = SCE->REG_100H; + OutData_PrivKeyIndex[15] = SCE->REG_100H; + OutData_PrivKeyIndex[16] = SCE->REG_100H; + HW_SCE_p_func100(0x13b2eeb6u, 0xc897657du, 0x440a39ffu, 0xa369cdd9u); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PrivKeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func100(0x5582f747u, 0x39e01cb7u, 0x3691c4c7u, 0xe0da29edu); + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052u; + SCE->REG_C4H = 0x01000c84u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_E0H = 0x80010000u; + SCE->REG_00H = 0x00008207u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_00H = 0x0000020fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_ECH = 0x000034e0u; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000027u); + HW_SCE_p_func101(0x70f41c99u, 0xba1e2bc7u, 0xa7b2ae76u, 0xe6f2e9fcu); + HW_SCE_p_func043(); + HW_SCE_p_func077(); + SCE->REG_ECH = 0x000034feu; + SCE->REG_104H = 0x00000058u; + SCE->REG_E0H = 0x800103a0u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000028u); + HW_SCE_p_func101(0x2cabf676u, 0x643a1a6bu, 0xb94816b0u, 0xd195fadau); + HW_SCE_p_func044(); + HW_SCE_p_func100(0x3901d920u, 0x63dad967u, 0x365fd72cu, 0x2905477du); + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x02e08887u; + SCE->REG_00H = 0x00002333u; + SCE->REG_2CH = 0x00000022u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[1] = SCE->REG_100H; + OutData_PubKeyIndex[2] = SCE->REG_100H; + OutData_PubKeyIndex[3] = SCE->REG_100H; + OutData_PubKeyIndex[4] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[5] = SCE->REG_100H; + OutData_PubKeyIndex[6] = SCE->REG_100H; + OutData_PubKeyIndex[7] = SCE->REG_100H; + OutData_PubKeyIndex[8] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[9] = SCE->REG_100H; + OutData_PubKeyIndex[10] = SCE->REG_100H; + OutData_PubKeyIndex[11] = SCE->REG_100H; + OutData_PubKeyIndex[12] = SCE->REG_100H; + HW_SCE_p_func100(0xdc1ff7abu, 0x50b66339u, 0x2bc1b6f1u, 0x0303639fu); + SCE->REG_D0H = 0x40000200u; + SCE->REG_C4H = 0x00e08887u; + SCE->REG_00H = 0x00002333u; + SCE->REG_2CH = 0x00000023u; + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800u; + SCE->REG_04H = 0x00000232u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[13] = SCE->REG_100H; + OutData_PubKeyIndex[14] = SCE->REG_100H; + OutData_PubKeyIndex[15] = SCE->REG_100H; + OutData_PubKeyIndex[16] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[17] = SCE->REG_100H; + OutData_PubKeyIndex[18] = SCE->REG_100H; + OutData_PubKeyIndex[19] = SCE->REG_100H; + OutData_PubKeyIndex[20] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[21] = SCE->REG_100H; + OutData_PubKeyIndex[22] = SCE->REG_100H; + OutData_PubKeyIndex[23] = SCE->REG_100H; + OutData_PubKeyIndex[24] = SCE->REG_100H; + HW_SCE_p_func100(0x7d1ad014u, 0xbcf9baa2u, 0x3a53ca7cu, 0x64a40b32u); + SCE->REG_104H = 0x00000052u; + SCE->REG_D0H = 0x40000000u; + SCE->REG_C4H = 0x000089c4u; + /* WAIT_LOOP */ + while (1u != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000u); + SCE->REG_04H = 0x00000212u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[25] = SCE->REG_100H; + OutData_PubKeyIndex[26] = SCE->REG_100H; + OutData_PubKeyIndex[27] = SCE->REG_100H; + OutData_PubKeyIndex[28] = SCE->REG_100H; + HW_SCE_p_func100(0x5e7bb2b6u, 0xa502456fu, 0xbca534c6u, 0x74f8870fu); + SCE->REG_E0H = 0x81010000u; + SCE->REG_04H = 0x00000606u; + /* WAIT_LOOP */ + while (1u != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_PubKeyIndex[0] = SCE->REG_100H; + HW_SCE_p_func102(0xad16c748u, 0x1d60a10du, 0xfbdbbe7au, 0xd146affau); + SCE->REG_1B8H = 0x00000040u; + /* WAIT_LOOP */ + while (0u != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_pf9_r3.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c new file mode 100644 index 000000000..0dc98aaa5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/hw_sce_p_subprc01.c @@ -0,0 +1,213 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2020 1.00 First Release. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +void HW_SCE_SelfCheck1SubSub(void) +{ + uint32_t iLoop = 0u, iLoop1 = 0u, iLoop2 = 0u, jLoop = 0u, kLoop = 0u, oLoop = 0u, oLoop1 = 0u, oLoop2 = 0u, KEY_ADR = 0u, OFS_ADR = 0u, MAX_CNT2 = 0u; + uint32_t dummy = 0u; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + SCE->REG_138H = 0xf597806Au; + SCE->REG_10CH = 0x00010001u; + SCE->REG_10H = 0x01234567u; + SCE->REG_7CH = 0x00000001u; + SCE->REG_78H = 0x00008007u; + SCE->REG_134H = 0x76543210u; + HW_SCE_p_func054(change_endian_long(0x00003008u), change_endian_long(0x00003018u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + HW_SCE_p_func050(change_endian_long(0x00010001u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + SCE->REG_68H = 0x00000417u; + SCE->REG_6CH = 0xabcdef01u; + HW_SCE_p_func054(change_endian_long(0x10003008u), change_endian_long(0x10003018u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + HW_SCE_p_func050(change_endian_long(0x00000001u)); + SCE->REG_28H = 0x00000001u; + SCE->REG_3CH = 0x00010173u; + SCE->REG_4CH = 0x23456789u; + SCE->REG_80H = 0x00000001u; + SCE->REG_8CH = 0x000080BBu; + SCE->REG_94H = 0xabcdef01u; + SCE->REG_7CH = 0x00000001u; + SCE->REG_78H = 0x0000011fu; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + SCE->REG_68H = 0x00000017u; + HW_SCE_p_func054(change_endian_long(0x72f01007u), change_endian_long(0x72f01017u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + HW_SCE_p_func050(change_endian_long(0x00000001u)); + HW_SCE_p_func054(change_endian_long(0x72f03007u), change_endian_long(0x72f03017u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + } + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + HW_SCE_p_func050(change_endian_long(0x00000001u)); + SCE->REG_28H = 0x00000001u; + SCE->REG_80H = 0x00000001u; + SCE->REG_7CH = 0x00000001u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + HW_SCE_p_func054(change_endian_long(0x72f03007u), change_endian_long(0x72f03017u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + HW_SCE_p_func050(change_endian_long(0x00000001u)); + SCE->REG_28H = 0x00000001u; + SCE->REG_3CH = 0x00010173u; + SCE->REG_80H = 0x00000001u; + SCE->REG_B0H = 0x40000010u; + SCE->REG_D0H = 0x40000010u; + SCE->REG_A4H = 0x00008000u; + SCE->REG_C4H = 0x00008000u; + SCE->REG_8CH = 0x0000888Bu; + SCE->REG_7CH = 0x00000001u; + SCE->REG_78H = 0x00000007u; + /* WAIT_LOOP */ + while (0u != SCE->REG_64H_b.B11) + { + /* waiting */ + } + SCE->REG_64H = 0x00000008u; + SCE->REG_68H = 0x00000017u; + HW_SCE_p_func054(change_endian_long(0x7af03007u), change_endian_long(0x7af03017u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + } + HW_SCE_p_func051(); + SCE->REG_28H = 0x00000001u; + SCE->REG_3CH = 0x00810173u; + HW_SCE_p_func054(change_endian_long(0x00003008u), change_endian_long(0x00003018u)); + /* WAIT_LOOP */ + while (0u != SCE->REG_00H_b.B31) + { + /* waiting */ + } + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + HW_SCE_p_func052(change_endian_long(0x00810173u)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + HW_SCE_p_func052(change_endian_long(0x0080197fu)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + HW_SCE_p_func052(change_endian_long(0x00fe017bu)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + HW_SCE_p_func052(change_endian_long(0x00af091Fu)); + } + HW_SCE_p_func053(change_endian_long(0x000380BBu)); + for(iLoop = 0; iLoop < 6; iLoop = iLoop + 1) + { + HW_SCE_p_func053(change_endian_long(0x000380BBu)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + HW_SCE_p_func053(change_endian_long(0x000191BBu)); + } + for(iLoop = 0; iLoop < 3; iLoop = iLoop + 1) + { + HW_SCE_p_func053(change_endian_long(0x000185B7u)); + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/S6C1/Cryptographic_PlainKey/HW_SCE_p_subprc01.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c new file mode 100644 index 000000000..e803ba6a1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/primitive/s_flash2.c @@ -0,0 +1,761 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * File Name : s_flash.c + * Version : 1.09 + * Description : Key information file. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.03.2020 1.09 First Release + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "r_sce_if.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global variables + *********************************************************************************************************************/ +uint32_t const S_FLASH2[] = +{ +#ifndef __ARMEB__ /* Little endian */ + 0xdd502103, 0xd9183176, 0x71a905af, 0xfec6c807, + 0x93ca3bcb, 0x12e7b5e8, 0xfb59e99d, 0x8f3d8dd9, + 0xe2fbde9d, 0x2d97cadf, 0xab178605, 0x9c1cfdef, + 0x4ca22949, 0x4032cc5d, 0x7c0774ed, 0x3b97134b, + 0x4a15273b, 0xbb6e4195, 0xe4e8eade, 0x7e1a663a, + 0x834c97fa, 0xe814872a, 0xba83f030, 0x5a476c81, + 0x9d048cc2, 0xd5363ffa, 0x60c89876, 0x5eb4e383, + 0x7546e44d, 0x1020d8ae, 0x659f651f, 0x31202e98, + 0x151c8ea1, 0x068191e2, 0xcc55a315, 0x3e5d9265, + 0x491d6e35, 0x5ca371ca, 0x76dde15e, 0x956a2fcc, + 0xf139beed, 0x126cdc36, 0xc6758140, 0x4959bf70, + 0x146c840c, 0x4ac37409, 0xd5a0f83e, 0xb5faca5e, + 0xa6e62ab5, 0x5b89b2bb, 0xf9a99e96, 0xa0549da1, + 0x23ecd0e3, 0xde0d6717, 0x84279612, 0x51d37326, + 0x05dbd8e3, 0x46cf99ba, 0xefe8b388, 0x4b3c2762, + 0x29774aa4, 0x7b0cd205, 0x66a4911d, 0x7bbe274d, + 0xff564352, 0x5ec47ee4, 0x20b53536, 0xd2c49bce, + 0xdc2fbc7b, 0x174d7f9f, 0xf5fec4d3, 0xb07c4d83, + 0x6c4ed5ec, 0xb0a395fc, 0xb12e6414, 0x4b99c00f, + 0x4e5b8ef7, 0x073cec04, 0x72e04fd2, 0x493d2687, + 0x00fa2924, 0xfd412295, 0x6123ea82, 0x793c42df, + 0x6acbc9ed, 0xce2ce5f0, 0x381b7d86, 0x9e60a724, + 0x2b4d6674, 0x9ff7e07f, 0x10306f0a, 0xbf1aa3fe, + 0x1910beca, 0x52459b47, 0x17378cf6, 0x3bb240e3, + 0xfa43e7ea, 0x7f7fb3e0, 0x2f824b27, 0x18686740, + 0xd0c486ce, 0xdfb0726a, 0x2bbd32c7, 0x5edb0058, + 0x0b62df82, 0x55eef53f, 0xf9238b1c, 0x26af924d, + 0x7d977012, 0x4f1126bb, 0x7b887564, 0x99c1b1c7, + 0x72ac7491, 0x0ed3dc58, 0xce5c704f, 0x952f7570, + 0xdfaa5f69, 0x5b237031, 0x888d2540, 0x802121e8, + 0xc5642c69, 0xe3444168, 0xf17d2b54, 0x1cfab3eb, + 0x0e62628a, 0x8e21497e, 0xfe08555f, 0xc043ea33, + 0xd10041c4, 0x790d5a7c, 0x403efe1d, 0xc368e331, + 0x05b2b426, 0x7df201c2, 0xd5d56897, 0xe8f3340b, + 0x925849c6, 0x63c03afd, 0x2d4ce596, 0x0bd72787, + 0x51e10cc4, 0x19fc7c4e, 0x583de3c5, 0x5db86155, + 0x5555f5bd, 0xec96f0e3, 0xfb58fbc1, 0x812997d8, + 0xcdb0111a, 0x6c37393a, 0xede922e7, 0x945a51d2, + 0xbcbb9315, 0x3ea7242f, 0x9505420f, 0x490d7d17, + 0x7a9623e5, 0xc9386691, 0xe826fc95, 0x9b4af647, + 0x74a8f50e, 0x870ea4e7, 0x1533eb0a, 0x29616e0b, + 0x285933dc, 0x02a0d596, 0x3b781c4c, 0x3eb05458, + 0x1e3e275c, 0x3a159d48, 0x73ebe204, 0x468acc45, + 0x85cf6a1d, 0xd1055350, 0xe0e4f622, 0x1304e990, + 0x09e4aa7e, 0x72e7ee98, 0xb1de602f, 0x44beec64, + 0xe26e1dfe, 0xdffdfd01, 0x62c668b4, 0x8245c35c, + 0xbcb225f8, 0x811e185c, 0x7283352f, 0x96c17572, + 0x9ac73d4c, 0x79a5c426, 0x4e61bed9, 0x1a9c0649, + 0x07a3f222, 0xe1aed316, 0x62d97ed7, 0x7fd40d97, + 0x02cc6bc7, 0x179ec919, 0x5d1273dd, 0x393ddfa4, + 0x33a57a1d, 0xad3cbbb2, 0x8f249c68, 0xfe19dc28, + 0x4a5bd96b, 0xf19096dd, 0x3ed59c48, 0x94777cc8, + 0x28c61df6, 0xf56d2df1, 0xe2a87678, 0x4c16b6c0, + 0xb35fbe16, 0xdb30f584, 0x9c5bbcd4, 0x442bd65f, + 0x12dcad82, 0xb575a8b7, 0xbadd7e9b, 0x21388394, + 0x1b738c96, 0xfe123240, 0x7e11bb78, 0xc813085d, + 0xf280bb1a, 0x3bee0a85, 0x2bfea15b, 0x1a1ddc12, + 0x830b641e, 0xda11d02b, 0x290be194, 0x337ce862, + 0x889274b6, 0x65188565, 0x97fdcc19, 0xd1fec76f, + 0xe5c01654, 0x41149690, 0x4fcf9e05, 0xc3d1c46d, + 0x0ca429f7, 0x86c6f8ff, 0xd7557d5b, 0x447735a6, + 0x996fe728, 0x0b96224b, 0x8048bedf, 0xaea8740f, + 0x273553f5, 0xfef21b6a, 0xb69b59fe, 0x2830b136, + 0x8e646d47, 0xbd70f0a7, 0xdca46c07, 0x625f8b13, + 0xdc10e10b, 0x78ed0540, 0x4dec07b9, 0x4b9797b7, + 0x2a74cd0d, 0x0ddeeaba, 0x71579b62, 0x1f869b4c, + 0x70d23a25, 0x8d0685b8, 0x4f1bda6e, 0x564a0ac0, + 0x533a7419, 0x5e17e68f, 0x44afde8d, 0x9600db58, + 0xcb9511d4, 0x8a3a2ae2, 0x2ad3e68b, 0xb4bc03b7, + 0x7a1a50ea, 0xe31dbe23, 0xda6d2dbe, 0xfccad5a0, + 0x0059c6d2, 0xf772170f, 0xbc8cac6a, 0x14da0a87, + 0xf2ec1a1f, 0xa3702b88, 0x15966394, 0x9c3e49b8, + 0x07bc5abc, 0xc1a30c87, 0xe898bb59, 0xf3d1ed4c, + 0xd3b0f9e1, 0x48cee253, 0xdf587104, 0x99773b42, + 0xbca2974c, 0x4c1ef8de, 0x28da0b84, 0x46341861, + 0x96a1dfb3, 0x10fb4725, 0x62a53cf2, 0x31bc54f3, + 0xfb046761, 0xd30d5365, 0x31ba0ef1, 0x60aed6f2, + 0xf022d530, 0xb99836c6, 0x7fcdc95d, 0x2211cbed, + 0xfc503ddc, 0x10c21f64, 0xacf00db4, 0x0b427a47, + 0x8ff773be, 0xdae8f5b9, 0x6ebe5924, 0xdb2460c8, + 0xafcfeb3d, 0x9368e608, 0xf42000c3, 0x2cf59f90, + 0xf7fe2adf, 0x9c552280, 0x44e58bfb, 0x735a3ecc, + 0xb1edfaae, 0xc2b6ceae, 0x9d549823, 0xfe008818, + 0xe2a06be5, 0x0c96afa9, 0x45e0baf4, 0x4dc7f084, + 0xccd00f50, 0xfc75da65, 0x983a17a5, 0x5fd64fad, + 0x338e4250, 0xfbcc2d40, 0x367b4bd7, 0xda2e30c2, + 0x58a8b55c, 0x49fc8b0f, 0x15132c39, 0xad64fa42, + 0x22a90ce0, 0x56cb83c3, 0xbe2bd150, 0x69fc9c11, + 0x44fe0878, 0xdf4c9866, 0x5a07f984, 0x792e6627, + 0x66a46566, 0x4db32f8a, 0xbd05806d, 0x04f1bcba, + 0x868cb837, 0x854f8df5, 0x6c7f55d9, 0x57e8f107, + 0xbcf6988b, 0x8e10ee89, 0xd4ffe0ab, 0x17e715a0, + 0x37148962, 0x43b72722, 0x03b2eb40, 0x6003d14e, + 0x06c74fbb, 0xed7b5cde, 0x8d2ea577, 0xc5fee509, + 0xc843ce52, 0x5bdffac2, 0x020d9e88, 0x2f0b8760, + 0x509d2bff, 0x97f464dd, 0xee55839e, 0xd4a61328, + 0xe76bd4ce, 0x54d7c908, 0x739b5f68, 0x53f814f3, + 0xff638447, 0x1bb93af1, 0x045c82d3, 0x33287474, + 0xf904311b, 0x27264390, 0x645b3078, 0x7768671a, + 0xcce1a520, 0xd9890be0, 0x35d58bb4, 0xcadadee9, + 0x49c31313, 0xfd0c9127, 0xfcc283fa, 0x4b5b8e06, + 0x9ee352c2, 0xbe1914bf, 0x9e97a769, 0x25d2c450, + 0x8542b849, 0xb9daaf9c, 0x42860a34, 0xc5918c84, + 0x2a580252, 0xc2c369c8, 0xabd27275, 0xf2aaac7e, + 0xbaa300dd, 0x39180f20, 0xc0bf3e94, 0xe56053ac, + 0x143d0424, 0x1a7ff8d4, 0x7f06dffe, 0xc076ce66, + 0x518405af, 0x103ccb20, 0xe023bc64, 0xdec520ba, + 0x86e1f9ca, 0xf0361144, 0x665e0314, 0x200dcd6a, + 0x92162fb1, 0x7d2b16f9, 0xed897397, 0x41abce1c, + 0x6b89a607, 0x9beb2abb, 0x5c76ed37, 0x25b97c6f, + 0x12d39ccf, 0xe35a84d0, 0x31968aa2, 0xbb4e7f17, + 0x265075a2, 0x5150e3a9, 0xcc214e98, 0x7a5c1021, + 0xe0037392, 0x30ca7678, 0x30cd8fd7, 0x87cfd362, + 0x03f353cb, 0x5831a5cf, 0xb506259e, 0x7d94dffe, + 0x9304beec, 0x87abd31f, 0x0e81dddc, 0x14adac14, + 0x5e3830ff, 0xed00f55d, 0xbc2ff45c, 0xffb38a2e, + 0x69c30468, 0xf80ba68f, 0xd8464e40, 0xd523bac9, + 0x623e1c2c, 0x278a1f49, 0x1c2b59a7, 0xf10374ff, + 0x23015b76, 0xeb5b389f, 0x1631a01a, 0x7ea30437, + 0xa5a9b11f, 0x3cbad734, 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0x31a8a75e, 0xb780ad8f, + 0xadccef0d, 0x71b320de, 0x2bebaf18, 0x12c11d84, + 0x2ea4814c, 0xc09436b7, 0x01cb9224, 0x7d1372e4, + 0x71da541a, 0xf7f15add, 0xb7ed54c6, 0x0c8d324e, + 0xc932869a, 0x164ddef4, 0xef3fc071, 0xef4b4bf5, + 0x764fd1a0, 0x1f78d159, 0x5cea38ee, 0xd79917a1, + 0xd9fb3e46, 0x31b2f904, 0x8df7c0b1, 0xdf6b4884, + 0x7e9a34ce, 0x39205f7b, 0x409a1901, 0x63a3bf35, + 0xb544a6c3, 0xfaccd9ff, 0x43bce0b5, 0xb149b7f3, + 0xa0aad6d7, 0xcd086a1b, 0xcfb2e563, 0x8a419617, + 0x69b3ca01, 0xed9992d1, 0xca95b076, 0xc043119b, + 0x76df0789, 0xc7dedb91, 0x2af16340, 0x962bf359, + 0xbc3c4382, 0x3696e0dd, 0x1d799a9b, 0x1f2d7a21, + 0x25fd07de, 0xfdf497c9, 0x006ef6e0, 0x5c9ca8c3, + 0x6ac7ad94, 0x183ec408, 0xe1bb333c, 0x7a583226, + 0xfb1f881b, 0xf70f11ef, 0xbbd7811f, 0xd150d21e, + 0xeb23afa3, 0xfdb3f2c7, 0xe9d3a4be, 0x9a28b72d, + 0x1f0c2d17, 0xd0bcd29a, 0x5c7bf5b1, 0x81dba8f0, + 0xfcd37206, 0xe6642e1b, 0x38cc79e3, 0x293bb08c, + 0xd65cc8bf, 0x4c3a52d2, 0xab6aa13c, 0x250fe7fb, + 0x837a63e7, 0x2197af7f, 0xf6f42a80, 0x27ad39a2, + 0xc676f01c, 0x01959ee1, 0x714cfb31, 0x04cbb5dc, + 0xbd96e699, 0x0245d9db, 0xd37a57ad, 0x1bed9622, + 0xe2fe2df7, 0x16821c8a, 0xe9f1470b, 0xb6f5e02b, + 0xa893af17, 0xe89f83e2, 0xefd5578c, 0x7887a4f3, + 0xdd74f9ab, 0x186a5a0a, 0xfae9aeca, 0x8e2f4cf2, + 0x1c8e5436, 0x6324fe93, 0xae4dbf4e, 0xc6fb94f6, + 0x46536e72, 0x634ef238, 0x92f6d797, 0x998a4495, + 0xbc9045b5, 0x3711c67a, 0x06398c82, 0xd400d007, + 0x9a7ab900, 0x2bac3f07, 0x25287997, 0x3cf6ea82, + 0x8659ba53, 0x04225b0f, 0xf8d8df07, 0x2810ec68, + 0x6f6ac63a, 0x059421ec, 0xacbf0003, 0x8c814bd6, + 0x729f7df0, 0xa4e71474, 0xbe6fa67e, 0x285187ca, + 0xb4e10c6a, 0xe75eb871, 0x069f279a, 0x8f077838, + 0xc7da5fe8, 0x33f9018a, 0xb25ac608, 0x3800a999, + 0x4a0d5281, 0x0035732f, 0xf29716ea, 0xeadf79cf, + 0xaa334c92, 0x006c5e92, 0x800993b0, 0x73087119, + 0x8a96c964, 0xb77cf734, 0xf6cb19ce, 0xcfb89d15, + 0x3d540bc5, 0x857f1191, 0x2da68eb2, 0x2ef16da1, + 0xa57160fd, 0xbf16cf7b, 0x5bb56f3c, 0x0f3f3a96, + 0xe702a064, 0x2add1bb8, 0x05280bb0, 0x49445ab8, + 0xf560ef61, 0x3af163ab, 0xd35cb600, 0x8b8f9ae6, + 0x06576967, 0xd80dfea3, 0x259b0191, 0x2278a868, + 0xf45319d8, 0x425b6c40, 0x3bae950d, 0x26444870, + 0x4ff182bb, 0x2e53b357, 0x24a8f9b2, 0x7aae7740, + 0x2a360653, 0xdc564384, 0x053b1f16, 0x3dae0afa, + 0x11c0079d, 0x6ecc742c, 0x01cf0947, 0x68f33267, + 0x828d35ad, 0x6f4d5a11, 0x01d09dc1, 0x09aeefeb, + 0xf0e8412b, 0xa959fc23, 0x91bad736, 0x265b2075, + 0xe3ddc4b7, 0x07569527, 0xc34f7ec1, 0x0c97d192, + 0x0a43f79c, 0x7ad3abf4, 0xf69b9033, 0x1bdf0124, + 0x3961aaa6, 0xa7b78b13, 0xdcd1dffd, 0x59611fb2, + 0x64b2f04b, 0x506cc54e, 0x5f7fc2ab, 0xd22018a0, + 0x1e2064a9, 0x1db995c0, 0xeddc7fe1, 0xf91b245c, + 0xb062a7ad, 0xbe199ab8, 0x15d22c79, 0x7a7cdab2, + 0xc37df0be, 0x2007b582, 0x2f04c75f, 0x4b84ab20, + 0x1998d8e3, 0x2169ca81, 0xff3c8a5c, 0xc30af54a, + 0x87015fe3, 0xd52edcab, 0xed6c8706, 0x9db80ec3, + 0x10d62f38, 0xa5268e7d, 0x77ab0d49, 0xe60c8031, + 0x74288339, 0x0094f2e2, 0x9d850c3c, 0x9899990f, + 0x04dccf5e, 0x0c7fd917, 0x6d31624f, 0xfc003f1c, + 0x283add48, 0x7517c415, 0x2bf12ccd, 0xb66ce8b6, + 0x605be298, 0x685c18e1, 0x9970558c, 0x41a706e0, + 0xb90628db, 0x10857227, 0x37587353, 0xe6ba1c2e, + 0xf090e241, 0xf98cd147, 0x8985233d, 0xf2750b6d, + 0xf97cf9ae, 0x5d7ea61e, 0xe0e1671d, 0x49b8ae4a, + 0xeff49261, 0xdb288fdd, 0x19833ef2, 0xf1dd599f, + 0xb9611ffd, 0x6f4237cd, 0x0d0f54f0, 0x7245776a, + 0x404e9b1d, 0x8d20e5da, 0xf2d36b59, 0x00c9cabc, + 0x6db48924, 0xecae72b4, 0x6e76329b, 0xbf3f6b1a, + 0x91b8e699, 0x6c251849, 0x894f45ad, 0x99ae898a, + 0x177d0a36, 0x5ad9c3a0, 0x6dee12b7, 0xa3468398, + 0x167bc972, 0x9d6077b5, 0x926dfc50, 0xd03e6ce7, + 0x2acc9202, 0xcd06ca90, 0x0e817154, 0xc80d72e7, +#else /* Big endian */ + 0x032150dd, 0x763118d9, 0xaf05a971, 0x07c8c6fe, + 0xcb3bca93, 0xe8b5e712, 0x9de959fb, 0xd98d3d8f, + 0x9ddefbe2, 0xdfca972d, 0x058617ab, 0xeffd1c9c, + 0x4929a24c, 0x5dcc3240, 0xed74077c, 0x4b13973b, + 0x3b27154a, 0x95416ebb, 0xdeeae8e4, 0x3a661a7e, + 0xfa974c83, 0x2a8714e8, 0x30f083ba, 0x816c475a, + 0xc28c049d, 0xfa3f36d5, 0x7698c860, 0x83e3b45e, + 0x4de44675, 0xaed82010, 0x1f659f65, 0x982e2031, + 0xa18e1c15, 0xe2918106, 0x15a355cc, 0x65925d3e, + 0x356e1d49, 0xca71a35c, 0x5ee1dd76, 0xcc2f6a95, + 0xedbe39f1, 0x36dc6c12, 0x408175c6, 0x70bf5949, + 0x0c846c14, 0x0974c34a, 0x3ef8a0d5, 0x5ecafab5, + 0xb52ae6a6, 0xbbb2895b, 0x969ea9f9, 0xa19d54a0, + 0xe3d0ec23, 0x17670dde, 0x12962784, 0x2673d351, + 0xe3d8db05, 0xba99cf46, 0x88b3e8ef, 0x62273c4b, + 0xa44a7729, 0x05d20c7b, 0x1d91a466, 0x4d27be7b, + 0x524356ff, 0xe47ec45e, 0x3635b520, 0xce9bc4d2, + 0x7bbc2fdc, 0x9f7f4d17, 0xd3c4fef5, 0x834d7cb0, + 0xecd54e6c, 0xfc95a3b0, 0x14642eb1, 0x0fc0994b, + 0xf78e5b4e, 0x04ec3c07, 0xd24fe072, 0x87263d49, + 0x2429fa00, 0x952241fd, 0x82ea2361, 0xdf423c79, + 0xedc9cb6a, 0xf0e52cce, 0x867d1b38, 0x24a7609e, + 0x74664d2b, 0x7fe0f79f, 0x0a6f3010, 0xfea31abf, + 0xcabe1019, 0x479b4552, 0xf68c3717, 0xe340b23b, + 0xeae743fa, 0xe0b37f7f, 0x274b822f, 0x40676818, + 0xce86c4d0, 0x6a72b0df, 0xc732bd2b, 0x5800db5e, + 0x82df620b, 0x3ff5ee55, 0x1c8b23f9, 0x4d92af26, + 0x1270977d, 0xbb26114f, 0x6475887b, 0xc7b1c199, + 0x9174ac72, 0x58dcd30e, 0x4f705cce, 0x70752f95, + 0x695faadf, 0x3170235b, 0x40258d88, 0xe8212180, + 0x692c64c5, 0x684144e3, 0x542b7df1, 0xebb3fa1c, + 0x8a62620e, 0x7e49218e, 0x5f5508fe, 0x33ea43c0, + 0xc44100d1, 0x7c5a0d79, 0x1dfe3e40, 0x31e368c3, + 0x26b4b205, 0xc201f27d, 0x9768d5d5, 0x0b34f3e8, + 0xc6495892, 0xfd3ac063, 0x96e54c2d, 0x8727d70b, + 0xc40ce151, 0x4e7cfc19, 0xc5e33d58, 0x5561b85d, + 0xbdf55555, 0xe3f096ec, 0xc1fb58fb, 0xd8972981, + 0x1a11b0cd, 0x3a39376c, 0xe722e9ed, 0xd2515a94, + 0x1593bbbc, 0x2f24a73e, 0x0f420595, 0x177d0d49, + 0xe523967a, 0x916638c9, 0x95fc26e8, 0x47f64a9b, + 0x0ef5a874, 0xe7a40e87, 0x0aeb3315, 0x0b6e6129, + 0xdc335928, 0x96d5a002, 0x4c1c783b, 0x5854b03e, + 0x5c273e1e, 0x489d153a, 0x04e2eb73, 0x45cc8a46, + 0x1d6acf85, 0x505305d1, 0x22f6e4e0, 0x90e90413, + 0x7eaae409, 0x98eee772, 0x2f60deb1, 0x64ecbe44, + 0xfe1d6ee2, 0x01fdfddf, 0xb468c662, 0x5cc34582, + 0xf825b2bc, 0x5c181e81, 0x2f358372, 0x7275c196, + 0x4c3dc79a, 0x26c4a579, 0xd9be614e, 0x49069c1a, + 0x22f2a307, 0x16d3aee1, 0xd77ed962, 0x970dd47f, + 0xc76bcc02, 0x19c99e17, 0xdd73125d, 0xa4df3d39, + 0x1d7aa533, 0xb2bb3cad, 0x689c248f, 0x28dc19fe, + 0x6bd95b4a, 0xdd9690f1, 0x489cd53e, 0xc87c7794, + 0xf61dc628, 0xf12d6df5, 0x7876a8e2, 0xc0b6164c, + 0x16be5fb3, 0x84f530db, 0xd4bc5b9c, 0x5fd62b44, + 0x82addc12, 0xb7a875b5, 0x9b7eddba, 0x94833821, + 0x968c731b, 0x403212fe, 0x78bb117e, 0x5d0813c8, + 0x1abb80f2, 0x850aee3b, 0x5ba1fe2b, 0x12dc1d1a, + 0x1e640b83, 0x2bd011da, 0x94e10b29, 0x62e87c33, + 0xb6749288, 0x65851865, 0x19ccfd97, 0x6fc7fed1, + 0x5416c0e5, 0x90961441, 0x059ecf4f, 0x6dc4d1c3, + 0xf729a40c, 0xfff8c686, 0x5b7d55d7, 0xa6357744, + 0x28e76f99, 0x4b22960b, 0xdfbe4880, 0x0f74a8ae, + 0xf5533527, 0x6a1bf2fe, 0xfe599bb6, 0x36b13028, + 0x476d648e, 0xa7f070bd, 0x076ca4dc, 0x138b5f62, + 0x0be110dc, 0x4005ed78, 0xb907ec4d, 0xb797974b, + 0x0dcd742a, 0xbaeade0d, 0x629b5771, 0x4c9b861f, + 0x253ad270, 0xb885068d, 0x6eda1b4f, 0xc00a4a56, + 0x19743a53, 0x8fe6175e, 0x8ddeaf44, 0x58db0096, + 0xd41195cb, 0xe22a3a8a, 0x8be6d32a, 0xb703bcb4, + 0xea501a7a, 0x23be1de3, 0xbe2d6dda, 0xa0d5cafc, + 0xd2c65900, 0x0f1772f7, 0x6aac8cbc, 0x870ada14, + 0x1f1aecf2, 0x882b70a3, 0x94639615, 0xb8493e9c, + 0xbc5abc07, 0x870ca3c1, 0x59bb98e8, 0x4cedd1f3, + 0xe1f9b0d3, 0x53e2ce48, 0x047158df, 0x423b7799, + 0x4c97a2bc, 0xdef81e4c, 0x840bda28, 0x61183446, + 0xb3dfa196, 0x2547fb10, 0xf23ca562, 0xf354bc31, + 0x616704fb, 0x65530dd3, 0xf10eba31, 0xf2d6ae60, + 0x30d522f0, 0xc63698b9, 0x5dc9cd7f, 0xedcb1122, + 0xdc3d50fc, 0x641fc210, 0xb40df0ac, 0x477a420b, + 0xbe73f78f, 0xb9f5e8da, 0x2459be6e, 0xc86024db, + 0x3debcfaf, 0x08e66893, 0xc30020f4, 0x909ff52c, + 0xdf2afef7, 0x8022559c, 0xfb8be544, 0xcc3e5a73, + 0xaefaedb1, 0xaeceb6c2, 0x2398549d, 0x188800fe, + 0xe56ba0e2, 0xa9af960c, 0xf4bae045, 0x84f0c74d, + 0x500fd0cc, 0x65da75fc, 0xa5173a98, 0xad4fd65f, + 0x50428e33, 0x402dccfb, 0xd74b7b36, 0xc2302eda, + 0x5cb5a858, 0x0f8bfc49, 0x392c1315, 0x42fa64ad, + 0xe00ca922, 0xc383cb56, 0x50d12bbe, 0x119cfc69, + 0x7808fe44, 0x66984cdf, 0x84f9075a, 0x27662e79, + 0x6665a466, 0x8a2fb34d, 0x6d8005bd, 0xbabcf104, + 0x37b88c86, 0xf58d4f85, 0xd9557f6c, 0x07f1e857, + 0x8b98f6bc, 0x89ee108e, 0xabe0ffd4, 0xa015e717, + 0x62891437, 0x2227b743, 0x40ebb203, 0x4ed10360, + 0xbb4fc706, 0xde5c7bed, 0x77a52e8d, 0x09e5fec5, + 0x52ce43c8, 0xc2fadf5b, 0x889e0d02, 0x60870b2f, + 0xff2b9d50, 0xdd64f497, 0x9e8355ee, 0x2813a6d4, + 0xced46be7, 0x08c9d754, 0x685f9b73, 0xf314f853, + 0x478463ff, 0xf13ab91b, 0xd3825c04, 0x74742833, + 0x1b3104f9, 0x90432627, 0x78305b64, 0x1a676877, + 0x20a5e1cc, 0xe00b89d9, 0xb48bd535, 0xe9dedaca, + 0x1313c349, 0x27910cfd, 0xfa83c2fc, 0x068e5b4b, + 0xc252e39e, 0xbf1419be, 0x69a7979e, 0x50c4d225, + 0x49b84285, 0x9cafdab9, 0x340a8642, 0x848c91c5, + 0x5202582a, 0xc869c3c2, 0x7572d2ab, 0x7eacaaf2, + 0xdd00a3ba, 0x200f1839, 0x943ebfc0, 0xac5360e5, + 0x24043d14, 0xd4f87f1a, 0xfedf067f, 0x66ce76c0, + 0xaf058451, 0x20cb3c10, 0x64bc23e0, 0xba20c5de, + 0xcaf9e186, 0x441136f0, 0x14035e66, 0x6acd0d20, + 0xb12f1692, 0xf9162b7d, 0x977389ed, 0x1cceab41, + 0x07a6896b, 0xbb2aeb9b, 0x37ed765c, 0x6f7cb925, + 0xcf9cd312, 0xd0845ae3, 0xa28a9631, 0x177f4ebb, + 0xa2755026, 0xa9e35051, 0x984e21cc, 0x21105c7a, + 0x927303e0, 0x7876ca30, 0xd78fcd30, 0x62d3cf87, + 0xcb53f303, 0xcfa53158, 0x9e2506b5, 0xfedf947d, + 0xecbe0493, 0x1fd3ab87, 0xdcdd810e, 0x14acad14, + 0xff30385e, 0x5df500ed, 0x5cf42fbc, 0x2e8ab3ff, + 0x6804c369, 0x8fa60bf8, 0x404e46d8, 0xc9ba23d5, + 0x2c1c3e62, 0x491f8a27, 0xa7592b1c, 0xff7403f1, + 0x765b0123, 0x9f385beb, 0x1aa03116, 0x3704a37e, + 0x1fb1a9a5, 0x34d7ba3c, 0x6e4974c3, 0x35ef356e, + 0x57038fe4, 0xbff273e1, 0xa7fd5da7, 0x8729be16, + 0x85ea90d1, 0xa8c80f91, 0xd322a72c, 0x25d971bf, + 0xc51ad065, 0x5933ff5c, 0xa44ab840, 0x54096d6b, + 0x938f4052, 0x59cfd204, 0x4a0cf0ca, 0xdc1e22b5, + 0x8927fd4c, 0x27b2baf1, 0x6820f21b, 0x91c4812c, + 0x155da2bf, 0xf04d1b44, 0x8aded909, 0x31cb4733, + 0x2531df7a, 0xd32a6762, 0x9fbbbf4b, 0xa4757bf5, + 0x5d3d23a0, 0xa70cb060, 0xca41b823, 0x14c218c7, + 0x4d688250, 0x345be2ee, 0x03398052, 0x47f4518a, + 0x5b8067db, 0x663b8396, 0xa5c174d1, 0x45e55e0f, + 0xed3cc41f, 0xdb27c299, 0xec46017a, 0x381bb8bd, + 0x03f0d5a3, 0xe43c64c5, 0x4bb51810, 0x4b2dd8e5, + 0x2f93594a, 0x3512d9f9, 0xbd0d8c51, 0x37e30d66, + 0xfc4fa6c9, 0xe4a6b6db, 0x9911413d, 0x6af9d1bd, + 0xc7ea2313, 0x6381927a, 0x25d6f3cc, 0xe702353a, + 0xa87d53a4, 0x8c112c89, 0x80dc46b9, 0xb572f18a, + 0x6dbaf788, 0xce86c758, 0xf81c7613, 0xc6ee0bc8, + 0x2a628f4a, 0xaa6bca48, 0x0c66a932, 0x1fa302ee, + 0x107a812c, 0xcd561a35, 0x49cef74a, 0x66264dc1, + 0xd3f3efcd, 0x6b8e1c3b, 0x57363f06, 0x5ce046e5, + 0x39733b60, 0xcc574079, 0xba1ddf88, 0x472a44bc, + 0x33abdd67, 0xaa83c1e7, 0x7d7786dd, 0x2c3eac7b, + 0x9b2bb4b3, 0x06e555f9, 0xc74a76f7, 0xd50a401f, + 0xab370294, 0xa12d8b09, 0x9608fdab, 0xdfc5f8ab, + 0xd5f48e68, 0xfd1d0209, 0x3c391d82, 0x473fe32c, + 0xd8d19273, 0xf2cbd229, 0xe32787ca, 0xfba0ce48, + 0xf871436f, 0xd97e3bc8, 0xf607b979, 0x9787ff54, + 0x4a27326a, 0xc540a7c8, 0x59728047, 0xbba1a232, + 0xc34f032d, 0xcab24e6b, 0x250efb18, 0xd2e8a920, + 0x6e024243, 0x6ac0563b, 0x600be237, 0xdb21eac4, + 0xcab784a2, 0x79cb1ea2, 0xf9bc48b8, 0x110246a3, + 0xb04ffe75, 0x4325a7f3, 0x4ad099bf, 0x3b75a4c1, + 0x162ef9ea, 0x0f4e16d1, 0xc3d5e20b, 0x35daa8a8, + 0xdeef1e66, 0xfc9951c6, 0x742c112d, 0xcd28e8c3, + 0x63504ba5, 0xb89a4f9f, 0xcf3984e8, 0x70cdf63f, + 0x5309330f, 0x43481313, 0x6cb1a5b6, 0x1f614329, + 0x0ee349e7, 0x36b5a93f, 0x78cae082, 0xe6c49c6f, + 0x223ad81d, 0x6adeea01, 0x4a6ea977, 0x9c383b6f, + 0xbf3b7a4e, 0xe80b7d61, 0x59f0d065, 0x0493a415, + 0x64cabebe, 0xb16b6998, 0xcd4d2229, 0xc485f795, + 0x2ce9e286, 0xc692bc74, 0x0485f7ba, 0xc6000832, + 0x45f1c14c, 0x0511a00e, 0x009eb505, 0x5a81dccb, + 0x57c2b3d7, 0x51fa8ad0, 0x6234e65a, 0xfbd6f329, + 0x1adda2b7, 0x64a62985, 0x6991cc1a, 0x3dae87fe, + 0x22926ef2, 0x6578904b, 0x017d9808, 0x0d6e3d47, + 0x1a090f5a, 0xd56d1a5f, 0x124fbc5b, 0xaebfc35e, + 0x7f04f5b9, 0x1e3d65c5, 0x89bdf916, 0x96247f94, + 0xd260bd8e, 0x727ea29a, 0x9d36f2a8, 0x62a27215, + 0xf4238362, 0x6461896d, 0x19f278aa, 0xb56bfb72, + 0xfbe57af4, 0xd26f8dcb, 0x09f4770e, 0x7929d678, + 0x46f59a84, 0xac7929ac, 0x7296d8ff, 0x394143e8, + 0x928fddd6, 0xaca1da1e, 0xea9e6891, 0x9727c4be, + 0xcf840f4a, 0xdd1be31d, 0x8f30e588, 0xc9a8f6be, + 0x9b93ea5d, 0x7492f7a6, 0xb1d6cee5, 0x95a87cb3, + 0x9ee43ee6, 0xd8e372a8, 0x3d35a8eb, 0x32098155, + 0x8614adb9, 0x9e32c6ef, 0xead62942, 0x57b8de9a, + 0xc1253d8a, 0x18b231d7, 0x44eedd85, 0x150582b0, + 0x07f1be31, 0x39f684e7, 0x6a03918b, 0x42b109c9, + 0xd3bdaabf, 0x30e6fda4, 0xd97aea04, 0x909c06d8, + 0xd70e1c70, 0xe9bf27dc, 0xcd352018, 0x7d2163f1, + 0x2887de8b, 0x4b6be73d, 0x3d192717, 0xbf3cc76d, + 0xb4728f54, 0x5229835a, 0xbc68ccad, 0xfdd0ab5f, + 0x69ac96fd, 0x9740fbed, 0xbc2fa7c6, 0x0de3042f, + 0x5a5e3d4f, 0xb1d6b275, 0xa9b7407d, 0xac1691e3, + 0xdf7637f2, 0x74b874ea, 0x36020e6b, 0xfd36321a, + 0xa5a45e01, 0x180d0337, 0xb21bf552, 0x06a431fb, + 0x75ff33b1, 0xabbb603c, 0xe916c459, 0x49e10371, + 0x8e65e60b, 0x3df7f8c5, 0x5d8a980d, 0x710eedc4, + 0xcadb653e, 0x1cf814cb, 0xad5679b6, 0x8406c5a5, + 0x0cbd3558, 0x6b693037, 0x87f2f04b, 0x677c0878, + 0x013c86aa, 0x36e736e7, 0x25edbcd8, 0x59842d52, + 0x3eea2e08, 0xfe8df17c, 0x6828fcf0, 0x9c4cd6bf, + 0x38eb74a0, 0x76298f63, 0x1e5c1e16, 0xd65d0095, + 0x0f21ca88, 0x473eb1d5, 0xacb45cbc, 0x28c19269, + 0x950290e1, 0x41a85722, 0x92fd6c09, 0x625dc5de, + 0xec8b87f0, 0x12fcc4b3, 0x6677b585, 0x8467a81a, + 0xd84989cc, 0xe08ff19b, 0x7031a28a, 0x888a213d, + 0xc09b024a, 0x5b269127, 0xd082983e, 0x306e5f42, + 0x3e3275b7, 0x4ade3493, 0x1e30e31f, 0x432544c0, + 0xdfe1b89f, 0x1b020bb4, 0xd289a15d, 0xb47e6ed1, + 0xb6bcec8f, 0x5e7d5cf0, 0xe5243325, 0x3d161360, + 0x8a189892, 0xe2fcb714, 0x24323676, 0x0b783d24, + 0x2d0c5de0, 0x605adc6c, 0xf08a48bd, 0x3780292b, + 0xac1345ed, 0x19acf5e0, 0x14a0e9ca, 0x6693b797, + 0xede2aec9, 0x171f3513, 0xaf0cc796, 0xfd536607, + 0x35fe7a3f, 0x3060c0f5, 0xa834433e, 0xf0a825d4, + 0x0a297ffc, 0xff900aaa, 0xad8176f9, 0x4c52f059, + 0xf9837bfc, 0xe4df1ef2, 0x1a6afe07, 0x928cda83, + 0xc4e206db, 0x8ad021b0, 0xc1da95d4, 0xab0a9d55, + 0xcb0b17cf, 0xdf13feeb, 0x6befc003, 0xc965457a, + 0x35481ca1, 0x7fa4e244, 0x5049709d, 0x506a99df, + 0x0eebd7a0, 0x57082b12, 0xa65a85e4, 0x47279d6e, + 0x1b1db9bf, 0x88c8903b, 0x6bbfe95f, 0x787b40b2, + 0x3c638e83, 0x7701c216, 0xaee62103, 0x2618df71, + 0x265faa7c, 0x0688ab96, 0x41fe6dc0, 0xe6a25d50, + 0x0ed854a9, 0x7322b840, 0xe2f18643, 0xcd47f9b2, + 0x70315a67, 0x7b533295, 0x3cdb2f76, 0x28722eb2, + 0x53bb283b, 0xe1d9178a, 0x7cf0c578, 0x74f32d4d, + 0x5df88f1f, 0x36f28a5f, 0x93049cc1, 0x1b67f35e, + 0xfaf71107, 0xcdb2223d, 0x8116646f, 0xadcbb984, + 0xbb810283, 0x770428de, 0x7f055afe, 0x55926f61, + 0x3cb8ffa0, 0xd8de2a84, 0xda85cf86, 0xd0ab4089, + 0x8e483edd, 0xa464ab0d, 0xf9fe4b50, 0xaa8a398d, + 0xd3ea43cd, 0x9bffb5c2, 0x5e1fc86a, 0xd4ce2de6, + 0x9e910929, 0xe052f316, 0x29128865, 0xaaacd8d2, + 0x6a0af765, 0xc65f8a0b, 0x5c421aa9, 0xc7438e43, + 0x0313f7f1, 0x351dc465, 0x5cd11fda, 0xb9c1a4c9, + 0x748b67de, 0x227757be, 0xf12439ea, 0x25a3c656, + 0xf2a8130f, 0xc507ea1a, 0xf2b9d4b9, 0x18db074a, + 0x1568c873, 0xfc2d6d22, 0xba80b5ba, 0xa66bbe21, + 0x2e05b794, 0x61de03ed, 0xef9aa166, 0x38edb3f1, + 0xc5af7d6b, 0x0d6b201d, 0x05b59096, 0x8978960f, + 0x7158192c, 0xaf3204a9, 0xa2efb524, 0x9224f5b1, + 0x21e9c2c8, 0xe68fec8c, 0x42fed4f8, 0xc31222ab, + 0x5ea175c2, 0xdd0b129c, 0xba921672, 0x6812cbe4, + 0x8bb9ac49, 0xd30c8613, 0x5ab8d776, 0xae9dd616, + 0xa57c731c, 0x4ec2cc9e, 0x6c1c8fd2, 0xd64bbc64, + 0xa49289b5, 0xb70bac9b, 0x2966be85, 0x6b9add49, + 0x1eaed5d2, 0x7b5dc71e, 0x91c2e9a7, 0x86ee3a2a, + 0xb1716972, 0xa263bb68, 0x5e4203b5, 0x5f807557, + 0xa902dce4, 0x00c4d8cb, 0xe86bc835, 0xafb3e079, + 0xa481f6bb, 0x75a8d0e5, 0xf8d0c00e, 0xeca9d69e, + 0x4bfac55d, 0x20ca4fe6, 0x528028de, 0x25c2c029, + 0x630d31cb, 0x24c2ac90, 0xf7c818a8, 0x8370070c, + 0xa40454d2, 0xbc626881, 0xf75228a3, 0xb0910df9, + 0xc0d3f181, 0xbe0fe37f, 0x67df53bf, 0x3a7ecd46, + 0x03103f29, 0x8b708a7e, 0xd52fa2f3, 0x2980e01e, + 0x3a332ef8, 0x240112ee, 0xbc418331, 0x363a928a, + 0x4c1a784c, 0xfc7b33a9, 0x9857151e, 0x1a171702, + 0x8e8d5077, 0x711190ea, 0x0c537fa8, 0x56fa6036, + 0x3676d8f3, 0xaa03d3e1, 0x6ed9603c, 0xed154b7d, + 0x54ede682, 0x049c956c, 0x2728ddcb, 0x8fcb0bcb, + 0xfd8d804e, 0x462bd2b8, 0xfab74af9, 0x4854db66, + 0x956efff4, 0xe424678a, 0x8ca7dc77, 0xc71fe712, + 0xcbbc4650, 0xdc27de0a, 0xc5c29d05, 0xb398c619, + 0x37574ff3, 0xbb531ff1, 0xb1e4a6c8, 0x38a7d0a7, + 0x91d482d9, 0x0399d50e, 0x4fdf4895, 0xd5af2860, + 0x2de8be74, 0x96dd0097, 0xb0348c8b, 0x5e12f208, + 0xd746b55b, 0x81c83f65, 0xe2ab1729, 0x1340c95a, + 0x1d5f2d9c, 0x178bcefe, 0x0b597ea6, 0xeea916dc, + 0xd8f39882, 0x4960f175, 0x3cfbacfa, 0xb8f9e94f, + 0xc6e968d8, 0xfa8a05ef, 0x540f57ac, 0x99a5d41d, + 0xce11e1b6, 0x4cde578d, 0xce91ab33, 0xc2402b77, + 0x1878874f, 0x38da95c2, 0x7364cb4d, 0x78d33ae8, + 0x5404d777, 0x7ebc13c9, 0x020b9fd8, 0x3b2457d2, + 0xffcdd8ed, 0xabbe2125, 0x9edfc568, 0x47f980e5, + 0x42629cb8, 0x05d19c95, 0x9e15d503, 0x7d8a78b4, + 0x7e8a00d1, 0x7a61d8ca, 0x609c6648, 0x78efe49d, + 0xe07f514f, 0xc28eb52e, 0x4ee13e9b, 0xb669c8dd, + 0xb6b56de1, 0xcd1e0b57, 0xf914a6b1, 0x05443ed8, + 0xa8e0f160, 0x1a2f663d, 0x7ecbb9db, 0xa996c4de, + 0x714165dd, 0x164e3c6d, 0x6799e088, 0xc4844910, + 0x2f11c084, 0x6c9b16f1, 0x498d0277, 0x48d4e108, + 0xdd3cbc0e, 0xafc99cba, 0x6bc6be33, 0x67b777b4, + 0x3814b32b, 0x084df57c, 0x91497993, 0x031aa91e, + 0xad31ea96, 0xf3d525cd, 0xdfa76674, 0x30cd4b3e, + 0xa67cd93b, 0x2be19f6c, 0xde035d1f, 0xac2f17ff, + 0xd062444c, 0xea130882, 0x841810ef, 0x8b72c626, + 0xa233058b, 0x6dad86c7, 0x83143b86, 0x9fa105ff, + 0xe5a29b1c, 0x8ceef5c3, 0x5ea7a831, 0x8fad80b7, + 0x0defccad, 0xde20b371, 0x18afeb2b, 0x841dc112, + 0x4c81a42e, 0xb73694c0, 0x2492cb01, 0xe472137d, + 0x1a54da71, 0xdd5af1f7, 0xc654edb7, 0x4e328d0c, + 0x9a8632c9, 0xf4de4d16, 0x71c03fef, 0xf54b4bef, + 0xa0d14f76, 0x59d1781f, 0xee38ea5c, 0xa11799d7, + 0x463efbd9, 0x04f9b231, 0xb1c0f78d, 0x84486bdf, + 0xce349a7e, 0x7b5f2039, 0x01199a40, 0x35bfa363, + 0xc3a644b5, 0xffd9ccfa, 0xb5e0bc43, 0xf3b749b1, + 0xd7d6aaa0, 0x1b6a08cd, 0x63e5b2cf, 0x1796418a, + 0x01cab369, 0xd19299ed, 0x76b095ca, 0x9b1143c0, + 0x8907df76, 0x91dbdec7, 0x4063f12a, 0x59f32b96, + 0x82433cbc, 0xdde09636, 0x9b9a791d, 0x217a2d1f, + 0xde07fd25, 0xc997f4fd, 0xe0f66e00, 0xc3a89c5c, + 0x94adc76a, 0x08c43e18, 0x3c33bbe1, 0x2632587a, + 0x1b881ffb, 0xef110ff7, 0x1f81d7bb, 0x1ed250d1, + 0xa3af23eb, 0xc7f2b3fd, 0xbea4d3e9, 0x2db7289a, + 0x172d0c1f, 0x9ad2bcd0, 0xb1f57b5c, 0xf0a8db81, + 0x0672d3fc, 0x1b2e64e6, 0xe379cc38, 0x8cb03b29, + 0xbfc85cd6, 0xd2523a4c, 0x3ca16aab, 0xfbe70f25, + 0xe7637a83, 0x7faf9721, 0x802af4f6, 0xa239ad27, + 0x1cf076c6, 0xe19e9501, 0x31fb4c71, 0xdcb5cb04, + 0x99e696bd, 0xdbd94502, 0xad577ad3, 0x2296ed1b, + 0xf72dfee2, 0x8a1c8216, 0x0b47f1e9, 0x2be0f5b6, + 0x17af93a8, 0xe2839fe8, 0x8c57d5ef, 0xf3a48778, + 0xabf974dd, 0x0a5a6a18, 0xcaaee9fa, 0xf24c2f8e, + 0x36548e1c, 0x93fe2463, 0x4ebf4dae, 0xf694fbc6, + 0x726e5346, 0x38f24e63, 0x97d7f692, 0x95448a99, + 0xb54590bc, 0x7ac61137, 0x828c3906, 0x07d000d4, + 0x00b97a9a, 0x073fac2b, 0x97792825, 0x82eaf63c, + 0x53ba5986, 0x0f5b2204, 0x07dfd8f8, 0x68ec1028, + 0x3ac66a6f, 0xec219405, 0x0300bfac, 0xd64b818c, + 0xf07d9f72, 0x7414e7a4, 0x7ea66fbe, 0xca875128, + 0x6a0ce1b4, 0x71b85ee7, 0x9a279f06, 0x3878078f, + 0xe85fdac7, 0x8a01f933, 0x08c65ab2, 0x99a90038, + 0x81520d4a, 0x2f733500, 0xea1697f2, 0xcf79dfea, + 0x924c33aa, 0x925e6c00, 0xb0930980, 0x19710873, + 0x64c9968a, 0x34f77cb7, 0xce19cbf6, 0x159db8cf, + 0xc50b543d, 0x91117f85, 0xb28ea62d, 0xa16df12e, + 0xfd6071a5, 0x7bcf16bf, 0x3c6fb55b, 0x963a3f0f, + 0x64a002e7, 0xb81bdd2a, 0xb00b2805, 0xb85a4449, + 0x61ef60f5, 0xab63f13a, 0x00b65cd3, 0xe69a8f8b, + 0x67695706, 0xa3fe0dd8, 0x91019b25, 0x68a87822, + 0xd81953f4, 0x406c5b42, 0x0d95ae3b, 0x70484426, + 0xbb82f14f, 0x57b3532e, 0xb2f9a824, 0x4077ae7a, + 0x5306362a, 0x844356dc, 0x161f3b05, 0xfa0aae3d, + 0x9d07c011, 0x2c74cc6e, 0x4709cf01, 0x6732f368, + 0xad358d82, 0x115a4d6f, 0xc19dd001, 0xebefae09, + 0x2b41e8f0, 0x23fc59a9, 0x36d7ba91, 0x75205b26, + 0xb7c4dde3, 0x27955607, 0xc17e4fc3, 0x92d1970c, + 0x9cf7430a, 0xf4abd37a, 0x33909bf6, 0x2401df1b, + 0xa6aa6139, 0x138bb7a7, 0xfddfd1dc, 0xb21f6159, + 0x4bf0b264, 0x4ec56c50, 0xabc27f5f, 0xa01820d2, + 0xa964201e, 0xc095b91d, 0xe17fdced, 0x5c241bf9, + 0xada762b0, 0xb89a19be, 0x792cd215, 0xb2da7c7a, + 0xbef07dc3, 0x82b50720, 0x5fc7042f, 0x20ab844b, + 0xe3d89819, 0x81ca6921, 0x5c8a3cff, 0x4af50ac3, + 0xe35f0187, 0xabdc2ed5, 0x06876ced, 0xc30eb89d, + 0x382fd610, 0x7d8e26a5, 0x490dab77, 0x31800ce6, + 0x39832874, 0xe2f29400, 0x3c0c859d, 0x0f999998, + 0x5ecfdc04, 0x17d97f0c, 0x4f62316d, 0x1c3f00fc, + 0x48dd3a28, 0x15c41775, 0xcd2cf12b, 0xb6e86cb6, + 0x98e25b60, 0xe1185c68, 0x8c557099, 0xe006a741, + 0xdb2806b9, 0x27728510, 0x53735837, 0x2e1cbae6, + 0x41e290f0, 0x47d18cf9, 0x3d238589, 0x6d0b75f2, + 0xaef97cf9, 0x1ea67e5d, 0x1d67e1e0, 0x4aaeb849, + 0x6192f4ef, 0xdd8f28db, 0xf23e8319, 0x9f59ddf1, + 0xfd1f61b9, 0xcd37426f, 0xf0540f0d, 0x6a774572, + 0x1d9b4e40, 0xdae5208d, 0x596bd3f2, 0xbccac900, + 0x2489b46d, 0xb472aeec, 0x9b32766e, 0x1a6b3fbf, + 0x99e6b891, 0x4918256c, 0xad454f89, 0x8a89ae99, + 0x360a7d17, 0xa0c3d95a, 0xb712ee6d, 0x988346a3, + 0x72c97b16, 0xb577609d, 0x50fc6d92, 0xe76c3ed0, + 0x0292cc2a, 0x90ca06cd, 0x5471810e, 0xe7720dc8, +#endif /* defined __LIT */ +}; + +/********************************************************************************************************************** + Private (static) variables and functions + *********************************************************************************************************************/ + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h new file mode 100644 index 000000000..5f1bfaade --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/SCE_module.h @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x40161000UL + +#endif // HW_SCE_MODULE_H diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h new file mode 100644 index 000000000..fd7ce6311 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h @@ -0,0 +1,589 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2017-2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * File Name : hw_sce_ra_private.h + * Version : 1.09 + * Description : SCE function private header file. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "r_sce_if.h" +#include "SCE_ProcCommon.h" + +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#if SCE_SECURE_BOOT != 0 +/* Required for each variable definition with no initial value to be placed in the SECURE_BOOT section. */ +#define SCE_PRV_SEC_B_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(B, SECURE_BOOT, 4) +/* Required for each function definition to be placed in the SECURE_BOOT section. */ +#define SCE_PRV_SEC_P_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(P, SECURE_BOOT) +/* Revert to default section. */ +#define SCE_PRV_SEC_DEFAULT R_BSP_ATTRIB_SECTION_CHANGE_END +#else +/* Required for each variable definition with no initial value to be placed in the SECURE_BOOT section.(dummy) */ +#define SCE_PRV_SEC_B_SECURE_BOOT +/* Required for each function definition to be placed in the SECURE_BOOT section.(dummy) */ +#define SCE_PRV_SEC_P_SECURE_BOOT +/* Revert to default section.(dummy) */ +#define SCE_PRV_SEC_DEFAULT +#endif /* SCE_SECURE_BOOT != 0 */ + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +extern uint32_t const S_FLASH2[]; + +extern uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +extern uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +extern uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +extern uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +extern SCE_GEN_MAC_CB_FUNC_T SCE_GEN_MAC_CB_FUNC; + +extern uint32_t INST_DATA_SIZE; +extern const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM]; + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ +/* --------------------- SCE driver wrapper layer ---------------------- */ + +fsp_err_t HW_SCE_Aes128EcbEncryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EcbEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128EcbDecryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EcbDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128CbcEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128CbcEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CbcEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes128CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes256EcbEncryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EcbEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256EcbDecryptInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EcbDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256CbcEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256CbcEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CbcEncryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); +fsp_err_t HW_SCE_Aes256CbcDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256CbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CbcDecryptFinalPrivate(uint32_t *OutData_Text, uint32_t *OutData_length); + +fsp_err_t HW_SCE_Aes128GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes128GcmDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256GcmEncryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256GcmDecryptInitPrivate(sce_aes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdateAadPrivate(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_Aes128GcmEncryptUpdateTransitionPrivate(void); +void HW_SCE_Aes128GcmDecryptUpdateTransitionPrivate(void); +void HW_SCE_Aes256GcmEncryptUpdateTransitionPrivate(void); +void HW_SCE_Aes256GcmDecryptUpdateTransitionPrivate(void); + +fsp_err_t HW_SCE_Aes128CcmEncryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalPrivate(uint32_t *InData_TextLen, uint32_t *InData_Text, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes128CcmDecryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256CcmEncryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmEncryptFinalPrivate(uint32_t *InData_TextLen, uint32_t *InData_Text, + uint32_t *OutData_Text, uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes256CcmDecryptInitPrivate(sce_aes_key_index_t *KeyIndex, uint32_t *InData_IV, + uint32_t *InData_Header, uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmDecryptFinalPrivate(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes128CmacGenerateInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacGenerateUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, + uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes128CmacVerifyInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacVerifyUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacVerifyFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen); +fsp_err_t HW_SCE_Aes256CmacGenerateInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacGenerateUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, + uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256CmacVerifyInitPrivate(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacVerifyUpdatePrivate(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacVerifyFinalPrivate(uint32_t All_Msg_Len, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen); + +fsp_err_t HW_SCE_Sha1InitPrivate(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Sha1UpdatePrivate(sce_sha_md5_handle_t *handle, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha1FinalPrivate(sce_sha_md5_handle_t *handle, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, + uint32_t *OutData_MsgDigest, uint32_t *OutData_Length); +fsp_err_t HW_SCE_Sha256InitPrivate(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Sha256UpdatePrivate(sce_sha_md5_handle_t *handle, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha256FinalPrivate(sce_sha_md5_handle_t *handle, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, + uint32_t *OutData_MsgDigest, uint32_t *OutData_Length); +fsp_err_t HW_SCE_Md5InitPrivate(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Md5UpdatePrivate(sce_sha_md5_handle_t *handle, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Md5FinalPrivate(sce_sha_md5_handle_t *handle, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, + uint32_t *OutData_MsgDigest, uint32_t *OutData_Length); + +fsp_err_t HW_SCE_Sha1HmacGenerateInitPrivate(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha1HmacGenerateUpdatePrivate(sce_hmac_sha_handle_t *handle, uint32_t *InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha1HmacGenerateFinalPrivate(sce_hmac_sha_handle_t *handle, uint32_t *OutData_Mac); +fsp_err_t HW_SCE_Sha1HmacVerifyInitPrivate(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha1HmacVerifyUpdatePrivate(sce_hmac_sha_handle_t *handle, uint32_t *InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha1HmacVerifyFinalPrivate(sce_hmac_sha_handle_t *handle, uint32_t *InData_Mac, + uint32_t *InData_length); +fsp_err_t HW_SCE_Sha256HmacGenerateInitPrivate(sce_hmac_sha_handle_t *handle, + sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha256HmacGenerateUpdatePrivate(sce_hmac_sha_handle_t *handle, uint32_t *InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha256HmacGenerateFinalPrivate(sce_hmac_sha_handle_t *handle, uint32_t *OutData_Mac); +fsp_err_t HW_SCE_Sha256HmacVerifyInitPrivate(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha256HmacVerifyUpdatePrivate(sce_hmac_sha_handle_t *handle, uint32_t *InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha256HmacVerifyFinalPrivate(sce_hmac_sha_handle_t *handle, uint32_t *InData_Mac, + uint32_t *InData_length); + +fsp_err_t HW_SCE_Rsa1024ModularExponentEncryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa1024ModularExponentDecryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa2048ModularExponentEncryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa3072ModularExponentDecryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa4096ModularExponentDecryptPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationPrivate(uint32_t *InData_CurveType, uint32_t *InData_Cmd, + uint32_t *InData_KeyIndex, uint32_t *InData_PubKey, uint32_t *OutData_R); +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, + const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationPrivate(uint32_t *InData_CurveType, + uint32_t *InData_KeyIndex, uint32_t *InData_PubKey, uint32_t *OutData_R); +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, + const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); + +fsp_err_t HW_SCE_TdesEcbEncryptInitPrivate(sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_TdesEcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_TdesEcbEncryptFinalPrivate(void); +fsp_err_t HW_SCE_TdesEcbDecryptInitPrivate(sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_TdesEcbDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_TdesEcbDecryptFinalPrivate(void); +fsp_err_t HW_SCE_TdesCbcEncryptInitPrivate(sce_tdes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_TdesCbcEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_TdesCbcEncryptFinalPrivate(void); +fsp_err_t HW_SCE_TdesCbcDecryptInitPrivate(sce_tdes_key_index_t *key_index, uint32_t *InData_IV); +fsp_err_t HW_SCE_TdesCbcDecryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_TdesCbcDecryptFinalPrivate(void); + +fsp_err_t HW_SCE_EcdhReadPublicKeyPrivate(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_data, + uint32_t *InData_Signature, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_EcdhMakePublicKeyPrivate(uint32_t *InData_Cmd, uint32_t *InData_KeyType, + uint32_t *InData_PubKeyIndex, uint32_t *InData_PrivKeyIndex, uint32_t *InData_key_id, uint32_t *OutData_data, + uint32_t *OutData_Signature, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_EcdhCalculateSharedSecretIndexPrivate(uint32_t *InData_KeyType, uint32_t *InData_PubKeyIndex, + uint32_t *InData_PrivKeyIndex, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_EcdhKeyDerivationPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_Aes128KeyWrapPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_WrappedKeyType, + uint32_t *InData_WrappedKeyIndex, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256KeyWrapPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_WrappedKeyType, + uint32_t *InData_WrappedKeyIndex, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes128KeyUnWrapPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_WrappedKeyType, + uint32_t *InData_Text, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_Aes256KeyUnWrapPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_WrappedKeyType, + uint32_t *InData_Text, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_KeyUnwrapPrivate(uint32_t *InData_KeyIndex, uint32_t *InData_Text, uint32_t *OutData_KeyIndex); + + +/* --------------------- SCE control procedure related ---------------------- */ + +void HW_SCE_SoftwareResetSub(void); +fsp_err_t HW_SCE_SelfCheck1Sub(void); +fsp_err_t HW_SCE_SelfCheck2Sub(void); +fsp_err_t HW_SCE_LoadHukSub(uint32_t *InData_LC); + +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndexSub(uint32_t *InData_LC, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); +fsp_err_t HW_SCE_UpdateOemKeyIndexSub(uint32_t *InData_LC, uint32_t *InData_Cmd, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateOemKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_Cmd, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); + +fsp_err_t HW_SCE_GenerateAes128KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256KeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateTdesKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateTdesRandomKeyIndexSub(uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa1024PublicKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa1024PrivateKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa2048PublicKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa2048PrivateKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa3072PublicKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa3072PrivateKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa4096PublicKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa4096PrivateKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRsa1024RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PrivKeyIndex); +fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PrivKeyIndex); +fsp_err_t HW_SCE_GenerateRsa3072RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PrivKeyIndex); +fsp_err_t HW_SCE_GenerateRsa4096RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PrivKeyIndex); +fsp_err_t HW_SCE_GenerateTlsRsaInstallDataSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); +fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndexSub(uint32_t *OutData_KeyIndex, uint32_t *OutData_PubKey); +fsp_err_t HW_SCE_GenerateEccPrivateKeyIndexSub(uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, uint32_t *InData_Cmd, uint32_t *InData_IV, + uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateEccPublicKeyIndexSub(uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, uint32_t *InData_Cmd, uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, uint32_t *OutData_PubKeyIndex, + uint32_t *OutData_PrivKeyIndex); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveType, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PrivKeyIndex); +fsp_err_t HW_SCE_GenerateShaHmacKeyIndexSub(uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_Cmd, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateRandomNumberSub(uint32_t *OutData_Text); +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndexSub(uint32_t *InData_LC, uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); + +fsp_err_t HW_SCE_UpdateAes128KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateAes256KeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateTdesKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa1024PrivateKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa2048PublicKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa2048PrivateKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa3072PublicKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa3072PrivateKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa4096PublicKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateRsa4096PrivateKeyIndexSub(uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateTlsRsaDataSub(uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_InstData); +fsp_err_t HW_SCE_UpdateEccPrivateKeyIndexSub(uint32_t *InData_Cmd, uint32_t *InData_IV, + uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateEccPublicKeyIndexSub(uint32_t *InData_Cmd, uint32_t *InData_IV, + uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndexSub(uint32_t *InData_IV, + uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndexSub(uint32_t *InData_IV, + uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateShaHmacKeyIndexSub(uint32_t *InData_Cmd, uint32_t *InData_IV, uint32_t *InData_InstData, + uint32_t *OutData_KeyIndex); + +fsp_err_t HW_SCE_StartUpdateFirmwareSub(void); +fsp_err_t HW_SCE_GenerateFirmwareMacSub(uint32_t *InData_KeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_UpProgram, uint32_t *InData_IV, uint32_t *OutData_Program, uint32_t MAX_CNT, + sce_firmware_generate_mac_resume_handle_t *sce_firmware_generate_mac_resume_handle); +fsp_err_t HW_SCE_VerifyFirmwareMacSub(uint32_t *InData_Program, uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +void HW_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub(const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_IV); +void HW_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t *InData_Text, uint32_t *OutData_Text, const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); + +fsp_err_t HW_SCE_Ghash(uint32_t *InData_HV, uint32_t *InData_IV, uint32_t *InData_Text, uint32_t *OutData_DataT, + uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes128GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub(void); +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub(void); +void HW_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256GcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataALen, + uint32_t *InData_TextLen, uint32_t *OutData_Text, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_Aes256GcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataALen, uint32_t *InData_TextLen, uint32_t *InData_DataTLen, uint32_t *OutData_Text); +void HW_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); +void HW_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t *InData_DataA, uint32_t MAX_CNT); + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes128CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, + uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes128CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes256CcmEncryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(uint32_t *InData_TextLen, uint32_t *InData_Text, uint32_t *OutData_Text, + uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(uint32_t *InData_KeyIndex, uint32_t *InData_IV, uint32_t *InData_Header, + uint32_t Header_Len); +void HW_SCE_Aes256CcmDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(uint32_t *InData_Text, uint32_t *InData_TextLen, uint32_t *InData_MAC, + uint32_t *InData_MACLength, uint32_t *OutData_Text); + +fsp_err_t HW_SCE_Aes128CmacInitSub(uint32_t *InData_KeyIndex); +void HW_SCE_Aes128CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen, uint32_t *OutData_DataT); +fsp_err_t HW_SCE_Aes256CmacInitSub(uint32_t *InData_KeyIndex); +void HW_SCE_Aes256CmacUpdateSub(uint32_t *InData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_Text, uint32_t *InData_DataT, + uint32_t *InData_DataTLen, uint32_t *OutData_DataT); + +fsp_err_t HW_SCE_Sha1GenerateMessageDigestSub(uint32_t *InData_SHA1InitVal, uint32_t *InData_PaddedMsg, + uint32_t MAX_CNT, uint32_t *OutData_MsgDigest); +fsp_err_t HW_SCE_Sha224256GenerateMessageDigestSub(const uint32_t *InData_SHAInitVal, const uint32_t *InData_PaddedMsg, + const uint32_t MAX_CNT, uint32_t *OutData_MsgDigest); +fsp_err_t HW_SCE_Md5GenerateMessageDigestSub(uint32_t *InData_MD5InitVal, uint32_t *InData_PaddedMsg, + uint32_t MAX_CNT, uint32_t *OutData_MsgDigest); + +fsp_err_t HW_SCE_Sha1HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t LEN); +void HW_SCE_Sha1HmacUpdateSub(uint32_t *InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha1HmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_MAC, uint32_t *InData_length, + uint32_t *OutData_MAC); +fsp_err_t HW_SCE_Sha256HmacInitSub(uint32_t *InData_KeyType, uint32_t *InData_KeyIndex, uint32_t LEN); +void HW_SCE_Sha256HmacUpdateSub(uint32_t *InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha256HmacFinalSub(uint32_t *InData_Cmd, uint32_t *InData_MAC, uint32_t *InData_length, + uint32_t *OutData_MAC); + +fsp_err_t HW_SCE_TdesEncryptDecryptInitSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_IV); +void HW_SCE_TdesEncryptDecryptUpdateSub(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); +fsp_err_t HW_SCE_TdesEncryptDecryptFinalSub(void); + +fsp_err_t HW_SCE_TlsRootCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, uint32_t *InData_Certificates, + uint32_t *InData_CertificatesLength, uint32_t *InData_Signature, uint32_t *InData_CertificatesInfo, + uint32_t length, uint32_t *OutData_PubKey); +fsp_err_t HW_SCE_TlsCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, uint32_t *InData_PubKey, + uint32_t *InData_TBSCertificate, uint32_t *InData_TBSCertificateLength, uint32_t *InData_Signature, + uint32_t *InData_TBSCertificateInfo, uint32_t length, uint32_t *OutData_PubKey); +fsp_err_t HW_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, uint32_t *InData_PreMasterSecret, + uint32_t *OutData_PreMasterSecret); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecretSub(uint32_t *OutData_PreMasterSecret); +fsp_err_t HW_SCE_TlsGenerateMasterSecretSub(uint32_t *InData_Sel_CipherSuite, uint32_t *InData_PreMasterSecret, + uint32_t *InData_ClientRandom, uint32_t *InData_ServerRandom, uint32_t *OutData_MasterSecret); +fsp_err_t HW_SCE_TlsGenerateSessionKeySub(uint32_t *InData_Sel_CipherSuite, uint32_t *InData_MasterSecret, + uint32_t *InData_ClientRandom, uint32_t *InData_ServerRandom, uint32_t *InData_NonceExplicit, + uint32_t *OutData_ClientMACKeyOperationCode, uint32_t *OutData_ServerMACKeyOperationCode, + uint32_t *OutData_ClientEncKeyOperationCode, uint32_t *OutData_ServerEncKeyOperationCode, uint32_t OutLen); +fsp_err_t HW_SCE_TlsGenerateVerifyDataSub(uint32_t *InData_Sel_VerifyData, uint32_t *InData_MasterSecret, + uint32_t *InData_HandShakeHash, uint32_t *OutData_VerifyData); + +fsp_err_t HW_SCE_TlsGeneratePreMasterSecretWithEccP256KeySub(uint32_t *InData_PubKey, uint32_t *InData_KeyIndex, + uint32_t *OutData_PreMasterSecretIndex); +fsp_err_t HW_SCE_TlsServersEphemeralEcdhPublicKeyRetrievesSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_ClientRandom, uint32_t *InData_ServerRandom, uint32_t *InData_Sel_CompressType, + uint32_t *InData_SKE_Message, uint32_t *InData_SKE_Signature, uint32_t *InData_PubKey, + uint32_t *OutData_EphemeralPubKey); + +fsp_err_t HW_SCE_Rsa1024ModularExponentEncryptSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa1024ModularExponentDecryptSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa2048ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub(uint32_t *InData_KeyIndex, const uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa3072ModularExponentDecryptSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t *InData_KeyIndex, const uint32_t *InData_Text, + uint32_t *OutData_Text); +fsp_err_t HW_SCE_Rsa4096ModularExponentDecryptSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, + uint32_t *OutData_Text); + +fsp_err_t HW_SCE_EcdsaSigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, + const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); +fsp_err_t HW_SCE_EcdsaP384SigunatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, + const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); +fsp_err_t HW_SCE_EcdsaSigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, + const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); +fsp_err_t HW_SCE_EcdsaP384SigunatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, + const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); + +fsp_err_t HW_SCE_DlmsCosemQeuSignatureVerificationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, + uint32_t *InData_data, uint32_t *InData_Signature, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_DlmsCosemQevSignatureGenerationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyType, + uint32_t *InData_PubKeyIndex, uint32_t *InData_PrivKeyIndex, uint32_t *InData_key_id, uint32_t *OutData_data, + uint32_t *OutData_Signature, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_DlmsCosemCalculateZSub(uint32_t *InData_KeyType, uint32_t *InData_PubKeyIndex, + uint32_t *InData_PrivKeyIndex, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_DlmsCosemCalculateKekSub(uint32_t *InData_KeyIndex, uint32_t *InData_PaddedMsg, uint32_t MAX_CNT, + uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_DlmsCosemKeyUnwrapSub(uint32_t *InData_KeyIndex, uint32_t *InData_Text, uint32_t *OutData_KeyIndex); + +fsp_err_t HW_SCE_AESKeyWrapSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t KEY_INDEX_SIZE, uint32_t + *InData_WrappedKeyType, uint32_t *InData_WrappedKeyIndex, uint32_t WRAPPED_KEY_SIZE, uint32_t *OutData_Text); +fsp_err_t HW_SCE_AESKeyUnwrapSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t KEY_INDEX_SIZE, uint32_t + *InData_WrappedKeyType, uint32_t *InData_Text, uint32_t WRAPPED_KEY_SIZE, uint32_t *OutData_KeyIndex); + +void HW_SCE_TlsRootCertificateVerificationSubSub(void); +void HW_SCE_TlsGenerateSubSub(void); + +void HW_SCE_SelfCheck1SubSub(void); +void HW_SCE_SelfCheck2SubSub(void); + +void HW_SCE_p_func000(uint32_t *InData_PaddedMsg, int32_t MAX_CNT); +void HW_SCE_p_func001(void); +void HW_SCE_p_func002(void); +void HW_SCE_p_func027_r2(uint32_t ARG1); +void HW_SCE_p_func028_r2(uint32_t ARG1); +void HW_SCE_p_func043(void); +void HW_SCE_p_func044(void); +void HW_SCE_p_func048(uint32_t* ARG1); +void HW_SCE_p_func049(uint32_t* ARG1); +void HW_SCE_p_func050(uint32_t ARG1); +void HW_SCE_p_func051(void); +void HW_SCE_p_func052(uint32_t ARG1); +void HW_SCE_p_func053(uint32_t ARG1); +void HW_SCE_p_func054(uint32_t ARG1, uint32_t ARG2); +void HW_SCE_p_func057_r1(uint32_t* ARG1, uint32_t* ARG2, uint32_t* ARG3); +void HW_SCE_p_func058(uint32_t* ARG1, uint32_t ARG2); +void HW_SCE_p_func059(void); +void HW_SCE_p_func060(void); +void HW_SCE_p_func061(uint32_t ARG1, uint32_t* ARG2); +void HW_SCE_p_func062(uint32_t ARG1, uint32_t* ARG2); +void HW_SCE_p_func063(uint32_t ARG1, uint32_t* ARG2); +void HW_SCE_p_func064(uint32_t ARG1, uint32_t* ARG2); +void HW_SCE_p_func065_r1(uint32_t* ARG1, uint32_t* ARG2); +void HW_SCE_p_func066(uint32_t ARG1, uint32_t* ARG2); +void HW_SCE_p_func067(uint32_t ARG1, uint32_t* ARG2); +void HW_SCE_p_func068(void); +void HW_SCE_p_func070_r2(uint32_t ARG1); +void HW_SCE_p_func071_r2(uint32_t ARG1); +void HW_SCE_p_func074_r1(void); +void HW_SCE_p_func075_r1(void); +void HW_SCE_p_func076(void); +void HW_SCE_p_func077(void); +void HW_SCE_p_func080(void); +void HW_SCE_p_func081(void); +void HW_SCE_p_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func103(void); +void HW_SCE_p_func200(void); +void HW_SCE_p_func202(void); +void HW_SCE_p_func206(void); +void HW_SCE_p_func300(void); +void HW_SCE_p_func301(void); +void HW_SCE_p_func302(void); +void HW_SCE_p_func304(void); +void HW_SCE_p_func307(void); +void HW_SCE_p_func308(void); +void HW_SCE_p_func309(void); +void HW_SCE_p_func310(void); +void HW_SCE_p_func311(void); +void HW_SCE_p_func312(uint32_t ARG1); +void HW_SCE_p_func313(uint32_t ARG1); +void HW_SCE_p_func314(uint32_t ARG1); +void HW_SCE_p_func315(uint32_t ARG1); +void HW_SCE_p_func316(void); +void HW_SCE_p_func317(void); +void HW_SCE_p_func318(void); +void HW_SCE_p_func319(uint32_t ARG1); +void HW_SCE_p_func320(uint32_t ARG1); +void HW_SCE_p_func321(uint32_t ARG1); +void HW_SCE_p_func322(uint32_t ARG1); +void HW_SCE_p_func323(void); +void HW_SCE_p_func324(void); +void HW_SCE_p_func325(void); + + +void firm_mac_read(uint32_t *InData_Program); + +uint32_t change_endian_long(uint32_t data); + +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h new file mode 100644 index 000000000..d64611b31 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h @@ -0,0 +1,1123 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2015-2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * File Name : r_sce_if.h + * Version : 1.09 + * Description : Interface definition for the r_sce module. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +// added for RA6M4 start +//#include "platform.h" +#include "bsp_api.h" +// added for RA6M4 end + + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE +#define R_SCE_IF_HEADER_FILE + + +// added for RA6M4 start +#if 0 +// added for RA6M4 end + +#if R_BSP_VERSION_MAJOR < 5 +#error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif +#if (defined BSP_MCU_RX231 || defined BSP_MCU_RX23W) && (BSP_CFG_MCU_PART_VERSION == 0xB) /* B */ +#elif (defined BSP_MCU_RX66T || defined BSP_MCU_RX72T) && ((BSP_CFG_MCU_PART_FUNCTION == 0xE /* E */) || \ + (BSP_CFG_MCU_PART_FUNCTION == 0xF /* F */) || (BSP_CFG_MCU_PART_FUNCTION == 0x10 /* G */)) +#elif (defined BSP_MCU_RX65N || defined BSP_MCU_RX651) && (BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED == true) +#elif (defined BSP_MCU_RX72M || defined BSP_MCU_RX72N || defined BSP_MCU_RX66N) && \ + (BSP_CFG_MCU_PART_FUNCTION == 0x11 /* H */) +#else +#error "Your MCU does not support SCE functions. Please confirm BSP_MCU_xxx macro in r_bsp_config.h." +#endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W && BSP_CFG_MCU_PART_VERSION == 0xB */ + +// added for RA6M4 start +#endif +// added for RA6M4 end + +/* Version Number of API. */ +#define SCE_VERSION_MAJOR (1U) +#define SCE_VERSION_MINOR (9U) + +/* Various information. */ +#define HW_SCE_SRAM_WORD_SIZE (32U) +#define HW_SCE_SINST_WORD_SIZE (140U) +#define HW_SCE_SINST2_WORD_SIZE (16U) +#define HW_SCE_SHEAP_WORD_SIZE (1504U) +#define HW_SCE_MAC_SIZE (16U) + +/* For AES operation. */ +#define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_AES128_KEY_WORD_SIZE (4U) +#define HW_SCE_AES256_KEY_WORD_SIZE (8U) +#define HW_SCE_AES128_KEY_BYTE_SIZE (16U) +#define HW_SCE_AES256_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) +#define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) +#define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) + +/* For TDES operation. */ +#define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_TDES_BLOCK_BYTE_SIZE (8U) +#define HW_SCE_TDES_CBC_IV_BYTE_SIZE (8U) +#define HW_SCE_TDES_KEY_WORD_SIZE (8U) +#define HW_SCE_TDES_KEY_BYTE_SIZE (32U) + +/* For ARC4 operation. */ +#define HW_SCE_ARC4_KEY_INDEX_WORD_SIZE (72U) +#define HW_SCE_ARC4_KEY_WORD_SIZE (64U) +#define HW_SCE_ARC4_KEY_BYTE_SIZE (256U) +#define HW_SCE_ARC4_BLOCK_BYTE_SIZE (16U) + +/* For SHA operation. */ +#define HW_SCE_SHA1_HASH_LENGTH_BYTE_SIZE (20U) +#define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) +#define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) + +/* For MD5 operation. */ +#define HW_SCE_MD5_HASH_LENGTH_BYTE_SIZE (16U) + +/* For HMAC operation. */ +#define HW_SCE_HMAC_KEY_INDEX_BYTE_SIZE (32U) +#define HW_SCE_HMAC_KEY_INDEX_WORD_SIZE (8U) + +/* For RSA operation. */ +#define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) +#define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) +#define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) +#define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) +#define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) +#define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) +#define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) +#define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) +#define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) +#define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) +#define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA3072_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA4096_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA1024_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (76U) +#define HW_SCE_RSA1024_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (104U) +#define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +//#define HW_SCE_RSA3072_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +//#define HW_SCE_RSA3072_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +//#define HW_SCE_RSA4096_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +//#define HW_SCE_RSA4096_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +#define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) +#define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + +/* RSA HASH type. */ +#define HW_SCE_RSA_HASH_MD5 (0x01) /* MD5 */ +#define HW_SCE_RSA_HASH_SHA1 (0x02) /* SHA-1 */ +#define HW_SCE_RSA_HASH_SHA256 (0x03) /* SHA-256 */ + +/* For ECC operation. */ +//#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (32U) +//#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +//#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +//#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +//#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (12U) +//#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +//#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +//#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +//#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +//#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +//#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +//#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) +//#define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) +#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) +#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (4U) +#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (20U) +#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) + +/* For KeyWrap. */ +#define HW_SCE_KEYWRAP_AES128 (0U) +#define HW_SCE_KEYWRAP_AES256 (2U) + +/* For TLS. */ +#define HW_SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (140U) +#define HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) +#define HW_SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) +#define HW_SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) +#define HW_SCE_TLS_GENERATE_CLIENT_VERIFY (0U) +#define HW_SCE_TLS_GENERATE_SERVER_VERIFY (1U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ +#define HW_SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ +#define HW_SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +/* Key update. */ +#define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + +/* Firmware update. */ +#define HW_SCE_FIRMWARE_MAC_BYTE_SIZE (16U) +#if defined BSP_MCU_RX231 || defined BSP_MCU_RX23W +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF8000) +#else +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF0000) +#endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W */ + +#define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) +#define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) +#define SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD (20) + +#define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) +#define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) +#define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) +#define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) +#define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) +#define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) +#define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) +#define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + +#define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD (36) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD (12) + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ +/* request type for Callback of firmware update */ +typedef enum +{ + SCE_FW_CB_REQ_PRG_WT = 0U, + SCE_FW_CB_REQ_PRG_RD, + SCE_FW_CB_REQ_BUFF_CNT, + SCE_FW_CB_REQ_PRG_WT_LAST_BLK, + SCE_FW_CB_REQ_GET_UPDATE_PRG_CHKSUM, + SCE_FW_CB_REQ_STORE_MAC, +} SCE_FW_CB_REQ_TYPE; + +/* key index type */ +typedef enum +{ + SCE_KEY_INDEX_TYPE_INVALID = 0U, + SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES256, + SCE_KEY_INDEX_TYPE_TDES, + SCE_KEY_INDEX_TYPE_HMAC_SHA1, + SCE_KEY_INDEX_TYPE_HMAC_SHA256, + SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA3072_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, + SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, + SCE_KEY_INDEX_TYPE_UPDATE_KEY_RING, + SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY, + SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY, + SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_ESCP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_ESCP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, +} SCE_KEY_INDEX_TYPE; + +// added for RA6M4 start +/* LIFE CYCLE */ +typedef enum +{ + SCE_CM1 = 0, + SCE_CM2, + SCE_SSD, + SCE_NSECSD, + SCE_DPL, + SCE_LCK_DBG, + SCE_LCK_BOOT, + SCE_RMA_REQ, + SCE_RMA_ACK, +} lifecycle_t; + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; + +// added for RA6M4 end + +/* Byte data structure */ +typedef struct sce_byte_data +{ + uint8_t *pdata; + uint32_t data_length; + uint32_t data_type; +} sce_byte_data_t; + +/* RSA byte data structure */ +typedef sce_byte_data_t sce_rsa_byte_data_t; + +/* ECDSA byte data structure */ +typedef sce_byte_data_t sce_ecdsa_byte_data_t; + +/* AES key index data structure */ +typedef struct sce_aes_key_index +{ + uint32_t type; + /* AES128, AES256, AES128 for TLS, AES256 for TLS are supported */ + uint32_t value[HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE]; +} sce_aes_key_index_t; + +/* TDES key index data structure */ +typedef struct sce_tdes_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TDES_KEY_INDEX_WORD_SIZE]; /* DES/TDES are supported */ +} sce_tdes_key_index_t; + +/* HMAC-SHA key index data structure */ +typedef struct sce_hmac_sha_key_index +{ + uint32_t type; + /* HMAC-SHA1, HMAC-SHA256, HMAC-SHA for TLS, HMAC-SHA256 for TLS are supported */ + uint32_t value[HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE]; +} sce_hmac_sha_key_index_t; + +/* RSA 1024bit public key index data structure */ +typedef struct sce_rsa1024_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa1024_public_key_index_t; + +/* RSA 1024bit private key index data structure */ +typedef struct sce_rsa1024_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa1024_private_key_index_t; + +/* RSA 2048bit public key index data structure */ +typedef struct sce_rsa2048_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa2048_public_key_index_t; + +/* RSA 2048bit private key index data structure */ +typedef struct sce_rsa2048_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa2048_private_key_index_t; + +/* RSA 3072bit public key index data structure */ +typedef struct sce_rsa3072_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa3072_public_key_index_t; + +/* RSA 3072bit private key index data structure */ +typedef struct sce_rsa3072_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa3072_private_key_index_t; + +/* RSA 4096bit public key index data structure */ +typedef struct sce_rsa4096_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa4096_public_key_index_t; + +/* RSA 4096bit private key index data structure */ +typedef struct sce_rsa4096_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } + value; +} sce_rsa4096_private_key_index_t; + +/* RSA 1024bit key index pair structure */ +typedef struct sce_rsa1024_key_pair_index +{ + sce_rsa1024_private_key_index_t private; + sce_rsa1024_public_key_index_t public; +} sce_rsa1024_key_pair_index_t; + +/* RSA 2048bit key index pair structure */ +typedef struct sce_rsa2048_key_pair_index +{ + sce_rsa2048_private_key_index_t private; + sce_rsa2048_public_key_index_t public; +} sce_rsa2048_key_pair_index_t; + +/* RSA 3072bit key index pair structure */ +typedef struct sce_rsa3072_key_pair_index +{ + sce_rsa3072_private_key_index_t private; + sce_rsa3072_public_key_index_t public; +} sce_rsa3072_key_pair_index_t; + +/* RSA 4096bit key index pair structure */ +typedef struct sce_rsa4096_key_pair_index +{ + sce_rsa4096_private_key_index_t private; + sce_rsa4096_public_key_index_t public; +} sce_rsa4096_key_pair_index_t; + +/* ECC P-192/224/256 public key index data structure */ +typedef struct sce_ecc_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE]; + } + value; +} sce_ecc_public_key_index_t; + +/* ECC P-192/224/256 private key index data structure */ +typedef struct sce_ecc_private_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE]; +} sce_ecc_private_key_index_t; + +/* ECC P-192/224/256 key index pair structure */ +typedef struct sce_ecc_key_pair_index +{ + sce_ecc_private_key_index_t private; + sce_ecc_public_key_index_t public; +} sce_ecc_key_pair_index_t; + +/* ECDH key index data structure */ +typedef struct sce_ecdh_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE]; +} sce_ecdh_key_index_t; + +/* TLS CA certification public key index data structure */ +typedef struct sce_tls_ca_certification_public_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE]; +} sce_tls_ca_certification_public_key_index_t; + +/* TLS P-256 ECC key index data structure */ +typedef struct sce_tls_p256_ecc_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE]; +} sce_tls_p256_ecc_key_index_t; + +/* Update key ring index data structure */ +typedef struct sce_update_key_ring +{ + uint32_t type; + uint32_t value[HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE]; +} sce_update_key_ring_t; + + +/* The work area for AES */ +typedef struct sce_aes_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t current_ivec[HW_SCE_AES_CBC_IV_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_aes_handle_t; + +/* The work area for TDES */ +typedef struct sce_tdes_handle +{ + uint32_t id; + sce_tdes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_TDES_BLOCK_BYTE_SIZE]; + uint8_t current_ivec[HW_SCE_TDES_CBC_IV_BYTE_SIZE*2]; + uint8_t flag_call_init; +} sce_tdes_handle_t; + +/* The work area for MD5 */ +typedef struct sce_sha_md5_handle +{ + uint32_t id; + uint8_t sha_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + /* SHA1(20byte), SHA256(32byte), MD5(16byte) are supported */ + uint8_t current_hash[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_sha_md5_handle_t; + +/* The work area for HMAC-SHA */ +typedef struct sce_hmac_sha_handle +{ + uint32_t id; + sce_hmac_sha_key_index_t key_index; + uint8_t hmac_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_hmac_sha_handle_t; + +/* The work area for CMAC */ +typedef struct sce_cmac_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t cmac_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_cmac_handle_t; + +/* The work area for GCM */ +typedef struct sce_gcm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t gcm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t gcm_aad_buffer[HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t all_received_aad_length; + uint32_t buffering_length; + uint32_t buffering_aad_length; + uint8_t flag_call_init; + uint8_t flag_update_input_data; +} sce_gcm_handle_t; + +/* The work area for CCM */ +typedef struct sce_ccm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t formatted_data[HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE]; + uint8_t counter[HW_SCE_AES_CCM_COUNTER_BYTE_SIZE]; + uint8_t ccm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_ccm_handle_t; + +/* The work area for ECDH */ +typedef struct sce_ecdh_handle +{ + uint32_t id; + uint32_t flag_use_key_id; + uint32_t key_id; + uint32_t key_type; + uint8_t flag_call_init; + uint8_t flag_call_make_public; + uint8_t flag_call_read_public; + uint8_t flag_call_shared_secret; +} sce_ecdh_handle_t; + +/* The work area for firmware update */ +typedef struct sce_firmware_generate_mac_resume_handle +{ + uint32_t iLoop; + uint32_t counter; + uint32_t previous_counter; + bool use_resume_flag; +} sce_firmware_generate_mac_resume_handle_t; + +/* The callback function pointer type for HW_SCE_GenerateFirmwareMAC */ +typedef void (*SCE_GEN_MAC_CB_FUNC_T) (SCE_FW_CB_REQ_TYPE req_type, uint32_t iLoop, uint32_t *counter, + uint32_t *InData_UpProgram, uint32_t *OutData_Program, uint32_t MAX_CNT); + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ +fsp_err_t HW_SCE_Open(lifecycle_t lifecycle, sce_tls_ca_certification_public_key_index_t *key_index_1, + sce_update_key_ring_t *key_index_2); +fsp_err_t HW_SCE_Close(void); +void HW_SCE_SoftwareReset(void); + +// added for RA6M4 start +fsp_err_t HW_SCE_FwIntegrityCheck(void); +fsp_err_t HW_SCE_UpdateOemKeyIndex(lifecycle_t lifecycle, sce_oem_cmd_t key_type, uint8_t *iv, uint8_t *encrypted_oem_key, uint32_t *key_index); + +// added for RA6M4 end + +fsp_err_t HW_SCE_GenerateAes128KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256KeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateTdesKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, uint8_t *encrypted_key, + sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa1024PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa1024_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa1024PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa1024_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa2048_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa3072_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa3072_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa4096_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_rsa4096_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateTlsRsaPublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_tls_ca_certification_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP192PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP192PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateSha1HmacKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateSha256HmacKeyIndex(uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndex(sce_tls_p256_ecc_key_index_t *tls_p256_ecc_key_index, + uint8_t *ephemeral_ecdh_public_key); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndex(sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa1024RandomKeyIndex(sce_rsa1024_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndex(sce_rsa2048_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRsa3072RandomKeyIndex(sce_rsa3072_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRsa4096RandomKeyIndex(sce_rsa4096_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateTdesRandomKeyIndex(sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP192RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateEccP224RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateEccP256RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndex(uint32_t *indata_curvetype, sce_ecc_key_pair_index_t *key_pair_index); +fsp_err_t HW_SCE_GenerateRandomNumber(uint32_t *random); +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndex(lifecycle_t lifecycle, uint8_t *encrypted_provisioning_key, uint8_t *iv, + uint8_t *encrypted_key, sce_update_key_ring_t *key_index); +uint32_t HW_SCE_GetVersion(void); + +fsp_err_t HW_SCE_GenerateAes128PlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateAes256PlainKeyIndex(uint8_t *plain_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicPlainKeyIndex(uint8_t *plain_key, sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivatePlainKeyIndex(uint8_t *plain_key, sce_rsa2048_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicPlainKeyIndex(uint8_t *plain_key, sce_rsa3072_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivatePlainKeyIndex(uint8_t *plain_key, sce_rsa3072_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicPlainKeyIndex(uint8_t *plain_key, sce_rsa4096_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivatePlainKeyIndex(uint8_t *plain_key, sce_rsa4096_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateSha256HmacPlainKeyIndex(uint8_t *plain_key, sce_hmac_sha_key_index_t *key_index); + +fsp_err_t HW_SCE_GenerateEccSecp256k1PublicPlainKeyIndex(uint8_t *plain_key, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_GenerateEccSecp256k1PrivatePlainKeyIndex(uint8_t *plain_key, sce_ecc_private_key_index_t *key_index); + +fsp_err_t HW_SCE_UpdateAes128KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateAes256KeyIndex(lifecycle_t lifecycle, uint8_t *iv, uint8_t *encrypted_key, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateTdesKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa1024_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa1024PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa1024_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa2048PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa2048PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa2048_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa3072PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa3072_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa3072PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa3072_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa4096PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa4096_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateRsa4096PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_rsa4096_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateTlsRsaPublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_tls_ca_certification_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP192PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP224PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP256PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP192PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP224PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP256PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndex(uint8_t *iv, uint8_t *encrypted_key, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_Ecc256ScalarMultiplication(uint32_t *InData_CurveType, uint32_t *InData_Cmd, + uint32_t *InData_KeyIndex, uint32_t *InData_PubKey, uint32_t *OutData_R); +fsp_err_t HW_SCE_Ecc384ScalarMultiplication(uint32_t *InData_CurveType, + uint32_t *InData_KeyIndex, uint32_t *InData_PubKey, uint32_t *OutData_R); +fsp_err_t HW_SCE_UpdateSha1HmacKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_UpdateSha256HmacKeyIndex(uint8_t *iv, uint8_t *encrypted_key, sce_hmac_sha_key_index_t *key_index); + +fsp_err_t HW_SCE_StartUpdateFirmware(void); +fsp_err_t HW_SCE_GenerateFirmwareMAC(uint32_t *InData_KeyIndex, uint32_t *InData_SessionKey, + uint32_t *InData_UpProgram, uint32_t *InData_IV, uint32_t *OutData_Program, uint32_t MAX_CNT, + SCE_GEN_MAC_CB_FUNC_T p_callback, + sce_firmware_generate_mac_resume_handle_t *sce_firmware_generate_mac_resume_handle); +fsp_err_t HW_SCE_VerifyFirmwareMAC(uint32_t *InData_Program, uint32_t MAX_CNT, uint32_t *InData_MAC); + +fsp_err_t HW_SCE_Aes128EcbEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128EcbEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128EcbDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes128CbcEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes128CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes256EcbEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256EcbEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256EcbDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes256CbcEncryptUpdate(sce_aes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptFinal(sce_aes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptInit(sce_aes_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_Aes256CbcDecryptUpdate(sce_aes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptFinal(sce_aes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Aes128GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmEncryptFinal(sce_gcm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_data_len, + uint8_t *atag); +fsp_err_t HW_SCE_Aes128GcmDecryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdate(sce_gcm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmDecryptFinal(sce_gcm_handle_t *handle, uint8_t *plain, uint32_t *plain_data_len, + uint8_t *atag, uint32_t atag_len); +fsp_err_t HW_SCE_Aes256GcmEncryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdate(sce_gcm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmEncryptFinal(sce_gcm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_data_len, + uint8_t *atag); +fsp_err_t HW_SCE_Aes256GcmDecryptInit(sce_gcm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdate(sce_gcm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_data_len, uint8_t *aad, uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmDecryptFinal(sce_gcm_handle_t *handle, uint8_t *plain, uint32_t *plain_data_len, + uint8_t *atag, uint32_t atag_len); + +fsp_err_t HW_SCE_Aes128CcmEncryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmEncryptUpdate(sce_ccm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CcmEncryptFinal(sce_ccm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes128CcmDecryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmDecryptUpdate(sce_ccm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CcmDecryptFinal(sce_ccm_handle_t *handle, uint8_t *plain, uint32_t *plain_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CcmEncryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmEncryptUpdate(sce_ccm_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CcmEncryptFinal(sce_ccm_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length, + uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CcmDecryptInit(sce_ccm_handle_t *handle, sce_aes_key_index_t *key_index, uint8_t *nonce, + uint32_t nonce_len, uint8_t *adata, uint8_t a_len, uint32_t payload_len, uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmDecryptUpdate(sce_ccm_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CcmDecryptFinal(sce_ccm_handle_t *handle, uint8_t *plain, uint32_t *plain_length, + uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_Aes128CmacGenerateInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacGenerateUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacGenerateFinal(sce_cmac_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Aes128CmacVerifyInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes128CmacVerifyUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacVerifyFinal(sce_cmac_handle_t *handle, uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CmacGenerateInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacGenerateUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacGenerateFinal(sce_cmac_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Aes256CmacVerifyInit(sce_cmac_handle_t *handle, sce_aes_key_index_t *key_index); +fsp_err_t HW_SCE_Aes256CmacVerifyUpdate(sce_cmac_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacVerifyFinal(sce_cmac_handle_t *handle, uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_TdesEcbEncryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_TdesEcbEncryptUpdate(sce_tdes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesEcbEncryptFinal(sce_tdes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index); +fsp_err_t HW_SCE_TdesEcbDecryptUpdate(sce_tdes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptFinal(sce_tdes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_TdesCbcEncryptUpdate(sce_tdes_handle_t *handle, uint8_t *plain, uint8_t *cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptFinal(sce_tdes_handle_t *handle, uint8_t *cipher, uint32_t *cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptInit(sce_tdes_handle_t *handle, sce_tdes_key_index_t *key_index, uint8_t *ivec); +fsp_err_t HW_SCE_TdesCbcDecryptUpdate(sce_tdes_handle_t *handle, uint8_t *cipher, uint8_t *plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptFinal(sce_tdes_handle_t *handle, uint8_t *plain, uint32_t *plain_length); + +fsp_err_t HW_SCE_Md5Init(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Md5Update(sce_sha_md5_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Md5Final(sce_sha_md5_handle_t *handle, uint8_t *digest, uint32_t *digest_length); + +fsp_err_t HW_SCE_Sha1Init(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Sha1Update(sce_sha_md5_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1Final(sce_sha_md5_handle_t *handle, uint8_t *digest, uint32_t *digest_length); +fsp_err_t HW_SCE_Sha256Init(sce_sha_md5_handle_t *handle); +fsp_err_t HW_SCE_Sha256Update(sce_sha_md5_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256Final(sce_sha_md5_handle_t *handle, uint8_t *digest, uint32_t *digest_length); + +fsp_err_t HW_SCE_Sha1HmacGenerateInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha1HmacGenerateUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacGenerateFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Sha256HmacGenerateInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha256HmacGenerateUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, + uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacGenerateFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac); +fsp_err_t HW_SCE_Sha1HmacVerifyInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha1HmacVerifyUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacVerifyFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac, uint32_t mac_length); +fsp_err_t HW_SCE_Sha256HmacVerifyInit(sce_hmac_sha_handle_t *handle, sce_hmac_sha_key_index_t *key_index); +fsp_err_t HW_SCE_Sha256HmacVerifyUpdate(sce_hmac_sha_handle_t *handle, uint8_t *message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacVerifyFinal(sce_hmac_sha_handle_t *handle, uint8_t *mac, uint32_t mac_length); + +fsp_err_t HW_SCE_RsassaPkcs1024SignatureGenerate(sce_rsa_byte_data_t *message_hash, + sce_rsa_byte_data_t *signature, sce_rsa1024_private_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs1024SignatureVerification(sce_rsa_byte_data_t *signature, + sce_rsa_byte_data_t *message_hash, sce_rsa1024_public_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureGenerate(sce_rsa_byte_data_t *message_hash, + sce_rsa_byte_data_t *signature, sce_rsa2048_private_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureVerification(sce_rsa_byte_data_t *signature, + sce_rsa_byte_data_t *message_hash, sce_rsa2048_public_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs3072SignatureGenerate(sce_rsa_byte_data_t *message_hash, + sce_rsa_byte_data_t *signature, sce_rsa3072_private_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs3072SignatureVerification(sce_rsa_byte_data_t *signature, + sce_rsa_byte_data_t *message_hash, sce_rsa3072_public_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs4096SignatureGenerate(sce_rsa_byte_data_t *message_hash, + sce_rsa_byte_data_t *signature, sce_rsa4096_private_key_index_t *key_index, uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs4096SignatureVerification(sce_rsa_byte_data_t *signature, + sce_rsa_byte_data_t *message_hash, sce_rsa4096_public_key_index_t *key_index, uint8_t hash_type); + +fsp_err_t HW_SCE_RsaesPkcs1024Encrypt(sce_rsa_byte_data_t *plain, sce_rsa_byte_data_t *cipher, + sce_rsa1024_public_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs1024Decrypt(sce_rsa_byte_data_t *cipher, sce_rsa_byte_data_t *plain, + sce_rsa1024_private_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Encrypt(sce_rsa_byte_data_t *plain, sce_rsa_byte_data_t *cipher, + sce_rsa2048_public_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Decrypt(sce_rsa_byte_data_t *cipher, sce_rsa_byte_data_t *plain, + sce_rsa2048_private_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs3072Encrypt(sce_rsa_byte_data_t *plain, sce_rsa_byte_data_t *cipher, + sce_rsa3072_public_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs3072Decrypt(sce_rsa_byte_data_t *cipher, sce_rsa_byte_data_t *plain, + sce_rsa3072_private_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs4096Encrypt(sce_rsa_byte_data_t *plain, sce_rsa_byte_data_t *cipher, + sce_rsa4096_public_key_index_t *key_index); +fsp_err_t HW_SCE_RsaesPkcs4096Decrypt(sce_rsa_byte_data_t *cipher, sce_rsa_byte_data_t *plain, + sce_rsa4096_private_key_index_t *key_index); + +fsp_err_t HW_SCE_TlsRootCertificateVerification(uint32_t public_key_type, uint8_t *certificate, + uint32_t certificate_length, uint32_t public_key_n_start_position, uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, uint8_t *signature, + uint32_t *encrypted_root_public_key); +fsp_err_t HW_SCE_TlsCertificateVerification(uint32_t public_key_type, uint32_t *encrypted_input_public_key, + uint8_t *certificate, uint32_t certificate_length, uint8_t *signature, uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, + uint32_t *encrypted_output_public_key); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecret(uint32_t *sce_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateMasterSecret(uint32_t select_cipher_suite, uint32_t *sce_pre_master_secret, + uint8_t *client_random, uint8_t *server_random, uint32_t *sce_master_secret); +fsp_err_t HW_SCE_TlsEncryptPreMasterSecretWithRsa2048PublicKey(uint32_t *encrypted_public_key, + uint32_t *sce_pre_master_secret, uint8_t *encrypted_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateSessionKey(uint32_t select_cipher_suite, uint32_t *sce_master_secret, + uint8_t *client_random, uint8_t *server_random, uint8_t* nonce_explicit, + sce_hmac_sha_key_index_t *client_mac_key_index, sce_hmac_sha_key_index_t *server_mac_key_index, + sce_aes_key_index_t *client_crypto_key_index, sce_aes_key_index_t *server_crypto_key_index, + uint8_t *client_iv, uint8_t *server_iv); +fsp_err_t HW_SCE_TlsGenerateVerifyData(uint32_t select_verify_data, uint32_t *sce_master_secret, + uint8_t *hand_shake_hash, uint8_t *verify_data); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecretWithEccP256Key(uint32_t *encrypted_public_key, + sce_tls_p256_ecc_key_index_t *tls_p256_ecc_key_index, uint32_t *sce_pre_master_secret); +fsp_err_t HW_SCE_TlsServersEphemeralEcdhPublicKeyRetrieves(uint32_t public_key_type, uint8_t *client_random, + uint8_t *server_random, uint8_t *server_ephemeral_ecdh_public_key, uint8_t *server_key_exchange_signature, + uint32_t *encrypted_public_key, uint32_t *encrypted_ephemeral_ecdh_public_key); + +fsp_err_t HW_SCE_EcdsaP192SignatureGenerate(sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerate(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *message_hash, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP192SignatureVerification(sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureVerification(uint32_t *indata_curvetype, sce_ecdsa_byte_data_t *signature, + sce_ecdsa_byte_data_t *message_hash, sce_ecc_public_key_index_t *key_index); + +fsp_err_t HW_SCE_RSA_IF_HASH(uint8_t *p_mes, uint8_t *p_hash, uint32_t mes_len, uint8_t hash_type); + +fsp_err_t HW_SCE_EcdhInit(sce_ecdh_handle_t *handle, uint32_t key_type, uint32_t use_key_id); +fsp_err_t HW_SCE_EcdhReadPublicKey(sce_ecdh_handle_t *handle, sce_ecc_public_key_index_t *public_key_index, + uint8_t *public_key_data, sce_ecdsa_byte_data_t *signature, sce_ecc_public_key_index_t *key_index); +fsp_err_t HW_SCE_EcdhMakePublicKey(sce_ecdh_handle_t *handle, sce_ecc_public_key_index_t *public_key_index, + sce_ecc_private_key_index_t *private_key_index, uint8_t *public_key, sce_ecdsa_byte_data_t *signature, + sce_ecc_private_key_index_t *key_index); +fsp_err_t HW_SCE_EcdhCalculateSharedSecretIndex(sce_ecdh_handle_t *handle, + sce_ecc_public_key_index_t *public_key_index, sce_ecc_private_key_index_t *private_key_index, + sce_ecdh_key_index_t *shared_secret_index); +fsp_err_t HW_SCE_EcdhKeyDerivation(sce_ecdh_handle_t *handle, sce_ecdh_key_index_t *shared_secret_index, + uint32_t algorithm_id, uint8_t *other_info, uint32_t other_info_length, sce_aes_key_index_t *key_index); + +fsp_err_t HW_SCE_Aes128KeyWrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + sce_aes_key_index_t *target_key_index, uint32_t *wrapped_key); +fsp_err_t HW_SCE_Aes256KeyWrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + sce_aes_key_index_t *target_key_index, uint32_t *wrapped_key); +fsp_err_t HW_SCE_Aes128KeyUnwrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + uint32_t *wrapped_key, sce_aes_key_index_t *target_key_index); +fsp_err_t HW_SCE_Aes256KeyUnwrap(sce_aes_key_index_t *wrap_key_index, uint32_t target_key_type, + uint32_t *wrapped_key, sce_aes_key_index_t *target_key_index); + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/hw_sce_aes_private.h b/ra/fsp/src/r_sce/hw_sce_aes_private.h index 0baa3bfd4..0ee552df6 100644 --- a/ra/fsp/src/r_sce/hw_sce_aes_private.h +++ b/ra/fsp/src/r_sce/hw_sce_aes_private.h @@ -173,4 +173,24 @@ extern fsp_err_t HW_SCE_AES_256EcbDecryptUsingEncryptedKey(const uint32_t * InDa const uint32_t * InData_Text, uint32_t * OutData_Text); +extern fsp_err_t HW_SCE_Aes128EncryptDecryptInit(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); + +extern void HW_SCE_Aes128EncryptDecryptUpdate(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t num_words); + +extern fsp_err_t HW_SCE_Aes128EncryptDecryptFinal(void); + +extern fsp_err_t HW_SCE_Aes256EncryptDecryptInit(const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); + +extern void HW_SCE_Aes256EncryptDecryptUpdate(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t num_words); + +extern fsp_err_t HW_SCE_Aes256EncryptDecryptFinal(void); + #endif /* HW_SCE_AES_PRIVATE_H */ diff --git a/ra/fsp/src/r_sce/hw_sce_ecc_private.h b/ra/fsp/src/r_sce/hw_sce_ecc_private.h index 905e9a1af..a839f40bf 100644 --- a/ra/fsp/src/r_sce/hw_sce_ecc_private.h +++ b/ra/fsp/src/r_sce/hw_sce_ecc_private.h @@ -58,8 +58,15 @@ #define ECC_384_PRIVATE_KEY_HRK_LENGTH_BITS (544U) /* Function pointer declarations */ +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + #define ECC_PUBLIC_KEY_SIZE_BYTES(curve_size) (curve_size * 2 + 20U) +typedef fsp_err_t (* hw_sce_ecc_scalarmultiplication_t)(const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, + const uint32_t * InData_K, const uint32_t * InData_P, + uint32_t * OutData_R); +#else typedef fsp_err_t (* hw_sce_ecc_scalarmultiplication_t)(const uint32_t * InData_DomainParam, const uint32_t * InData_K, const uint32_t * InData_P, uint32_t * OutData_R); +#endif typedef fsp_err_t (* hw_sce_ecc_generatekey_t)(const uint32_t * InData_DomainParam, const uint32_t * InData_G, uint32_t * OutData_PubKey, uint32_t * OutData_PrivKey); @@ -114,6 +121,12 @@ fsp_err_t HW_SCE_ECC_256HrkScalarMultiplication(const uint32_t * InData_DomainPa const uint32_t * InData_P, uint32_t * OutData_R); +fsp_err_t HW_SCE_ECC_256WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + uint32_t * OutData_R); + /* ECC - 384 HW Procedure definitions */ fsp_err_t HW_SCE_ECC_384ScalarMultiplication(const uint32_t * InData_DomainParam, const uint32_t * InData_K, @@ -156,5 +169,10 @@ fsp_err_t HW_SCE_ECC_384HrkScalarMultiplication(const uint32_t * InData_DomainPa const uint32_t * InData_KeyIndex, const uint32_t * InData_P, uint32_t * OutData_R); +fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication(const uint32_t * InData_CurveType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_P, + uint32_t * OutData_R); #endif /* HW_SCE_ECC_PRIVATE_H */ diff --git a/ra/fsp/src/r_sce/hw_sce_hash_private.h b/ra/fsp/src/r_sce/hw_sce_hash_private.h index cfa8f6e3a..cc777ba92 100644 --- a/ra/fsp/src/r_sce/hw_sce_hash_private.h +++ b/ra/fsp/src/r_sce/hw_sce_hash_private.h @@ -27,6 +27,10 @@ #include "bsp_api.h" #include "hw_sce_common.h" -fsp_err_t HW_SCE_SHA256_UpdateHash(const uint32_t * p_source, uint32_t num_words, uint32_t * p_digest); +fsp_err_t HW_SCE_SHA256_UpdateHash(const uint32_t * p_source, uint32_t num_words, uint32_t * p_digest); +extern fsp_err_t HW_SCE_Sha224256GenerateMessageDigestSub(const uint32_t * InData_InitVal, + const uint32_t * InData_PaddedMsg, + const uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest); #endif /* HW_SCE_HASH_PRIVATE_H */ diff --git a/ra/fsp/src/r_sce/hw_sce_private.h b/ra/fsp/src/r_sce/hw_sce_private.h index 3f7fa56dd..9d8cf4946 100644 --- a/ra/fsp/src/r_sce/hw_sce_private.h +++ b/ra/fsp/src/r_sce/hw_sce_private.h @@ -32,12 +32,13 @@ ***********************************************************************************************************************/ #include "bsp_api.h" #include "hw_sce_common.h" +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + #include "r_sce_if.h" +#endif /********************************************************************************************************************** * Macro definitions ***********************************************************************************************************************/ -#define R_SCE_S_HEAP_SIZE 256 -#define R_SCE_S_RAM_SIZE 80 /********************************************************************************************************************** * Typedef definitions @@ -49,6 +50,12 @@ typedef enum e_crypto_word_endian CRYPTO_WORD_ENDIAN_LITTLE = 1 } crypto_word_endian_t; +typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + /********************************************************************************************************************** * Function Prototypes ***********************************************************************************************************************/ @@ -57,9 +64,11 @@ typedef enum e_crypto_word_endian * Includes ***********************************************************************************************************************/ -extern uint32_t S_RAM[R_SCE_S_RAM_SIZE]; -extern uint32_t S_HEAP[R_SCE_S_HEAP_SIZE]; - +extern uint32_t S_RAM[]; +extern uint32_t S_HEAP[]; +extern uint32_t S_INST[]; +extern uint32_t S_INST2[]; +extern uint32_t INST_DATA_SIZE; extern void HW_SCE_SoftReset(void); extern fsp_err_t HW_SCE_Initialization1(void); @@ -76,6 +85,59 @@ fsp_err_t HW_SCE_secureBoot(void); void HW_SCE_EndianSetBig(void); void HW_SCE_EndianSetLittle(void); crypto_word_endian_t HW_SCE_EndianFlagGet(void); +fsp_err_t HW_SCE_McuSpecificInit(void); + +fsp_err_t HW_SCE_FW_IntegrityChk(void); +fsp_err_t HW_SCE_HUK_Load(uint32_t * InData_LC); +fsp_err_t HW_SCE_HUK_Load_LCS(void); +fsp_err_t HW_SCE_p07(uint32_t * OutData_KeyIndex); +void HW_SCE_ChangeToLittleEndian(void); + +#if !BSP_FEATURE_CRYPTO_HAS_SCE9 + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; +#endif +fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate(const sce_oem_key_type_t key_type, + const sce_oem_cmd_t cmd, + const uint8_t * encrypted_provisioning_key, + const uint8_t * iv, + const uint8_t * encrypted_oem_key, + uint32_t * key_index); #endif /* HW_SCE_PRIVATE_H */ diff --git a/ra/fsp/src/r_sce/hw_sce_rsa_private.h b/ra/fsp/src/r_sce/hw_sce_rsa_private.h index 5042ab2c3..e64155134 100644 --- a/ra/fsp/src/r_sce/hw_sce_rsa_private.h +++ b/ra/fsp/src/r_sce/hw_sce_rsa_private.h @@ -33,6 +33,19 @@ typedef fsp_err_t (* hw_sce_rsa_generatekey_t)(uint32_t num_tries, uint32_t * Ou typedef fsp_err_t (* hw_sce_rsa_private_decrypt_t)(const uint32_t * InData_Text, const uint32_t * InData_KeyIndex, const uint32_t * InData_N, uint32_t * OutData_Text); +typedef fsp_err_t (* hw_sce_rsa_public_encrypt_t)(const uint32_t * InData_Text, const uint32_t * InData_PublicKey, + const uint32_t * InData_N, uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_4096PublicKeyEncrypt(const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + +fsp_err_t HW_SCE_RSA_3072PublicKeyEncrypt(const uint32_t * InData_Text, + const uint32_t * InData_PublicKey, + const uint32_t * InData_N, + uint32_t * OutData_Text); + fsp_err_t HW_SCE_RSA_2048PublicKeyEncrypt(const uint32_t * InData_Text, const uint32_t * InData_PublicKey, const uint32_t * InData_N, diff --git a/ra/fsp/src/r_sce/ra2/SC324_private.h b/ra/fsp/src/r_sce/ra2/SC324_private.h index a7251fd27..b1edfd867 100644 --- a/ra/fsp/src/r_sce/ra2/SC324_private.h +++ b/ra/fsp/src/r_sce/ra2/SC324_private.h @@ -22,6 +22,7 @@ #define SC324_PRIVATE_H #include +#include "SCE_module.h" typedef struct /*!< SCE register structure */ { @@ -46,8 +47,7 @@ typedef struct /*!< SCE register structure * volatile uint8_t REG_07H; /*!< Reserved */ } SCE1_TRNG_Type; -#define SCE1_TRNG_BASE 0x400D1000UL -#define SCE1_TRNG ((volatile SCE1_TRNG_Type *) SCE1_TRNG_BASE) +#define SCE1_TRNG ((volatile SCE1_TRNG_Type *) SCE1_TRNG_BASE) typedef struct { @@ -94,7 +94,6 @@ typedef struct volatile uint32_t AESKW1; ///< AES Key Window 1 register } SCE1_AES_Type; -#define SCE1_AES_BASE 0x400D0000UL -#define SCE1_AES ((volatile SCE1_AES_Type *) SCE1_AES_BASE) +#define SCE1_AES ((volatile SCE1_AES_Type *) SCE1_AES_BASE) #endif /* SC324_PRIVATE_H */ diff --git a/ra/fsp/src/r_sce/ra2/SC324_utils.c b/ra/fsp/src/r_sce/ra2/SC324_utils.c new file mode 100644 index 000000000..5f5e69a51 --- /dev/null +++ b/ra/fsp/src/r_sce/ra2/SC324_utils.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_private.h" + +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + // power on the SCE module + HW_SCE_PowerOn(); + + HW_SCE_EndianSetLittle(); + + return FSP_SUCCESS; +} diff --git a/ra/fsp/src/r_sce/ra2/SCE_module.h b/ra/fsp/src/r_sce/ra2/SCE_module.h new file mode 100644 index 000000000..10457d0f6 --- /dev/null +++ b/ra/fsp/src/r_sce/ra2/SCE_module.h @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ +#define SCE1_TRNG_BASE 0x400D1000UL +#define SCE1_AES_BASE 0x400D0000UL + +#endif // HW_SCE_MODULE_H diff --git a/ra/fsp/src/r_sce/ra4_sce5/SC327_SoftReset.prc.c b/ra/fsp/src/r_sce/ra4_sce5/SC327_SoftReset.prc.c index d030aa583..b16b76253 100644 --- a/ra/fsp/src/r_sce/ra4_sce5/SC327_SoftReset.prc.c +++ b/ra/fsp/src/r_sce/ra4_sce5/SC327_SoftReset.prc.c @@ -19,7 +19,7 @@ **********************************************************************************************************************/ ///////////////////////////////////////////////////////////////////////// -// // +// // // File name : SC327_SoftReset.prc // // State Diagram : All state ransition // // Start State : All state // diff --git a/ra/fsp/src/r_sce/ra4_sce5/SC327_p01.prc.c b/ra/fsp/src/r_sce/ra4_sce5/SC327_p01.prc.c index 994cd026e..ba06073d9 100644 --- a/ra/fsp/src/r_sce/ra4_sce5/SC327_p01.prc.c +++ b/ra/fsp/src/r_sce/ra4_sce5/SC327_p01.prc.c @@ -19,7 +19,7 @@ **********************************************************************************************************************/ ///////////////////////////////////////////////////////////////////////// -// // +// // // Procedure number: 01 // // File name : SC327_p01.prc // // State Diagram : main(FSM1) // @@ -40,7 +40,7 @@ #include "SCE_ProcCommon.h" /*******************************************************************************************************************//** - * TSIP Selftest Function1 + * SCE Selftest Function1 * @retval FSP_SUCCESS The operation completed successfully. **********************************************************************************************************************/ fsp_err_t HW_SCE_Initialization1 () { diff --git a/ra/fsp/src/r_sce/ra4_sce5/SC327_utils.c b/ra/fsp/src/r_sce/ra4_sce5/SC327_utils.c new file mode 100644 index 000000000..607fa814e --- /dev/null +++ b/ra/fsp/src/r_sce/ra4_sce5/SC327_utils.c @@ -0,0 +1,65 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_private.h" +#include "SCE_ProcCommon.h" + +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; + + // power on the SCE module + HW_SCE_PowerOn(); + + HW_SCE_SoftReset(); + iret = HW_SCE_Initialization1(); + + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_Initialization2(); + if (FSP_SUCCESS == iret) + { + /* Set mode to little endian */ + WR1_PROG(REG_1D4H, 0x0000AAAA); + } + } + + return iret; +} diff --git a/ra/fsp/src/r_sce/ra4_sce5/SCE_module.h b/ra/fsp/src/r_sce/ra4_sce5/SCE_module.h new file mode 100644 index 000000000..da6198dd8 --- /dev/null +++ b/ra/fsp/src/r_sce/ra4_sce5/SCE_module.h @@ -0,0 +1,29 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x400C0000UL +#endif // HW_SCE_MODULE_H diff --git a/ra/fsp/src/r_sce/ra6_sce7/SC32_utils.c b/ra/fsp/src/r_sce/ra6_sce7/SC32_utils.c new file mode 100644 index 000000000..ed4eb8f8c --- /dev/null +++ b/ra/fsp/src/r_sce/ra6_sce7/SC32_utils.c @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "hw_sce_private.h" +#include "SCE_ProcCommon.h" + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; + + // power on the SCE module + HW_SCE_PowerOn(); + + HW_SCE_SoftReset(); + iret = HW_SCE_Initialization1(); + + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_Initialization2(); + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_secureBoot(); + + if (FSP_SUCCESS == iret) + { + /* Set mode to little endian */ + WR1_PROG(REG_1D4H, 0x0000EEEE); + } + } + } + + return iret; +} diff --git a/ra/fsp/src/r_sce/ra6_sce7/SCE_module.h b/ra/fsp/src/r_sce/ra6_sce7/SCE_module.h new file mode 100644 index 000000000..3a8c1d024 --- /dev/null +++ b/ra/fsp/src/r_sce/ra6_sce7/SCE_module.h @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x400C0000UL // should be changed for TAHOE + +#endif // HW_SCE_MODULE_H diff --git a/ra/fsp/src/r_sci_i2c/r_sci_i2c.c b/ra/fsp/src/r_sci_i2c/r_sci_i2c.c index 666f2a092..5066ddf4c 100644 --- a/ra/fsp/src/r_sci_i2c/r_sci_i2c.c +++ b/ra/fsp/src/r_sci_i2c/r_sci_i2c.c @@ -111,6 +111,12 @@ typedef enum e_sci_i2c_dtc_interrupt_trigger SCI_I2C_DTC_INTERRUPT_TRIGGER_RXI = 0x1 } sci_i2c_dtc_interrupt_trigger_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile sci_i2c_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_i2c_prv_ns_callback)(i2c_master_callback_args_t * p_args); +#endif + /********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -179,7 +185,8 @@ i2c_master_api_t const g_i2c_master_on_sci = .abort = R_SCI_I2C_Abort, .slaveAddressSet = R_SCI_I2C_SlaveAddressSet, .close = R_SCI_I2C_Close, - .versionGet = R_SCI_I2C_VersionGet + .versionGet = R_SCI_I2C_VersionGet, + .callbackSet = R_SCI_I2C_CallbackSet }; /*******************************************************************************************************************//** @@ -210,7 +217,6 @@ fsp_err_t R_SCI_I2C_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t FSP_ASSERT(p_ctrl != NULL); FSP_ASSERT(p_cfg != NULL); FSP_ASSERT(p_cfg->p_extend != NULL); - FSP_ASSERT(p_cfg->p_callback != NULL); FSP_ASSERT((p_cfg->rate == I2C_MASTER_RATE_STANDARD) || (p_cfg->rate == I2C_MASTER_RATE_FAST)); FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0); FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0); @@ -236,9 +242,15 @@ fsp_err_t R_SCI_I2C_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t p_ctrl->p_reg = (R_SCI0_Type *) ((uint32_t) R_SCI0 + (p_cfg->channel * ((uint32_t) R_SCI1 - (uint32_t) R_SCI0)));; /* Record the configuration on the device for use later */ - p_ctrl->p_cfg = p_cfg; - p_ctrl->slave = p_cfg->slave; - p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_cfg = p_cfg; + p_ctrl->slave = p_cfg->slave; + p_ctrl->addr_mode = p_cfg->addr_mode; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif #if SCI_I2C_CFG_DTC_ENABLE @@ -401,6 +413,48 @@ fsp_err_t R_SCI_I2C_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl, return err; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2c_master_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void const * const p_context, + i2c_master_callback_args_t * const p_callback_memory) +{ + sci_i2c_instance_ctrl_t * p_ctrl = (sci_i2c_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_I2C_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_I2C_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SCI_I2C_CFG_PARAM_CHECKING_ENABLE + if (!p_ctrl->callback_is_secure) + { + FSP_ASSERT(p_callback_memory); + } + #endif +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /******************************************************************************************************************//** * Closes the I2C device. Power down I2C peripheral. * @@ -495,6 +549,8 @@ static fsp_err_t sci_i2c_read_write (i2c_master_ctrl_t * const p_api_ctrl, #if SCI_I2C_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(p_buffer != NULL); FSP_ERROR_RETURN((p_ctrl->open == SCI_I2C_OPEN), FSP_ERR_NOT_OPEN); + FSP_ASSERT(((sci_i2c_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL); + #if SCI_I2C_CFG_DTC_ENABLE /* DTC on RX could actually receive 65535+3 = 65538 bytes as 3 bytes are handled separately. @@ -547,12 +603,24 @@ static fsp_err_t sci_i2c_read_write (i2c_master_ctrl_t * const p_api_ctrl, **********************************************************************************************************************/ void sci_i2c_notify (sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event) { - /* Fill in the argument to the callback */ - i2c_master_callback_args_t args = + i2c_master_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else { - .p_context = p_ctrl->p_cfg->p_context, - .event = event - }; + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = p_ctrl->p_context; + p_args->event = event; #if SCI_I2C_CFG_DTC_ENABLE @@ -572,7 +640,32 @@ void sci_i2c_notify (sci_i2c_instance_ctrl_t * const p_ctrl, i2c_master_event_t #endif /* Now do the callback here */ - p_ctrl->p_cfg->p_callback(&args); +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_i2c_prv_ns_callback p_callback = (sci_i2c_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } } /******************************************************************************************************************//** diff --git a/ra/fsp/src/r_sci_spi/r_sci_spi.c b/ra/fsp/src/r_sci_spi/r_sci_spi.c index b96c3383e..c214d6f2c 100644 --- a/ra/fsp/src/r_sci_spi/r_sci_spi.c +++ b/ra/fsp/src/r_sci_spi/r_sci_spi.c @@ -60,14 +60,25 @@ static const fsp_version_t g_sci_spi_version = const spi_api_t g_spi_on_sci = { - .open = R_SCI_SPI_Open, - .read = R_SCI_SPI_Read, - .write = R_SCI_SPI_Write, - .writeRead = R_SCI_SPI_WriteRead, - .close = R_SCI_SPI_Close, - .versionGet = R_SCI_SPI_VersionGet + .open = R_SCI_SPI_Open, + .read = R_SCI_SPI_Read, + .write = R_SCI_SPI_Write, + .writeRead = R_SCI_SPI_WriteRead, + .close = R_SCI_SPI_Close, + .versionGet = R_SCI_SPI_VersionGet, + .callbackSet = R_SCI_SPI_CallbackSet }; +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile sci_spi_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_spi_prv_ns_callback)(spi_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function declarations. **********************************************************************************************************************/ @@ -84,6 +95,7 @@ static fsp_err_t r_sci_spi_write_read_common(sci_spi_instance_ctrl_t * const p_c uint32_t const length); static void r_sci_spi_start_transfer(sci_spi_instance_ctrl_t * const p_ctrl); static void r_sci_spi_transmit(sci_spi_instance_ctrl_t * p_ctrl); +static void r_sci_spi_call_callback(sci_spi_instance_ctrl_t * p_ctrl, spi_event_t event); void sci_spi_txi_isr(void); void sci_spi_rxi_isr(void); @@ -137,6 +149,13 @@ fsp_err_t R_SCI_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg p_ctrl->p_reg = (R_SCI0_Type *) ((R_SCI1_BASE - R_SCI0_BASE) * p_cfg->channel + R_SCI0_BASE); p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif + #if SCI_SPI_DTC_SUPPORT_ENABLE == 1 /* Open the SCI SPI transfer interface if available. */ @@ -320,6 +339,41 @@ fsp_err_t R_SCI_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, return r_sci_spi_write_read_common(p_ctrl, p_src, p_dest, length); } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + sci_spi_instance_ctrl_t * p_ctrl = (sci_spi_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_SPI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Disable the SCI channel and set the instance as not open. Implements @ref spi_api_t::close. * @@ -795,6 +849,61 @@ static void r_sci_spi_transmit (sci_spi_instance_ctrl_t * p_ctrl) } } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_spi_call_callback (sci_spi_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_spi_prv_ns_callback p_callback = (sci_spi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * This function is the ISR handler for R_SCI_SPI Transmit Buffer Empty IRQ. * @@ -882,14 +991,7 @@ void sci_spi_tei_isr (void) p_ctrl->p_reg->SCR &= (uint8_t) R_SCI0_SCR_CKE_Msk; /* Notify the user that the transfer has completed. */ - spi_callback_args_t sci_spi_cb_data = - { - .channel = p_ctrl->p_cfg->channel, - .event = SPI_EVENT_TRANSFER_COMPLETE, - .p_context = p_ctrl->p_cfg->p_context - }; - - p_ctrl->p_cfg->p_callback(&sci_spi_cb_data); + r_sci_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); R_BSP_IrqStatusClear(irq); @@ -922,11 +1024,7 @@ void sci_spi_eri_isr (void) p_ctrl->p_reg->SSR = (uint8_t) (R_SCI0_SSR_TDRE_Msk | R_SCI0_SSR_TEND_Msk); /* Notify the user that an error occurred. */ - spi_callback_args_t sci_spi_cb_data = {0}; - sci_spi_cb_data.channel = p_ctrl->p_cfg->channel; - sci_spi_cb_data.event = SPI_EVENT_ERR_READ_OVERFLOW; - sci_spi_cb_data.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&sci_spi_cb_data); + r_sci_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); /* Clear pending IRQ to make sure it doesn't fire again after exiting. */ R_BSP_IrqStatusClear(irq); diff --git a/ra/fsp/src/r_sci_uart/r_sci_uart.c b/ra/fsp/src/r_sci_uart/r_sci_uart.c index 23e0be8ff..0f6c13708 100644 --- a/ra/fsp/src/r_sci_uart/r_sci_uart.c +++ b/ra/fsp/src/r_sci_uart/r_sci_uart.c @@ -152,6 +152,12 @@ typedef enum e_noise_cancel_lvl NOISE_CANCEL_LVL4 /**< Noise filter level 4(strong) */ } noise_cancel_lvl_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile sci_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sci_uart_prv_ns_callback)(uart_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -178,6 +184,7 @@ static void r_sci_uart_transfer_close(sci_uart_instance_ctrl_t * p_ctrl); #endif static void r_sci_uart_baud_set(R_SCI0_Type * p_sci_reg, baud_setting_t const * const p_baud_setting); +static void r_sci_uart_call_callback(sci_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event); #if SCI_UART_CFG_FIFO_SUPPORT static void r_sci_uart_fifo_cfg(sci_uart_instance_ctrl_t * const p_ctrl); @@ -274,6 +281,7 @@ const uart_api_t g_uart_on_sci = .baudSet = R_SCI_UART_BaudSet, .versionGet = R_SCI_UART_VersionGet, .communicationAbort = R_SCI_UART_Abort, + .callbackSet = R_SCI_UART_CallbackSet, }; /*******************************************************************************************************************//** @@ -336,6 +344,15 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co p_ctrl->p_cfg = p_cfg; +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_ctrl->callback_is_secure = true; +#endif + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + p_ctrl->data_bytes = 1U; if (UART_DATA_BITS_9 == p_cfg->data_bits) { @@ -364,7 +381,12 @@ fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * co p_ctrl->p_reg->SIMR2 = 0U; p_ctrl->p_reg->SIMR3 = 0U; p_ctrl->p_reg->CDR = 0U; - p_ctrl->p_reg->DCCR = SCI_UART_DCCR_DEFAULT_VALUE; + + /* Check if the channel supports address matching */ + if (BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS & (1U << p_cfg->channel)) + { + p_ctrl->p_reg->DCCR = SCI_UART_DCCR_DEFAULT_VALUE; + } /* Set the default level of the TX pin to 1. */ p_ctrl->p_reg->SPTR = (uint8_t) (1U << SPTR_SPB2D_BIT) | SPTR_OUTPUT_ENABLE_MASK; @@ -660,6 +682,42 @@ fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_api_ctrl, uint8_t const * cons #endif } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a baud_setting_t structure. * Implements @ref uart_api_t::baudSet @@ -1411,6 +1469,63 @@ static void r_sci_uart_baud_set (R_SCI0_Type * p_sci_reg, baud_setting_t const * (p_baud_setting->semr_baudrate_bits & SCI_UART_SEMR_BAUD_SETTING_MASK)); } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + uart_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sci_uart_prv_ns_callback p_callback = (sci_uart_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + #if (SCI_UART_CFG_TX_ENABLE) /*******************************************************************************************************************//** @@ -1491,13 +1606,7 @@ void sci_uart_txi_isr (void) p_ctrl->p_reg->SCR = scr_temp; p_ctrl->p_tx_src = NULL; - uart_callback_args_t args; - - args.channel = p_ctrl->p_cfg->channel; - args.data = 0U; - args.event = UART_EVENT_TX_DATA_EMPTY; - args.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&args); + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); } /* Restore context if RTOS is used */ @@ -1547,10 +1656,7 @@ void sci_uart_rxi_isr (void) } #endif - uint32_t data; - uart_callback_args_t args; - args.channel = p_ctrl->p_cfg->channel; - args.p_context = p_ctrl->p_cfg->p_context; + uint32_t data; #if SCI_UART_CFG_FIFO_SUPPORT do { @@ -1581,9 +1687,7 @@ void sci_uart_rxi_isr (void) if (0 == p_ctrl->rx_dest_bytes) { /* Call user callback with the data. */ - args.event = UART_EVENT_RX_CHAR; - args.data = data; - p_ctrl->p_cfg->p_callback(&args); + r_sci_uart_call_callback(p_ctrl, data, UART_EVENT_RX_CHAR); } else { @@ -1593,9 +1697,7 @@ void sci_uart_rxi_isr (void) if (0 == p_ctrl->rx_dest_bytes) { - args.data = 0U; - args.event = UART_EVENT_RX_COMPLETE; - p_ctrl->p_cfg->p_callback(&args); + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); } } @@ -1628,12 +1730,7 @@ void sci_uart_rxi_isr (void) p_ctrl->p_rx_dest = NULL; /* Call callback */ - uart_callback_args_t args; - args.channel = p_ctrl->p_cfg->channel; - args.data = 0U; - args.p_context = p_ctrl->p_cfg->p_context; - args.event = UART_EVENT_RX_COMPLETE; - p_ctrl->p_cfg->p_callback(&args); + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_RX_COMPLETE); } #endif @@ -1660,17 +1757,10 @@ void sci_uart_tei_isr (void) /* Recover ISR context saved in open. */ sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - uint8_t channel = p_ctrl->p_cfg->channel; - uart_callback_args_t args; - /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */ p_ctrl->p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK); - args.channel = channel; - args.data = 0U; - args.event = UART_EVENT_TX_COMPLETE; - args.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&args); + r_sci_uart_call_callback(p_ctrl, 0U, UART_EVENT_TX_COMPLETE); /* Clear pending IRQ to make sure it doesn't fire again after exiting */ R_BSP_IrqStatusClear(irq); @@ -1707,9 +1797,8 @@ void sci_uart_eri_isr (void) /* Recover ISR context saved in open. */ sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - uint8_t channel = p_ctrl->p_cfg->channel; - uint32_t data = 0U; - uart_callback_args_t args = {0U}; + uint32_t data = 0U; + uart_event_t event; /* Read data. */ if ( @@ -1728,22 +1817,19 @@ void sci_uart_eri_isr (void) } /* Determine cause of error. */ - args.event = (uart_event_t) (p_ctrl->p_reg->SSR & SCI_RCVR_ERR_MASK); + event = (uart_event_t) (p_ctrl->p_reg->SSR & SCI_RCVR_ERR_MASK); /* Check if there is a break detected. */ - if ((UART_EVENT_ERR_FRAMING == (args.event & UART_EVENT_ERR_FRAMING)) && (0U == p_ctrl->p_reg->SPTR_b.RXDMON)) + if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_ctrl->p_reg->SPTR_b.RXDMON)) { - args.event |= UART_EVENT_BREAK_DETECT; + event |= UART_EVENT_BREAK_DETECT; } /* Clear error condition. */ p_ctrl->p_reg->SSR &= (uint8_t) (~SCI_RCVR_ERR_MASK); /* Call callback. */ - args.channel = channel; - args.data = data; - args.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&args); + r_sci_uart_call_callback(p_ctrl, data, event); /* Clear pending IRQ to make sure it doesn't fire again after exiting */ R_BSP_IrqStatusClear(irq); diff --git a/ra/fsp/src/r_sdhi/r_sdhi.c b/ra/fsp/src/r_sdhi/r_sdhi.c index d8696d4cd..bf128b655 100644 --- a/ra/fsp/src/r_sdhi/r_sdhi.c +++ b/ra/fsp/src/r_sdhi/r_sdhi.c @@ -89,21 +89,21 @@ * Do not set BREM or BWEM when using DMA/DTC. This driver always uses DMA or DTC. */ #define SDHI_PRV_SDHI_INFO2_MASK_CMD_SEND (0x00007C80U) -/* The relationship of the SD Clock Control Register SD_CLK_CTRL CLKSEL to the division of PCLKA +/* The relationship of the SD Clock Control Register SD_CLK_CTRL CLKSEL to the division of the source PCLK * b7 b0 - * 0 0 0 0 0 0 0 0: PCLKA/2 - * 0 0 0 0 0 0 0 1: PCLKA/4 - * 0 0 0 0 0 0 1 0: PCLKA/8 - * 0 0 0 0 0 1 0 0: PCLKA/16 - * 0 0 0 0 1 0 0 0: PCLKA/32 - * 0 0 0 1 0 0 0 0: PCLKA/64 - * 0 0 1 0 0 0 0 0: PCLKA/128 - * 0 1 0 0 0 0 0 0: PCLKA/256 - * 1 0 0 0 0 0 0 0: PCLKA/512. + * 1 1 1 1 1 1 1 1: PCLK + * 0 0 0 0 0 0 0 0: PCLK/2 + * 0 0 0 0 0 0 0 1: PCLK/4 + * 0 0 0 0 0 0 1 0: PCLK/8 + * 0 0 0 0 0 1 0 0: PCLK/16 + * 0 0 0 0 1 0 0 0: PCLK/32 + * 0 0 0 1 0 0 0 0: PCLK/64 + * 0 0 1 0 0 0 0 0: PCLK/128 + * 0 1 0 0 0 0 0 0: PCLK/256 + * 1 0 0 0 0 0 0 0: PCLK/512. * Other settings are prohibited. */ #define SDHI_PRV_MAX_CLOCK_DIVISION_SHIFT (9U) /* 512 (2^9) is max clock division supported */ -#define SDHI_PRV_MIN_CLOCK_DIVISION_SHIFT (1U) /* 2 (2^1) is minimum division supported */ #define SDHI_PRV_CLK_CTRL_DIV_INVALID (0xFFU) @@ -182,6 +182,11 @@ /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile sdhi_prv_ns_callback)(sdmmc_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile sdhi_prv_ns_callback)(sdmmc_callback_args_t * p_args); +#endif /*********************************************************************************************************************** * Private function prototypes @@ -286,7 +291,7 @@ static fsp_err_t r_sdhi_transfer_write(sdhi_instance_ctrl_t * const p_ctrl, static void r_sdhi_transfer_end(sdhi_instance_ctrl_t * const p_ctrl); -static void sdhi_call_callback(sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args); +static void r_sdhi_call_callback(sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args); void r_sdhi_transfer_callback(sdhi_instance_ctrl_t * p_ctrl); @@ -329,6 +334,7 @@ const sdmmc_api_t g_sdmmc_on_sdhi = .ioIntEnable = R_SDHI_IoIntEnable, .statusGet = R_SDHI_StatusGet, .erase = R_SDHI_Erase, + .callbackSet = R_SDHI_CallbackSet, .close = R_SDHI_Close, .versionGet = R_SDHI_VersionGet, }; @@ -380,7 +386,11 @@ fsp_err_t R_SDHI_Open (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_cfg_t const * cons /* Initialize control block. */ memset(p_ctrl, 0, sizeof(*p_ctrl)); - p_ctrl->p_reg = R_SDHI0 + (p_cfg->channel * (R_SDHI1 - R_SDHI0)); +#if BSP_FEATURE_SDHI_VALID_CHANNEL_MASK > 1U + p_ctrl->p_reg = p_cfg->channel ? R_SDHI1 : R_SDHI0; +#else + p_ctrl->p_reg = R_SDHI0; +#endif p_ctrl->p_cfg = p_cfg; /* Clear module stop bit (turn module on). */ @@ -400,6 +410,11 @@ fsp_err_t R_SDHI_Open (sdmmc_ctrl_t * const p_api_ctrl, sdmmc_cfg_t const * cons p_ctrl->p_reg->SD_INFO1_MASK = SDHI_PRV_SD_INFO1_MASK_MASK_ALL; } + /* Set callback and context pointers, if configured */ + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + /* Configure and enable interrupts. */ R_BSP_IrqCfgEnable(p_cfg->access_irq, p_cfg->access_ipl, p_ctrl); r_sdhi_irq_enable(p_cfg->card_irq, p_cfg->card_ipl, p_ctrl); @@ -1022,6 +1037,56 @@ fsp_err_t R_SDHI_Erase (sdmmc_ctrl_t * const p_api_ctrl, uint32_t const start_se return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref sdmmc_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SDHI_CallbackSet (sdmmc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(sdmmc_callback_args_t *), + void const * const p_context, + sdmmc_callback_args_t * const p_callback_memory) +{ + sdhi_instance_ctrl_t * p_ctrl = (sdhi_instance_ctrl_t *) p_api_ctrl; + +#if SDHI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SDHI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SDHI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + sdmmc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(sdmmc_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Closes an open SD/MMC device. Implements @ref sdmmc_api_t::close(). * @@ -1414,28 +1479,25 @@ static fsp_err_t r_sdhi_max_clock_rate_set (sdhi_instance_ctrl_t * p_ctrl, uint3 { uint32_t setting = SDHI_PRV_CLK_CTRL_DIV_INVALID; - /* Get the runtime frequency of PCLKA, the source of the SD clock */ - uint32_t frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKA); + /* Get the runtime frequency of the source of the SD clock */ + uint32_t frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_SDHI_CLOCK); /* Iterate over all possible divisors, starting with the smallest, until the resulting clock rate is less than * or equal to the requested maximum rate. */ - for (uint32_t divisor_shift = SDHI_PRV_MIN_CLOCK_DIVISION_SHIFT; + for (uint32_t divisor_shift = BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT; divisor_shift <= SDHI_PRV_MAX_CLOCK_DIVISION_SHIFT; divisor_shift++) { if ((frequency >> divisor_shift) <= max_rate) { /* If the calculated frequency is less than or equal to the maximum supported by the device, - * select this frequency. */ - setting = 1U << divisor_shift; - - /* The register setting is the divisor value divided by 4. */ - setting >>= 2U; + * select this frequency. The register setting is the divisor value divided by 4, or 0xFF for no divider. */ + setting = divisor_shift ? ((1U << divisor_shift) >> 2U) : UINT8_MAX; /* Set the clock setting. */ /* The clock register is accessible 8 SD clock counts after the last command completes. Each register access - * requires at least one PCLKA count, so check the register up to 8 times the maximum PCLKA divisor value (512). */ + * requires at least one PCLK count, so check the register up to 8 times the maximum PCLK divisor value (512). */ uint32_t timeout = SDHI_PRV_SD_CLK_CTRLEN_TIMEOUT; while (timeout > 0U) @@ -2462,14 +2524,11 @@ void r_sdhi_transfer_callback (sdhi_instance_ctrl_t * p_ctrl) * callback is called. */ r_sdhi_transfer_end(p_ctrl); - if (NULL != p_ctrl->p_cfg->p_callback) - { - sdmmc_callback_args_t args; - memset(&args, 0U, sizeof(args)); - args.p_context = p_ctrl->p_cfg->p_context; - args.event |= SDMMC_EVENT_TRANSFER_COMPLETE; - p_ctrl->p_cfg->p_callback(&args); - } + sdmmc_callback_args_t args; + memset(&args, 0U, sizeof(args)); + args.p_context = p_ctrl->p_context; + args.event |= SDMMC_EVENT_TRANSFER_COMPLETE; + r_sdhi_call_callback(p_ctrl, &args); } } @@ -2630,18 +2689,63 @@ static void r_sdhi_transfer_end (sdhi_instance_ctrl_t * const p_ctrl) } /*******************************************************************************************************************//** - * Close transfer driver, clear transfer data, and disable transfer in the SDHI peripheral. + * Calls user callback * * @param[in] p_ctrl Pointer to the instance control block. * @param[in] p_args Pointer to callback arguments with event and response set. **********************************************************************************************************************/ -static void sdhi_call_callback (sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args) +static void r_sdhi_call_callback (sdhi_instance_ctrl_t * p_ctrl, sdmmc_callback_args_t * p_args) { /* Call user callback if provided, if an event was determined, and if the driver is initialized. */ - if ((NULL != p_ctrl->p_cfg->p_callback) && (p_ctrl->initialized) && (0U != p_args->event)) + if (NULL != p_ctrl->p_callback) { - p_args->p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(p_args); + sdmmc_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + sdmmc_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + + p_args_memory->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + sdhi_prv_ns_callback p_callback = (sdhi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } } } @@ -2661,7 +2765,10 @@ void sdhimmc_accs_isr (void) r_sdhi_access_irq_process(p_ctrl, &args); /* Call user callback */ - sdhi_call_callback(p_ctrl, &args); + if ((p_ctrl->initialized) && (0U != args.event)) + { + r_sdhi_call_callback(p_ctrl, &args); + } /* Clear the IR flag in the ICU */ /* Clearing the IR bit must be done after clearing the interrupt source in the the peripheral */ @@ -2702,12 +2809,9 @@ void sdhimmc_card_isr (void) info1.word &= SDHI_PRV_SDHI_INFO1_CARD_MASK; p_ctrl->p_reg->SD_INFO1 = (~info1.word); - /* Call user callback if provided, if an event was determined, and if the driver is initialized. */ - if (NULL != p_ctrl->p_cfg->p_callback) - { - args.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&args); - } + /* Call user callback if provided */ + args.p_context = p_ctrl->p_context; + r_sdhi_call_callback(p_ctrl, &args); /* Clear the IR flag in the ICU */ /* Clearing the IR bit must be done after clearing the interrupt source in the the peripheral */ @@ -2768,7 +2872,10 @@ void sdhimmc_sdio_isr (void) } /* Call user callback */ - sdhi_call_callback(p_ctrl, &args); + if (p_ctrl->initialized) + { + r_sdhi_call_callback(p_ctrl, &args); + } /* Clear interrupt flags */ p_ctrl->p_reg->SDIO_INFO1 = SDHI_PRV_SDIO_INFO1_IRQ_CLEAR; diff --git a/ra/fsp/src/r_spi/r_spi.c b/ra/fsp/src/r_spi/r_spi.c index b66fb0c91..4426f349e 100644 --- a/ra/fsp/src/r_spi/r_spi.c +++ b/ra/fsp/src/r_spi/r_spi.c @@ -79,6 +79,11 @@ /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile spi_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile spi_prv_ns_callback)(spi_callback_args_t * p_args); +#endif /* Frame data length */ typedef enum e_spi_spcmd_bit_length @@ -105,6 +110,7 @@ static fsp_err_t r_spi_write_read_common(spi_ctrl_t * const p_api_ctrl, static void r_spi_receive(spi_instance_ctrl_t * p_ctrl); static void r_spi_transmit(spi_instance_ctrl_t * p_ctrl); +static void r_spi_call_callback(spi_instance_ctrl_t * p_ctrl, spi_event_t event); /*********************************************************************************************************************** * ISR prototypes @@ -134,12 +140,13 @@ static const fsp_version_t module_version = /* SPI implementation of SPI interface. */ const spi_api_t g_spi_on_spi = { - .open = R_SPI_Open, - .read = R_SPI_Read, - .write = R_SPI_Write, - .writeRead = R_SPI_WriteRead, - .close = R_SPI_Close, - .versionGet = R_SPI_VersionGet + .open = R_SPI_Open, + .read = R_SPI_Read, + .write = R_SPI_Write, + .writeRead = R_SPI_WriteRead, + .close = R_SPI_Close, + .versionGet = R_SPI_VersionGet, + .callbackSet = R_SPI_CallbackSet }; /*******************************************************************************************************************//** @@ -227,7 +234,14 @@ fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) FSP_ERROR_RETURN(FSP_SUCCESS == err, err); /* Get the register address of the channel. */ - p_ctrl->p_cfg = p_cfg; + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif + p_ctrl->p_regs = SPI_REG(p_ctrl->p_cfg->channel); /* Configure hardware registers according to the r_spi_api configuration structure. */ @@ -309,6 +323,41 @@ fsp_err_t R_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, return r_spi_write_read_common(p_api_ctrl, p_src, p_dest, length, bit_width); } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if (SPI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * This function manages the closing of a channel by the following task. Implements @ref spi_api_t::close. * @@ -649,6 +698,10 @@ static void r_spi_hw_config (spi_instance_ctrl_t * p_ctrl) p_ctrl->p_regs->SPCR2 = (uint8_t) spcr2; p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0; p_ctrl->p_regs->SPDCR2 = (uint8_t) spdcr2; + +#if BSP_FEATURE_SPI_HAS_SPCR3 == 1 + p_ctrl->p_regs->SPCR3 = R_SPI0_SPCR3_CENDIE_Msk; +#endif } /*******************************************************************************************************************//** @@ -940,6 +993,61 @@ static void r_spi_transmit (spi_instance_ctrl_t * p_ctrl) p_ctrl->tx_count = tx_count + 1; } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_spi_call_callback (spi_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + spi_prv_ns_callback p_callback = (spi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * ISR called when data is loaded into SPI data register from the shift register. **********************************************************************************************************************/ @@ -1040,14 +1148,8 @@ void spi_tei_isr (void) /* Disable the SPI Transfer. */ p_ctrl->p_regs->SPCR_b.SPE = 0; - /* Setup callback args. */ - spi_callback_args_t spi_cb_data; - spi_cb_data.channel = p_ctrl->p_cfg->channel; - spi_cb_data.event = SPI_EVENT_TRANSFER_COMPLETE; - spi_cb_data.p_context = p_ctrl->p_cfg->p_context; - /* Signal that a transfer has completed. */ - p_ctrl->p_cfg->p_callback(&spi_cb_data); + r_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); } /* Restore context if RTOS is used */ @@ -1068,11 +1170,6 @@ void spi_eri_isr (void) /* Disable the SPI Transfer. */ p_ctrl->p_regs->SPCR_b.SPE = 0; - /* Setup callback args. */ - spi_callback_args_t spi_cb_data; - spi_cb_data.channel = p_ctrl->p_cfg->channel; - spi_cb_data.p_context = p_ctrl->p_cfg->p_context; - /* Read the status register. */ uint8_t status = p_ctrl->p_regs->SPSR; @@ -1082,15 +1179,13 @@ void spi_eri_isr (void) /* Check if the error is a Parity Error. */ if (R_SPI0_SPSR_PERF_Msk & status) { - spi_cb_data.event = SPI_EVENT_ERR_PARITY; - p_ctrl->p_cfg->p_callback(&spi_cb_data); + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_PARITY); } /* Check if the error is a Receive Buffer Overflow Error. */ if (R_SPI0_SPSR_OVRF_Msk & status) { - spi_cb_data.event = SPI_EVENT_ERR_READ_OVERFLOW; - p_ctrl->p_cfg->p_callback(&spi_cb_data); + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); } /* Check if the error is a Mode Fault Error. */ @@ -1099,8 +1194,7 @@ void spi_eri_isr (void) /* Check if the error is a Transmit Buffer Underflow Error. */ if (R_SPI0_SPSR_UDRF_Msk & status) { - spi_cb_data.event = SPI_EVENT_ERR_MODE_UNDERRUN; - p_ctrl->p_cfg->p_callback(&spi_cb_data); + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_MODE_UNDERRUN); } } diff --git a/ra/fsp/src/r_ssi/r_ssi.c b/ra/fsp/src/r_ssi/r_ssi.c index 4ee792167..e07d9c8e8 100644 --- a/ra/fsp/src/r_ssi/r_ssi.c +++ b/ra/fsp/src/r_ssi/r_ssi.c @@ -78,6 +78,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile i2s_prv_ns_callback)(i2s_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile i2s_prv_ns_callback)(i2s_callback_args_t * p_args); +#endif + /* SSI communication direction */ typedef enum e_ssi_dir { @@ -104,6 +110,8 @@ void ssi_txi_isr(void); void ssi_rxi_isr(void); void ssi_int_isr(void); +static void r_ssi_call_callback(ssi_instance_ctrl_t * p_ctrl, i2s_event_t event); + /* ISR subroutines */ static void r_ssi_tx_fifo_write(ssi_instance_ctrl_t * p_instance_ctrl, uint32_t stages_to_write); static void r_ssi_rx_fifo_read(ssi_instance_ctrl_t * p_instance_ctrl, uint32_t stages_to_read); @@ -155,15 +163,16 @@ static const fsp_version_t g_version = /*LDRA_INSPECTED 27 D This structure must be accessible in user code. It cannot be static. */ const i2s_api_t g_i2s_on_ssi = { - .open = R_SSI_Open, - .stop = R_SSI_Stop, - .write = R_SSI_Write, - .read = R_SSI_Read, - .writeRead = R_SSI_WriteRead, - .mute = R_SSI_Mute, - .statusGet = R_SSI_StatusGet, - .close = R_SSI_Close, - .versionGet = R_SSI_VersionGet + .open = R_SSI_Open, + .stop = R_SSI_Stop, + .write = R_SSI_Write, + .read = R_SSI_Read, + .writeRead = R_SSI_WriteRead, + .mute = R_SSI_Mute, + .statusGet = R_SSI_StatusGet, + .close = R_SSI_Close, + .versionGet = R_SSI_VersionGet, + .callbackSet = R_SSI_CallbackSet, }; /*******************************************************************************************************************//** @@ -220,9 +229,14 @@ fsp_err_t R_SSI_Open (i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg) FSP_ERR_IP_CHANNEL_NOT_PRESENT); #endif +#if BSP_FEATURE_SSI_VALID_CHANNEL_MASK == 1 + uint32_t base_address = (uint32_t) R_SSI0; +#else + /* Calculate base address for registers on this channel. */ - uint32_t base_address = (uint32_t) R_SSI0 + (p_cfg->channel * ((uint32_t) R_SSI1 - (uint32_t) R_SSI0)); - R_SSI0_Type * p_reg = (R_SSI0_Type *) base_address; + uint32_t base_address = (uint32_t) R_SSI0 + (p_cfg->channel * ((uint32_t) R_SSI1 - (uint32_t) R_SSI0)); +#endif + R_SSI0_Type * p_reg = (R_SSI0_Type *) base_address; /* Determine how to access the FIFO (1 byte, 2 byte, or 4 byte access). */ transfer_size_t fifo_access_size = TRANSFER_SIZE_4_BYTE; @@ -294,6 +308,15 @@ fsp_err_t R_SSI_Open (i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg) * procedure)" of the RA6M3 manual R01UH0886EJ0100. This function follows this procedure except for enabling * interrupts and enabling communication, which are done before communication begins. */ +#if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_instance_ctrl->callback_is_secure = true; +#endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + /* Enable PCLK to SSIE. */ R_BSP_MODULE_START(FSP_IP_SSI, p_instance_ctrl->p_cfg->channel); @@ -627,6 +650,44 @@ fsp_err_t R_SSI_VersionGet (fsp_version_t * const p_version) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements i2s_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SSI_CallbackSet (i2s_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2s_callback_args_t *), + void const * const p_context, + i2s_callback_args_t * const p_callback_memory) +{ + ssi_instance_ctrl_t * p_ctrl = (ssi_instance_ctrl_t *) p_api_ctrl; + +#if (SSI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SSI_PRV_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * @} (end addtogroup R_SSI) **********************************************************************************************************************/ @@ -1085,6 +1146,60 @@ static void r_ssi_rx_fifo_read (ssi_instance_ctrl_t * p_instance_ctrl, uint32_t } } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to I2S instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_ssi_call_callback (ssi_instance_ctrl_t * p_ctrl, i2s_event_t event) +{ + i2s_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + i2s_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + i2s_prv_ns_callback p_callback = (i2s_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * Transmit ISR. Calls callback when transmission is complete. Fills FIFO if transfer interface is not used. **********************************************************************************************************************/ @@ -1099,25 +1214,23 @@ void ssi_txi_isr (void) /* Clear the IR flag in the ICU */ R_BSP_IrqStatusClear(irq); - bool call_callback = true; - i2s_callback_args_t args; + bool call_callback = true; + if (NULL != p_instance_ctrl->p_tx_src) { - /* If transfer is not used, write data. */ - r_ssi_fifo_write(p_instance_ctrl); - /* If there is more data to send, don't call the callback. */ if (p_instance_ctrl->tx_src_samples > 0) { call_callback = false; } + + /* If transfer is not used, write data. */ + r_ssi_fifo_write(p_instance_ctrl); } if (call_callback) { - args.event = I2S_EVENT_TX_EMPTY; - args.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&args); + r_ssi_call_callback(p_instance_ctrl, I2S_EVENT_TX_EMPTY); } /* Restore context if RTOS is used */ @@ -1138,8 +1251,8 @@ void ssi_rxi_isr (void) /* Clear the IR flag in the ICU */ R_BSP_IrqStatusClear(irq); - bool call_callback = true; - i2s_callback_args_t args; + bool call_callback = true; + if (NULL != p_instance_ctrl->p_rx_dest) { /* If transfer is not used, read data into the destination buffer. */ @@ -1154,9 +1267,7 @@ void ssi_rxi_isr (void) if (call_callback) { - args.event = I2S_EVENT_RX_FULL; - args.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&args); + r_ssi_call_callback(p_instance_ctrl, I2S_EVENT_RX_FULL); } /* Restore context if RTOS is used */ @@ -1190,10 +1301,7 @@ void ssi_int_isr (void) p_instance_ctrl->p_reg->SSICR_b.IIEN = 0U; /* If peripheral is idle, call idle callback. */ - i2s_callback_args_t args; - args.event = I2S_EVENT_IDLE; - args.p_context = p_instance_ctrl->p_cfg->p_context; - p_instance_ctrl->p_cfg->p_callback(&args); + r_ssi_call_callback(p_instance_ctrl, I2S_EVENT_IDLE); } else { diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h index 750cee838..e0b9bcfe6 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h +++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h @@ -212,7 +212,13 @@ /* USB module definition */ #define USB_M0 (R_USB_FS0) -#define USB_M1 (R_USB_HS0) +#if defined(BSP_MCU_GROUP_RA6M3) /* High-speed module */ + #define USB_M1 (R_USB_HS0) +#else /* defined(BSP_MCU_GROUP_RA6M3) */ /* Full-speed module*/ + #define R_USB_HS0_BASE 0x40060000 + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + #define USB_M1 (R_USB_HS0) +#endif /* defined(BSP_MCU_GROUP_RA6M3) */ /* FIFO port register default access size */ #define USB0_CFIFO_MBW (USB_MBW_16) diff --git a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h index 169b4a02f..8ab1f8cbb 100644 --- a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h +++ b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_patapi.h @@ -106,7 +106,7 @@ typedef enum USB_ATAPI_MODE_SENSE10_ERR_RCVR_P_SIZE = 20, USB_ATAPI_MODE_SENSE10_CASHING_P_SIZE = 20, USB_ATAPI_MODE_SENSE10_CAP_P_SIZE = 20, - USB_ATAPI_MODE_SENSE10_OP_CMD_SIZE = 8, + USB_ATAPI_MODE_SENSE10_OP_CMD_SIZE = 20, USB_ATAPI_MODE_SENSE10_ALL_P_SIZE = 44, USB_ATAPI_MODE_SENSE10_P_CODE_ERR_SIZE = 8, USB_ATAPI_DATA_SIZE_0 = 0 diff --git a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h index f0b94cf9d..f1f620d8a 100644 --- a/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h +++ b/ra/fsp/src/r_usb_pmsc/src/inc/r_usb_pmsc_driver.h @@ -82,11 +82,12 @@ typedef enum { /* Generic ioctl command (defined for compatibility with FatFs) */ - USB_MEDIA_IOCTL_SYNC = 0, /* Flush media write cache. */ - USB_MEDIA_IOCTL_GET_NUM_BLOCKS = 1, /* For use un calculating media size. */ - USB_MEDIA_IOCTL_GET_SECTOR_SIZE = 2, /* Get sector size (for multiple sector size. (_MAX_SS >= 1024)) */ - USB_MEDIA_IOCTL_GET_BLOCK_SIZE = 3, /* Get number of byes per block. */ - USB_MEDIA_IOCTL_CTRL_ERASE_SECTOR = 4, /* Force erased a sector group. (for only _USE_ERASE) */ + USB_MEDIA_IOCTL_SYNC = 0, /* Flush media write cache. */ + USB_MEDIA_IOCTL_GET_NUM_BLOCKS = 1, /* For use un calculating media size. */ + USB_MEDIA_IOCTL_GET_SECTOR_SIZE = 2, /* Get sector size (for multiple sector size. (_MAX_SS >= 1024)) */ + USB_MEDIA_IOCTL_GET_BLOCK_SIZE = 3, /* Get number of byes per block. */ + USB_MEDIA_IOCTL_CTRL_ERASE_SECTOR = 4, /* Force erased a sector group. (for only _USE_ERASE) */ + USB_MEDIA_IOCTL_GET_WRITE_PROTECT_INFO = 5, /* Get write protect sinfo. */ /* Add more IOCTL commands starting below here. */ } usb_ioctl_cmd_t; diff --git a/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c b/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c index b80edaa31..a21c45864 100644 --- a/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c +++ b/ra/fsp/src/r_usb_pmsc/src/r_media_driver_api.c @@ -239,6 +239,8 @@ fsp_err_t r_usb_pmsc_media_write (uint8_t const * const p_wbuffer, uint32_t cons ***********************************************************************************************************************/ void r_usb_pmsc_media_ioctl (usb_ioctl_cmd_t ioctl_cmd, uint32_t * ioctl_data) { + rm_block_media_info_t info; + switch (ioctl_cmd) { case USB_MEDIA_IOCTL_GET_NUM_BLOCKS: @@ -261,6 +263,13 @@ void r_usb_pmsc_media_ioctl (usb_ioctl_cmd_t ioctl_cmd, uint32_t * ioctl_data) break; } + case USB_MEDIA_IOCTL_GET_WRITE_PROTECT_INFO: + { + gp_block_media_instance->p_api->infoGet(gp_block_media_instance->p_ctrl, &info); + *ioctl_data = (uint32_t) info.write_protected; + break; + } + default: { break; diff --git a/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c b/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c index 41541cc92..f964b3d41 100644 --- a/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c +++ b/ra/fsp/src/r_usb_pmsc/src/r_usb_atapi_driver.c @@ -45,6 +45,7 @@ #define USB_VALUE_RMB (0x80) #define USB_VALUE_MASK_FFH (0xFF) #define USB_VALUE_32 (32) +#define USB_VALUE_ALL_PAGE_LENGTH (0x24) /*********************************************************************************************************************** * Private global variables and functions @@ -145,7 +146,7 @@ static const uint8_t g_usb_atapi_rs_tbl[USB_ATAPI_REQUEST_SENSE_SIZE] = }; /* Mode Sense data (Mode Parameter) */ -static const uint8_t g_usb_atapi_ms_mp_tbl[USB_ATAPI_MODE_SENSE10_MODE_PARAM_SIZE] = +static uint8_t g_usb_atapi_ms_mp_tbl[USB_ATAPI_MODE_SENSE10_MODE_PARAM_SIZE] = { 0x00, /* [0]Mode Data Length */ 0x00, /* [1]Mode Data Length */ @@ -158,7 +159,7 @@ static const uint8_t g_usb_atapi_ms_mp_tbl[USB_ATAPI_MODE_SENSE10_MODE_PARAM_SIZ }; /* Mode Sense data (ReadWrite Error Recovery Page 12byte) */ -static const uint8_t g_usb_atapi_ms_rcvr_tbl[USB_ATAPI_MODE_SENSE10_ERR_RCVR_P_SIZE] = +static uint8_t g_usb_atapi_ms_rcvr_tbl[USB_ATAPI_MODE_SENSE10_ERR_RCVR_P_SIZE] = { /* Mode Parameter List */ 0x00, /* [0]Mode Data Length */ @@ -186,7 +187,7 @@ static const uint8_t g_usb_atapi_ms_rcvr_tbl[USB_ATAPI_MODE_SENSE10_ERR_RCVR_P_S }; /* Mode Sense data (Cashing Page 12byte) */ -static const uint8_t g_usb_atapi_ms_cash_tbl[USB_ATAPI_MODE_SENSE10_CASHING_P_SIZE] = +static uint8_t g_usb_atapi_ms_cash_tbl[USB_ATAPI_MODE_SENSE10_CASHING_P_SIZE] = { /* Mode Parameter List */ 0x00, /* [0]Mode Data Length */ @@ -213,7 +214,7 @@ static const uint8_t g_usb_atapi_ms_cash_tbl[USB_ATAPI_MODE_SENSE10_CASHING_P_SI }; /* Mode Sense data (Removable Block Access Capacities Page 12byte) */ -static const uint8_t g_usb_atapi_ms_capa_tbl[USB_ATAPI_MODE_SENSE10_CAP_P_SIZE] = +static uint8_t g_usb_atapi_ms_capa_tbl[USB_ATAPI_MODE_SENSE10_CAP_P_SIZE] = { /* Mode Parameter List */ 0x00, /* [0]Mode Data Length */ @@ -239,25 +240,39 @@ static const uint8_t g_usb_atapi_ms_capa_tbl[USB_ATAPI_MODE_SENSE10_CAP_P_SIZE] 0x00 /* [11]Reserved */ }; -/* Mode Sense data (Timer & Protect Page) */ -static const uint8_t g_usb_atapi_ms_op_cmd_tbl[USB_ATAPI_MODE_SENSE10_OP_CMD_SIZE] = +/* Mode Sense data (Timer & Protect Page 8byte) */ +static uint8_t g_usb_atapi_ms_op_cmd_tbl[USB_ATAPI_MODE_SENSE10_OP_CMD_SIZE] = { + /* Mode Parameter List */ + 0x00, /* [0]Mode Data Length */ + 0x08, /* [1]Mode Data Length */ + 0x00, /* [2]Medium Type Code(00h-FFh Vendor Specific) */ + 0x00, /* [3]b7:WP(Write Protect), b6-b0:Reserved */ + 0x00, /* [4]Reserved */ + 0x00, /* [5]Reserved */ + 0x00, /* [6]Reserved */ + 0x00, /* [7]Reserved */ + /* Page(Timer & Protect Page 8byte) */ 0x1C, /* [0]b7:PS, b6:Reserved, b5-b0:Page Code(1Ch) */ - 0x06, /* [1]Page Length(06h) */ + 0x0A, /* [1]Page Length(06h) */ 0x00, /* [2]Reserved */ 0x00, /* [3]b7-b4:Reserved, b3-b0:Inactivity Time Multiplier */ 0x00, /* [4]b7-b2:Reserved, b2:WCE, b1:DISP, b0:SWPP */ 0x00, /* [5]Reserved */ 0x00, /* [6]Reserved */ + 0x00, /* [7]Reserved */ + 0x00, /* [4]b7-b2:Reserved, b2:WCE, b1:DISP, b0:SWPP */ + 0x00, /* [5]Reserved */ + 0x00, /* [6]Reserved */ 0x00 /* [7]Reserved */ }; /* Mode Sense data (All Page) */ -static const uint8_t g_usb_atapi_ms_all_tbl[USB_ATAPI_MODE_SENSE10_ALL_P_SIZE] = +static uint8_t g_usb_atapi_ms_all_tbl[USB_ATAPI_MODE_SENSE10_ALL_P_SIZE] = { /* Mode Parameter List */ 0x00, /* [0]Mode Data Length */ - 0x24, /* [1]Mode Data Length */ + USB_VALUE_ALL_PAGE_LENGTH, /* [1]Mode Data Length */ 0x00, /* [2]Medium Type Code(00h-FFh Vendor Specific) */ 0x00, /* [3]b7:WP(Write Protect), b6-b0:Reserved */ 0x00, /* [4]Reserved */ @@ -307,7 +322,7 @@ static const uint8_t g_usb_atapi_ms_all_tbl[USB_ATAPI_MODE_SENSE10_ALL_P_SIZE] = }; /* Mode Sense data (Page code error) */ -static const uint8_t g_usb_atapi_ms_err_tbl[USB_ATAPI_MODE_SENSE10_P_CODE_ERR_SIZE] = +static uint8_t g_usb_atapi_ms_err_tbl[USB_ATAPI_MODE_SENSE10_P_CODE_ERR_SIZE] = { 0x00, /* [0]Mode Data Length */ 0x00, /* [1]Mode Data Length */ @@ -894,61 +909,71 @@ void pmsc_atapi_command_processing (uint8_t * cbw, uint16_t usb_result, usb_cb_t static void pmsc_atapi_get_mode_sense10_data (uint8_t page_code, uint32_t * size, uint8_t ** buff) { uint8_t * p_data; + uint32_t write_protect = 0; + + r_usb_pmsc_media_ioctl(USB_MEDIA_IOCTL_GET_WRITE_PROTECT_INFO, &write_protect); switch (page_code) { case 0x00: /* Mode Parameter Header */ { - *size = USB_ATAPI_MODE_SENSE10_MODE_PARAM_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_mp_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_MODE_PARAM_SIZE; + g_usb_atapi_ms_mp_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_mp_tbl[0]; break; } case 0x01: /* ReadWrite Error Recovery Page */ { - *size = USB_ATAPI_MODE_SENSE10_ERR_RCVR_P_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_rcvr_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_ERR_RCVR_P_SIZE; + g_usb_atapi_ms_rcvr_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_rcvr_tbl[0]; break; } case 0x08: /* Cashing Page */ { - *size = USB_ATAPI_MODE_SENSE10_CASHING_P_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_cash_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_CASHING_P_SIZE; + g_usb_atapi_ms_cash_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_cash_tbl[0]; break; } case 0x1B: /* Removable Block Access Capacities Page */ { - *size = USB_ATAPI_MODE_SENSE10_CAP_P_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_capa_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_CAP_P_SIZE; + g_usb_atapi_ms_capa_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_capa_tbl[0]; break; } case 0x1C: /* Timer & Protect Page */ { - *size = USB_ATAPI_MODE_SENSE10_OP_CMD_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_op_cmd_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_OP_CMD_SIZE; + g_usb_atapi_ms_op_cmd_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_op_cmd_tbl[0]; break; } case USB_VALUE_MODE_SENSE10_ALL_PAGE: /* All Page */ { - *size = USB_ATAPI_MODE_SENSE10_ALL_P_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_all_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_ALL_P_SIZE; + g_usb_atapi_ms_all_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_all_tbl[0]; break; } default: { - *size = USB_ATAPI_MODE_SENSE10_P_CODE_ERR_SIZE; - p_data = (uint8_t *) &g_usb_atapi_ms_err_tbl[0]; + *size = USB_ATAPI_MODE_SENSE10_P_CODE_ERR_SIZE; + g_usb_atapi_ms_err_tbl[3] |= (uint8_t) (write_protect << 0x07); + p_data = &g_usb_atapi_ms_err_tbl[0]; break; } diff --git a/ra/fsp/src/r_wdt/r_wdt.c b/ra/fsp/src/r_wdt/r_wdt.c index f16e1655e..00f04f45a 100644 --- a/ra/fsp/src/r_wdt/r_wdt.c +++ b/ra/fsp/src/r_wdt/r_wdt.c @@ -101,6 +101,12 @@ * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile wdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile wdt_prv_ns_callback)(wdt_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -166,7 +172,7 @@ static const uint8_t g_wdt_division_lookup[] = }; /** Global pointer to control structure for use by the NMI callback. */ -static wdt_instance_ctrl_t * gp_wdt_ctrl = NULL; +static volatile wdt_instance_ctrl_t * gp_wdt_ctrl = NULL; /*********************************************************************************************************************** * Global variables @@ -182,6 +188,7 @@ const wdt_api_t g_wdt_on_wdt = .statusClear = R_WDT_StatusClear, .counterGet = R_WDT_CounterGet, .timeoutGet = R_WDT_TimeoutGet, + .callbackSet = R_WDT_CallbackSet, .versionGet = R_WDT_VersionGet, }; @@ -207,6 +214,7 @@ const wdt_api_t g_wdt_on_wdt = * @retval FSP_SUCCESS WDT successfully configured. * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. * * @note In auto start mode the only valid configuration option is for registering the callback for the NMI ISR if * NMI output has been selected. @@ -231,6 +239,7 @@ fsp_err_t R_WDT_Open (wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg) /* Register callback with BSP NMI ISR. */ r_wdt_nmi_initialize(p_instance_ctrl, p_cfg); } + #else /* Eliminate toolchain warning when NMI output is not being used. */ @@ -473,6 +482,42 @@ fsp_err_t R_WDT_CounterGet (wdt_ctrl_t * const p_ctrl, uint32_t * const p_count) return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements wdt_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_WDT_CallbackSet (wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void const * const p_context, + wdt_callback_args_t * const p_callback_memory) +{ + wdt_instance_ctrl_t * p_instance_ctrl = (wdt_instance_ctrl_t *) p_ctrl; + +#if WDT_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(WDT_OPEN == p_instance_ctrl->wdt_open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + + /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ + p_instance_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); +#endif + + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Return WDT HAL driver version. Implements @ref wdt_api_t::versionGet. * @@ -512,9 +557,49 @@ static void r_wdt_nmi_internal_callback (bsp_grp_irq_t irq) { if (NULL != gp_wdt_ctrl->p_callback) { - wdt_callback_args_t p_args; - p_args.p_context = gp_wdt_ctrl->p_context; - gp_wdt_ctrl->p_callback(&p_args); + wdt_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + wdt_callback_args_t * p_args = gp_wdt_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->p_context = gp_wdt_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (gp_wdt_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + gp_wdt_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + wdt_prv_ns_callback p_callback = (wdt_prv_ns_callback) (gp_wdt_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + gp_wdt_ctrl->p_callback(p_args); +#endif + if (NULL != gp_wdt_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *gp_wdt_ctrl->p_callback_memory = args; + } } } } @@ -554,8 +639,15 @@ static void r_wdt_nmi_initialize (wdt_instance_ctrl_t * const p_instance_ctrl, w /* NMI output mode. */ R_BSP_GroupIrqWrite(BSP_GRP_IRQ_WDT_ERROR, r_wdt_nmi_internal_callback); - p_instance_ctrl->p_callback = p_cfg->p_callback; - p_instance_ctrl->p_context = p_cfg->p_context; + + #if BSP_TZ_SECURE_BUILD + + /* If this is a secure build, the callback provided in p_cfg must be secure. */ + p_instance_ctrl->callback_is_secure = true; + #endif + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; /* Enable the WDT underflow/refresh error interrupt (will generate an NMI). NMIER bits cannot be cleared after reset, * so no need to read-modify-write. */ @@ -573,6 +665,7 @@ static void r_wdt_nmi_initialize (wdt_instance_ctrl_t * const p_instance_ctrl, w * @retval FSP_SUCCESS WDT successfully configured. * @retval FSP_ERR_ASSERTION Null pointer, or one or more configuration options is invalid. * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_INVALID_STATE The security state of the NMI and the module do not match. **********************************************************************************************************************/ static fsp_err_t r_wdt_parameter_checking (wdt_instance_ctrl_t * const p_instance_ctrl, wdt_cfg_t const * const p_cfg) { @@ -583,6 +676,13 @@ static fsp_err_t r_wdt_parameter_checking (wdt_instance_ctrl_t * const p_instanc FSP_ASSERT(NULL != p_instance_ctrl); FSP_ERROR_RETURN(WDT_OPEN != p_instance_ctrl->wdt_open, FSP_ERR_ALREADY_OPEN); + /* Ensure this module is in the same security state as the NMI */ + #if defined(BSP_TZ_NONSECURE_BUILD) && BSP_TZ_NONSECURE_BUILD + FSP_ERROR_RETURN(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk, FSP_ERR_INVALID_STATE); + #elif defined(BSP_TZ_SECURE_BUILD) && BSP_TZ_SECURE_BUILD + FSP_ERROR_RETURN(!(SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk), FSP_ERR_INVALID_STATE); + #endif + /* Check timeout parameter is supported by WDT. */ /* Enum checking is done here because some enums in wdt_timeout_t are not supported by the WDT peripheral (they are @@ -605,6 +705,7 @@ static fsp_err_t r_wdt_parameter_checking (wdt_instance_ctrl_t * const p_instanc { FSP_ASSERT(NULL == p_cfg->p_callback); } + #else FSP_ASSERT(p_cfg->reset_control == WDT_RESET_CONTROL_RESET); #endif diff --git a/ra/fsp/src/rm_aws_pkcs11_pal/inc/rm_aws_pkcs11_pal.h b/ra/fsp/src/rm_aws_pkcs11_pal/inc/rm_aws_pkcs11_pal.h index f3d82bd1e..1d2a57789 100644 --- a/ra/fsp/src/rm_aws_pkcs11_pal/inc/rm_aws_pkcs11_pal.h +++ b/ra/fsp/src/rm_aws_pkcs11_pal/inc/rm_aws_pkcs11_pal.h @@ -32,6 +32,11 @@ #include #include +/* + * @brief Initialize the PAL. + */ +extern CK_RV PKCS11_PAL_Initialize(); + /* * @brief Save an object to storage. */ @@ -40,7 +45,7 @@ extern CK_OBJECT_HANDLE PKCS11_PAL_SaveObject(CK_ATTRIBUTE_PTR pxLabel, uint8_t /* * @brief Look up an object handle using it's label. */ -extern CK_OBJECT_HANDLE PKCS11_PAL_FindObject(uint8_t * pLabel, uint8_t usLength); +extern CK_OBJECT_HANDLE PKCS11_PAL_FindObject(uint8_t * pxLabel, uint8_t usLength); /* * @brief Get the value of an object. diff --git a/ra/fsp/src/rm_aws_pkcs11_pal/rm_aws_pkcs11_pal.c b/ra/fsp/src/rm_aws_pkcs11_pal/rm_aws_pkcs11_pal.c index 6de65efb0..b820b7546 100644 --- a/ra/fsp/src/rm_aws_pkcs11_pal/rm_aws_pkcs11_pal.c +++ b/ra/fsp/src/rm_aws_pkcs11_pal/rm_aws_pkcs11_pal.c @@ -44,6 +44,7 @@ #include #include +#include "rm_aws_pkcs11_pal.h" #include "r_flash_hp.h" #define FLASH_HP_DATA_BLOCK_NUM (1024U) @@ -180,29 +181,12 @@ const flash_cfg_t fsp_flash_cfg = // } /* - * @brief Save an object to storage. + * @brief Initialize the PAL. */ -extern CK_OBJECT_HANDLE PKCS11_PAL_SaveObject(CK_ATTRIBUTE_PTR pxLabel, uint8_t * pucData, uint32_t ulDataSize); - -/* - * @brief Look up an object handle using it's label. - */ -extern CK_OBJECT_HANDLE PKCS11_PAL_FindObject(uint8_t * pLabel, uint8_t usLength); - -/* - * @brief Get the value of an object. - * @note Buffers may be allocated by this call, and should be - * freed up by calling PKCS11_PAL_GetObjectValueCleanup(). - */ -extern CK_RV PKCS11_PAL_GetObjectValue(CK_OBJECT_HANDLE xHandle, - uint8_t ** ppucData, - uint32_t * pulDataSize, - CK_BBOOL * xIsPrivate); - -/** - * @brief Free the buffer allocated in PKCS11_PAL_GetObjectValue() (see PAL). - */ -extern void PKCS11_PAL_GetObjectValueCleanup(uint8_t * pucBuffer, uint32_t ulBufferSize); +CK_RV PKCS11_PAL_Initialize () +{ + return CKR_OK; +} /** * @brief Writes a file to local storage. @@ -352,14 +336,14 @@ CK_OBJECT_HANDLE PKCS11_PAL_SaveObject (CK_ATTRIBUTE_PTR pxLabel, uint8_t * pucD * Port-specific object handle retrieval. * * - * @param[in] pLabel Pointer to the label of the object + * @param[in] pxLabel Pointer to the label of the object * who's handle should be found. * @param[in] usLength The length of the label, in bytes. * * @return The object handle if operation was successful. * Returns eInvalidHandle if unsuccessful. */ -CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pLabel, uint8_t usLength) +CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pxLabel, uint8_t usLength) { /* Avoid compiler warnings about unused variables. */ FSP_PARAMETER_NOT_USED(usLength); @@ -369,7 +353,7 @@ CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pLabel, uint8_t usLength) for (i = 1; i < PKCS_OBJECT_HANDLES_NUM; i++) { - if (!strcmp((char *) &object_handle_dictionary[i], (char *) pLabel)) + if (!strcmp((char *) &object_handle_dictionary[i], (char *) pxLabel)) { if (pkcs_control_block_data_image.data.pkcs_data[i].status == PKCS_DATA_STATUS_REGISTERED) { diff --git a/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c b/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c index 45944e31a..aa0b7a232 100644 --- a/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c +++ b/ra/fsp/src/rm_aws_pkcs11_pal_littlefs/rm_aws_pkcs11_pal_littlefs.c @@ -81,6 +81,14 @@ uint8_t g_object_handle_dictionary[pkcs11configMAX_NUM_OBJECTS][pkcs11configMAX_ #endif }; +/* + * @brief Initialize the PAL. + */ +CK_RV PKCS11_PAL_Initialize () +{ + return CKR_OK; +} + /** * @brief Writes a file to local storage. * @@ -92,7 +100,7 @@ uint8_t g_object_handle_dictionary[pkcs11configMAX_NUM_OBJECTS][pkcs11configMAX_ * * @return The file handle of the object that was stored. */ -CK_OBJECT_HANDLE PKCS11_PAL_SaveObject (CK_ATTRIBUTE_PTR pxLabel, uint8_t * pucData, uint32_t ulDataSize) +CK_OBJECT_HANDLE PKCS11_PAL_SaveObject (CK_ATTRIBUTE_PTR pxLabel, CK_BYTE_PTR pucData, CK_ULONG ulDataSize) { CK_OBJECT_HANDLE xHandle = eInvalidHandle; @@ -144,14 +152,14 @@ CK_OBJECT_HANDLE PKCS11_PAL_SaveObject (CK_ATTRIBUTE_PTR pxLabel, uint8_t * pucD * Port-specific object handle retrieval. * * - * @param[in] pLabel Pointer to the label of the object + * @param[in] pxLabel Pointer to the label of the object * who's handle should be found. * @param[in] usLength The length of the label, in bytes. * * @return The object handle if operation was successful. * Returns eInvalidHandle if unsuccessful. */ -CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pLabel, uint8_t usLength) +CK_OBJECT_HANDLE PKCS11_PAL_FindObject (CK_BYTE_PTR pxLabel, CK_ULONG usLength) { /* Avoid compiler warnings about unused variables. */ FSP_PARAMETER_NOT_USED(usLength); @@ -161,11 +169,11 @@ CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pLabel, uint8_t usLength) for (i = 1; i < pkcs11configMAX_NUM_OBJECTS; i++) { - if (!strcmp((char *) &g_object_handle_dictionary[i], (char *) pLabel)) + if (!strcmp((char *) &g_object_handle_dictionary[i], (char *) pxLabel)) { lfs_file_t file; - int lfs_err = lfs_file_open(&RM_STDIO_LITTLEFS_CFG_LFS, &file, (char *) pLabel, LFS_O_RDONLY); + int lfs_err = lfs_file_open(&RM_STDIO_LITTLEFS_CFG_LFS, &file, (char *) pxLabel, LFS_O_RDONLY); if (LFS_ERR_OK == lfs_err) { @@ -194,7 +202,7 @@ CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pLabel, uint8_t usLength) * @param[in] xHandle Handle of the file to be read. * @param[out] ppucData Pointer to buffer for file data. * @param[out] pulDataSize Size (in bytes) of data located in file. - * @param[out] xIsPrivate Boolean indicating if value is private (CK_TRUE) + * @param[out] pIsPrivate Boolean indicating if value is private (CK_TRUE) * or exportable (CK_FALSE) * * @return CKR_OK if operation was successful. CKR_KEY_HANDLE_INVALID ifshit @@ -203,10 +211,10 @@ CK_OBJECT_HANDLE PKCS11_PAL_FindObject (uint8_t * pLabel, uint8_t usLength) * error. */ -BaseType_t PKCS11_PAL_GetObjectValue (CK_OBJECT_HANDLE xHandle, - uint8_t ** ppucData, - uint32_t * pulDataSize, - CK_BBOOL * xIsPrivate) +CK_RV PKCS11_PAL_GetObjectValue (CK_OBJECT_HANDLE xHandle, + CK_BYTE_PTR * ppucData, + CK_ULONG_PTR pulDataSize, + CK_BBOOL * pIsPrivate) { BaseType_t xReturn = CKR_FUNCTION_FAILED; CK_OBJECT_HANDLE xHandleStorage = xHandle; @@ -243,11 +251,11 @@ BaseType_t PKCS11_PAL_GetObjectValue (CK_OBJECT_HANDLE xHandle, if (xHandle == eAwsDevicePrivateKey) { - *xIsPrivate = CK_TRUE; + *pIsPrivate = CK_TRUE; } else { - *xIsPrivate = CK_FALSE; + *pIsPrivate = CK_FALSE; } } @@ -260,17 +268,17 @@ BaseType_t PKCS11_PAL_GetObjectValue (CK_OBJECT_HANDLE xHandle, /** * @brief Cleanup after PKCS11_GetObjectValue(). * - * @param[in] pucBuffer The buffer to free. + * @param[in] pucData The buffer to free. * (*ppucData from PKCS11_PAL_GetObjectValue()) - * @param[in] ulBufferSize The length of the buffer to free. + * @param[in] ulDataSize The length of the buffer to free. * (*pulDataSize from PKCS11_PAL_GetObjectValue()) */ -void PKCS11_PAL_GetObjectValueCleanup (uint8_t * pucBuffer, uint32_t ulBufferSize) +void PKCS11_PAL_GetObjectValueCleanup (CK_BYTE_PTR pucData, CK_ULONG ulDataSize) { /* Avoid compiler warnings about unused variables. */ - FSP_PARAMETER_NOT_USED(ulBufferSize); + FSP_PARAMETER_NOT_USED(ulDataSize); - vPortFree(pucBuffer); + vPortFree(pucData); } /*-----------------------------------------------------------*/ diff --git a/ra/fsp/src/rm_bl2_port/tfm_common_config.h b/ra/fsp/src/rm_bl2_port/tfm_common_config.h new file mode 100644 index 000000000..8df6b893e --- /dev/null +++ b/ra/fsp/src/rm_bl2_port/tfm_common_config.h @@ -0,0 +1,26 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef TFM_COMMON_CONFIG_H +#define TFM_COMMON_CONFIG_H + +#include "rm_bl2_cfg.h" + +#endif /* TFM_COMMON_CONFIG_H */ diff --git a/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c b/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c index 1d443f58d..7456df670 100644 --- a/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c +++ b/ra/fsp/src/rm_block_media_sdmmc/rm_block_media_sdmmc.c @@ -36,6 +36,13 @@ /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile rm_block_media_sdmmc_prv_ns_callback)(rm_block_media_callback_args_t * + p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile rm_block_media_sdmmc_prv_ns_callback)(rm_block_media_callback_args_t * + p_args); +#endif /*********************************************************************************************************************** * Private function prototypes @@ -61,15 +68,16 @@ static const fsp_version_t g_rm_block_media_sdmmc_version = const rm_block_media_api_t g_rm_block_media_on_sdmmc = { - .open = RM_BLOCK_MEDIA_SDMMC_Open, - .mediaInit = RM_BLOCK_MEDIA_SDMMC_MediaInit, - .read = RM_BLOCK_MEDIA_SDMMC_Read, - .write = RM_BLOCK_MEDIA_SDMMC_Write, - .erase = RM_BLOCK_MEDIA_SDMMC_Erase, - .infoGet = RM_BLOCK_MEDIA_SDMMC_InfoGet, - .statusGet = RM_BLOCK_MEDIA_SDMMC_StatusGet, - .close = RM_BLOCK_MEDIA_SDMMC_Close, - .versionGet = RM_BLOCK_MEDIA_SDMMC_VersionGet, + .open = RM_BLOCK_MEDIA_SDMMC_Open, + .mediaInit = RM_BLOCK_MEDIA_SDMMC_MediaInit, + .read = RM_BLOCK_MEDIA_SDMMC_Read, + .write = RM_BLOCK_MEDIA_SDMMC_Write, + .erase = RM_BLOCK_MEDIA_SDMMC_Erase, + .callbackSet = RM_BLOCK_MEDIA_SDMMC_CallbackSet, + .infoGet = RM_BLOCK_MEDIA_SDMMC_InfoGet, + .statusGet = RM_BLOCK_MEDIA_SDMMC_StatusGet, + .close = RM_BLOCK_MEDIA_SDMMC_Close, + .versionGet = RM_BLOCK_MEDIA_SDMMC_VersionGet, }; /*******************************************************************************************************************//** @@ -118,9 +126,15 @@ fsp_err_t RM_BLOCK_MEDIA_SDMMC_Open (rm_block_media_ctrl_t * const p_ctrl, rm_bl fsp_err_t err = p_sdmmc->p_api->open(p_sdmmc->p_ctrl, p_sdmmc->p_cfg); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + /* Set callback and context pointers, if configured */ + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + /* This module is now open. */ - p_instance_ctrl->initialized = false; - p_instance_ctrl->open = RM_BLOCK_MEDIA_SDMMC_OPEN; + p_instance_ctrl->initialized = false; + p_instance_ctrl->write_protected = false; + p_instance_ctrl->open = RM_BLOCK_MEDIA_SDMMC_OPEN; return FSP_SUCCESS; } @@ -159,6 +173,7 @@ fsp_err_t RM_BLOCK_MEDIA_SDMMC_MediaInit (rm_block_media_ctrl_t * const p_ctrl) p_instance_ctrl->sector_count = device.sector_count; p_instance_ctrl->sector_size_bytes = device.sector_size_bytes; + p_instance_ctrl->write_protected = device.write_protected; p_instance_ctrl->initialized = true; return FSP_SUCCESS; @@ -282,6 +297,57 @@ fsp_err_t RM_BLOCK_MEDIA_SDMMC_Erase (rm_block_media_ctrl_t * const p_ctrl, return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref rm_block_media_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_SDMMC_CallbackSet (rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)( + rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory) +{ + rm_block_media_sdmmc_instance_ctrl_t * p_instance_ctrl = (rm_block_media_sdmmc_instance_ctrl_t *) p_ctrl; + +#if RM_BLOCK_MEDIA_SDMMC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(RM_BLOCK_MEDIA_SDMMC_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if RM_BLOCK_MEDIA_SDMMC_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + rm_block_media_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_instance_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(rm_block_media_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_instance_ctrl->p_callback = p_callback; +#endif + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Provides driver status. Implements @ref rm_block_media_api_t::statusGet(). * @@ -338,6 +404,7 @@ fsp_err_t RM_BLOCK_MEDIA_SDMMC_InfoGet (rm_block_media_ctrl_t * const p_ctrl, rm p_info->sector_size_bytes = p_instance_ctrl->sector_size_bytes; p_info->num_sectors = p_instance_ctrl->sector_count; p_info->reentrant = false; + p_info->write_protected = p_instance_ctrl->write_protected; return FSP_SUCCESS; } @@ -394,6 +461,38 @@ fsp_err_t RM_BLOCK_MEDIA_SDMMC_VersionGet (fsp_version_t * const p_version) * @} (end addtogroup RM_BLOCK_MEDIA_SDMMC) **********************************************************************************************************************/ +/*******************************************************************************************************************//** + * Call configured callback function. + * + * @param[in] p_instance_ctrl Pointer to instance control block + * @param[in] p_args Pointer to callback arguments + **********************************************************************************************************************/ +static inline void rm_block_media_sdmmc_call_callback (rm_block_media_sdmmc_instance_ctrl_t * p_instance_ctrl, + rm_block_media_callback_args_t * p_args) +{ +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_instance_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_instance_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + rm_block_media_sdmmc_prv_ns_callback p_callback = + (rm_block_media_sdmmc_prv_ns_callback) (p_instance_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_instance_ctrl->p_callback(p_args); +#endif +} + /*******************************************************************************************************************//** * Passes callback event from the lower layer driver to the user. * @@ -405,7 +504,7 @@ void rm_block_media_sdmmc_callback (sdmmc_callback_args_t * p_args) rm_block_media_callback_args_t args; memset(&args, 0U, sizeof(rm_block_media_callback_args_t)); - args.p_context = p_instance_ctrl->p_cfg->p_context; + args.p_context = p_instance_ctrl->p_context; if ((SDMMC_EVENT_ERASE_COMPLETE | SDMMC_EVENT_TRANSFER_COMPLETE) & p_args->event) { args.event |= RM_BLOCK_MEDIA_EVENT_OPERATION_COMPLETE; @@ -435,9 +534,34 @@ void rm_block_media_sdmmc_callback (sdmmc_callback_args_t * p_args) if (args.event) { - if (NULL != p_instance_ctrl->p_cfg->p_callback) + if (NULL != p_instance_ctrl->p_callback) { - p_instance_ctrl->p_cfg->p_callback(&args); + rm_block_media_callback_args_t args_stacked; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + rm_block_media_callback_args_t * p_args_memory = p_instance_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args_stacked = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = args; + } + + rm_block_media_sdmmc_call_callback(p_instance_ctrl, p_args_memory); + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args_stacked; + } } } } diff --git a/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c b/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c index e1381eedf..bd449035e 100644 --- a/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c +++ b/ra/fsp/src/rm_block_media_usb/rm_block_media_usb.c @@ -70,15 +70,16 @@ static const fsp_version_t g_rm_block_media_usb_version = const rm_block_media_api_t g_rm_block_media_on_usb = { - .open = RM_BLOCK_MEDIA_USB_Open, - .mediaInit = RM_BLOCK_MEDIA_USB_MediaInit, - .read = RM_BLOCK_MEDIA_USB_Read, - .write = RM_BLOCK_MEDIA_USB_Write, - .erase = RM_BLOCK_MEDIA_USB_Erase, - .infoGet = RM_BLOCK_MEDIA_USB_InfoGet, - .statusGet = RM_BLOCK_MEDIA_USB_StatusGet, - .close = RM_BLOCK_MEDIA_USB_Close, - .versionGet = RM_BLOCK_MEDIA_USB_VersionGet, + .open = RM_BLOCK_MEDIA_USB_Open, + .mediaInit = RM_BLOCK_MEDIA_USB_MediaInit, + .read = RM_BLOCK_MEDIA_USB_Read, + .write = RM_BLOCK_MEDIA_USB_Write, + .erase = RM_BLOCK_MEDIA_USB_Erase, + .callbackSet = RM_BLOCK_MEDIA_USB_CallbackSet, + .infoGet = RM_BLOCK_MEDIA_USB_InfoGet, + .statusGet = RM_BLOCK_MEDIA_USB_StatusGet, + .close = RM_BLOCK_MEDIA_USB_Close, + .versionGet = RM_BLOCK_MEDIA_USB_VersionGet, }; /*******************************************************************************************************************//** @@ -350,6 +351,28 @@ fsp_err_t RM_BLOCK_MEDIA_USB_Erase (rm_block_media_ctrl_t * const p_ctrl, return FSP_SUCCESS; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * Implements @ref rm_block_media_api_t::callbackSet. + * + * @note This function is currently unsupported for Block Media over USB. + * + * @retval FSP_ERR_UNSUPPORTED CallbackSet is not currently supported for Block Media over USB. + **********************************************************************************************************************/ +fsp_err_t RM_BLOCK_MEDIA_USB_CallbackSet (rm_block_media_ctrl_t * const p_ctrl, + void ( * p_callback)( + rm_block_media_callback_args_t *), + void const * const p_context, + rm_block_media_callback_args_t * const p_callback_memory) +{ + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_callback); + FSP_PARAMETER_NOT_USED(p_context); + FSP_PARAMETER_NOT_USED(p_callback_memory); + + return FSP_ERR_UNSUPPORTED; +} + /*******************************************************************************************************************//** * Provides driver status. Implements @ref rm_block_media_api_t::statusGet(). * @@ -419,6 +442,7 @@ fsp_err_t RM_BLOCK_MEDIA_USB_InfoGet (rm_block_media_ctrl_t * const p_ctrl, rm_b p_info->sector_size_bytes = p_instance_ctrl->sector_size_bytes; p_info->num_sectors = p_instance_ctrl->sector_count; p_info->reentrant = false; + p_info->write_protected = false; return FSP_SUCCESS; } diff --git a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c index 115439c9f..04ad70e04 100644 --- a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c +++ b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c @@ -82,10 +82,6 @@ static TaskHandle_t xRxHanderTaskHandle = NULL; /*********************************************************************************************************************** * Exported global function ***********************************************************************************************************************/ -uint32_t ulApplicationGetNextSequenceNumber(uint32_t ulSourceAddress, - uint16_t usSourcePort, - uint32_t ulDestinationAddress, - uint16_t usDestinationPort) __attribute__((weak)); /*********************************************************************************************************************** * Prototype declaration of global functions @@ -329,7 +325,6 @@ __attribute__((weak)) BaseType_t xApplicationGetRandomNumber (uint32_t * pulNumb * rand() in returns a 16-bit number. so create 32 bit Random number using 16 bit rand(). * In this case just a psuedo random number is used so THIS IS NOT RECOMMENDED FOR PRODUCTION SYSTEMS. */ - uint32_t ulRandomValue = 0; ulRandomValue = ((((uint32_t) rand()) & UNSIGNED_SHORT_RANDOM_NUMBER_MASK)) | // NOLINT (rand() has limited randomness. But c99 does not support random) @@ -340,10 +335,10 @@ __attribute__((weak)) BaseType_t xApplicationGetRandomNumber (uint32_t * pulNumb return pdTRUE; } -uint32_t ulApplicationGetNextSequenceNumber (uint32_t ulSourceAddress, - uint16_t usSourcePort, - uint32_t ulDestinationAddress, - uint16_t usDestinationPort) +BSP_WEAK_REFERENCE uint32_t ulApplicationGetNextSequenceNumber (uint32_t ulSourceAddress, + uint16_t usSourcePort, + uint32_t ulDestinationAddress, + uint16_t usDestinationPort) { /* * Callback that provides the inputs necessary to generate a randomized TCP diff --git a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c index d425b002d..035028da8 100644 --- a/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c +++ b/ra/fsp/src/rm_littlefs_flash/rm_littlefs_flash.c @@ -36,11 +36,11 @@ #ifdef RM_LITTLEFS_FLASH_DATA_START static const uint32_t rm_littlefs_flash_data_start = RM_LITTLEFS_FLASH_DATA_START; #else -static const uint32_t rm_littlefs_flash_data_start = BSP_FEATURE_FLASH_DATA_FLASH_START; + #define rm_littlefs_flash_data_start BSP_FEATURE_FLASH_DATA_FLASH_START #endif /** "RLFS" in ASCII, used to determine if channel is open. */ -#define RM_LITTLEFS_FLASH_OPEN (0x524C4653ULL) +#define RM_LITTLEFS_FLASH_OPEN (0x524C4653ULL) const fsp_version_t g_rm_littlefs_flash_version = { diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c index b36f59c7a..54241efe4 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c @@ -38,6 +38,7 @@ #include "mbedtls/aesni.h" #endif #include "hw_sce_aes_private.h" + #include "hw_sce_private.h" /* * 32-bit integer manipulation macros (little endian) @@ -81,13 +82,34 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un { FSP_ASSERT(ctx); FSP_ASSERT(key); - int ret = 0; - unsigned int local_keybits = 0; + int ret = 0; + unsigned int local_keybits = 0; + const unsigned char * p_internal_key = key; + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + /* Create storage to hold the generated OEM key index. Size = Largest key size possible. */ + uint8_t encrypted_aes_key[SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED] = {0}; + #endif switch (keybits) { case SIZE_AES_128BIT_KEYLEN_BITS: { + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + local_keybits = SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED; + ctx->nr = 10; + if (false == (bool) ctx->vendor_ctx) + { + p_internal_key = encrypted_aes_key; + ret = (int) HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_AES128, + NULL, + NULL, + key, + (uint32_t *) p_internal_key); + ctx->vendor_ctx = (bool *) true; + } + + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED; @@ -96,13 +118,29 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un { local_keybits = keybits; } - ctx->nr = 10; + #endif break; } case SIZE_AES_256BIT_KEYLEN_BITS: { + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; + ctx->nr = 14; + if (false == (bool) ctx->vendor_ctx) + { + p_internal_key = encrypted_aes_key; + ret = (int) HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_AES256, + NULL, + NULL, + key, + (uint32_t *) p_internal_key); + ctx->vendor_ctx = (bool *) true; + } + + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; @@ -111,8 +149,9 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un { local_keybits = keybits; } - ctx->nr = 14; + #endif + break; } @@ -123,10 +162,11 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un if (0 == ret) { - /* Store the key into the buffer */ + /* Store the encrypted key into the buffer */ for (uint32_t i = 0; i < (local_keybits >> 5); i++) { - GET_UINT32_LE(ctx->buf[i], key, i << 2); + /* buf is large enough to hold AES 256 bit wrapped key */ + GET_UINT32_LE(ctx->buf[i], p_internal_key, i << 2); } } diff --git a/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c b/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c new file mode 100644 index 000000000..014ed743a --- /dev/null +++ b/ra/fsp/src/rm_psa_crypto/ctr_drbg_alt.c @@ -0,0 +1,1591 @@ +/* + * CTR_DRBG implementation based on AES-256 (NIST SP 800-90) + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ +/* + * The NIST SP 800-90 DRBGs are described in the following publication. + * + * http://csrc.nist.gov/publications/nistpubs/800-90/SP800-90revised_March2007.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_CTR_DRBG_C_ALT) + +#include "ctr_drbg_alt.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +#include + +#if defined(MBEDTLS_FS_IO) +#include +#endif + +#if defined(MBEDTLS_SELF_TEST) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST */ + +/* Macros from mbedtls/aes.h */ + #define MBEDTLS_AES_ENCRYPT 1 /**< AES encryption. */ + #define MBEDTLS_AES_DECRYPT 0 /**< AES decryption. */ +/* Error codes in range 0x0021-0x0025 */ + #define MBEDTLS_ERR_AES_BAD_INPUT_DATA -0x0021 /**< Invalid input data. */ +/* Functions to support software AES for CTR DRBG */ +static void mbedtls_aes_free(mbedtls_aes_context * ctx); +static int mbedtls_aes_crypt_ecb(mbedtls_aes_context * ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]); +static void mbedtls_aes_init(mbedtls_aes_context * ctx); +static int mbedtls_aes_setkey_enc(mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits); + + #if defined(__ICCARM__) /* IAR Compiler */ +static int ferror(FILE * f); + +int ferror (FILE * f) +{ + return EOF; +} + #endif +/* + * CTR_DRBG context initialization + */ +void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_ctr_drbg_context ) ); + /* Indicate that the entropy nonce length is not set explicitly. + * See mbedtls_ctr_drbg_set_nonce_len(). */ + ctx->reseed_counter = -1; + +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_init( &ctx->mutex ); +#endif +} + +void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx ) +{ + if( ctx == NULL ) + return; + +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_free( &ctx->mutex ); +#endif + mbedtls_aes_free( &ctx->aes_ctx ); + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_ctr_drbg_context ) ); +} + +void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx, + int resistance ) +{ + ctx->prediction_resistance = resistance; +} + +void mbedtls_ctr_drbg_set_entropy_len( mbedtls_ctr_drbg_context *ctx, + size_t len ) +{ + ctx->entropy_len = len; +} + +int mbedtls_ctr_drbg_set_nonce_len( mbedtls_ctr_drbg_context *ctx, + size_t len ) +{ + /* If mbedtls_ctr_drbg_seed() has already been called, it's + * too late. Return the error code that's closest to making sense. */ + if( ctx->f_entropy != NULL ) + return( MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED ); + + if( len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); +#if SIZE_MAX > INT_MAX + /* This shouldn't be an issue because + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT < INT_MAX in any sensible + * configuration, but make sure anyway. */ + if( len > INT_MAX ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); +#endif + + /* For backward compatibility with Mbed TLS <= 2.19, store the + * entropy nonce length in a field that already exists, but isn't + * used until after the initial seeding. */ + /* Due to the capping of len above, the value fits in an int. */ + ctx->reseed_counter = (int) len; + return( 0 ); +} + +void mbedtls_ctr_drbg_set_reseed_interval( mbedtls_ctr_drbg_context *ctx, + int interval ) +{ + ctx->reseed_interval = interval; +} + +static int block_cipher_df( unsigned char *output, + const unsigned char *data, size_t data_len ) +{ + unsigned char buf[MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + + MBEDTLS_CTR_DRBG_BLOCKSIZE + 16]; + unsigned char tmp[MBEDTLS_CTR_DRBG_SEEDLEN]; + unsigned char key[MBEDTLS_CTR_DRBG_KEYSIZE]; + unsigned char chain[MBEDTLS_CTR_DRBG_BLOCKSIZE]; + unsigned char *p, *iv; + mbedtls_aes_context aes_ctx; + int ret = 0; + + int i, j; + size_t buf_len, use_len; + + if( data_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + + memset( buf, 0, MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + + MBEDTLS_CTR_DRBG_BLOCKSIZE + 16 ); + mbedtls_aes_init( &aes_ctx ); + + /* + * Construct IV (16 bytes) and S in buffer + * IV = Counter (in 32-bits) padded to 16 with zeroes + * S = Length input string (in 32-bits) || Length of output (in 32-bits) || + * data || 0x80 + * (Total is padded to a multiple of 16-bytes with zeroes) + */ + p = buf + MBEDTLS_CTR_DRBG_BLOCKSIZE; + *p++ = ( data_len >> 24 ) & 0xff; + *p++ = ( data_len >> 16 ) & 0xff; + *p++ = ( data_len >> 8 ) & 0xff; + *p++ = ( data_len ) & 0xff; + p += 3; + *p++ = MBEDTLS_CTR_DRBG_SEEDLEN; + memcpy( p, data, data_len ); + p[data_len] = 0x80; + + buf_len = MBEDTLS_CTR_DRBG_BLOCKSIZE + 8 + data_len + 1; + + for( i = 0; i < MBEDTLS_CTR_DRBG_KEYSIZE; i++ ) + key[i] = i; + + if( ( ret = mbedtls_aes_setkey_enc( &aes_ctx, key, + MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) + { + goto exit; + } + + /* + * Reduce data to MBEDTLS_CTR_DRBG_SEEDLEN bytes of data + */ + for( j = 0; j < MBEDTLS_CTR_DRBG_SEEDLEN; j += MBEDTLS_CTR_DRBG_BLOCKSIZE ) + { + p = buf; + memset( chain, 0, MBEDTLS_CTR_DRBG_BLOCKSIZE ); + use_len = buf_len; + + while( use_len > 0 ) + { + for( i = 0; i < MBEDTLS_CTR_DRBG_BLOCKSIZE; i++ ) + chain[i] ^= p[i]; + p += MBEDTLS_CTR_DRBG_BLOCKSIZE; + use_len -= ( use_len >= MBEDTLS_CTR_DRBG_BLOCKSIZE ) ? + MBEDTLS_CTR_DRBG_BLOCKSIZE : use_len; + + if( ( ret = mbedtls_aes_crypt_ecb( &aes_ctx, MBEDTLS_AES_ENCRYPT, + chain, chain ) ) != 0 ) + { + goto exit; + } + } + + memcpy( tmp + j, chain, MBEDTLS_CTR_DRBG_BLOCKSIZE ); + + /* + * Update IV + */ + buf[3]++; + } + + /* + * Do final encryption with reduced data + */ + if( ( ret = mbedtls_aes_setkey_enc( &aes_ctx, tmp, + MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) + { + goto exit; + } + iv = tmp + MBEDTLS_CTR_DRBG_KEYSIZE; + p = output; + + for( j = 0; j < MBEDTLS_CTR_DRBG_SEEDLEN; j += MBEDTLS_CTR_DRBG_BLOCKSIZE ) + { + if( ( ret = mbedtls_aes_crypt_ecb( &aes_ctx, MBEDTLS_AES_ENCRYPT, + iv, iv ) ) != 0 ) + { + goto exit; + } + memcpy( p, iv, MBEDTLS_CTR_DRBG_BLOCKSIZE ); + p += MBEDTLS_CTR_DRBG_BLOCKSIZE; + } +exit: + mbedtls_aes_free( &aes_ctx ); + /* + * tidy up the stack + */ + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + mbedtls_platform_zeroize( tmp, sizeof( tmp ) ); + mbedtls_platform_zeroize( key, sizeof( key ) ); + mbedtls_platform_zeroize( chain, sizeof( chain ) ); + if( 0 != ret ) + { + /* + * wipe partial seed from memory + */ + mbedtls_platform_zeroize( output, MBEDTLS_CTR_DRBG_SEEDLEN ); + } + + return( ret ); +} + +/* CTR_DRBG_Update (SP 800-90A §10.2.1.2) + * ctr_drbg_update_internal(ctx, provided_data) + * implements + * CTR_DRBG_Update(provided_data, Key, V) + * with inputs and outputs + * ctx->aes_ctx = Key + * ctx->counter = V + */ +static int ctr_drbg_update_internal( mbedtls_ctr_drbg_context *ctx, + const unsigned char data[MBEDTLS_CTR_DRBG_SEEDLEN] ) +{ + unsigned char tmp[MBEDTLS_CTR_DRBG_SEEDLEN]; + unsigned char *p = tmp; + int i, j; + int ret = 0; + + memset( tmp, 0, MBEDTLS_CTR_DRBG_SEEDLEN ); + + for( j = 0; j < MBEDTLS_CTR_DRBG_SEEDLEN; j += MBEDTLS_CTR_DRBG_BLOCKSIZE ) + { + /* + * Increase counter + */ + for( i = MBEDTLS_CTR_DRBG_BLOCKSIZE; i > 0; i-- ) + if( ++ctx->counter[i - 1] != 0 ) + break; + + /* + * Crypt counter block + */ + if( ( ret = mbedtls_aes_crypt_ecb( &ctx->aes_ctx, MBEDTLS_AES_ENCRYPT, + ctx->counter, p ) ) != 0 ) + { + goto exit; + } + + p += MBEDTLS_CTR_DRBG_BLOCKSIZE; + } + + for( i = 0; i < MBEDTLS_CTR_DRBG_SEEDLEN; i++ ) + tmp[i] ^= data[i]; + + /* + * Update key and counter + */ + if( ( ret = mbedtls_aes_setkey_enc( &ctx->aes_ctx, tmp, + MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) + { + goto exit; + } + memcpy( ctx->counter, tmp + MBEDTLS_CTR_DRBG_KEYSIZE, + MBEDTLS_CTR_DRBG_BLOCKSIZE ); + +exit: + mbedtls_platform_zeroize( tmp, sizeof( tmp ) ); + return( ret ); +} + +/* CTR_DRBG_Instantiate with derivation function (SP 800-90A §10.2.1.3.2) + * mbedtls_ctr_drbg_update(ctx, additional, add_len) + * implements + * CTR_DRBG_Instantiate(entropy_input, nonce, personalization_string, + * security_strength) -> initial_working_state + * with inputs + * ctx->counter = all-bits-0 + * ctx->aes_ctx = context from all-bits-0 key + * additional[:add_len] = entropy_input || nonce || personalization_string + * and with outputs + * ctx = initial_working_state + */ +int mbedtls_ctr_drbg_update_ret( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t add_len ) +{ + unsigned char add_input[MBEDTLS_CTR_DRBG_SEEDLEN]; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( add_len == 0 ) + return( 0 ); + + if( ( ret = block_cipher_df( add_input, additional, add_len ) ) != 0 ) + goto exit; + if( ( ret = ctr_drbg_update_internal( ctx, add_input ) ) != 0 ) + goto exit; + +exit: + mbedtls_platform_zeroize( add_input, sizeof( add_input ) ); + return( ret ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_ctr_drbg_update( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t add_len ) +{ + /* MAX_INPUT would be more logical here, but we have to match + * block_cipher_df()'s limits since we can't propagate errors */ + if( add_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ) + add_len = MBEDTLS_CTR_DRBG_MAX_SEED_INPUT; + (void) mbedtls_ctr_drbg_update_ret( ctx, additional, add_len ); +} +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/* CTR_DRBG_Reseed with derivation function (SP 800-90A §10.2.1.4.2) + * mbedtls_ctr_drbg_reseed(ctx, additional, len, nonce_len) + * implements + * CTR_DRBG_Reseed(working_state, entropy_input, additional_input) + * -> new_working_state + * with inputs + * ctx contains working_state + * additional[:len] = additional_input + * and entropy_input comes from calling ctx->f_entropy + * for (ctx->entropy_len + nonce_len) bytes + * and with output + * ctx contains new_working_state + */ +static int mbedtls_ctr_drbg_reseed_internal( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t len, + size_t nonce_len ) +{ + unsigned char seed[MBEDTLS_CTR_DRBG_MAX_SEED_INPUT]; + size_t seedlen = 0; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( ctx->entropy_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + if( nonce_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - ctx->entropy_len ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + if( len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - ctx->entropy_len - nonce_len ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + + memset( seed, 0, MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ); + + /* Gather entropy_len bytes of entropy to seed state. */ + if( 0 != ctx->f_entropy( ctx->p_entropy, seed, ctx->entropy_len ) ) + { + return( MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED ); + } + seedlen += ctx->entropy_len; + + /* Gather entropy for a nonce if requested. */ + if( nonce_len != 0 ) + { + if( 0 != ctx->f_entropy( ctx->p_entropy, seed, nonce_len ) ) + { + return( MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED ); + } + seedlen += nonce_len; + } + + /* Add additional data if provided. */ + if( additional != NULL && len != 0 ) + { + memcpy( seed + seedlen, additional, len ); + seedlen += len; + } + + /* Reduce to 384 bits. */ + if( ( ret = block_cipher_df( seed, seed, seedlen ) ) != 0 ) + goto exit; + + /* Update state. */ + if( ( ret = ctr_drbg_update_internal( ctx, seed ) ) != 0 ) + goto exit; + ctx->reseed_counter = 1; + +exit: + mbedtls_platform_zeroize( seed, sizeof( seed ) ); + return( ret ); +} + +int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, size_t len ) +{ + return( mbedtls_ctr_drbg_reseed_internal( ctx, additional, len, 0 ) ); +} + +/* Return a "good" nonce length for CTR_DRBG. The chosen nonce length + * is sufficient to achieve the maximum security strength given the key + * size and entropy length. If there is enough entropy in the initial + * call to the entropy function to serve as both the entropy input and + * the nonce, don't make a second call to get a nonce. */ +static size_t good_nonce_len( size_t entropy_len ) +{ + if( entropy_len >= MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 ) + return( 0 ); + else + return( ( entropy_len + 1 ) / 2 ); +} + +/* CTR_DRBG_Instantiate with derivation function (SP 800-90A §10.2.1.3.2) + * mbedtls_ctr_drbg_seed(ctx, f_entropy, p_entropy, custom, len) + * implements + * CTR_DRBG_Instantiate(entropy_input, nonce, personalization_string, + * security_strength) -> initial_working_state + * with inputs + * custom[:len] = nonce || personalization_string + * where entropy_input comes from f_entropy for ctx->entropy_len bytes + * and with outputs + * ctx = initial_working_state + */ +int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char key[MBEDTLS_CTR_DRBG_KEYSIZE]; + size_t nonce_len; + + memset( key, 0, MBEDTLS_CTR_DRBG_KEYSIZE ); + + mbedtls_aes_init( &ctx->aes_ctx ); + + ctx->f_entropy = f_entropy; + ctx->p_entropy = p_entropy; + + if( ctx->entropy_len == 0 ) + ctx->entropy_len = MBEDTLS_CTR_DRBG_ENTROPY_LEN; + /* ctx->reseed_counter contains the desired amount of entropy to + * grab for a nonce (see mbedtls_ctr_drbg_set_nonce_len()). + * If it's -1, indicating that the entropy nonce length was not set + * explicitly, use a sufficiently large nonce for security. */ + nonce_len = ( ctx->reseed_counter >= 0 ? + (size_t) ctx->reseed_counter : + good_nonce_len( ctx->entropy_len ) ); + + ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; + + /* Initialize with an empty key. */ + if( ( ret = mbedtls_aes_setkey_enc( &ctx->aes_ctx, key, + MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) + { + return( ret ); + } + + /* Do the initial seeding. */ + if( ( ret = mbedtls_ctr_drbg_reseed_internal( ctx, custom, len, + nonce_len ) ) != 0 ) + { + return( ret ); + } + return( 0 ); +} + +/* CTR_DRBG_Generate with derivation function (SP 800-90A §10.2.1.5.2) + * mbedtls_ctr_drbg_random_with_add(ctx, output, output_len, additional, add_len) + * implements + * CTR_DRBG_Reseed(working_state, entropy_input, additional[:add_len]) + * -> working_state_after_reseed + * if required, then + * CTR_DRBG_Generate(working_state_after_reseed, + * requested_number_of_bits, additional_input) + * -> status, returned_bits, new_working_state + * with inputs + * ctx contains working_state + * requested_number_of_bits = 8 * output_len + * additional[:add_len] = additional_input + * and entropy_input comes from calling ctx->f_entropy + * and with outputs + * status = SUCCESS (this function does the reseed internally) + * returned_bits = output[:output_len] + * ctx contains new_working_state + */ +int mbedtls_ctr_drbg_random_with_add( void *p_rng, + unsigned char *output, size_t output_len, + const unsigned char *additional, size_t add_len ) +{ + int ret = 0; + mbedtls_ctr_drbg_context *ctx = (mbedtls_ctr_drbg_context *) p_rng; + unsigned char add_input[MBEDTLS_CTR_DRBG_SEEDLEN]; + unsigned char *p = output; + unsigned char tmp[MBEDTLS_CTR_DRBG_BLOCKSIZE]; + int i; + size_t use_len; + + if( output_len > MBEDTLS_CTR_DRBG_MAX_REQUEST ) + return( MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG ); + + if( add_len > MBEDTLS_CTR_DRBG_MAX_INPUT ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + + memset( add_input, 0, MBEDTLS_CTR_DRBG_SEEDLEN ); + + if( ctx->reseed_counter > ctx->reseed_interval || + ctx->prediction_resistance ) + { + if( ( ret = mbedtls_ctr_drbg_reseed( ctx, additional, add_len ) ) != 0 ) + { + return( ret ); + } + add_len = 0; + } + + if( add_len > 0 ) + { + if( ( ret = block_cipher_df( add_input, additional, add_len ) ) != 0 ) + goto exit; + if( ( ret = ctr_drbg_update_internal( ctx, add_input ) ) != 0 ) + goto exit; + } + + while( output_len > 0 ) + { + /* + * Increase counter + */ + for( i = MBEDTLS_CTR_DRBG_BLOCKSIZE; i > 0; i-- ) + if( ++ctx->counter[i - 1] != 0 ) + break; + + /* + * Crypt counter block + */ + if( ( ret = mbedtls_aes_crypt_ecb( &ctx->aes_ctx, MBEDTLS_AES_ENCRYPT, + ctx->counter, tmp ) ) != 0 ) + { + goto exit; + } + + use_len = ( output_len > MBEDTLS_CTR_DRBG_BLOCKSIZE ) + ? MBEDTLS_CTR_DRBG_BLOCKSIZE : output_len; + /* + * Copy random block to destination + */ + memcpy( p, tmp, use_len ); + p += use_len; + output_len -= use_len; + } + + if( ( ret = ctr_drbg_update_internal( ctx, add_input ) ) != 0 ) + goto exit; + + ctx->reseed_counter++; + +exit: + mbedtls_platform_zeroize( add_input, sizeof( add_input ) ); + mbedtls_platform_zeroize( tmp, sizeof( tmp ) ); + return( ret ); +} + +int mbedtls_ctr_drbg_random( void *p_rng, unsigned char *output, + size_t output_len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ctr_drbg_context *ctx = (mbedtls_ctr_drbg_context *) p_rng; + +#if defined(MBEDTLS_THREADING_C) + if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) + return( ret ); +#endif + + ret = mbedtls_ctr_drbg_random_with_add( ctx, output, output_len, NULL, 0 ); + +#if defined(MBEDTLS_THREADING_C) + if( mbedtls_mutex_unlock( &ctx->mutex ) != 0 ) + return( MBEDTLS_ERR_THREADING_MUTEX_ERROR ); +#endif + + return( ret ); +} + +#if defined(MBEDTLS_FS_IO) +int mbedtls_ctr_drbg_write_seed_file( mbedtls_ctr_drbg_context *ctx, + const char *path ) +{ + int ret = MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR; + FILE *f; + unsigned char buf[ MBEDTLS_CTR_DRBG_MAX_INPUT ]; + + if( ( f = fopen( path, "wb" ) ) == NULL ) + return( MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR ); + + if( ( ret = mbedtls_ctr_drbg_random( ctx, buf, + MBEDTLS_CTR_DRBG_MAX_INPUT ) ) != 0 ) + goto exit; + + if( fwrite( buf, 1, MBEDTLS_CTR_DRBG_MAX_INPUT, f ) != + MBEDTLS_CTR_DRBG_MAX_INPUT ) + { + ret = MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR; + } + else + { + ret = 0; + } + +exit: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + + fclose( f ); + return( ret ); +} + +int mbedtls_ctr_drbg_update_seed_file( mbedtls_ctr_drbg_context *ctx, + const char *path ) +{ + int ret = 0; + FILE *f = NULL; + size_t n; + unsigned char buf[ MBEDTLS_CTR_DRBG_MAX_INPUT ]; + unsigned char c; + + if( ( f = fopen( path, "rb" ) ) == NULL ) + return( MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR ); + + n = fread( buf, 1, sizeof( buf ), f ); + if( fread( &c, 1, 1, f ) != 0 ) + { + ret = MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG; + goto exit; + } + if( n == 0 || ferror( f ) ) + { + ret = MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR; + goto exit; + } + fclose( f ); + f = NULL; + + ret = mbedtls_ctr_drbg_update_ret( ctx, buf, n ); + +exit: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + if( f != NULL ) + fclose( f ); + if( ret != 0 ) + return( ret ); + return( mbedtls_ctr_drbg_write_seed_file( ctx, path ) ); +} +#endif /* MBEDTLS_FS_IO */ + +#if defined(MBEDTLS_SELF_TEST) + +static const unsigned char entropy_source_pr[96] = + { 0xc1, 0x80, 0x81, 0xa6, 0x5d, 0x44, 0x02, 0x16, + 0x19, 0xb3, 0xf1, 0x80, 0xb1, 0xc9, 0x20, 0x02, + 0x6a, 0x54, 0x6f, 0x0c, 0x70, 0x81, 0x49, 0x8b, + 0x6e, 0xa6, 0x62, 0x52, 0x6d, 0x51, 0xb1, 0xcb, + 0x58, 0x3b, 0xfa, 0xd5, 0x37, 0x5f, 0xfb, 0xc9, + 0xff, 0x46, 0xd2, 0x19, 0xc7, 0x22, 0x3e, 0x95, + 0x45, 0x9d, 0x82, 0xe1, 0xe7, 0x22, 0x9f, 0x63, + 0x31, 0x69, 0xd2, 0x6b, 0x57, 0x47, 0x4f, 0xa3, + 0x37, 0xc9, 0x98, 0x1c, 0x0b, 0xfb, 0x91, 0x31, + 0x4d, 0x55, 0xb9, 0xe9, 0x1c, 0x5a, 0x5e, 0xe4, + 0x93, 0x92, 0xcf, 0xc5, 0x23, 0x12, 0xd5, 0x56, + 0x2c, 0x4a, 0x6e, 0xff, 0xdc, 0x10, 0xd0, 0x68 }; + +static const unsigned char entropy_source_nopr[64] = + { 0x5a, 0x19, 0x4d, 0x5e, 0x2b, 0x31, 0x58, 0x14, + 0x54, 0xde, 0xf6, 0x75, 0xfb, 0x79, 0x58, 0xfe, + 0xc7, 0xdb, 0x87, 0x3e, 0x56, 0x89, 0xfc, 0x9d, + 0x03, 0x21, 0x7c, 0x68, 0xd8, 0x03, 0x38, 0x20, + 0xf9, 0xe6, 0x5e, 0x04, 0xd8, 0x56, 0xf3, 0xa9, + 0xc4, 0x4a, 0x4c, 0xbd, 0xc1, 0xd0, 0x08, 0x46, + 0xf5, 0x98, 0x3d, 0x77, 0x1c, 0x1b, 0x13, 0x7e, + 0x4e, 0x0f, 0x9d, 0x8e, 0xf4, 0x09, 0xf9, 0x2e }; + +static const unsigned char nonce_pers_pr[16] = + { 0xd2, 0x54, 0xfc, 0xff, 0x02, 0x1e, 0x69, 0xd2, + 0x29, 0xc9, 0xcf, 0xad, 0x85, 0xfa, 0x48, 0x6c }; + +static const unsigned char nonce_pers_nopr[16] = + { 0x1b, 0x54, 0xb8, 0xff, 0x06, 0x42, 0xbf, 0xf5, + 0x21, 0xf1, 0x5c, 0x1c, 0x0b, 0x66, 0x5f, 0x3f }; + +#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) +static const unsigned char result_pr[16] = + { 0x95, 0x3c, 0xa5, 0xbd, 0x44, 0x1, 0x34, 0xb7, + 0x13, 0x58, 0x3e, 0x6a, 0x6c, 0x7e, 0x88, 0x8a }; + +static const unsigned char result_nopr[16] = + { 0x6c, 0x25, 0x27, 0x95, 0xa3, 0x62, 0xd6, 0xdb, + 0x90, 0xfd, 0x69, 0xb5, 0x42, 0x9, 0x4b, 0x84 }; +#else /* MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ +static const unsigned char result_pr[16] = + { 0x34, 0x01, 0x16, 0x56, 0xb4, 0x29, 0x00, 0x8f, + 0x35, 0x63, 0xec, 0xb5, 0xf2, 0x59, 0x07, 0x23 }; + +static const unsigned char result_nopr[16] = + { 0xa0, 0x54, 0x30, 0x3d, 0x8a, 0x7e, 0xa9, 0x88, + 0x9d, 0x90, 0x3e, 0x07, 0x7c, 0x6f, 0x21, 0x8f }; +#endif /* MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ + +static size_t test_offset; +static int ctr_drbg_self_test_entropy( void *data, unsigned char *buf, + size_t len ) +{ + const unsigned char *p = data; + memcpy( buf, p + test_offset, len ); + test_offset += len; + return( 0 ); +} + +#define CHK( c ) if( (c) != 0 ) \ + { \ + if( verbose != 0 ) \ + mbedtls_printf( "failed\n" ); \ + return( 1 ); \ + } + +/* + * Checkup routine + */ +int mbedtls_ctr_drbg_self_test( int verbose ) +{ + mbedtls_ctr_drbg_context ctx; + unsigned char buf[16]; + + mbedtls_ctr_drbg_init( &ctx ); + + /* + * Based on a NIST CTR_DRBG test vector (PR = True) + */ + if( verbose != 0 ) + mbedtls_printf( " CTR_DRBG (PR = TRUE) : " ); + + test_offset = 0; + mbedtls_ctr_drbg_set_entropy_len( &ctx, 32 ); + mbedtls_ctr_drbg_set_nonce_len( &ctx, 0 ); + CHK( mbedtls_ctr_drbg_seed( &ctx, + ctr_drbg_self_test_entropy, + (void *) entropy_source_pr, + nonce_pers_pr, 16 ) ); + mbedtls_ctr_drbg_set_prediction_resistance( &ctx, MBEDTLS_CTR_DRBG_PR_ON ); + CHK( mbedtls_ctr_drbg_random( &ctx, buf, MBEDTLS_CTR_DRBG_BLOCKSIZE ) ); + CHK( mbedtls_ctr_drbg_random( &ctx, buf, MBEDTLS_CTR_DRBG_BLOCKSIZE ) ); + CHK( memcmp( buf, result_pr, MBEDTLS_CTR_DRBG_BLOCKSIZE ) ); + + mbedtls_ctr_drbg_free( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + /* + * Based on a NIST CTR_DRBG test vector (PR = FALSE) + */ + if( verbose != 0 ) + mbedtls_printf( " CTR_DRBG (PR = FALSE): " ); + + mbedtls_ctr_drbg_init( &ctx ); + + test_offset = 0; + mbedtls_ctr_drbg_set_entropy_len( &ctx, 32 ); + mbedtls_ctr_drbg_set_nonce_len( &ctx, 0 ); + CHK( mbedtls_ctr_drbg_seed( &ctx, + ctr_drbg_self_test_entropy, + (void *) entropy_source_nopr, + nonce_pers_nopr, 16 ) ); + CHK( mbedtls_ctr_drbg_random( &ctx, buf, 16 ) ); + CHK( mbedtls_ctr_drbg_reseed( &ctx, NULL, 0 ) ); + CHK( mbedtls_ctr_drbg_random( &ctx, buf, 16 ) ); + CHK( memcmp( buf, result_nopr, 16 ) ); + + mbedtls_ctr_drbg_free( &ctx ); + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + return( 0 ); +} +#endif /* MBEDTLS_SELF_TEST */ + +/* AES */ + + #include "mbedtls/error.h" + #if defined(MBEDTLS_PADLOCK_C) + #include "mbedtls/padlock.h" + #endif + #if defined(MBEDTLS_AESNI_C) + #include "mbedtls/aesni.h" + #endif + #define MBEDTLS_AES_FEWER_TABLES (1) + +/* Parameter validation macros based on platform_util.h */ + #define AES_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA) + #define AES_VALIDATE(cond) \ + MBEDTLS_INTERNAL_VALIDATE(cond) + +/* + * 32-bit integer manipulation macros (little endian) + */ + #ifndef GET_UINT32_LE + #define GET_UINT32_LE(n, b, i) \ + { \ + (n) = ((uint32_t) (b)[(i)]) \ + | ((uint32_t) (b)[(i) + 1] << 8) \ + | ((uint32_t) (b)[(i) + 2] << 16) \ + | ((uint32_t) (b)[(i) + 3] << 24); \ + } + #endif + + #ifndef PUT_UINT32_LE + #define PUT_UINT32_LE(n, b, i) \ + { \ + (b)[(i)] = (unsigned char) (((n)) & 0xFF); \ + (b)[(i) + 1] = (unsigned char) (((n) >> 8) & 0xFF); \ + (b)[(i) + 2] = (unsigned char) (((n) >> 16) & 0xFF); \ + (b)[(i) + 3] = (unsigned char) (((n) >> 24) & 0xFF); \ + } + #endif + + #if defined(MBEDTLS_PADLOCK_C) && \ + (defined(MBEDTLS_HAVE_X86) || defined(MBEDTLS_PADLOCK_ALIGN16)) +static int aes_padlock_ace = -1; + #endif + + #if defined(MBEDTLS_AES_ROM_TABLES) + +/* + * Forward S-box + */ +static const unsigned char FSb[256] = +{ + 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, + 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, + 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, + 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, + 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, + 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, + 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, + 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, + 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, + 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, + 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, + 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, + 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, + 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, + 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, + 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, + 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, + 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, + 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, + 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, + 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, + 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, + 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, + 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, + 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, + 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, + 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, + 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, + 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, + 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, + 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, + 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 +}; + +/* + * Forward tables + */ + #define FT \ + \ + V(A5, 63, 63, C6), V(84, 7C, 7C, F8), V(99, 77, 77, EE), V(8D, 7B, 7B, F6), \ + V(0D, F2, F2, FF), V(BD, 6B, 6B, D6), V(B1, 6F, 6F, DE), V(54, C5, C5, 91), \ + V(50, 30, 30, 60), V(03, 01, 01, 02), V(A9, 67, 67, CE), V(7D, 2B, 2B, 56), \ + V(19, FE, FE, E7), V(62, D7, D7, B5), V(E6, AB, AB, 4D), V(9A, 76, 76, EC), \ + V(45, CA, CA, 8F), V(9D, 82, 82, 1F), V(40, C9, C9, 89), V(87, 7D, 7D, FA), \ + V(15, FA, FA, EF), V(EB, 59, 59, B2), V(C9, 47, 47, 8E), V(0B, F0, F0, FB), \ + V(EC, AD, AD, 41), V(67, D4, D4, B3), V(FD, A2, A2, 5F), V(EA, AF, AF, 45), \ + V(BF, 9C, 9C, 23), V(F7, A4, A4, 53), V(96, 72, 72, E4), V(5B, C0, C0, 9B), \ + V(C2, B7, B7, 75), V(1C, FD, FD, E1), V(AE, 93, 93, 3D), V(6A, 26, 26, 4C), \ + V(5A, 36, 36, 6C), V(41, 3F, 3F, 7E), V(02, F7, F7, F5), V(4F, CC, CC, 83), \ + V(5C, 34, 34, 68), V(F4, A5, A5, 51), V(34, E5, E5, D1), V(08, F1, F1, F9), \ + V(93, 71, 71, E2), V(73, D8, D8, AB), V(53, 31, 31, 62), V(3F, 15, 15, 2A), \ + V(0C, 04, 04, 08), V(52, C7, C7, 95), V(65, 23, 23, 46), V(5E, C3, C3, 9D), \ + V(28, 18, 18, 30), V(A1, 96, 96, 37), V(0F, 05, 05, 0A), V(B5, 9A, 9A, 2F), \ + V(09, 07, 07, 0E), V(36, 12, 12, 24), V(9B, 80, 80, 1B), V(3D, E2, E2, DF), \ + V(26, EB, EB, CD), V(69, 27, 27, 4E), V(CD, B2, B2, 7F), V(9F, 75, 75, EA), \ + V(1B, 09, 09, 12), V(9E, 83, 83, 1D), V(74, 2C, 2C, 58), V(2E, 1A, 1A, 34), \ + V(2D, 1B, 1B, 36), V(B2, 6E, 6E, DC), V(EE, 5A, 5A, B4), V(FB, A0, A0, 5B), \ + V(F6, 52, 52, A4), V(4D, 3B, 3B, 76), V(61, D6, D6, B7), V(CE, B3, B3, 7D), \ + V(7B, 29, 29, 52), V(3E, E3, E3, DD), V(71, 2F, 2F, 5E), V(97, 84, 84, 13), \ + V(F5, 53, 53, A6), V(68, D1, D1, B9), V(00, 00, 00, 00), V(2C, ED, ED, C1), \ + V(60, 20, 20, 40), V(1F, FC, FC, E3), V(C8, B1, B1, 79), V(ED, 5B, 5B, B6), \ + V(BE, 6A, 6A, D4), V(46, CB, CB, 8D), V(D9, BE, BE, 67), V(4B, 39, 39, 72), \ + V(DE, 4A, 4A, 94), V(D4, 4C, 4C, 98), V(E8, 58, 58, B0), V(4A, CF, CF, 85), \ + V(6B, D0, D0, BB), V(2A, EF, EF, C5), V(E5, AA, AA, 4F), V(16, FB, FB, ED), \ + V(C5, 43, 43, 86), V(D7, 4D, 4D, 9A), V(55, 33, 33, 66), V(94, 85, 85, 11), \ + V(CF, 45, 45, 8A), V(10, F9, F9, E9), V(06, 02, 02, 04), V(81, 7F, 7F, FE), \ + V(F0, 50, 50, A0), V(44, 3C, 3C, 78), V(BA, 9F, 9F, 25), V(E3, A8, A8, 4B), \ + V(F3, 51, 51, A2), V(FE, A3, A3, 5D), V(C0, 40, 40, 80), V(8A, 8F, 8F, 05), \ + V(AD, 92, 92, 3F), V(BC, 9D, 9D, 21), V(48, 38, 38, 70), V(04, F5, F5, F1), \ + V(DF, BC, BC, 63), V(C1, B6, B6, 77), V(75, DA, DA, AF), V(63, 21, 21, 42), \ + V(30, 10, 10, 20), V(1A, FF, FF, E5), V(0E, F3, F3, FD), V(6D, D2, D2, BF), \ + V(4C, CD, CD, 81), V(14, 0C, 0C, 18), V(35, 13, 13, 26), V(2F, EC, EC, C3), \ + V(E1, 5F, 5F, BE), V(A2, 97, 97, 35), V(CC, 44, 44, 88), V(39, 17, 17, 2E), \ + V(57, C4, C4, 93), V(F2, A7, A7, 55), V(82, 7E, 7E, FC), V(47, 3D, 3D, 7A), \ + V(AC, 64, 64, C8), V(E7, 5D, 5D, BA), V(2B, 19, 19, 32), V(95, 73, 73, E6), \ + V(A0, 60, 60, C0), V(98, 81, 81, 19), V(D1, 4F, 4F, 9E), V(7F, DC, DC, A3), \ + V(66, 22, 22, 44), V(7E, 2A, 2A, 54), V(AB, 90, 90, 3B), V(83, 88, 88, 0B), \ + V(CA, 46, 46, 8C), V(29, EE, EE, C7), V(D3, B8, B8, 6B), V(3C, 14, 14, 28), \ + V(79, DE, DE, A7), V(E2, 5E, 5E, BC), V(1D, 0B, 0B, 16), V(76, DB, DB, AD), \ + V(3B, E0, E0, DB), V(56, 32, 32, 64), V(4E, 3A, 3A, 74), V(1E, 0A, 0A, 14), \ + V(DB, 49, 49, 92), V(0A, 06, 06, 0C), V(6C, 24, 24, 48), V(E4, 5C, 5C, B8), \ + V(5D, C2, C2, 9F), V(6E, D3, D3, BD), V(EF, AC, AC, 43), V(A6, 62, 62, C4), \ + V(A8, 91, 91, 39), V(A4, 95, 95, 31), V(37, E4, E4, D3), V(8B, 79, 79, F2), \ + V(32, E7, E7, D5), V(43, C8, C8, 8B), V(59, 37, 37, 6E), V(B7, 6D, 6D, DA), \ + V(8C, 8D, 8D, 01), V(64, D5, D5, B1), V(D2, 4E, 4E, 9C), V(E0, A9, A9, 49), \ + V(B4, 6C, 6C, D8), V(FA, 56, 56, AC), V(07, F4, F4, F3), V(25, EA, EA, CF), \ + V(AF, 65, 65, CA), V(8E, 7A, 7A, F4), V(E9, AE, AE, 47), V(18, 08, 08, 10), \ + V(D5, BA, BA, 6F), V(88, 78, 78, F0), V(6F, 25, 25, 4A), V(72, 2E, 2E, 5C), \ + V(24, 1C, 1C, 38), V(F1, A6, A6, 57), V(C7, B4, B4, 73), V(51, C6, C6, 97), \ + V(23, E8, E8, CB), V(7C, DD, DD, A1), V(9C, 74, 74, E8), V(21, 1F, 1F, 3E), \ + V(DD, 4B, 4B, 96), V(DC, BD, BD, 61), V(86, 8B, 8B, 0D), V(85, 8A, 8A, 0F), \ + V(90, 70, 70, E0), V(42, 3E, 3E, 7C), V(C4, B5, B5, 71), V(AA, 66, 66, CC), \ + V(D8, 48, 48, 90), V(05, 03, 03, 06), V(01, F6, F6, F7), V(12, 0E, 0E, 1C), \ + V(A3, 61, 61, C2), V(5F, 35, 35, 6A), V(F9, 57, 57, AE), V(D0, B9, B9, 69), \ + V(91, 86, 86, 17), V(58, C1, C1, 99), V(27, 1D, 1D, 3A), V(B9, 9E, 9E, 27), \ + V(38, E1, E1, D9), V(13, F8, F8, EB), V(B3, 98, 98, 2B), V(33, 11, 11, 22), \ + V(BB, 69, 69, D2), V(70, D9, D9, A9), V(89, 8E, 8E, 07), V(A7, 94, 94, 33), \ + V(B6, 9B, 9B, 2D), V(22, 1E, 1E, 3C), V(92, 87, 87, 15), V(20, E9, E9, C9), \ + V(49, CE, CE, 87), V(FF, 55, 55, AA), V(78, 28, 28, 50), V(7A, DF, DF, A5), \ + V(8F, 8C, 8C, 03), V(F8, A1, A1, 59), V(80, 89, 89, 09), V(17, 0D, 0D, 1A), \ + V(DA, BF, BF, 65), V(31, E6, E6, D7), V(C6, 42, 42, 84), V(B8, 68, 68, D0), \ + V(C3, 41, 41, 82), V(B0, 99, 99, 29), V(77, 2D, 2D, 5A), V(11, 0F, 0F, 1E), \ + V(CB, B0, B0, 7B), V(FC, 54, 54, A8), V(D6, BB, BB, 6D), V(3A, 16, 16, 2C) + + #define V(a, b, c, d) 0x ## a ## b ## c ## d +static const uint32_t FT0[256] = {FT}; + #undef V + + #if !defined(MBEDTLS_AES_FEWER_TABLES) + + #define V(a, b, c, d) 0x ## b ## c ## d ## a +static const uint32_t FT1[256] = {FT}; + #undef V + + #define V(a, b, c, d) 0x ## c ## d ## a ## b +static const uint32_t FT2[256] = {FT}; + #undef V + + #define V(a, b, c, d) 0x ## d ## a ## b ## c +static const uint32_t FT3[256] = {FT}; + #undef V + + #endif /* !MBEDTLS_AES_FEWER_TABLES */ + + #undef FT + +/* + * Reverse S-box + */ +static const unsigned char RSb[256] = +{ + 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, + 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, + 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, + 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, + 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, + 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, + 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, + 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, + 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, + 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, + 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, + 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, + 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, + 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, + 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, + 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, + 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, + 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, + 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, + 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, + 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, + 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, + 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, + 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, + 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, + 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, + 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, + 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, + 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, + 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, + 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D +}; + +/* + * Reverse tables + */ + #define RT \ + \ + V(50, A7, F4, 51), V(53, 65, 41, 7E), V(C3, A4, 17, 1A), V(96, 5E, 27, 3A), \ + V(CB, 6B, AB, 3B), V(F1, 45, 9D, 1F), V(AB, 58, FA, AC), V(93, 03, E3, 4B), \ + V(55, FA, 30, 20), V(F6, 6D, 76, AD), V(91, 76, CC, 88), V(25, 4C, 02, F5), \ + V(FC, D7, E5, 4F), V(D7, CB, 2A, C5), V(80, 44, 35, 26), V(8F, A3, 62, B5), \ + V(49, 5A, B1, DE), V(67, 1B, BA, 25), V(98, 0E, EA, 45), V(E1, C0, FE, 5D), \ + V(02, 75, 2F, C3), V(12, F0, 4C, 81), V(A3, 97, 46, 8D), V(C6, F9, D3, 6B), \ + V(E7, 5F, 8F, 03), V(95, 9C, 92, 15), V(EB, 7A, 6D, BF), V(DA, 59, 52, 95), \ + V(2D, 83, BE, D4), V(D3, 21, 74, 58), V(29, 69, E0, 49), V(44, C8, C9, 8E), \ + V(6A, 89, C2, 75), V(78, 79, 8E, F4), V(6B, 3E, 58, 99), V(DD, 71, B9, 27), \ + V(B6, 4F, E1, BE), V(17, AD, 88, F0), V(66, AC, 20, C9), V(B4, 3A, CE, 7D), \ + V(18, 4A, DF, 63), V(82, 31, 1A, E5), V(60, 33, 51, 97), V(45, 7F, 53, 62), \ + V(E0, 77, 64, B1), V(84, AE, 6B, BB), V(1C, A0, 81, FE), V(94, 2B, 08, F9), \ + V(58, 68, 48, 70), V(19, FD, 45, 8F), V(87, 6C, DE, 94), V(B7, F8, 7B, 52), \ + V(23, D3, 73, AB), V(E2, 02, 4B, 72), V(57, 8F, 1F, E3), V(2A, AB, 55, 66), \ + V(07, 28, EB, B2), V(03, C2, B5, 2F), V(9A, 7B, C5, 86), V(A5, 08, 37, D3), \ + V(F2, 87, 28, 30), V(B2, A5, BF, 23), V(BA, 6A, 03, 02), V(5C, 82, 16, ED), \ + V(2B, 1C, CF, 8A), V(92, B4, 79, A7), V(F0, F2, 07, F3), V(A1, E2, 69, 4E), \ + V(CD, F4, DA, 65), V(D5, BE, 05, 06), V(1F, 62, 34, D1), V(8A, FE, A6, C4), \ + V(9D, 53, 2E, 34), V(A0, 55, F3, A2), V(32, E1, 8A, 05), V(75, EB, F6, A4), \ + V(39, EC, 83, 0B), V(AA, EF, 60, 40), V(06, 9F, 71, 5E), V(51, 10, 6E, BD), \ + V(F9, 8A, 21, 3E), V(3D, 06, DD, 96), V(AE, 05, 3E, DD), V(46, BD, E6, 4D), \ + V(B5, 8D, 54, 91), V(05, 5D, C4, 71), V(6F, D4, 06, 04), V(FF, 15, 50, 60), \ + V(24, FB, 98, 19), V(97, E9, BD, D6), V(CC, 43, 40, 89), V(77, 9E, D9, 67), \ + V(BD, 42, E8, B0), V(88, 8B, 89, 07), V(38, 5B, 19, E7), V(DB, EE, C8, 79), \ + V(47, 0A, 7C, A1), V(E9, 0F, 42, 7C), V(C9, 1E, 84, F8), V(00, 00, 00, 00), \ + V(83, 86, 80, 09), V(48, ED, 2B, 32), V(AC, 70, 11, 1E), V(4E, 72, 5A, 6C), \ + V(FB, FF, 0E, FD), V(56, 38, 85, 0F), V(1E, D5, AE, 3D), V(27, 39, 2D, 36), \ + V(64, D9, 0F, 0A), V(21, A6, 5C, 68), V(D1, 54, 5B, 9B), V(3A, 2E, 36, 24), \ + V(B1, 67, 0A, 0C), V(0F, E7, 57, 93), V(D2, 96, EE, B4), V(9E, 91, 9B, 1B), \ + V(4F, C5, C0, 80), V(A2, 20, DC, 61), V(69, 4B, 77, 5A), V(16, 1A, 12, 1C), \ + V(0A, BA, 93, E2), V(E5, 2A, A0, C0), V(43, E0, 22, 3C), V(1D, 17, 1B, 12), \ + V(0B, 0D, 09, 0E), V(AD, C7, 8B, F2), V(B9, A8, B6, 2D), V(C8, A9, 1E, 14), \ + V(85, 19, F1, 57), V(4C, 07, 75, AF), V(BB, DD, 99, EE), V(FD, 60, 7F, A3), \ + V(9F, 26, 01, F7), V(BC, F5, 72, 5C), V(C5, 3B, 66, 44), V(34, 7E, FB, 5B), \ + V(76, 29, 43, 8B), V(DC, C6, 23, CB), V(68, FC, ED, B6), V(63, F1, E4, B8), \ + V(CA, DC, 31, D7), V(10, 85, 63, 42), V(40, 22, 97, 13), V(20, 11, C6, 84), \ + V(7D, 24, 4A, 85), V(F8, 3D, BB, D2), V(11, 32, F9, AE), V(6D, A1, 29, C7), \ + V(4B, 2F, 9E, 1D), V(F3, 30, B2, DC), V(EC, 52, 86, 0D), V(D0, E3, C1, 77), \ + V(6C, 16, B3, 2B), V(99, B9, 70, A9), V(FA, 48, 94, 11), V(22, 64, E9, 47), \ + V(C4, 8C, FC, A8), V(1A, 3F, F0, A0), V(D8, 2C, 7D, 56), V(EF, 90, 33, 22), \ + V(C7, 4E, 49, 87), V(C1, D1, 38, D9), V(FE, A2, CA, 8C), V(36, 0B, D4, 98), \ + V(CF, 81, F5, A6), V(28, DE, 7A, A5), V(26, 8E, B7, DA), V(A4, BF, AD, 3F), \ + V(E4, 9D, 3A, 2C), V(0D, 92, 78, 50), V(9B, CC, 5F, 6A), V(62, 46, 7E, 54), \ + V(C2, 13, 8D, F6), V(E8, B8, D8, 90), V(5E, F7, 39, 2E), V(F5, AF, C3, 82), \ + V(BE, 80, 5D, 9F), V(7C, 93, D0, 69), V(A9, 2D, D5, 6F), V(B3, 12, 25, CF), \ + V(3B, 99, AC, C8), V(A7, 7D, 18, 10), V(6E, 63, 9C, E8), V(7B, BB, 3B, DB), \ + V(09, 78, 26, CD), V(F4, 18, 59, 6E), V(01, B7, 9A, EC), V(A8, 9A, 4F, 83), \ + V(65, 6E, 95, E6), V(7E, E6, FF, AA), V(08, CF, BC, 21), V(E6, E8, 15, EF), \ + V(D9, 9B, E7, BA), V(CE, 36, 6F, 4A), V(D4, 09, 9F, EA), V(D6, 7C, B0, 29), \ + V(AF, B2, A4, 31), V(31, 23, 3F, 2A), V(30, 94, A5, C6), V(C0, 66, A2, 35), \ + V(37, BC, 4E, 74), V(A6, CA, 82, FC), V(B0, D0, 90, E0), V(15, D8, A7, 33), \ + V(4A, 98, 04, F1), V(F7, DA, EC, 41), V(0E, 50, CD, 7F), V(2F, F6, 91, 17), \ + V(8D, D6, 4D, 76), V(4D, B0, EF, 43), V(54, 4D, AA, CC), V(DF, 04, 96, E4), \ + V(E3, B5, D1, 9E), V(1B, 88, 6A, 4C), V(B8, 1F, 2C, C1), V(7F, 51, 65, 46), \ + V(04, EA, 5E, 9D), V(5D, 35, 8C, 01), V(73, 74, 87, FA), V(2E, 41, 0B, FB), \ + V(5A, 1D, 67, B3), V(52, D2, DB, 92), V(33, 56, 10, E9), V(13, 47, D6, 6D), \ + V(8C, 61, D7, 9A), V(7A, 0C, A1, 37), V(8E, 14, F8, 59), V(89, 3C, 13, EB), \ + V(EE, 27, A9, CE), V(35, C9, 61, B7), V(ED, E5, 1C, E1), V(3C, B1, 47, 7A), \ + V(59, DF, D2, 9C), V(3F, 73, F2, 55), V(79, CE, 14, 18), V(BF, 37, C7, 73), \ + V(EA, CD, F7, 53), V(5B, AA, FD, 5F), V(14, 6F, 3D, DF), V(86, DB, 44, 78), \ + V(81, F3, AF, CA), V(3E, C4, 68, B9), V(2C, 34, 24, 38), V(5F, 40, A3, C2), \ + V(72, C3, 1D, 16), V(0C, 25, E2, BC), V(8B, 49, 3C, 28), V(41, 95, 0D, FF), \ + V(71, 01, A8, 39), V(DE, B3, 0C, 08), V(9C, E4, B4, D8), V(90, C1, 56, 64), \ + V(61, 84, CB, 7B), V(70, B6, 32, D5), V(74, 5C, 6C, 48), V(42, 57, B8, D0) + + #define V(a, b, c, d) 0x ## a ## b ## c ## d +static const uint32_t RT0[256] = {RT}; + #undef V + + #if !defined(MBEDTLS_AES_FEWER_TABLES) + + #define V(a, b, c, d) 0x ## b ## c ## d ## a +static const uint32_t RT1[256] = {RT}; + #undef V + + #define V(a, b, c, d) 0x ## c ## d ## a ## b +static const uint32_t RT2[256] = {RT}; + #undef V + + #define V(a, b, c, d) 0x ## d ## a ## b ## c +static const uint32_t RT3[256] = {RT}; + #undef V + + #endif /* !MBEDTLS_AES_FEWER_TABLES */ + + #undef RT + +/* + * Round constants + */ +static const uint32_t RCON[10] = +{ + 0x00000001, 0x00000002, 0x00000004, 0x00000008, + 0x00000010, 0x00000020, 0x00000040, 0x00000080, + 0x0000001B, 0x00000036 +}; + + #else /* MBEDTLS_AES_ROM_TABLES */ + +/* + * Forward S-box & tables + */ +static unsigned char FSb[256]; // NOLINT(readability-magic-numbers) +static uint32_t FT0[256]; // NOLINT(readability-magic-numbers) + #if !defined(MBEDTLS_AES_FEWER_TABLES) +static uint32_t FT1[256]; +static uint32_t FT2[256]; +static uint32_t FT3[256]; + #endif /* !MBEDTLS_AES_FEWER_TABLES */ + +/* + * Reverse S-box & tables + */ +static unsigned char RSb[256]; +static uint32_t RT0[256]; + #if !defined(MBEDTLS_AES_FEWER_TABLES) +static uint32_t RT1[256]; +static uint32_t RT2[256]; +static uint32_t RT3[256]; + #endif /* !MBEDTLS_AES_FEWER_TABLES */ + +/* + * Round constants + */ +static uint32_t RCON[10]; + +/* + * Tables generation code + */ + #define ROTL8(x) (((x) << 8) & 0xFFFFFFFF) | ((x) >> 24) // NOLINT(readability-magic-numbers) + #define XTIME(x) (((x) << 1) ^ (((x) & 0x80) ? 0x1B : 0x00)) // NOLINT(readability-magic-numbers) + #define MUL(x, y) (((x) && (y)) ? pow[(log[(x)] + log[(y)]) % 255] : 0) // NOLINT(readability-magic-numbers) + +static int aes_init_done = 0; + +static void aes_gen_tables (void) +{ + int i; + int x; + int y; + int z; + int pow[256]; + int log[256]; + (void) (RT0); /* To remove unused variable warning */ + + /* + * compute pow and log tables over GF(2^8) + */ + x = 1; + for (i = 0; i < 256; i++) + { + pow[i] = x; + log[x] = i; + x = (x ^ XTIME(x)) & 0xFF; // NOLINT(readability-magic-numbers) + } + + /* + * calculate the round constants + */ + x = 1; + for (i = 0; i < 10; i++) + { + RCON[i] = (uint32_t) x; + x = XTIME(x) & 0xFF; // NOLINT(readability-magic-numbers) + } + + /* + * generate the forward and reverse S-boxes + */ + FSb[0x00] = 0x63; // NOLINT(readability-magic-numbers) + RSb[0x63] = 0x00; // NOLINT(readability-magic-numbers) + + for (i = 1; i < 256; i++) + { + x = pow[255 - log[i]]; // NOLINT(readability-magic-numbers) + + y = x; y = ((y << 1) | (y >> 7)) & 0xFF; // NOLINT(readability-magic-numbers) + x ^= y; y = ((y << 1) | (y >> 7)) & 0xFF; // NOLINT(readability-magic-numbers) + x ^= y; y = ((y << 1) | (y >> 7)) & 0xFF; // NOLINT(readability-magic-numbers) + x ^= y; y = ((y << 1) | (y >> 7)) & 0xFF; // NOLINT(readability-magic-numbers) + x ^= y ^ 0x63; // NOLINT(readability-magic-numbers) + + FSb[i] = (unsigned char) x; + RSb[x] = (unsigned char) i; + } + + /* + * generate the forward and reverse tables + */ + for (i = 0; i < 256; i++) + { + x = FSb[i]; + y = XTIME(x) & 0xFF; // NOLINT(readability-magic-numbers) + z = (y ^ x) & 0xFF; // NOLINT(readability-magic-numbers) + + FT0[i] = ((uint32_t) y) ^ + ((uint32_t) x << 8) ^ + ((uint32_t) x << 16) ^ + ((uint32_t) z << 24); + + #if !defined(MBEDTLS_AES_FEWER_TABLES) + FT1[i] = ROTL8(FT0[i]); + FT2[i] = ROTL8(FT1[i]); + FT3[i] = ROTL8(FT2[i]); + #endif /* !MBEDTLS_AES_FEWER_TABLES */ + + x = RSb[i]; + + RT0[i] = ((uint32_t) MUL(0x0E, x)) ^ + ((uint32_t) MUL(0x09, x) << 8) ^ + ((uint32_t) MUL(0x0D, x) << 16) ^ + ((uint32_t) MUL(0x0B, x) << 24); + + #if !defined(MBEDTLS_AES_FEWER_TABLES) + RT1[i] = ROTL8(RT0[i]); + RT2[i] = ROTL8(RT1[i]); + RT3[i] = ROTL8(RT2[i]); + #endif /* !MBEDTLS_AES_FEWER_TABLES */ + } +} + + #undef ROTL8 + + #endif /* MBEDTLS_AES_ROM_TABLES */ + + #if defined(MBEDTLS_AES_FEWER_TABLES) + + #define ROTL8(x) ((uint32_t) ((x) << 8) + (uint32_t) ((x) >> 24)) + #define ROTL16(x) ((uint32_t) ((x) << 16) + (uint32_t) ((x) >> 16)) + #define ROTL24(x) ((uint32_t) ((x) << 24) + (uint32_t) ((x) >> 8)) + + #define AES_RT0(idx) RT0[idx] + #define AES_RT1(idx) ROTL8(RT0[idx]) + #define AES_RT2(idx) ROTL16(RT0[idx]) + #define AES_RT3(idx) ROTL24(RT0[idx]) + + #define AES_FT0(idx) FT0[idx] + #define AES_FT1(idx) ROTL8(FT0[idx]) + #define AES_FT2(idx) ROTL16(FT0[idx]) + #define AES_FT3(idx) ROTL24(FT0[idx]) + + #else /* MBEDTLS_AES_FEWER_TABLES */ + + #define AES_RT0(idx) RT0[idx] + #define AES_RT1(idx) RT1[idx] + #define AES_RT2(idx) RT2[idx] + #define AES_RT3(idx) RT3[idx] + + #define AES_FT0(idx) FT0[idx] + #define AES_FT1(idx) FT1[idx] + #define AES_FT2(idx) FT2[idx] + #define AES_FT3(idx) FT3[idx] + + #endif /* MBEDTLS_AES_FEWER_TABLES */ + +static void mbedtls_aes_init (mbedtls_aes_context * ctx) +{ + AES_VALIDATE(ctx != NULL); + + memset(ctx, 0, sizeof(mbedtls_aes_context)); +} + +static void mbedtls_aes_free (mbedtls_aes_context * ctx) +{ + if (ctx == NULL) + { + return; + } + + mbedtls_platform_zeroize(ctx, sizeof(mbedtls_aes_context)); +} + +/* + * AES key schedule (encryption) + */ + +// #if !defined(MBEDTLS_AES_SETKEY_ENC_ALT) +static int mbedtls_aes_setkey_enc (mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits) +{ + unsigned int i; + uint32_t * RK; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(key != NULL); + ctx->nr = 14; + + #if !defined(MBEDTLS_AES_ROM_TABLES) + if (aes_init_done == 0) + { + aes_gen_tables(); + aes_init_done = 1; + } + #endif + + #if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_PADLOCK_ALIGN16) + if (aes_padlock_ace == -1) + { + aes_padlock_ace = mbedtls_padlock_has_support(MBEDTLS_PADLOCK_ACE); + } + + if (aes_padlock_ace) + { + ctx->rk = RK = MBEDTLS_PADLOCK_ALIGN16(ctx->buf); + } + else + #endif + RK = ctx->buf; + ctx->rk = ctx->buf; + + #if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + if (mbedtls_aesni_has_support(MBEDTLS_AESNI_AES)) + { + return mbedtls_aesni_setkey_enc((unsigned char *) ctx->rk, key, keybits); + } + #endif + + for (i = 0; i < (keybits >> 5); i++) + { + GET_UINT32_LE(RK[i], key, i << 2); + } + + for (i = 0; i < 7; i++, RK += 8) + { + RK[8] = RK[0] ^ RCON[i] ^ + ((uint32_t) FSb[(RK[7] >> 8) & 0xFF]) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(RK[7] >> 16) & 0xFF] << 8) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(RK[7] >> 24) & 0xFF] << 16) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(RK[7]) & 0xFF] << 24); // NOLINT(readability-magic-numbers) + + RK[9] = RK[1] ^ RK[8]; + RK[10] = RK[2] ^ RK[9]; + RK[11] = RK[3] ^ RK[10]; + + RK[12] = RK[4] ^ + ((uint32_t) FSb[(RK[11]) & 0xFF]) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(RK[11] >> 8) & 0xFF] << 8) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(RK[11] >> 16) & 0xFF] << 16) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(RK[11] >> 24) & 0xFF] << 24); // NOLINT(readability-magic-numbers) + + RK[13] = RK[5] ^ RK[12]; + RK[14] = RK[6] ^ RK[13]; + RK[15] = RK[7] ^ RK[14]; + } + + return 0; +} + +// #endif /* !MBEDTLS_AES_SETKEY_ENC_ALT */ + + #define AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3) \ + do \ + { \ + (X0) = *RK++ ^ AES_FT0(((Y0)) & 0xFF) ^ \ + AES_FT1(((Y1) >> 8) & 0xFF) ^ \ + AES_FT2(((Y2) >> 16) & 0xFF) ^ \ + AES_FT3(((Y3) >> 24) & 0xFF); \ + \ + (X1) = *RK++ ^ AES_FT0(((Y1)) & 0xFF) ^ \ + AES_FT1(((Y2) >> 8) & 0xFF) ^ \ + AES_FT2(((Y3) >> 16) & 0xFF) ^ \ + AES_FT3(((Y0) >> 24) & 0xFF); \ + \ + (X2) = *RK++ ^ AES_FT0(((Y2)) & 0xFF) ^ \ + AES_FT1(((Y3) >> 8) & 0xFF) ^ \ + AES_FT2(((Y0) >> 16) & 0xFF) ^ \ + AES_FT3(((Y1) >> 24) & 0xFF); \ + \ + (X3) = *RK++ ^ AES_FT0(((Y3)) & 0xFF) ^ \ + AES_FT1(((Y0) >> 8) & 0xFF) ^ \ + AES_FT2(((Y1) >> 16) & 0xFF) ^ \ + AES_FT3(((Y2) >> 24) & 0xFF); \ + } while (0) + + #define AES_RROUND(X0, \ + X1, \ + X2, \ + X3, \ + Y0, \ + Y1, \ + Y2, \ + Y3) \ + do \ + { \ + (X0) = *RK++ ^ AES_RT0(((Y0)) & 0xFF) ^ \ + AES_RT1(((Y3) >> 8) & 0xFF) ^ \ + AES_RT2(((Y2) >> 16) & 0xFF) ^ \ + AES_RT3(((Y1) >> 24) & 0xFF); \ + \ + (X1) = *RK++ ^ AES_RT0(((Y1)) & 0xFF) ^ \ + AES_RT1(((Y0) >> 8) & 0xFF) ^ \ + AES_RT2(((Y3) >> 16) & 0xFF) ^ \ + AES_RT3(((Y2) >> 24) & 0xFF); \ + \ + (X2) = *RK++ ^ AES_RT0(((Y2)) & 0xFF) ^ \ + AES_RT1(((Y1) >> 8) & 0xFF) ^ \ + AES_RT2(((Y0) >> 16) & 0xFF) ^ \ + AES_RT3(((Y3) >> 24) & 0xFF); \ + \ + (X3) = *RK++ ^ AES_RT0(((Y3)) & 0xFF) ^ \ + AES_RT1(((Y2) >> 8) & 0xFF) ^ \ + AES_RT2(((Y1) >> 16) & 0xFF) ^ \ + AES_RT3(((Y0) >> 24) & 0xFF); \ + } while (0) + +/* + * AES-ECB block encryption + */ +static int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char input[16], + unsigned char output[16]) +{ + int i; + uint32_t * RK; + uint32_t X0; + uint32_t X1; + uint32_t X2; + uint32_t X3; + uint32_t Y0; + uint32_t Y1; + uint32_t Y2; + uint32_t Y3; + + RK = ctx->rk; + + GET_UINT32_LE(X0, input, 0); X0 ^= *RK++; + GET_UINT32_LE(X1, input, 4); X1 ^= *RK++; + GET_UINT32_LE(X2, input, 8); X2 ^= *RK++; + GET_UINT32_LE(X3, input, 12); X3 ^= *RK++; + + for (i = (ctx->nr >> 1) - 1; i > 0; i--) + { + AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); + AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); + } + + AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); + + X0 = *RK++ ^ \ + ((uint32_t) FSb[(Y0) & 0xFF]) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y1 >> 8) & 0xFF] << 8) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y2 >> 16) & 0xFF] << 16) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y3 >> 24) & 0xFF] << 24); // NOLINT(readability-magic-numbers) + + X1 = *RK++ ^ \ + ((uint32_t) FSb[(Y1) & 0xFF]) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y2 >> 8) & 0xFF] << 8) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y3 >> 16) & 0xFF] << 16) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y0 >> 24) & 0xFF] << 24); // NOLINT(readability-magic-numbers) + + X2 = *RK++ ^ \ + ((uint32_t) FSb[(Y2) & 0xFF]) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y3 >> 8) & 0xFF] << 8) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y0 >> 16) & 0xFF] << 16) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y1 >> 24) & 0xFF] << 24); // NOLINT(readability-magic-numbers) + + X3 = *RK++ ^ \ + ((uint32_t) FSb[(Y3) & 0xFF]) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y0 >> 8) & 0xFF] << 8) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y1 >> 16) & 0xFF] << 16) ^ // NOLINT(readability-magic-numbers) + ((uint32_t) FSb[(Y2 >> 24) & 0xFF] << 24); // NOLINT(readability-magic-numbers) + + PUT_UINT32_LE(X0, output, 0); + PUT_UINT32_LE(X1, output, 4); + PUT_UINT32_LE(X2, output, 8); + PUT_UINT32_LE(X3, output, 12); + + mbedtls_platform_zeroize(&X0, sizeof(X0)); + mbedtls_platform_zeroize(&X1, sizeof(X1)); + mbedtls_platform_zeroize(&X2, sizeof(X2)); + mbedtls_platform_zeroize(&X3, sizeof(X3)); + + mbedtls_platform_zeroize(&Y0, sizeof(Y0)); + mbedtls_platform_zeroize(&Y1, sizeof(Y1)); + mbedtls_platform_zeroize(&Y2, sizeof(Y2)); + mbedtls_platform_zeroize(&Y3, sizeof(Y3)); + + mbedtls_platform_zeroize(&RK, sizeof(RK)); + + return 0; +} + +/* + * AES-ECB block encryption/decryption + */ +static int mbedtls_aes_crypt_ecb (mbedtls_aes_context * ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]) +{ + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT); + + #if defined(MBEDTLS_AESNI_C) && defined(MBEDTLS_HAVE_X86_64) + if (mbedtls_aesni_has_support(MBEDTLS_AESNI_AES)) + { + return mbedtls_aesni_crypt_ecb(ctx, mode, input, output); + } + #endif + + #if defined(MBEDTLS_PADLOCK_C) && defined(MBEDTLS_HAVE_X86) + if (aes_padlock_ace) + { + if (mbedtls_padlock_xcryptecb(ctx, mode, input, output) == 0) + { + return 0; + } + + // If padlock data misaligned, we just fall back to + // unaccelerated mode + // + } + #endif + + return mbedtls_internal_aes_encrypt(ctx, input, output); +} + +void sw_aes_256_enc_test (void) +{ + uint8_t input[128] = {0xa5}; // NOLINT(readability-magic-numbers) + uint8_t output[256] = {0}; // NOLINT(readability-magic-numbers) + uint8_t aes256key[32] = {0x55}; // NOLINT(readability-magic-numbers) + memset(input, 0xa5, 128); // NOLINT(readability-magic-numbers) + memset(aes256key, 0x55, 32); // NOLINT(readability-magic-numbers) + mbedtls_aes_context ctx; + mbedtls_aes_init(&ctx); + mbedtls_aes_setkey_enc(&ctx, aes256key, 256); // NOLINT(readability-magic-numbers) + mbedtls_aes_crypt_ecb(&ctx, MBEDTLS_AES_ENCRYPT, input, output); +} + +#endif /* MBEDTLS_CTR_DRBG_C_ALT */ diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c index 423e39cc3..2f4079be4 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt.c @@ -45,6 +45,7 @@ #endif #include "psa/crypto.h" + #include "hw_sce_private.h" /* Parameter validation macros based on platform_util.h */ #define ECDSA_VALIDATE_RET(cond) \ @@ -61,6 +62,7 @@ uint32_t ecp_load_key_size(bool wrapped_mode_ctx, mbedtls_ecp_group * grp); static void ecp_mpi_load(mbedtls_mpi * X, const mbedtls_mpi_uint * p, size_t len) __attribute__((unused)); int ecp_load_parameters_sce(const mbedtls_ecp_group * grp, uint8_t * p_curve_params_buff); int ecp_can_do_sce(mbedtls_ecp_group_id gid); +int ecp_load_curve_attributes_sce(const mbedtls_ecp_group * grp, uint32_t * p_curve_type, uint32_t * p_cmd, sce_oem_cmd_t * oem_priv_cmd); static const hw_sce_ecc_generatesign_t g_ecdsa_generate_sign_lookup[][2] = { @@ -313,6 +315,45 @@ int ecp_can_do_sce (mbedtls_ecp_group_id gid) } } +int ecp_load_curve_attributes_sce (const mbedtls_ecp_group * grp, uint32_t * p_curve_type, uint32_t * p_cmd, sce_oem_cmd_t * oem_priv_cmd) +{ + int ret = 0; + sce_oem_cmd_t priv_key_command = SCE_OEM_CMD_NUM; + switch (grp->id) + { + case MBEDTLS_ECP_DP_SECP256R1: + { + *p_curve_type = 0x0; + *p_cmd = 0x0; + priv_key_command = SCE_OEM_CMD_ECC_P256_PRIVATE; + break; + } + case MBEDTLS_ECP_DP_SECP384R1: + { + *p_curve_type = 0x0; + *p_cmd = 0x0; + priv_key_command = SCE_OEM_CMD_ECC_P384_PRIVATE; + break; + } + case MBEDTLS_ECP_DP_SECP256K1: + { + *p_curve_type = 0x2; + *p_cmd = 0x0; + priv_key_command = SCE_OEM_CMD_ECC_SECP256K1_PRIVATE; + break; + } + default: + { + ret = -1; + } + } + if (NULL != oem_priv_cmd) + { + *oem_priv_cmd = priv_key_command; + } + return ret; +} + #endif // (defined(MBEDTLS_ECDSA_SIGN_ALT) || defined(MBEDTLS_ECDSA_VERIFY_ALT) || defined(MBEDTLS_ECP_ALT)) #if defined(MBEDTLS_ECDSA_SIGN_ALT) @@ -344,7 +385,6 @@ int mbedtls_ecdsa_sign (mbedtls_ecp_group * grp, int ret = 0; hw_sce_ecc_generatesign_t p_hw_sce_ecc_generatesign = NULL; - uint32_t * p_curve_params_buff_32; uint32_t * p_private_key_buff_32; uint32_t * p_signature_buff_32; uint32_t * p_common_buff_32; @@ -370,7 +410,68 @@ int mbedtls_ecdsa_sign (mbedtls_ecp_group * grp, { return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: + * Private Key (D) of size private_key_size_words + * Signature (rs) of size curve_bytes * 2 + * Padded/truncated 32-bit aligned copy of input hash of size curve_bytes */ + p_common_buff_32 = mbedtls_calloc(((curve_bytes * 3) / 4) + private_key_size_words, sizeof(uint32_t)); + + if (NULL == p_common_buff_32) + { + return MBEDTLS_ERR_ECP_ALLOC_FAILED; + } + + p_private_key_buff_32 = p_common_buff_32; + p_signature_buff_32 = p_private_key_buff_32 + private_key_size_words; + + /* The hash input (buf) should have a length of at least the curve size: + * nist.fips.186-4: " A hash function that provides a lower security strength than + * the security strength associated with the bit length of 'n' ordinarily should not be used, since this + * would reduce the security strength of the digital signature process to a level no greater than that + * provided by the hash function." + * However, the SCE HW functions only parse hash of exactly curve_bytes length so + * *-Any larger hash data will be truncated. + * *-Any smaller data will be 0-padded to the LEFT. + * + * Even if the hash input is the same size as the curve, we will still do a copy because the user input + * is an 8-bit pointer whereas the SCE HW expects a 32-bit pointer and there could possibly be + * an alignment issue. */ + p_buf_8 = (uint8_t *) (p_signature_buff_32 + ((curve_bytes * 2) / 4)); + uint32_t bytes_to_copy = blen > curve_bytes ? curve_bytes : blen; + memcpy(p_buf_8 + (curve_bytes - bytes_to_copy), buf, bytes_to_copy); + uint32_t curve_type; + uint32_t cmd; + ret = ecp_load_curve_attributes_sce(grp, &curve_type, &cmd, NULL); + if (ret) + { + } + else if (0 != mbedtls_mpi_write_binary(d, (uint8_t *) p_private_key_buff_32, private_key_size_words * 4)) + { + ret = MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL; + } + else if (FSP_SUCCESS != + p_hw_sce_ecc_generatesign(&curve_type, &cmd, + p_private_key_buff_32, (uint32_t *) p_buf_8, p_signature_buff_32, + p_signature_buff_32 + curve_bytes / 4)) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + /* Import the generated signature into the r and s mpis */ + else if (0 != mbedtls_mpi_read_binary(r, (uint8_t *) p_signature_buff_32, curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + } + else if (0 != mbedtls_mpi_read_binary(s, (uint8_t *) (p_signature_buff_32 + (curve_bytes / 4)), curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + } + else + { + ret = 0; + } +#else /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: * Curve parameters a, b, p, n, Gx, Gy. Each of the 6 fields are of size curve_bytes = PSA_BITS_TO_BYTES( ecp->grp.pbits ) * Private Key (D) of size private_key_size_words @@ -383,7 +484,7 @@ int mbedtls_ecdsa_sign (mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_ALLOC_FAILED; } - p_curve_params_buff_32 = p_common_buff_32; + uint32_t * p_curve_params_buff_32 = p_common_buff_32; p_private_key_buff_32 = p_curve_params_buff_32 + ((curve_bytes * 6) / 4); p_signature_buff_32 = p_private_key_buff_32 + private_key_size_words; @@ -431,7 +532,7 @@ int mbedtls_ecdsa_sign (mbedtls_ecp_group * grp, { ret = 0; } - +#endif mbedtls_free(p_common_buff_32); return ret; @@ -460,7 +561,6 @@ int mbedtls_ecdsa_verify (mbedtls_ecp_group * grp, ECDSA_VALIDATE_RET(buf != NULL || blen == 0); int ret; - uint32_t * p_curve_params_buff_32; uint32_t * p_public_key_buff_32; uint32_t * p_signature_buff_32; uint32_t * p_common_buff_32; @@ -488,7 +588,70 @@ int mbedtls_ecdsa_verify (mbedtls_ecp_group * grp, { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; } +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + /* Obtain a 32-bit aligned block of memory. It will be used for all the following items in this order: + * Public Key (Q) of size curve_bytes * 2 + * Signature (rs) of size curve_bytes * 2 + * Padded/truncated 32-bit aligned copy of input hash of size curve_bytes */ + p_common_buff_32 = mbedtls_calloc(((curve_bytes * 5) / 4), sizeof(uint32_t)); + + if (NULL == p_common_buff_32) + { + return MBEDTLS_ERR_ECP_ALLOC_FAILED; + } + + p_public_key_buff_32 = p_common_buff_32; + p_signature_buff_32 = p_public_key_buff_32 + ((curve_bytes * 2) / 4); + /* The hash input (buf) should have a length of at least the curve size: + * nist.fips.186-4: " A hash function that provides a lower security strength than + * the security strength associated with the bit length of 'n' ordinarily should not be used, since this + * would reduce the security strength of the digital signature process to a level no greater than that + * provided by the hash function." + * However, the SCE HW functions only parse hash of exactly curve_bytes length so + * *-Any larger hash data will be truncated. + * *-Any smaller data will be 0-padded to the LEFT. + * + * Even if the hash input is the same size as the curve, we will still do a copy because the user input + * is an 8-bit pointer whereas the SCE HW expects a 32-bit pointer and there could possibly be + * an alignment issue. */ + p_buf_8 = (uint8_t *) (p_signature_buff_32 + ((curve_bytes * 2) / 4)); + uint32_t bytes_to_copy = blen > curve_bytes ? curve_bytes : blen; + memcpy(p_buf_8 + (curve_bytes - bytes_to_copy), buf, bytes_to_copy); + + uint32_t curve_type; + uint32_t cmd; + ret = ecp_load_curve_attributes_sce(grp, &curve_type, &cmd, NULL); + if (ret) + { + } + else if (0 != mbedtls_mpi_write_binary(&Q->X, (uint8_t *) p_public_key_buff_32, curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL; + } + else if (0 != mbedtls_mpi_write_binary(&Q->Y, (uint8_t *) (p_public_key_buff_32 + (curve_bytes / 4)), curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL; + } + else if (0 != mbedtls_mpi_write_binary(r, (uint8_t *) p_signature_buff_32, curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL; + } + else if (0 != mbedtls_mpi_write_binary(s, (uint8_t *) (p_signature_buff_32 + (curve_bytes / 4)), curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL; + } + else + { + if (FSP_SUCCESS != + p_hw_sce_ecc_verifysign(&curve_type, &cmd, + p_public_key_buff_32, (uint32_t *) p_buf_8, p_signature_buff_32, + p_signature_buff_32 + (curve_bytes / 4))) + { + ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; + } + } +#else /* Obtain a 32-bit aligned block of memory. It will be used for all the following items in this order: * Curve parameters a, b, p, n, Gx, Gy. Each of the 6 fields are of size curve_bytes = PSA_BITS_TO_BYTES( ecp->grp.pbits ) * Public Key (Q) of size curve_bytes * 2 @@ -501,7 +664,7 @@ int mbedtls_ecdsa_verify (mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_ALLOC_FAILED; } - p_curve_params_buff_32 = p_common_buff_32; + uint32_t * p_curve_params_buff_32 = p_common_buff_32; p_public_key_buff_32 = p_curve_params_buff_32 + ((curve_bytes * 6) / 4); p_signature_buff_32 = p_public_key_buff_32 + ((curve_bytes * 2) / 4); @@ -551,7 +714,7 @@ int mbedtls_ecdsa_verify (mbedtls_ecp_group * grp, ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; } } - +#endif mbedtls_free(p_common_buff_32); return ret; diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c index ef0af07a9..14f2cb400 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c @@ -81,6 +81,7 @@ #include "mbedtls/ecp_internal.h" #include "psa/crypto.h" + #include "hw_sce_private.h" static const hw_sce_ecc_generatekey_t g_ecp_keygen_lookup[][2] = { @@ -107,36 +108,65 @@ static const hw_sce_ecc_generatekey_t g_ecp_keygen_lookup[][2] = #endif }; + #if !BSP_FEATURE_CRYPTO_HAS_SCE9 static const hw_sce_ecc_scalarmultiplication_t g_ecp_scalar_multiplication_lookup[][2] = { - #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ + #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) - #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_256_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = HW_SCE_ECC_256ScalarMultiplication, - #endif - #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_256_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = HW_SCE_ECC_256HrkScalarMultiplication, + #endif #endif - #endif - #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) - #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = HW_SCE_ECC_384ScalarMultiplication, - #endif - #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = HW_SCE_ECC_384HrkScalarMultiplication, + #endif + #endif +}; + #else + +static const hw_sce_ecc_scalarmultiplication_t g_ecp_scalar_multiplication_lookup[][2] = +{ + #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_256_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_256WrappedScalarMultiplication, + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_256_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_256WrappedScalarMultiplication, + #endif + #endif + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT] = + HW_SCE_ECC_384WrappedScalarMultiplication, + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_ECC_FORMAT) + [RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(ECC_384_PRIVATE_KEY_LENGTH_BITS)][RM_PSA_CRYPTO_ECC_KEY_WRAPPED] = + HW_SCE_ECC_384WrappedScalarMultiplication, + #endif #endif - #endif }; + #endif /* * Generate a private key */ extern int ecp_load_parameters_sce(const mbedtls_ecp_group * grp, uint8_t * p_curve_params_buff); extern int ecp_can_do_sce(mbedtls_ecp_group_id gid); +extern int ecp_load_curve_attributes_sce(const mbedtls_ecp_group * grp, uint32_t * p_curve_type, uint32_t * p_cmd, sce_oem_cmd_t * oem_priv_cmd); uint32_t ecp_load_key_size(bool wrapped_mode_ctx, const mbedtls_ecp_group * grp); @@ -195,7 +225,6 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, ECP_VALIDATE_RET(grp != NULL); ECP_VALIDATE_RET(d != NULL); - uint32_t * p_curve_params_buff_32; uint32_t * p_public_key_buff_32; uint32_t * p_private_key_buff_32; uint32_t * p_common_buff_32; @@ -230,7 +259,46 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, } size_t curve_bytes = PSA_BITS_TO_BYTES(grp->pbits); +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: + * Private Key (D) of size private_key_size_words + * Public Key (Q) of size ECC_PUBLIC_KEY_SIZE_BYTES */ + p_common_buff_32 = mbedtls_calloc((ECC_PUBLIC_KEY_SIZE_BYTES(curve_bytes) / 4) + private_key_size_words, sizeof(uint32_t)); + + if (NULL == p_common_buff_32) + { + return MBEDTLS_ERR_ECP_ALLOC_FAILED; + } + p_private_key_buff_32 = p_common_buff_32; + p_public_key_buff_32 = p_private_key_buff_32 + private_key_size_words; + + uint32_t curve_type; + uint32_t cmd; + ret = ecp_load_curve_attributes_sce(grp, &curve_type, &cmd, NULL); + if (ret) + { + } + /* Public key generated within p_public_key_buff_32 is unused. + * The caller, if needed, generates the public key using scalar multiply + * */ + else if (FSP_SUCCESS != + p_hw_sce_ecc_generatekey(&curve_type, &cmd, p_private_key_buff_32, p_public_key_buff_32)) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + else if (0 != + mbedtls_mpi_read_binary(d, (uint8_t *) p_private_key_buff_32, private_key_size_words * 4)) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + } + else + { + ret = 0; + } + /* Clear out the allocated buffer */ + memset(p_common_buff_32, 0, (ECC_PUBLIC_KEY_SIZE_BYTES(curve_bytes) + (private_key_size_words * 4))); +#else /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: * Curve parameters a, b, p, n, Gx, Gy. Each of the 6 fields are of size curve_bytes = PSA_BITS_TO_BYTES( ecp->grp.pbits ) * Private Key (D) of size private_key_size_words @@ -242,7 +310,7 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_ALLOC_FAILED; } - p_curve_params_buff_32 = p_common_buff_32; + uint32_t * p_curve_params_buff_32 = p_common_buff_32; p_private_key_buff_32 = p_curve_params_buff_32 + ((curve_bytes * 6) / 4); p_public_key_buff_32 = p_private_key_buff_32 + private_key_size_words; @@ -268,7 +336,7 @@ int mbedtls_ecp_gen_privkey (const mbedtls_ecp_group * grp, /* Clear out the allocated buffer */ memset(p_common_buff_32, 0, ((curve_bytes * 8) + (private_key_size_words * 4))); - +#endif mbedtls_free(p_common_buff_32); return ret; @@ -292,15 +360,13 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, ECP_VALIDATE_RET(P != NULL); int ret = 0; - fsp_err_t err; + fsp_err_t err = FSP_SUCCESS; hw_sce_ecc_scalarmultiplication_t p_hw_sce_ecc_scalarmultiplication = NULL; - uint32_t * p_curve_params_buff_32; uint32_t * p_point_buff_P_32; uint32_t * p_integer_buff_m_32; uint32_t * p_point_result_buff_R_32; uint32_t * p_common_buff_32; - uint32_t integer_size_words = 0; /* Fail cleanly on curves that HW doesn't support. * Fail if the point co-ordinates are in Jacobian format (only Affine is supported). @@ -317,14 +383,109 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, { return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; } + + size_t curve_bytes = PSA_BITS_TO_BYTES(grp->pbits); - integer_size_words = ecp_load_key_size((bool) grp->vendor_ctx, grp); - if (0 == integer_size_words) +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + /* Scalar multiply only accepts wrapped scalars. */ + uint32_t m_size_wrapped_words = ecp_load_key_size((bool) true, grp); + if (0 == m_size_wrapped_words) { return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; } - size_t curve_bytes = PSA_BITS_TO_BYTES(grp->pbits); + uint32_t m_size_words = ecp_load_key_size((bool) grp->vendor_ctx, grp); + if (0 == m_size_words) + { + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + + /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: + * Multiplication point (P) of size curve_bytes * 2 in format (Px|Py) + * Multiplication result (R) of size curve_bytes * 2 in format (Rx|Ry) + * Input scalar (m) of size m_size_words + * Input wrapped scalar (m) of size m_size_wrapped_words */ + p_common_buff_32 = mbedtls_calloc(((curve_bytes * 4) / 4) + m_size_wrapped_words + m_size_words, sizeof(uint32_t)); + + if (NULL == p_common_buff_32) + { + return MBEDTLS_ERR_ECP_ALLOC_FAILED; + } + + p_point_buff_P_32 = p_common_buff_32; + p_point_result_buff_R_32 = p_point_buff_P_32 + ((curve_bytes * 2) / 4); + p_integer_buff_m_32 = p_point_result_buff_R_32 + ((curve_bytes * 2) / 4); + uint32_t * p_integer_buff_m_wrapped_32 = p_integer_buff_m_32 + m_size_words; + + uint32_t curve_type; + uint32_t cmd; + sce_oem_cmd_t oem_cmd; + ret = ecp_load_curve_attributes_sce(grp, &curve_type, &cmd, &oem_cmd); + if (0 == ret) + { + ret = mbedtls_mpi_write_binary(m, (uint8_t *) p_integer_buff_m_32, m_size_words * 4); + } + if (m_size_words != m_size_wrapped_words) + { + + /* Install the plaintext private key to get the wrapped private key */ + err = HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + oem_cmd, + NULL, + NULL, + (const uint8_t *)p_integer_buff_m_32, + p_integer_buff_m_wrapped_32); + } + else + { + memcpy(p_integer_buff_m_wrapped_32, p_integer_buff_m_32, m_size_wrapped_words * 4); + } + if ((FSP_SUCCESS != err) || (0 != ret)) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + /* Write Px into the buffer in reverse */ + else if (0 != + mbedtls_mpi_write_binary(&P->X, (uint8_t *) p_point_buff_P_32, curve_bytes)) + { + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + } + /* Write Py into the buffer in reverse */ + else if (0 != + mbedtls_mpi_write_binary(&P->Y, (uint8_t *) (p_point_buff_P_32 + ((curve_bytes) / 4)), curve_bytes)) + { + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + } + else if (FSP_SUCCESS != + p_hw_sce_ecc_scalarmultiplication(&curve_type, + &cmd, + p_integer_buff_m_wrapped_32, + p_point_buff_P_32, + p_point_result_buff_R_32)) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + else if (0 != + mbedtls_mpi_read_binary(&R->X, (uint8_t *) p_point_result_buff_R_32, curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + } + else if (0 != + mbedtls_mpi_read_binary(&R->Y, (uint8_t *) (p_point_result_buff_R_32 + ((curve_bytes) / 4)), + curve_bytes)) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + } + else + { + ret = 0; + } +#else + uint32_t integer_size_words = ecp_load_key_size((bool) grp->vendor_ctx, grp); + if (0 == integer_size_words) + { + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } /* Obtain a common 32-bit aligned buffer. It will be used for all the following items in this order: * Curve parameters a, b, p, n, Gx, Gy. Each of the 6 fields are of size curve_bytes = PSA_BITS_TO_BYTES( ecp->grp.pbits ) @@ -338,7 +499,7 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, return MBEDTLS_ERR_ECP_ALLOC_FAILED; } - p_curve_params_buff_32 = p_common_buff_32; + uint32_t * p_curve_params_buff_32 = p_common_buff_32; p_point_buff_P_32 = p_curve_params_buff_32 + ((curve_bytes * 6) / 4); p_point_result_buff_R_32 = p_point_buff_P_32 + ((curve_bytes * 2) / 4); p_integer_buff_m_32 = p_point_result_buff_R_32 + ((curve_bytes * 2) / 4); @@ -392,6 +553,7 @@ int mbedtls_ecp_mul_restartable (mbedtls_ecp_group * grp, ret = 0; } } +#endif /* * For Affine format, copy the input Z value to the output. diff --git a/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h b/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h index eccf77e5b..8d6673bec 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h @@ -23,7 +23,7 @@ extern "C" { #endif -#if defined(MBEDTLS_AES_ALT) +#if defined(MBEDTLS_AES_ALT) || defined(MBEDTLS_CTR_DRBG_C_ALT) /** * \brief The AES context-type definition. @@ -42,7 +42,8 @@ extern "C" *

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    • */ void *vendor_ctx; /*!< Vendor defined context. */ } mbedtls_aes_context; - +#endif +#if defined(MBEDTLS_AES_ALT) #if defined(MBEDTLS_CIPHER_MODE_XTS) /** diff --git a/ra/fsp/src/rm_psa_crypto/inc/asymmetric_vendor.h b/ra/fsp/src/rm_psa_crypto/inc/asymmetric_vendor.h index efe32edac..65844369c 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/asymmetric_vendor.h +++ b/ra/fsp/src/rm_psa_crypto/inc/asymmetric_vendor.h @@ -63,26 +63,6 @@ psa_status_t psa_ecdsa_verify(mbedtls_ecp_keypair * ecp, size_t hash_length, const uint8_t * signature, size_t signature_length); -psa_status_t psa_import_rsa_key(psa_key_type_t type, - const uint8_t * data, - size_t data_length, - mbedtls_rsa_context ** p_rsa); -psa_status_t psa_read_rsa_exponent(const uint8_t * domain_parameters, - size_t domain_parameters_size, - int * exponent); -psa_status_t psa_rsa_sign(mbedtls_rsa_context * rsa, - psa_algorithm_t alg, - const uint8_t * hash, - size_t hash_length, - uint8_t * signature, - size_t signature_size, - size_t * signature_length); -psa_status_t psa_rsa_verify(mbedtls_rsa_context * rsa, - psa_algorithm_t alg, - const uint8_t * hash, - size_t hash_length, - const uint8_t * signature, - size_t signature_length); /* Functions to support vendor defined format */ psa_status_t psa_import_ec_private_key_vendor(psa_ecc_curve_t curve, @@ -104,4 +84,26 @@ int ecp_gen_key_vendor(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair * key); #endif /* MBEDTLS_ECP_ALT */ +#if defined(MBEDTLS_RSA_ALT) +psa_status_t psa_import_rsa_key(psa_key_type_t type, + const uint8_t * data, + size_t data_length, + mbedtls_rsa_context ** p_rsa); +psa_status_t psa_read_rsa_exponent(const uint8_t * domain_parameters, size_t domain_parameters_size, int * exponent); +psa_status_t psa_rsa_sign(mbedtls_rsa_context * rsa, + psa_algorithm_t alg, + const uint8_t * hash, + size_t hash_length, + uint8_t * signature, + size_t signature_size, + size_t * signature_length); +psa_status_t psa_rsa_verify(mbedtls_rsa_context * rsa, + psa_algorithm_t alg, + const uint8_t * hash, + size_t hash_length, + const uint8_t * signature, + size_t signature_length); + +#endif /* MBEDTLS_RSA_ALT */ + #endif /* ASYMMETRIC_VENDOR_H */ diff --git a/ra/fsp/src/rm_psa_crypto/inc/ctr_drbg_alt.h b/ra/fsp/src/rm_psa_crypto/inc/ctr_drbg_alt.h new file mode 100644 index 000000000..85ef7c53b --- /dev/null +++ b/ra/fsp/src/rm_psa_crypto/inc/ctr_drbg_alt.h @@ -0,0 +1,575 @@ +/** + * \file ctr_drbg_alt.h + * + * \brief This file contains definitions and functions for the + * CTR_DRBG pseudorandom generator. + * + * CTR_DRBG is a standardized way of building a PRNG from a block-cipher + * in counter mode operation, as defined in NIST SP 800-90A: + * Recommendation for Random Number Generation Using Deterministic Random + * Bit Generators. + * + * The Mbed TLS implementation of CTR_DRBG uses AES-256 (default) or AES-128 + * (if \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled at compile time) + * as the underlying block cipher, with a derivation function. + * + * The security strength as defined in NIST SP 800-90A is + * 128 bits when AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled) + * and 256 bits otherwise, provided that MBEDTLS_CTR_DRBG_ENTROPY_LEN is + * kept at its default value (and not overridden in config.h) and that the + * DRBG instance is set up with default parameters. + * See the documentation of mbedtls_ctr_drbg_seed() for more + * information. + */ + +/* + * Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +#ifndef MBEDTLS_CTR_DRBG_ALT_H + #define MBEDTLS_CTR_DRBG_ALT_H + + #if !defined(MBEDTLS_CONFIG_FILE) + #include "mbedtls/config.h" + #else + #include MBEDTLS_CONFIG_FILE + #endif + + #include "aes_alt.h" + + #if defined(MBEDTLS_THREADING_C) + #include "mbedtls/threading.h" + #endif + + #define MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED -0x0034 /**< The entropy source failed. */ + #define MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG -0x0036 /**< The requested random buffer length is too big. */ + #define MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG -0x0038 /**< The input (entropy + additional data) is too large. */ + #define MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR -0x003A /**< Read or write error in file. */ + + #define MBEDTLS_CTR_DRBG_BLOCKSIZE 16 /**< The block size used by the cipher. */ + + #if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) + #define MBEDTLS_CTR_DRBG_KEYSIZE 16 + +/**< The key size in bytes used by the cipher. + * + * Compile-time choice: 16 bytes (128 bits) + * because #MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled. + */ + #else + #define MBEDTLS_CTR_DRBG_KEYSIZE 32 + +/**< The key size in bytes used by the cipher. + * + * Compile-time choice: 32 bytes (256 bits) + * because \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled. + */ + #endif + + #define MBEDTLS_CTR_DRBG_KEYBITS (MBEDTLS_CTR_DRBG_KEYSIZE * 8) /**< The key size for the DRBG operation, in bits. */ + #define MBEDTLS_CTR_DRBG_SEEDLEN (MBEDTLS_CTR_DRBG_KEYSIZE + MBEDTLS_CTR_DRBG_BLOCKSIZE) /**< The seed length, calculated as (counter + AES key). */ + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h or define them using the compiler command + * line. + * \{ + */ + +/** \def MBEDTLS_CTR_DRBG_ENTROPY_LEN + * + * \brief The amount of entropy used per seed by default, in bytes. + */ + #if !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) + #if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) + +/** This is 48 bytes because the entropy module uses SHA-512 + * (\c MBEDTLS_ENTROPY_FORCE_SHA256 is disabled). + */ + #define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 + + #else /* defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) */ + +/** This is 32 bytes because the entropy module uses SHA-256 + * (the SHA512 module is disabled or + * \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled). + */ + #if !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) + +/** \warning To achieve a 256-bit security strength, you must pass a nonce + * to mbedtls_ctr_drbg_seed(). + */ + #endif /* !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) */ + #define MBEDTLS_CTR_DRBG_ENTROPY_LEN 32 + #endif /* defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) */ + #endif /* !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) */ + + #if !defined(MBEDTLS_CTR_DRBG_RESEED_INTERVAL) + #define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 + +/**< The interval before reseed is performed by default. */ + #endif + + #if !defined(MBEDTLS_CTR_DRBG_MAX_INPUT) + #define MBEDTLS_CTR_DRBG_MAX_INPUT 256 + +/**< The maximum number of additional input Bytes. */ + #endif + + #if !defined(MBEDTLS_CTR_DRBG_MAX_REQUEST) + #define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 + +/**< The maximum number of requested Bytes per call. */ + #endif + + #if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) + #define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 + +/**< The maximum size of seed or reseed buffer in bytes. */ + #endif + +/* \} name SECTION: Module settings */ + + #define MBEDTLS_CTR_DRBG_PR_OFF 0 + +/**< Prediction resistance is disabled. */ + #define MBEDTLS_CTR_DRBG_PR_ON 1 + +/**< Prediction resistance is enabled. */ + + #ifdef __cplusplus +extern "C" { + #endif + + #if MBEDTLS_CTR_DRBG_ENTROPY_LEN >= MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + +/** The default length of the nonce read from the entropy source. + * + * This is \c 0 because a single read from the entropy source is sufficient + * to include a nonce. + * See the documentation of mbedtls_ctr_drbg_seed() for more information. + */ + #define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN 0 + #else + +/** The default length of the nonce read from the entropy source. + * + * This is half of the default entropy length because a single read from + * the entropy source does not provide enough material to form a nonce. + * See the documentation of mbedtls_ctr_drbg_seed() for more information. + */ + #define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN (MBEDTLS_CTR_DRBG_ENTROPY_LEN + 1) / 2 + #endif + +/** + * \brief The CTR_DRBG context structure. + */ +typedef struct mbedtls_ctr_drbg_context +{ + unsigned char counter[16]; /*!< The counter (V). */ + int reseed_counter; /*!< The reseed counter. + * This is the number of requests that have + * been made since the last (re)seeding, + * minus one. + * Before the initial seeding, this field + * contains the amount of entropy in bytes + * to use as a nonce for the initial seeding, + * or -1 if no nonce length has been explicitly + * set (see mbedtls_ctr_drbg_set_nonce_len()). + */ + int prediction_resistance; /*!< This determines whether prediction + * resistance is enabled, that is + * whether to systematically reseed before + * each random generation. */ + size_t entropy_len; /*!< The amount of entropy grabbed on each + * seed or reseed operation, in bytes. */ + int reseed_interval; /*!< The reseed interval. + * This is the maximum number of requests + * that can be made between reseedings. */ + + mbedtls_aes_context aes_ctx; /*!< The AES context. */ + + /* + * Callbacks (Entropy) + */ + int (* f_entropy)(void *, unsigned char *, size_t); + + /*!< The entropy callback function. */ + + void * p_entropy; /*!< The context for the entropy function. */ + + #if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t mutex; + #endif +} mbedtls_ctr_drbg_context; + +/** + * \brief This function initializes the CTR_DRBG context, + * and prepares it for mbedtls_ctr_drbg_seed() + * or mbedtls_ctr_drbg_free(). + * + * \param ctx The CTR_DRBG context to initialize. + */ +void mbedtls_ctr_drbg_init(mbedtls_ctr_drbg_context * ctx); + +/** + * \brief This function seeds and sets up the CTR_DRBG + * entropy source for future reseeds. + * + * A typical choice for the \p f_entropy and \p p_entropy parameters is + * to use the entropy module: + * - \p f_entropy is mbedtls_entropy_func(); + * - \p p_entropy is an instance of mbedtls_entropy_context initialized + * with mbedtls_entropy_init() (which registers the platform's default + * entropy sources). + * + * The entropy length is MBEDTLS_CTR_DRBG_ENTROPY_LEN by default. + * You can override it by calling mbedtls_ctr_drbg_set_entropy_len(). + * + * The entropy nonce length is: + * - \c 0 if the entropy length is at least 3/2 times the entropy length, + * which guarantees that the security strength is the maximum permitted + * by the key size and entropy length according to NIST SP 800-90A §10.2.1; + * - Half the entropy length otherwise. + * You can override it by calling mbedtls_ctr_drbg_set_nonce_len(). + * With the default entropy length, the entropy nonce length is + * MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN. + * + * You can provide a nonce and personalization string in addition to the + * entropy source, to make this instantiation as unique as possible. + * See SP 800-90A §8.6.7 for more details about nonces. + * + * The _seed_material_ value passed to the derivation function in + * the CTR_DRBG Instantiate Process described in NIST SP 800-90A §10.2.1.3.2 + * is the concatenation of the following strings: + * - A string obtained by calling \p f_entropy function for the entropy + * length. + */ + #if MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN == 0 + +/** + * - If mbedtls_ctr_drbg_set_nonce_len() has been called, a string + * obtained by calling \p f_entropy function for the specified length. + */ + #else + +/** + * - A string obtained by calling \p f_entropy function for the entropy nonce + * length. If the entropy nonce length is \c 0, this function does not + * make a second call to \p f_entropy. + */ + #endif + +/** + * - The \p custom string. + * + * \note To achieve the nominal security strength permitted + * by CTR_DRBG, the entropy length must be: + * - at least 16 bytes for a 128-bit strength + * (maximum achievable strength when using AES-128); + * - at least 32 bytes for a 256-bit strength + * (maximum achievable strength when using AES-256). + * + * In addition, if you do not pass a nonce in \p custom, + * the sum of the entropy length + * and the entropy nonce length must be: + * - at least 24 bytes for a 128-bit strength + * (maximum achievable strength when using AES-128); + * - at least 48 bytes for a 256-bit strength + * (maximum achievable strength when using AES-256). + * + * \param ctx The CTR_DRBG context to seed. + * It must have been initialized with + * mbedtls_ctr_drbg_init(). + * After a successful call to mbedtls_ctr_drbg_seed(), + * you may not call mbedtls_ctr_drbg_seed() again on + * the same context unless you call + * mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init() + * again first. + * \param f_entropy The entropy callback, taking as arguments the + * \p p_entropy context, the buffer to fill, and the + * length of the buffer. + * \p f_entropy is always called with a buffer size + * less than or equal to the entropy length. + * \param p_entropy The entropy context to pass to \p f_entropy. + * \param custom The personalization string. + * This can be \c NULL, in which case the personalization + * string is empty regardless of the value of \p len. + * \param len The length of the personalization string. + * This must be at most + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * - MBEDTLS_CTR_DRBG_ENTROPY_LEN. + * + * \return \c 0 on success. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. + */ +int mbedtls_ctr_drbg_seed(mbedtls_ctr_drbg_context * ctx, + int (* f_entropy)(void *, unsigned char *, size_t), + void * p_entropy, + const unsigned char * custom, + size_t len); + +/** + * \brief This function clears CTR_CRBG context data. + * + * \param ctx The CTR_DRBG context to clear. + */ +void mbedtls_ctr_drbg_free(mbedtls_ctr_drbg_context * ctx); + +/** + * \brief This function turns prediction resistance on or off. + * The default value is off. + * + * \note If enabled, entropy is gathered at the beginning of + * every call to mbedtls_ctr_drbg_random_with_add() + * or mbedtls_ctr_drbg_random(). + * Only use this if your entropy source has sufficient + * throughput. + * + * \param ctx The CTR_DRBG context. + * \param resistance MBEDTLS_CTR_DRBG_PR_ON or MBEDTLS_CTR_DRBG_PR_OFF. + */ +void mbedtls_ctr_drbg_set_prediction_resistance(mbedtls_ctr_drbg_context * ctx, int resistance); + +/** + * \brief This function sets the amount of entropy grabbed on each + * seed or reseed. + * + * The default value is MBEDTLS_CTR_DRBG_ENTROPY_LEN. + * + * \note The security strength of CTR_DRBG is bounded by the + * entropy length. Thus: + * - When using AES-256 + * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled, + * which is the default), + * \p len must be at least 32 (in bytes) + * to achieve a 256-bit strength. + * - When using AES-128 + * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled) + * \p len must be at least 16 (in bytes) + * to achieve a 128-bit strength. + * + * \param ctx The CTR_DRBG context. + * \param len The amount of entropy to grab, in bytes. + * This must be at most MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * and at most the maximum length accepted by the + * entropy function that is set in the context. + */ +void mbedtls_ctr_drbg_set_entropy_len(mbedtls_ctr_drbg_context * ctx, size_t len); + +/** + * \brief This function sets the amount of entropy grabbed + * as a nonce for the initial seeding. + * + * Call this function before calling mbedtls_ctr_drbg_seed() to read + * a nonce from the entropy source during the initial seeding. + * + * \param ctx The CTR_DRBG context. + * \param len The amount of entropy to grab for the nonce, in bytes. + * This must be at most MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * and at most the maximum length accepted by the + * entropy function that is set in the context. + * + * \return \c 0 on success. + * \return MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if \p len is + * more than MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED + * if the initial seeding has already taken place. + */ +int mbedtls_ctr_drbg_set_nonce_len(mbedtls_ctr_drbg_context * ctx, size_t len); + +/** + * \brief This function sets the reseed interval. + * + * The reseed interval is the number of calls to mbedtls_ctr_drbg_random() + * or mbedtls_ctr_drbg_random_with_add() after which the entropy function + * is called again. + * + * The default value is MBEDTLS_CTR_DRBG_RESEED_INTERVAL. + * + * \param ctx The CTR_DRBG context. + * \param interval The reseed interval. + */ +void mbedtls_ctr_drbg_set_reseed_interval(mbedtls_ctr_drbg_context * ctx, int interval); + +/** + * \brief This function reseeds the CTR_DRBG context, that is + * extracts data from the entropy source. + * + * \param ctx The CTR_DRBG context. + * \param additional Additional data to add to the state. Can be \c NULL. + * \param len The length of the additional data. + * This must be less than + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * configured for the context. + * + * \return \c 0 on success. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. + */ +int mbedtls_ctr_drbg_reseed(mbedtls_ctr_drbg_context * ctx, const unsigned char * additional, size_t len); + +/** + * \brief This function updates the state of the CTR_DRBG context. + * + * \param ctx The CTR_DRBG context. + * \param additional The data to update the state with. This must not be + * \c NULL unless \p add_len is \c 0. + * \param add_len Length of \p additional in bytes. This must be at + * most MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * + * \return \c 0 on success. + * \return MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if + * \p add_len is more than + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * \return An error from the underlying AES cipher on failure. + */ +int mbedtls_ctr_drbg_update_ret(mbedtls_ctr_drbg_context * ctx, const unsigned char * additional, size_t add_len); + +/** + * \brief This function updates a CTR_DRBG instance with additional + * data and uses it to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + * + * \param p_rng The CTR_DRBG context. This must be a pointer to a + * #mbedtls_ctr_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * \param additional Additional data to update. Can be \c NULL, in which + * case the additional data is empty regardless of + * the value of \p add_len. + * \param add_len The length of the additional data + * if \p additional is not \c NULL. + * This must be less than MBEDTLS_CTR_DRBG_MAX_INPUT + * and less than + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * configured for the context. + * + * \return \c 0 on success. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or + * MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. + */ +int mbedtls_ctr_drbg_random_with_add(void * p_rng, + unsigned char * output, + size_t output_len, + const unsigned char * additional, + size_t add_len); + +/** + * \brief This function uses CTR_DRBG to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + * + * + * \param p_rng The CTR_DRBG context. This must be a pointer to a + * #mbedtls_ctr_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * + * \return \c 0 on success. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or + * MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. + */ +int mbedtls_ctr_drbg_random(void * p_rng, unsigned char * output, size_t output_len); + + #if !defined(MBEDTLS_DEPRECATED_REMOVED) + #if defined(MBEDTLS_DEPRECATED_WARNING) + #define MBEDTLS_DEPRECATED __attribute__((deprecated)) + #else + #define MBEDTLS_DEPRECATED + #endif + +/** + * \brief This function updates the state of the CTR_DRBG context. + * + * \deprecated Superseded by mbedtls_ctr_drbg_update_ret() + * in 2.16.0. + * + * \note If \p add_len is greater than + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT, only the first + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT Bytes are used. + * The remaining Bytes are silently discarded. + * + * \param ctx The CTR_DRBG context. + * \param additional The data to update the state with. + * \param add_len Length of \p additional data. + */ +MBEDTLS_DEPRECATED void mbedtls_ctr_drbg_update(mbedtls_ctr_drbg_context * ctx, + const unsigned char * additional, + size_t add_len); + + #undef MBEDTLS_DEPRECATED + #endif /* !MBEDTLS_DEPRECATED_REMOVED */ + + #if defined(MBEDTLS_FS_IO) + +/** + * \brief This function writes a seed file. + * + * \param ctx The CTR_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on reseed + * failure. + */ +int mbedtls_ctr_drbg_write_seed_file(mbedtls_ctr_drbg_context * ctx, const char * path); + +/** + * \brief This function reads and updates a seed file. The seed + * is added to this instance. + * + * \param ctx The CTR_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. + * \return MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on + * reseed failure. + * \return MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if the existing + * seed file is too large. + */ +int mbedtls_ctr_drbg_update_seed_file(mbedtls_ctr_drbg_context * ctx, const char * path); + + #endif /* MBEDTLS_FS_IO */ + + #if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The CTR_DRBG checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ctr_drbg_self_test(int verbose); + + #endif /* MBEDTLS_SELF_TEST */ +void sw_aes_256_enc_test(void); + + #ifdef __cplusplus +} + #endif + +#endif /* ctr_drbg.h */ diff --git a/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h b/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h index 25c27c452..45e0ca000 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/ecp_alt.h @@ -34,7 +34,6 @@ // Alternate implementation // - #define RM_PSA_CRYPTO_ECP_LOOKUP_INDEX(bits) ((bits >> 7) & (1U)) #define RM_PSA_CRYPTO_ECC_KEY_PLAINTEXT (0U) #define RM_PSA_CRYPTO_ECC_KEY_WRAPPED (1U) diff --git a/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h b/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h index b1c8f6f43..2cc31a47f 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/rsa_alt.h @@ -34,6 +34,47 @@ // Alternate implementation // + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + +/** Return RSA wrapped private key size in bytes from the specified RSA modulus size in bits. + * This is the size of sce_rsa2048_private_key_index_t. + */ + #define RSA_WRAPPED_PRIVATE_KEY_SIZE_BYTES(RSA_SIZE_BITS) ((RSA_SIZE_BITS / 8U) + 532U) + +/** Return size of any additional info generated by HW for the specified RSA modulus size in bits + * This is the size of everything in sce_rsa2048_public_key_index_t other than public key N + */ + #define RSA_ADDITIONAL_KEY_INFO_SIZE_BYTES(RSA_SIZE_BITS) ((1U * 4U) + 4U + 12U + (68U * 4U)) + +/** Return RSA public key size in bytes from the specified RSA modulus size in bits. + * This is the size of sce_rsa2048_public_key_index_t. + */ + #define RSA_WRAPPED_PUBLIC_KEY_SIZE_BYTES(RSA_SIZE_BITS) (((RSA_SIZE_BITS) / 8U) + \ + RSA_ADDITIONAL_KEY_INFO_SIZE_BYTES) + +/** Return RSA CRT private key size in bytes from the specified RSA modulus size in bits */ + #define RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(RSA_SIZE_BITS) (0U) + +/** Return RSA domain parameter size in bytes from the specified RSA modulus size in bits. + * This is not provided, but dummy values are used since mbedCrypto requires some values + * in Q and P in order to export them. + */ + #define RSA_PARAMETERS_SIZE_BYTES(RSA_SIZE_BITS) (5U) + + #else + +/** Return RSA wrapped private key size in bytes from the specified RSA modulus size in bits */ + #define RSA_WRAPPED_PRIVATE_KEY_SIZE_BYTES(RSA_SIZE_BITS) ((((uint32_t) RSA_SIZE_BITS) + (uint32_t) 160) / 8U) + +/** Return RSA CRT private key size in bytes from the specified RSA modulus size in bits */ + #define RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(RSA_SIZE_BITS) (((uint32_t) 5 * ((uint32_t) RSA_SIZE_BITS)) / 16U) + +/** Return size of any additional info generated by HW for the specified RSA modulus size in bits */ + #define RSA_ADDITIONAL_KEY_INFO_SIZE_BYTES(RSA_SIZE_BITS) RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(RSA_SIZE_BITS) + +/** Return RSA domain parameter size in bytes from the specified RSA modulus size in bits */ + #define RSA_PARAMETERS_SIZE_BYTES(RSA_SIZE_BITS) (((RSA_SIZE_BITS) / 8U) / 2) + #endif // BSP_FEATURE_CRYPTO_HAS_SCE9 /** Return RSA modulus size in bytes from the specified RSA modulus size in bits */ #define RSA_MODULUS_SIZE_BYTES(RSA_SIZE_BITS) ((RSA_SIZE_BITS) / 8U) @@ -44,12 +85,6 @@ /** Return RSA private key size in bytes from the specified RSA modulus size in bits */ #define RSA_PLAIN_TEXT_PRIVATE_KEY_SIZE_BYTES(RSA_SIZE_BITS) (((uint32_t) 2 * (uint32_t) RSA_SIZE_BITS) / 8U) -/** Return RSA CRT private key size in bytes from the specified RSA modulus size in bits */ - #define RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(RSA_SIZE_BITS) (((uint32_t) 5 * ((uint32_t) RSA_SIZE_BITS)) / 16U) - -/** Return RSA wrapped private key size in bytes from the specified RSA modulus size in bits */ - #define RSA_WRAPPED_PRIVATE_KEY_SIZE_BYTES(RSA_SIZE_BITS) ((((uint32_t) RSA_SIZE_BITS) + (uint32_t) 160) / 8U) - /** Return RSA wrapped private CRT key size in bytes from the specified RSA modulus size in bits */ #define RSA_WRAPPPED_PRIVATE_CRT_KEY_SIZE_BYTES(RSA_SIZE_BITS) ((RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(RSA_SIZE_BITS)) + \ 20U) @@ -58,17 +93,20 @@ #define SCE_RSA_NUM_TRIES_10240 (10240U) // NIST FIPS 186-4 recommended value for 2048-bit key generation. #define SCE_RSA_NUM_TRIES_20480 (20480U) // Double the "NIST FIPS 186-4 recommended value for 2048-bit key generation" due to empirically observed periodic failure from HW implementation -/** Return RSA domain parameter size in bytes from the specified RSA modulus size in bits */ - #define RSA_PARAMETERS_SIZE_BYTES(RSA_SIZE_BITS) (((RSA_SIZE_BITS) / 8U) / 2) - /** RSA Public Exponent (E) in little endian form */ - #define RSA_PUBLIC_EXPONENT_LE (0x01000100) + #define RSA_PUBLIC_EXPONENT_LE (0x01000100) /** RSA Public Exponent (E) in big endian form */ - #define RSA_PUBLIC_EXPONENT_BE (0x00010001) + #define RSA_PUBLIC_EXPONENT_BE (0x00010001) /** RSA2048 bits */ - #define RSA_2048_BITS (2048) + #define RSA_2048_BITS (2048) + +/** RSA3072 bits */ + #define RSA_3072_BITS (3072) + +/** RSA4096 bits */ + #define RSA_4096_BITS (4096) /** * \brief The RSA context structure. diff --git a/ra/fsp/src/rm_psa_crypto/platform_alt.c b/ra/fsp/src/rm_psa_crypto/platform_alt.c index c2720012e..8f7946045 100644 --- a/ra/fsp/src/rm_psa_crypto/platform_alt.c +++ b/ra/fsp/src/rm_psa_crypto/platform_alt.c @@ -28,6 +28,13 @@ #include "platform.h" #include "hw_sce_private.h" + #if defined(CONFIG_MEDTLS_USE_AFR_MEMORY) && defined(MBEDTLS_PLATFORM_MEMORY) && \ + !(defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && defined(MBEDTLS_PLATFORM_FREE_MACRO)) +extern void * pvCalloc(size_t xNumElements, size_t xSize); +extern void vPortFree(void * pv); + + #endif + /*******************************************************************************************************************//** * @addtogroup RM_PSA_CRYPTO * @{ @@ -47,27 +54,14 @@ int mbedtls_platform_setup (mbedtls_platform_context * ctx) { (void) ctx; - uint32_t iret = FSP_ERR_CRYPTO_SCE_FAIL; - - // power on the SCE module - HW_SCE_PowerOn(); - - HW_SCE_SoftReset(); - iret = HW_SCE_Initialization1(); + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; - if (FSP_SUCCESS == iret) - { - iret = HW_SCE_Initialization2(); - if (FSP_SUCCESS == iret) - { - iret = HW_SCE_secureBoot(); - } - } + #if defined(CONFIG_MEDTLS_USE_AFR_MEMORY) && defined(MBEDTLS_PLATFORM_MEMORY) && \ + !(defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && defined(MBEDTLS_PLATFORM_FREE_MACRO)) + mbedtls_platform_set_calloc_free(pvCalloc, vPortFree); + #endif - if (FSP_SUCCESS == iret) - { - HW_SCE_EndianSetLittle(); - } + iret = HW_SCE_McuSpecificInit(); if (iret != FSP_SUCCESS) { diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c index a732a778d..8c0399991 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c @@ -104,9 +104,10 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, (void) f_rng; (void) p_rng; - uint8_t * p_rsa2048_domain_parameters_8 = NULL; - uint32_t * p_common_buff_32 = NULL; - uint32_t private_key_size_bytes = RSA_MODULUS_SIZE_BYTES(2048); + uint8_t * p_additional_key_info_8 = NULL; + uint32_t * p_common_buff_32 = NULL; + uint32_t private_key_size_bytes = RSA_MODULUS_SIZE_BYTES(2048); + uint32_t public_key_size_bytes = RSA_MODULUS_SIZE_BYTES(2048); #if defined(MBEDTLS_CHECK_PARAMS) @@ -129,9 +130,9 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, } /* Calloc pointers created to remove clang warnings */ - uint32_t * p_rsa_private_exponent = NULL; - uint32_t * p_rsa_public_modulus = NULL; - uint32_t * p_rsa2048_domain_parameters = NULL; + uint32_t * p_rsa_private_exponent = NULL; + uint32_t * p_rsa_public_modulus = NULL; + uint32_t * p_additional_key_info = NULL; hw_sce_rsa_generatekey_t p_hw_sce_rsa_generatekey = NULL; uint8_t rsa_public_exponent[4] = {0x00, 0x01, 0x00, 0x01}; @@ -143,12 +144,14 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, } /* Obtain a 32-bit aligned block of memory. It will be used for all the following items in this order: - * Private Key D of size private_key_size_bytes - * Public Modulus N of size RSA_MODULUS_SIZE_BYTES(x) - * CRT parameters Dq|Q|Dp|P|Qp each of size RSA_PARAMETERS_SIZE_BYTES(x) */ + * Private Key D of size private_key_size_bytes + * Public Modulus N of size public_key_size_bytes + * Any additional info: + * With old procedures: CRT parameters Dq|Q|Dp|P|Qp each of size RSA_PARAMETERS_SIZE_BYTES(x) + * With new procedures: none. */ p_common_buff_32 = (uint32_t *) mbedtls_calloc((private_key_size_bytes + - (RSA_MODULUS_SIZE_BYTES(2048) + RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(2048))) / 4, + (public_key_size_bytes + RSA_ADDITIONAL_KEY_INFO_SIZE_BYTES(2048))) / 4, sizeof(uint32_t)); if (NULL == p_common_buff_32) @@ -156,20 +159,22 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, return MBEDTLS_ERR_MPI_ALLOC_FAILED; } - p_rsa_private_exponent = p_common_buff_32; - p_rsa_public_modulus = p_rsa_private_exponent + (private_key_size_bytes / 4); - p_rsa2048_domain_parameters = p_rsa_public_modulus + (RSA_MODULUS_SIZE_BYTES(2048) / 4); - p_rsa2048_domain_parameters_8 = (uint8_t *) p_rsa2048_domain_parameters; + p_rsa_private_exponent = p_common_buff_32; + p_rsa_public_modulus = p_rsa_private_exponent + (private_key_size_bytes / 4); + p_additional_key_info = p_rsa_public_modulus + (public_key_size_bytes / 4); + p_additional_key_info_8 = (uint8_t *) p_additional_key_info; if (FSP_SUCCESS != p_hw_sce_rsa_generatekey(SCE_RSA_NUM_TRIES_20480, p_rsa_private_exponent, p_rsa_public_modulus, - p_rsa2048_domain_parameters)) + p_additional_key_info)) { ret = MBEDTLS_ERR_RSA_KEY_GEN_FAILED; } /* Copy the public key data into the context */ + else if (0 != - mbedtls_mpi_read_binary(&ctx->N, (uint8_t *) p_rsa_public_modulus, RSA_MODULUS_SIZE_BYTES(2048))) + mbedtls_mpi_read_binary(&ctx->N, (uint8_t *) p_rsa_public_modulus, public_key_size_bytes)) + { ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; } @@ -185,14 +190,19 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, { ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; } - /* The generated domain parameters are in the format: + /* With old procedures: + * The generated domain parameters are in the format: * d mod (q-1) || q || d mod (p-1) || p || (1/q) mod p * Import these elements into the mbedtls_rsa_context structure * We are not using CRT so d mode (q-1), d mode (p-1) and (1/q) mod p are ignored + * With new procedures: + * These values are not generated by HW and are reading other data from the + * generated buffer. This can be removed entirely later, but will require updating + * ARM code to ignore these fields. * */ else if (0 != mbedtls_mpi_read_binary(&ctx->Q, - p_rsa2048_domain_parameters_8 + + p_additional_key_info_8 + (1 * RSA_PARAMETERS_SIZE_BYTES(2048)), RSA_PARAMETERS_SIZE_BYTES(2048))) { @@ -200,7 +210,7 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, } else if (0 != mbedtls_mpi_read_binary(&ctx->P, - p_rsa2048_domain_parameters_8 + + p_additional_key_info_8 + (3 * RSA_PARAMETERS_SIZE_BYTES(2048)), RSA_PARAMETERS_SIZE_BYTES(2048))) @@ -216,7 +226,7 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, memset(p_common_buff_32, 0, (private_key_size_bytes + - (RSA_MODULUS_SIZE_BYTES(2048) + RSA_PLAIN_TEXT_CRT_KEY_SIZE_BYTES(2048)))); + (public_key_size_bytes + RSA_ADDITIONAL_KEY_INFO_SIZE_BYTES(2048)))); /* Free the allocated memory */ mbedtls_free(p_common_buff_32); @@ -236,21 +246,51 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, /* * Do an RSA public key operation */ - +volatile mbedtls_rsa_context * rsa_temp_ctx; int mbedtls_rsa_public (mbedtls_rsa_context * ctx, const unsigned char * input, unsigned char * output) { uint32_t temp_E = 0U; fsp_err_t iret; + uint32_t public_key_size_bytes = ctx->len; + + hw_sce_rsa_public_encrypt_t p_hw_sce_rsa_public_encrypt; + + // TODO: temporary implementation. + if (ctx->len == RSA_MODULUS_SIZE_BYTES(RSA_2048_BITS)) + { + p_hw_sce_rsa_public_encrypt = HW_SCE_RSA_2048PublicKeyEncrypt; + } + + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + #if RM_PSA_CRYPTO_CFG_RSA3K_ENABLED + else if (ctx->len == RSA_MODULUS_SIZE_BYTES(RSA_3072_BITS)) + { + p_hw_sce_rsa_public_encrypt = HW_SCE_RSA_3072PublicKeyEncrypt; + } + #endif + #if RM_PSA_CRYPTO_CFG_RSA4K_ENABLED + else if (ctx->len == RSA_MODULUS_SIZE_BYTES(RSA_4096_BITS)) + { + p_hw_sce_rsa_public_encrypt = HW_SCE_RSA_4096PublicKeyEncrypt; + } + #endif + #endif + else + { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + rsa_temp_ctx = ctx; /* Calloc pointer created to remove clang warnings */ uint32_t * p_calloc_temp_buff_N = NULL; /* If the size of N is not equal to the modulus size, then that is because of the leading 00 (sign field) from the ASN1 import * Use openssl asn1parse -in private1.pem (in !test folder) to see asn1 format of key */ - if (ctx->N.n != (RSA_MODULUS_SIZE_BYTES(2048) / (sizeof(mbedtls_mpi_uint)))) + if (ctx->N.n != (ctx->len / (sizeof(mbedtls_mpi_uint)))) { /* There should be only 1 extra value (00) at the beginning; otherwise the key is in an unexpected format */ - if ((ctx->N.n - 1) != (RSA_MODULUS_SIZE_BYTES(2048) / (sizeof(mbedtls_mpi_uint)))) + if ((ctx->N.n - 1) != (ctx->len / (sizeof(mbedtls_mpi_uint)))) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -259,20 +299,20 @@ int mbedtls_rsa_public (mbedtls_rsa_context * ctx, const unsigned char * input, /* Reverse byte order for E */ temp_E = __REV(*ctx->E.p); - /* Obtain a 32-bit aligned block of memory to be used by the SCE for key generation */ - p_calloc_temp_buff_N = (uint32_t *) mbedtls_calloc(RSA_MODULUS_SIZE_BYTES(2048) / 4, sizeof(uint32_t)); + /* Obtain a 32-bit aligned block of memory to pass key data to the SCE */ + p_calloc_temp_buff_N = (uint32_t *) mbedtls_calloc(public_key_size_bytes / 4, sizeof(uint32_t)); if (p_calloc_temp_buff_N == NULL) { return MBEDTLS_ERR_MPI_ALLOC_FAILED;; } /* Write N into the buffer in reverse */ - mbedtls_mpi_write_binary(&ctx->N, (uint8_t *) p_calloc_temp_buff_N, RSA_MODULUS_SIZE_BYTES(2048)); + mbedtls_mpi_write_binary(&ctx->N, (uint8_t *) p_calloc_temp_buff_N, public_key_size_bytes); iret = FSP_ERR_CRYPTO_CONTINUE; for ( ; FSP_ERR_CRYPTO_CONTINUE == iret; ) { - iret = HW_SCE_RSA_2048PublicKeyEncrypt((uint32_t *) input, &temp_E, p_calloc_temp_buff_N, (uint32_t *) output); + iret = p_hw_sce_rsa_public_encrypt((uint32_t *) input, &temp_E, p_calloc_temp_buff_N, (uint32_t *) output); } /* Free the allocated buffer */ @@ -299,12 +339,12 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, (void) p_rng; fsp_err_t err; int ret = 0; - uint32_t private_key_size_bytes = RSA_MODULUS_SIZE_BYTES(2048); + uint32_t private_key_size_bytes = ctx->len; hw_sce_rsa_private_decrypt_t p_hw_sce_rsa_private_decrypt = NULL; if (true == (bool) ctx->vendor_ctx) { - private_key_size_bytes = RSA_WRAPPED_PRIVATE_KEY_SIZE_BYTES(2048); + private_key_size_bytes = RSA_WRAPPED_PRIVATE_KEY_SIZE_BYTES(ctx->len * 8U); } /* Calloc 32-bit pointer created to remove clang warnings */ @@ -318,10 +358,10 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, /* If the size of N is not equal to the modulus size, then that is because of the leading 00 (sign field) from the ASN1 import * Use openssl asn1parse -in private1.pem to see asn1 format of a .pem key */ - if (ctx->N.n != (RSA_MODULUS_SIZE_BYTES(2048) / (sizeof(mbedtls_mpi_uint)))) + if (ctx->N.n != (ctx->len / (sizeof(mbedtls_mpi_uint)))) { /* There should be only 1 extra value (00) at the beginning; otherwise the key is in an unexpected format */ - if ((ctx->N.n - 1) != (RSA_MODULUS_SIZE_BYTES(2048) / (sizeof(mbedtls_mpi_uint)))) + if ((ctx->N.n - 1) != (ctx->len / (sizeof(mbedtls_mpi_uint)))) { return MBEDTLS_ERR_RSA_BAD_INPUT_DATA; } @@ -337,7 +377,7 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, * Public Key (N) of size RSA_MODULUS_SIZE_BYTES(x) * Private Key (D) of size private_key_size_bytes */ - p_common_buff_32 = mbedtls_calloc(((RSA_MODULUS_SIZE_BYTES(2048) + private_key_size_bytes) / 4), sizeof(uint32_t)); + p_common_buff_32 = mbedtls_calloc(((ctx->len + private_key_size_bytes) / 4), sizeof(uint32_t)); if (NULL == p_common_buff_32) { @@ -345,10 +385,10 @@ int mbedtls_rsa_private (mbedtls_rsa_context * ctx, } p_calloc_temp_buff_N = p_common_buff_32; - p_calloc_temp_buff_D = p_calloc_temp_buff_N + (RSA_MODULUS_SIZE_BYTES(2048) / 4); + p_calloc_temp_buff_D = p_calloc_temp_buff_N + (ctx->len / 4); /* Write N into the buffer in reverse */ - if (0 != mbedtls_mpi_write_binary(&ctx->N, (uint8_t *) p_calloc_temp_buff_N, RSA_MODULUS_SIZE_BYTES(2048))) + if (0 != mbedtls_mpi_write_binary(&ctx->N, (uint8_t *) p_calloc_temp_buff_N, ctx->len)) { ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; } diff --git a/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_Flash.c b/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_Flash.c new file mode 100644 index 000000000..c7a5fd246 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_Flash.c @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_Flash.h" +#include "r_flash_hp.h" + +/** + * \file Driver_Flash.c + * + * \brief CMSIS Flash driver for RA flash controller + */ + +#ifndef ARG_UNUSED + #define ARG_UNUSED(arg) (void) arg +#endif + +#ifndef ARG_NOT_USED + #define ARG_NOT_USED 0U +#endif + +/* Driver version */ +#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +const ARM_DRIVER_VERSION Flash_Driver_Version = +{ + ARM_FLASH_API_VERSION, /* Defined in the CMSIS Flash Driver header file */ + ARM_FLASH_DRV_VERSION +}; + +#define DFLASH_DEV g_tfm_fsp_flash +#define CFLASH_DEV g_tfm_fsp_flash + +extern flash_instance_t DFLASH_DEV; +extern flash_instance_t CFLASH_DEV; + +/** + * Data types values + */ +typedef enum e_driver_flash_type +{ + CODE_FLASH, + DATA_FLASH +} driver_flash_type_t; + +/** + * Event ready values for ARM_FLASH_CAPABILITIES::event_ready + * \ref ARM_FLASH_CAPABILITIES + */ +enum +{ + EVENT_READY_NOT_AVAILABLE = 0u, + EVENT_READY_AVAILABLE +}; + +/** + * Data width values for ARM_FLASH_CAPABILITIES::data_width + * \ref ARM_FLASH_CAPABILITIES + */ +enum +{ + DATA_WIDTH_8BIT = 0u, + DATA_WIDTH_16BIT, + DATA_WIDTH_32BIT +}; + +/** + * Erase chip values for ARM_FLASH_CAPABILITIES::erase_chip + * \ref ARM_FLASH_CAPABILITIES + */ +enum +{ + CHIP_ERASE_NOT_SUPPORTED = 0u, + CHIP_ERASE_SUPPORTED +}; + +/** Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES DriverCapabilities = +{ + .event_ready = EVENT_READY_NOT_AVAILABLE, + .data_width = DATA_WIDTH_16BIT, + .erase_chip = CHIP_ERASE_SUPPORTED +}; + +/** + * \brief Flash busy values flash status \ref ARM_FLASH_STATUS + */ +enum +{ + DRIVER_STATUS_IDLE = 0u, + DRIVER_STATUS_BUSY +}; + +/** + * \brief Flash error values flash status \ref ARM_FLASH_STATUS + */ +enum +{ + DRIVER_STATUS_NO_ERROR = 0u, + DRIVER_STATUS_ERROR +}; + +/** + * \brief Arm Flash device structure. + */ +typedef struct _FLASHx_Resources +{ + flash_instance_t * dev; /*!< FLASH memory device structure */ + ARM_FLASH_INFO * data; /*!< FLASH memory device data */ + ARM_FLASH_STATUS * status; +} ARM_FLASHx_Resources; + +static ARM_DRIVER_VERSION ARM_Flash_GetVersion (void) +{ + return Flash_Driver_Version; +} + +static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void) +{ + return DriverCapabilities; +} + +static int32_t ARM_Flashx_Initialize (ARM_FLASHx_Resources * ARM_FLASHx_DEV, + ARM_Flash_SignalEvent_t cb_event, + driver_flash_type_t flash_type) +{ + ARG_UNUSED(cb_event); + uint32_t flash_size = 0U; + uint32_t page_size = 0U; + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_BUSY; + + R_FLASH_HP_Close(ARM_FLASHx_DEV->dev->p_ctrl); + fsp_err_t err = R_FLASH_HP_Open(ARM_FLASHx_DEV->dev->p_ctrl, ARM_FLASHx_DEV->dev->p_cfg); + if (FSP_SUCCESS != err) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + + flash_info_t info; + if (FSP_SUCCESS != R_FLASH_HP_InfoGet(ARM_FLASHx_DEV->dev->p_ctrl, &info)) + { + R_FLASH_HP_Close(ARM_FLASHx_DEV->dev->p_ctrl); + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + + if (flash_type == DATA_FLASH) + { + flash_size = + (info.data_flash.p_block_array[info.data_flash.num_regions - 1U].block_section_end_addr - + info.data_flash.p_block_array[0].block_section_st_addr + 1U); + page_size = info.data_flash.p_block_array[info.data_flash.num_regions - 1U].block_size; + } + else + { + /* Assuming the entire flash has only 32k flash blocks, since the bootloader is using all of the 8K blocks for itself and won't be updated. */ + flash_size = + (info.code_flash.p_block_array[info.code_flash.num_regions - 1U].block_section_end_addr - + info.code_flash.p_block_array[0].block_section_st_addr + 1U); + page_size = info.code_flash.p_block_array[info.code_flash.num_regions - 1U].block_size; + } + + /* Validate hardcoded parameters of the flash */ + if ((ARM_FLASHx_DEV->data->page_size != page_size) || + (ARM_FLASHx_DEV->data->sector_size != page_size) || + (ARM_FLASHx_DEV->data->sector_count != (flash_size / page_size))) + { + R_FLASH_HP_Close(ARM_FLASHx_DEV->dev->p_ctrl); + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR_PARAMETER; + } + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_NO_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flashx_Uninitialize (ARM_FLASHx_Resources * ARM_FLASHx_DEV) +{ + R_FLASH_HP_Close(ARM_FLASHx_DEV->dev->p_ctrl); + + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flashx_PowerControl (ARM_FLASHx_Resources * ARM_FLASHx_DEV, ARM_POWER_STATE state) +{ + ARG_UNUSED(ARM_FLASHx_DEV); + + switch (state) + { + case ARM_POWER_FULL: + { + + /* Nothing to do */ + return ARM_DRIVER_OK; + } + + case ARM_POWER_OFF: + case ARM_POWER_LOW: + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + default: + + return ARM_DRIVER_ERROR_PARAMETER; + } +} + +static int32_t ARM_Flashx_ReadData (ARM_FLASHx_Resources * ARM_FLASHx_DEV, + uint32_t addr, + void * data, + uint32_t cnt, + driver_flash_type_t flash_type) +{ + fsp_err_t err = FSP_SUCCESS; + flash_result_t blank_check_result = FLASH_RESULT_BLANK; + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_BUSY; + + flash_info_t info; + if (FSP_SUCCESS != R_FLASH_HP_InfoGet(ARM_FLASHx_DEV->dev->p_ctrl, &info)) + { + R_FLASH_HP_Close(ARM_FLASHx_DEV->dev->p_ctrl); + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + + if (flash_type == CODE_FLASH) + { + /* Check if range is valid */ + if ((addr + cnt) > + ((info.code_flash.p_block_array[0].block_section_st_addr) + + (ARM_FLASHx_DEV->data->sector_size * ARM_FLASHx_DEV->data->sector_count))) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + + return ARM_DRIVER_ERROR_PARAMETER; + } + + blank_check_result = FLASH_RESULT_NOT_BLANK; + } + else + { + /* Check if range is valid */ + if ((addr + cnt) > + ((info.data_flash.p_block_array[0].block_section_st_addr) + + (ARM_FLASHx_DEV->data->sector_size * ARM_FLASHx_DEV->data->sector_count))) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR_PARAMETER; + } + + err = R_FLASH_HP_BlankCheck(ARM_FLASHx_DEV->dev->p_ctrl, addr, cnt, &blank_check_result); + if (err != FSP_SUCCESS) + { + if ((err == FSP_ERR_INVALID_ADDRESS) || + (err == FSP_ERR_INVALID_SIZE)) + { + /* The native driver checks aligment and range */ + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_NO_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + + return ARM_DRIVER_OK; + } + + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + } + + /* Validate the blank check result */ + if (FLASH_RESULT_NOT_BLANK == blank_check_result) + { + memcpy(data, (const void *) addr, cnt); + } + else + { + memset(data, 0xFF, cnt); + } + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_NO_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flashx_ProgramData (ARM_FLASHx_Resources * ARM_FLASHx_DEV, + uint32_t addr, + const void * data, + uint32_t cnt) +{ + fsp_err_t err = FSP_SUCCESS; + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_BUSY; + + __disable_irq(); + err = R_FLASH_HP_Write(ARM_FLASHx_DEV->dev->p_ctrl, (uint32_t) data, addr, cnt); + __enable_irq(); + + if (err != FSP_SUCCESS) + { + if ((err == FSP_ERR_INVALID_ADDRESS) || + (err == FSP_ERR_INVALID_SIZE)) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + /* The native driver checks aligment and range */ + return ARM_DRIVER_ERROR_PARAMETER; + } + + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_NO_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flashx_EraseSector (ARM_FLASHx_Resources * ARM_FLASHx_DEV, uint32_t addr) +{ + fsp_err_t err = FSP_SUCCESS; + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_BUSY; + + /* The erase function checks whether the address is within the valid flash + * address range, and the HW will align the address to page boundary if + * it is not aligned. + */ + __disable_irq(); + err = R_FLASH_HP_Erase(ARM_FLASHx_DEV->dev->p_ctrl, addr, 1U); + __enable_irq(); + + if (err != FSP_SUCCESS) + { + if (err == FSP_ERR_INVALID_ADDRESS) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR_PARAMETER; + } + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_NO_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flashx_EraseChip (ARM_FLASHx_Resources * ARM_FLASHx_DEV, driver_flash_type_t flash_type) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t start_addr = 0U; + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_BUSY; + + /* The erase function checks whether the address is aligned with + * the sector or subsector and checks the Flash memory boundaries. + */ + + flash_info_t info; + err = R_FLASH_HP_InfoGet(ARM_FLASHx_DEV->dev->p_ctrl, &info); + + if (err != FSP_SUCCESS) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + + return ARM_DRIVER_ERROR; + } + + if (flash_type == DATA_FLASH) + { + start_addr = info.data_flash.p_block_array[0].block_section_st_addr; + } + else + { + start_addr = info.code_flash.p_block_array[0].block_section_st_addr; + } + + __disable_irq(); + err = R_FLASH_HP_Erase(ARM_FLASHx_DEV->dev->p_ctrl, start_addr, ARM_FLASHx_DEV->data->sector_count); + __enable_irq(); + + if (err != FSP_SUCCESS) + { + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_ERROR; + } + + ARM_FLASHx_DEV->status->error = DRIVER_STATUS_NO_ERROR; + ARM_FLASHx_DEV->status->busy = DRIVER_STATUS_IDLE; + return ARM_DRIVER_OK; +} + +static ARM_FLASH_STATUS ARM_Flashx_GetStatus (ARM_FLASHx_Resources * ARM_FLASHx_DEV) +{ + return *(ARM_FLASHx_DEV->status); +} + +static ARM_FLASH_INFO * ARM_Flashx_GetInfo (ARM_FLASHx_Resources * ARM_FLASHx_DEV) +{ + return ARM_FLASHx_DEV->data; +} + +static ARM_FLASH_INFO ARM_DFLASH_DEV_DATA = +{ + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = (BSP_DATA_FLASH_SIZE_BYTES / BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE), /* 8KB (data flash size) / 64B */ + .sector_size = BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE, /* 64B - as there are no sectors the page size + * size is used here + */ + .page_size = BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE, /* 64B */ + .program_unit = BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE, /* Minimum write size in bytes */ + .erased_value = 0xFF +}; + +static ARM_FLASH_STATUS shared_status = +{ + .busy = DRIVER_STATUS_IDLE, + .error = DRIVER_STATUS_NO_ERROR, + .reserved = 0, +}; + +static ARM_FLASHx_Resources ARM_DFLASH_DEV = +{ + .dev = &DFLASH_DEV, /* Shared between DFlash and Cflash */ + .data = &(ARM_DFLASH_DEV_DATA), + .status = &shared_status, /* Shared between DFlash and Cflash */ +}; + +static ARM_DRIVER_VERSION ARM_DFlash_GetVersion (void) +{ + return ARM_Flash_GetVersion(); +} + +static ARM_FLASH_CAPABILITIES ARM_DFlash_GetCapabilities (void) +{ + return ARM_Flash_GetCapabilities(); +} + +static int32_t ARM_DFlash_Initialize (ARM_Flash_SignalEvent_t cb_event) +{ + return ARM_Flashx_Initialize(&ARM_DFLASH_DEV, cb_event, DATA_FLASH); +} + +static int32_t ARM_DFlash_Uninitialize (void) +{ + return ARM_Flashx_Uninitialize(&ARM_DFLASH_DEV); +} + +static int32_t ARM_DFlash_PowerControl (ARM_POWER_STATE state) +{ + return ARM_Flashx_PowerControl(&ARM_DFLASH_DEV, state); +} + +static int32_t ARM_DFlash_ReadData (uint32_t addr, void * data, uint32_t cnt) +{ + return ARM_Flashx_ReadData(&ARM_DFLASH_DEV, addr, data, cnt, DATA_FLASH); +} + +static int32_t ARM_DFlash_ProgramData (uint32_t addr, const void * data, uint32_t cnt) +{ + return ARM_Flashx_ProgramData(&ARM_DFLASH_DEV, addr, data, cnt); +} + +static int32_t ARM_DFlash_EraseSector (uint32_t addr) +{ + return ARM_Flashx_EraseSector(&ARM_DFLASH_DEV, addr); +} + +static int32_t ARM_DFlash_EraseChip (void) +{ + return ARM_Flashx_EraseChip(&ARM_DFLASH_DEV, DATA_FLASH); +} + +static ARM_FLASH_STATUS ARM_DFlash_GetStatus (void) +{ + return ARM_Flashx_GetStatus(&ARM_DFLASH_DEV); +} + +static ARM_FLASH_INFO * ARM_DFlash_GetInfo (void) +{ + return ARM_Flashx_GetInfo(&ARM_DFLASH_DEV); +} + +ARM_DRIVER_FLASH Driver_DFLASH = +{ + ARM_DFlash_GetVersion, + ARM_DFlash_GetCapabilities, + ARM_DFlash_Initialize, + ARM_DFlash_Uninitialize, + ARM_DFlash_PowerControl, + ARM_DFlash_ReadData, + ARM_DFlash_ProgramData, + ARM_DFlash_EraseSector, + ARM_DFlash_EraseChip, + ARM_DFlash_GetStatus, + ARM_DFlash_GetInfo +}; + +static ARM_FLASH_INFO ARM_CFLASH_DEV_DATA = +{ + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = + ((BSP_ROM_SIZE_BYTES) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE), /* (flash size of 32k blocks only) / 32kB */ + .sector_size = BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE, /* 32kB - as there are no sectors the page size + * size is used here + */ + .page_size = BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE, /* 32kB */ + .program_unit = BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE, /* Minimum write size in bytes */ + .erased_value = 0xFF +}; + +static ARM_FLASHx_Resources ARM_CFLASH_DEV = +{ + .dev = &CFLASH_DEV, /* Shared between DFlash and Cflash */ + .data = &ARM_CFLASH_DEV_DATA, + .status = &shared_status, /* Shared between DFlash and Cflash */ +}; + +static ARM_DRIVER_VERSION ARM_CFlash_GetVersion (void) +{ + return ARM_Flash_GetVersion(); +} + +static ARM_FLASH_CAPABILITIES ARM_CFlash_GetCapabilities (void) +{ + return ARM_Flash_GetCapabilities(); +} + +static int32_t ARM_CFlash_Initialize (ARM_Flash_SignalEvent_t cb_event) +{ + return ARM_Flashx_Initialize(&ARM_CFLASH_DEV, cb_event, CODE_FLASH); +} + +static int32_t ARM_CFlash_Uninitialize (void) +{ + return ARM_Flashx_Uninitialize(&ARM_CFLASH_DEV); +} + +static int32_t ARM_CFlash_PowerControl (ARM_POWER_STATE state) +{ + return ARM_Flashx_PowerControl(&ARM_CFLASH_DEV, state); +} + +static int32_t ARM_CFlash_ReadData (uint32_t addr, void * data, uint32_t cnt) +{ + return ARM_Flashx_ReadData(&ARM_CFLASH_DEV, addr, data, cnt, CODE_FLASH); +} + +static int32_t ARM_CFlash_ProgramData (uint32_t addr, const void * data, uint32_t cnt) +{ + return ARM_Flashx_ProgramData(&ARM_CFLASH_DEV, addr, data, cnt); +} + +static int32_t ARM_CFlash_EraseSector (uint32_t addr) +{ + return ARM_Flashx_EraseSector(&ARM_CFLASH_DEV, addr); +} + +static int32_t ARM_CFlash_EraseChip (void) +{ + return ARM_Flashx_EraseChip(&ARM_CFLASH_DEV, CODE_FLASH); +} + +static ARM_FLASH_STATUS ARM_CFlash_GetStatus (void) +{ + return ARM_Flashx_GetStatus(&ARM_CFLASH_DEV); +} + +static ARM_FLASH_INFO * ARM_CFlash_GetInfo (void) +{ + return ARM_Flashx_GetInfo(&ARM_CFLASH_DEV); +} + +ARM_DRIVER_FLASH Driver_CFLASH = +{ + ARM_CFlash_GetVersion, + ARM_CFlash_GetCapabilities, + ARM_CFlash_Initialize, + ARM_CFlash_Uninitialize, + ARM_CFlash_PowerControl, + ARM_CFlash_ReadData, + ARM_CFlash_ProgramData, + ARM_CFlash_EraseSector, + ARM_CFlash_EraseChip, + ARM_CFlash_GetStatus, + ARM_CFlash_GetInfo +}; diff --git a/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_QSPI_Flash.c b/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_QSPI_Flash.c new file mode 100644 index 000000000..4a9d187c9 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_QSPI_Flash.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_Flash.h" + +#include +#include "flash_layout.h" + + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) ((void)arg) +#endif + +/* Driver version */ +#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_FLASH_API_VERSION, /* Defined in the CMSIS Flash Driver header file */ + ARM_FLASH_DRV_VERSION +}; + +/** + * \brief Flash driver capability macro definitions \ref ARM_FLASH_CAPABILITIES + */ +/* Flash Ready event generation capability values */ +#define EVENT_READY_NOT_AVAILABLE (0u) +#define EVENT_READY_AVAILABLE (1u) +/* Data access size values */ +#define DATA_WIDTH_8BIT (0u) +#define DATA_WIDTH_16BIT (1u) +#define DATA_WIDTH_32BIT (2u) +/* Chip erase capability values */ +#define CHIP_ERASE_NOT_SUPPORTED (0u) +#define CHIP_ERASE_SUPPORTED (1u) + +/* Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES DriverCapabilities = { + EVENT_READY_NOT_AVAILABLE, + DATA_WIDTH_32BIT, + CHIP_ERASE_SUPPORTED, + 0 +}; + +/** + * \brief Flash status macro definitions \ref ARM_FLASH_STATUS + */ +/* Busy status values of the Flash driver */ +#define DRIVER_STATUS_IDLE (0u) +#define DRIVER_STATUS_BUSY (1u) +/* Error status values of the Flash driver */ +#define DRIVER_STATUS_NO_ERROR (0u) +#define DRIVER_STATUS_ERROR (1u) + +/** + * \brief Arm Flash device structure. + */ +struct arm_flash_dev_t { + ARM_FLASH_INFO *data; /*!< FLASH memory device data */ +}; + +static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = QSPI_FLASH_TOTAL_SIZE / 0x1000, + .sector_size = 0x1000, + .page_size = 0x100000, + .program_unit = 1u, /* Minimum write size in bytes */ + .erased_value = 0xFF +}; + +static struct arm_flash_dev_t ARM_FLASH0_DEV = { + .data = &(ARM_FLASH0_DEV_DATA) +}; + +/* Flash Status */ +static ARM_FLASH_STATUS ARM_FLASH0_STATUS = {0, 0, 0}; + +static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) +{ + ARG_UNUSED(cb_event); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static int32_t ARM_Flash_Uninitialize(void) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) +{ + switch(state) { + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + case ARM_POWER_OFF: + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + default: + return ARM_DRIVER_ERROR_PARAMETER; + } +} + +static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) +{ + ARG_UNUSED(addr); + ARG_UNUSED(data); + ARG_UNUSED(cnt); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static int32_t ARM_Flash_ProgramData(uint32_t addr, + const void *data, uint32_t cnt) +{ + ARG_UNUSED(addr); + ARG_UNUSED(data); + ARG_UNUSED(cnt); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static int32_t ARM_Flash_EraseSector(uint32_t addr) +{ + ARG_UNUSED(addr); + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static int32_t ARM_Flash_EraseChip(void) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_FLASH_STATUS ARM_Flash_GetStatus(void) +{ + return ARM_FLASH0_STATUS; +} + +static ARM_FLASH_INFO * ARM_Flash_GetInfo(void) +{ + return ARM_FLASH0_DEV.data; +} + +ARM_DRIVER_FLASH Driver_QSPI_FLASH0 = { + ARM_Flash_GetVersion, + ARM_Flash_GetCapabilities, + ARM_Flash_Initialize, + ARM_Flash_Uninitialize, + ARM_Flash_PowerControl, + ARM_Flash_ReadData, + ARM_Flash_ProgramData, + ARM_Flash_EraseSector, + ARM_Flash_EraseChip, + ARM_Flash_GetStatus, + ARM_Flash_GetInfo +}; + diff --git a/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_USART.c b/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_USART.c new file mode 100644 index 000000000..2cb54b5b7 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/CMSIS_Driver/Driver_USART.c @@ -0,0 +1,279 @@ +/*********************************************************************************************************************** + * File Name : driver_usart.c + * Description : This file contains uart driver specific API implementation. + * ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ + +#include "tfm_common_config.h" + +#include +#include +#include + +#if CFG_UART_DEBUG_ENABLE +#include "r_sci_uart.h" +#include "r_uart_api.h" + +static volatile uart_event_t g_uart_evt = 0; +#endif + +#ifndef ARG_UNUSED + #define ARG_UNUSED(arg) ((void) arg) +#endif + +/* Driver version */ +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +static volatile uint32_t g_num = 0; + +extern ARM_DRIVER_USART Driver_USART; + +/* Driver Version */ +static ARM_DRIVER_VERSION DriverVersion = +{ + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +/* Driver Capabilities */ +static ARM_USART_CAPABILITIES DriverCapabilities = +{ + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */ + 0 /* Reserved */ +}; + +#if CFG_UART_DEBUG_ENABLE +/* FSP structures required by uart and flash drivers */ +extern sci_uart_instance_ctrl_t g_tfm_fsp_uart_ctrl; +extern const uart_cfg_t g_tfm_fsp_uart_cfg; +#endif + + +static ARM_DRIVER_VERSION ARM_USART_GetVersion (void) +{ +#if CFG_UART_DEBUG_ENABLE + fsp_version_t ver; + fsp_err_t fsp_err = FSP_SUCCESS; + + fsp_err = R_SCI_UART_VersionGet(&ver); + if (FSP_SUCCESS != fsp_err) + { + DriverVersion.api = (uint16_t) ((uint16_t) (ver.api_version_major << 8) | (ver.api_version_minor)); + DriverVersion.drv = (uint16_t) ((uint16_t) (ver.code_version_major << 8) | (ver.code_version_minor)); + } + else +#endif + { + memset(&DriverVersion, 0, sizeof(DriverVersion)); + } + + return DriverVersion; +} + +static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) +{ + return DriverCapabilities; +} + +static int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) +{ + ARG_UNUSED(cb_event); +#if CFG_UART_DEBUG_ENABLE + fsp_err_t fsp_err = FSP_SUCCESS; + + fsp_err = R_SCI_UART_Open(&g_tfm_fsp_uart_ctrl, &g_tfm_fsp_uart_cfg); + if (FSP_SUCCESS != fsp_err) + { + return ARM_DRIVER_ERROR; + } +#endif + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART_Uninitialize (void) +{ +#if CFG_UART_DEBUG_ENABLE + fsp_err_t fsp_err = FSP_SUCCESS; + + fsp_err = R_SCI_UART_Close(&g_tfm_fsp_uart_ctrl); + if (FSP_SUCCESS != fsp_err) + { + return ARM_DRIVER_ERROR; + } +#endif + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) +{ + ARG_UNUSED(state); /* Not used, avoid warning */ + + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static uint32_t ARM_USART_GetTxCount (void) +{ + /* Return the last successfully transmitted data count. + * This implementation will not work in a multithreaded environment. */ + return g_num; +} + +static int32_t ARM_USART_Control (uint32_t control, uint32_t arg) +{ + ARG_UNUSED(arg); /* Not used, avoid warning */ + ARG_UNUSED(control); /* Not used, avoid warning */ + + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS ARM_USART_GetStatus (void) +{ + /* Nothing to be done */ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + + return status; +} + +static int32_t ARM_USART_Send (const void * data, uint32_t num) +{ + ARG_UNUSED(data); +#if CFG_UART_DEBUG_ENABLE + fsp_err_t fsp_err = FSP_SUCCESS; + + if ((num == 0) || (data == NULL)) + { + return ARM_DRIVER_ERROR; + } + + g_uart_evt = 0; + + fsp_err = R_SCI_UART_Write(&g_tfm_fsp_uart_ctrl, data, num); + if (FSP_SUCCESS != fsp_err) + { + return ARM_DRIVER_ERROR; + } + + /* Wait for UART Tx to complete */ + while (!g_uart_evt) + { + ; + } + + if ((g_uart_evt != UART_EVENT_TX_DATA_EMPTY)) + { + g_num = 0; + + return ARM_DRIVER_ERROR; + } +#endif + /*Save the transmitted number to be used in ARM_USART_GetTxCount*/ + g_num = num; + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART_Receive (void * data, uint32_t num) +{ +#if CFG_UART_DEBUG_ENABLE + fsp_err_t fsp_err = FSP_SUCCESS; + + if (data == NULL) + { + return ARM_DRIVER_ERROR; + } + + g_uart_evt = 0; + + fsp_err = R_SCI_UART_Read(&g_tfm_fsp_uart_ctrl, data, num); + if (FSP_SUCCESS != fsp_err) + { + return ARM_DRIVER_ERROR; + } + + /* Wait for UART Rx to complete */ + while (!g_uart_evt) + { + ; + } + + if (g_uart_evt != UART_EVENT_RX_COMPLETE) + { + return ARM_DRIVER_ERROR; + } + + return ARM_DRIVER_OK; +#else + ARG_UNUSED(data); + ARG_UNUSED(num); + return ARM_DRIVER_ERROR; +#endif +} + +#if CFG_UART_DEBUG_ENABLE +void user_uart_callback (uart_callback_args_t * p_args) +{ + if (NULL != p_args) + { + g_uart_evt = p_args->event; + } +} +#endif + +ARM_DRIVER_USART Driver_USART = +{ + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART_Initialize, + ARM_USART_Uninitialize, + ARM_USART_PowerControl, + ARM_USART_Send, + ARM_USART_Receive, + NULL, + ARM_USART_GetTxCount, + NULL, + ARM_USART_Control, + ARM_USART_GetStatus, + NULL, + NULL +}; + diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Config/device_cfg.h b/ra/fsp/src/rm_tfm_port/ra/Device/Config/device_cfg.h new file mode 100644 index 000000000..c3a164193 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Config/device_cfg.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Macro used by uart_stdout.c, this macro has no affect on baudrate config */ +#define DEFAULT_UART_BAUDRATE 115200 + +#endif /* __DEVICE_CFG_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/cmsis.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/cmsis.h new file mode 100644 index 000000000..8b3c70c76 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/cmsis.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_H__ +#define __CMSIS_H__ + +/* Processor and Core Peripherals and Configurations */ + +/* ========================================================================== */ +/* ============= Processor and Core Peripheral Section ============= */ +/* ========================================================================== */ + +/* ----- Start of section using anonymous unions and disabling warnings ----- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#include "bsp_api.h" +#include "platform_irq.h" +#include "tfm_common_config.h" + +/* ------ End of section using anonymous unions and disabling warnings ------ */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#endif /*__CMSIS_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_base_address.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_base_address.h new file mode 100644 index 000000000..14421d0cb --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_base_address.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h + * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75 + */ + +#ifndef __PLATFORM_BASE_ADDRESS_H__ +#define __PLATFORM_BASE_ADDRESS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_api.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_description.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_description.h new file mode 100644 index 000000000..e5760c76f --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_description.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PLATFORM_DESCRIPTION_H__ +#define __PLATFORM_DESCRIPTION_H__ + +#include "platform_base_address.h" +#include "platform_pins.h" +#include "platform_regs.h" +#include "cmsis.h" + +#endif /* __PLATFORM_DESCRIPTION_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_irq.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_irq.h new file mode 100644 index 000000000..03b9d2593 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_irq.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PLATFORM_IRQ_H__ +#define __PLATFORM_IRQ_H__ +#include "vector_data.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* ============= Interrupt Number Definition ================ */ +/* ========================================================================== */ + +/* + * #define TIMER0_IRQn ((IRQn_Type) 1) + * #define TIMER1_IRQn ((IRQn_Type) 2) + * #define UART1_Tx_IRQn ((IRQn_Type) 3) + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PLATFORM_IRQ_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_pins.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_pins.h new file mode 100644 index 000000000..d76042369 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_pins.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file platform_pins.h + * \brief This file defines all the pins for this platform. + */ + +#ifndef __PLATFORM_PINS_H__ +#define __PLATFORM_PINS_H__ + +#include "bsp_api.h" + +#endif /* __PLATFORM_PINS_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_regs.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_regs.h new file mode 100644 index 000000000..2d94b91d7 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/platform_regs.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PLATFORM_REGS_H__ +#define __PLATFORM_REGS_H__ + +#include +#include "platform_base_address.h" + +#endif /* __PLATFORM_REGS_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Include/system_core_init.h b/ra/fsp/src/rm_tfm_port/ra/Device/Include/system_core_init.h new file mode 100644 index 000000000..ed0c6797c --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Include/system_core_init.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Include\system_ARMCM33.h + * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75 + * + */ + +#ifndef __SYSTEM_CORE_INIT_H__ +#define __SYSTEM_CORE_INIT_H__ + +#include +#include "bsp_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +extern void RM_TFM_SystemInit (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/Device/Source/system_core_init.c b/ra/fsp/src/rm_tfm_port/ra/Device/Source/system_core_init.c new file mode 100644 index 000000000..4193f563e --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Device/Source/system_core_init.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Source\system_ARMCM33.c + * https://github.com/ARM-software/CMSIS_5/tree/5.0.1 + * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75 + */ +#include +#include +#include +#include "system_core_init.h" +#include "platform_description.h" +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ + +extern void (* __init_array_start[])(void); + +extern void (* __init_array_end[])(void); + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void RM_TFM_SystemInit (void) +{ + /* Initialize C runtime */ + __asm volatile("ldr r4, =__copy_table_start__ \n" + "ldr r5, =__copy_table_end__ \n" + + ".L_loop0: \n" + "cmp r4, r5 \n" + "bge .L_loop0_done \n" + "ldr r1, [r4] \n" + "ldr r2, [r4, #4] \n" + "ldr r3, [r4, #8] \n" + + ".L_loop0_0: \n" + "subs r3, #4 \n" + "ittt ge \n" + "ldrge r0, [r1, r3] \n" + "strge r0, [r2, r3] \n" + "bge .L_loop0_0 \n" + + "adds r4, #12 \n" + "b .L_loop0 \n" + + ".L_loop0_done: \n" + "nop \n"); + + __asm volatile("ldr r3, =__zero_table_start__ \n" + "ldr r4, =__zero_table_end__ \n" + + ".L_loop2: \n" + "cmp r3, r4 \n" + "bge .L_loop2_done \n" + "ldr r1, [r3] \n" + "ldr r2, [r3, #4] \n" + "movs r0, 0 \n" + + ".L_loop2_0: \n" + "subs r2, #4 \n" + "itt ge \n" + "strge r0, [r1, r2] \n" + "bge .L_loop2_0 \n" + + "adds r3, #8 \n" + "b .L_loop2 \n" + ".L_loop2_done: \n" + "nop \n"); + + int32_t count = __init_array_end - __init_array_start; + for (int32_t i = 0; i < count; i++) + { + __init_array_start[i](); + } +} + diff --git a/ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.c b/ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.c new file mode 100644 index 000000000..ad9efab9c --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2017-2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "mpu_armv8m_drv.h" +#include "cmsis.h" + +/* + * FixMe: + * This is a beta quality driver for MPU in v8M. To be finalized. + */ + +enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, + uint32_t privdef_en, + uint32_t hfnmi_en) +{ + /*No error checking*/ + + MPU_Type *mpu = (MPU_Type *)dev->base; + + /* + * FixMe: Set 3 pre-defined MAIR_ATTR for memory. The attributes come + * from default memory map, need to check if fine-tune is necessary. + * + * MAIR0_0: Peripheral, Device-nGnRE. + * MAIR0_1: Code, WT RA. Same attr for Outer and Inner. + * MAIR0_2: SRAM, WBWA RA. Same attr for Outer and Inner. + */ + mpu->MAIR0 = (MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL << MPU_MAIR0_Attr0_Pos) | + (MPU_ARMV8M_MAIR_ATTR_CODE_VAL << MPU_MAIR0_Attr1_Pos) | + (MPU_ARMV8M_MAIR_ATTR_DATA_VAL << MPU_MAIR0_Attr2_Pos); + + mpu->CTRL = + (privdef_en ? MPU_CTRL_PRIVDEFENA_Msk : 0) | + (hfnmi_en ? MPU_CTRL_HFNMIENA_Msk : 0); + + /*Ensure all configuration is written before enable*/ + + mpu->CTRL |= MPU_CTRL_ENABLE_Msk; + + /* Enable MPU before next instruction */ + __DSB(); + __ISB(); + return MPU_ARMV8M_OK; +} + +enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + /* Reset all fields as enable does full setup */ + mpu->CTRL = 0; + + return MPU_ARMV8M_OK; +} + + +enum mpu_armv8m_error_t mpu_armv8m_region_enable( + struct mpu_armv8m_dev_t *dev, + struct mpu_armv8m_region_cfg_t *region_cfg) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + + enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; + uint32_t ctrl_before; + uint32_t base_cfg; + uint32_t limit_cfg; + + /*FIXME : Add complete error checking*/ + if ((region_cfg->region_base & ~MPU_RBAR_BASE_Msk) != 0) { + return MPU_ARMV8M_ERROR; + } + /* region_limit doesn't need to be aligned but the scatter + * file needs to be setup to ensure that partitions do not overlap. + */ + + ctrl_before = mpu->CTRL; + mpu->CTRL = 0; + + mpu->RNR = region_cfg->region_nr & MPU_RNR_REGION_Msk; + + /* This 0s the lower bits of the base address */ + base_cfg = region_cfg->region_base & MPU_RBAR_BASE_Msk; + base_cfg |= (region_cfg->attr_sh << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk; + base_cfg |= (region_cfg->attr_access << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk; + base_cfg |= (region_cfg->attr_exec << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk; + + mpu->RBAR = base_cfg; + + /*This 0s the lower bits of base address but they are treated as 1 */ + limit_cfg = (region_cfg->region_limit-1) & MPU_RLAR_LIMIT_Msk; + + limit_cfg |= (region_cfg->region_attridx << MPU_RLAR_AttrIndx_Pos) & + MPU_RLAR_AttrIndx_Msk; + + limit_cfg |= MPU_RLAR_EN_Msk; + + mpu->RLAR = limit_cfg; + + /*Restore main MPU control*/ + mpu->CTRL = ctrl_before; + + /* Enable MPU before the next instruction */ + __DSB(); + __ISB(); + + return ret_val; +} + + +enum mpu_armv8m_error_t mpu_armv8m_region_disable( + struct mpu_armv8m_dev_t *dev, + uint32_t region_nr) +{ + + MPU_Type *mpu = (MPU_Type *)dev->base; + + enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; + uint32_t ctrl_before; + + /*FIXME : Add complete error checking*/ + + ctrl_before = mpu->CTRL; + mpu->CTRL = 0; + + mpu->RNR = region_nr & MPU_RNR_REGION_Msk; + + mpu->RBAR = 0; + mpu->RLAR = 0; + + /*Restore main MPU control*/ + mpu->CTRL = ctrl_before; + + return ret_val; +} + +enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev) +{ + MPU_Type *mpu = (MPU_Type *)dev->base; + uint32_t i = (mpu->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + while (i > 0) { + mpu_armv8m_region_disable(dev, i-1); + i--; + } + + return MPU_ARMV8M_OK; + +} diff --git a/ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.h b/ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.h new file mode 100644 index 000000000..8b3b625cb --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/Native_Driver/mpu_armv8m_drv.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017-2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MPU_ARMV8M_DRV_H__ +#define __MPU_ARMV8M_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define PRIVILEGED_DEFAULT_ENABLE 1 +#define HARDFAULT_NMI_ENABLE 1 + +/* MAIR_ATTR */ +#define MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL 0x04 +#define MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX 0 +#define MPU_ARMV8M_MAIR_ATTR_CODE_VAL 0xAA +#define MPU_ARMV8M_MAIR_ATTR_CODE_IDX 1 +#define MPU_ARMV8M_MAIR_ATTR_DATA_VAL 0xFF +#define MPU_ARMV8M_MAIR_ATTR_DATA_IDX 2 + +struct mpu_armv8m_dev_t { + const uint32_t base; +}; + +enum mpu_armv8m_error_t { + MPU_ARMV8M_OK, + MPU_ARMV8M_ERROR +}; + +enum mpu_armv8m_attr_exec_t { + MPU_ARMV8M_XN_EXEC_OK, + MPU_ARMV8M_XN_EXEC_NEVER +}; + +enum mpu_armv8m_attr_access_t { + MPU_ARMV8M_AP_RW_PRIV_ONLY, + MPU_ARMV8M_AP_RW_PRIV_UNPRIV, + MPU_ARMV8M_AP_RO_PRIV_ONLY, + MPU_ARMV8M_AP_RO_PRIV_UNPRIV +}; + +enum mpu_armv8m_attr_shared_t { + MPU_ARMV8M_SH_NONE, + MPU_ARMV8M_SH_UNUSED, + MPU_ARMV8M_SH_OUTER, + MPU_ARMV8M_SH_INNER +}; + +struct mpu_armv8m_region_cfg_t { + uint32_t region_nr; + uint32_t region_base; + uint32_t region_limit; + uint32_t region_attridx; + enum mpu_armv8m_attr_exec_t attr_exec; + enum mpu_armv8m_attr_access_t attr_access; + enum mpu_armv8m_attr_shared_t attr_sh; +}; + +struct mpu_armv8m_region_cfg_raw_t { + uint32_t region_nr; + uint32_t region_base; + uint32_t region_limit; +}; + + +/** + * \brief Enable MPU + * + * \param[in] dev MPU device mpu_armv8m_dev_t + * \param[in] privdef_en privilege default region 1:enable 0:disable + * \param[in] hfnmi_en mpu for hard fault & nmi 1:enable 0:disable + * + * \return Error code mpu_armv8m_error_t + * + * \note This function doesn't check if dev is NULL. + */ + +enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, + uint32_t privdef_en, + uint32_t hfnmi_en); + +/** + * \brief Disable MPU + * + * \param[in] dev MPU device mpu_armv8m_dev_t + * + * \return Error code arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev); + +/** + * \brief Disable MPU and clean all regions + * + * \param[in] dev MPU device mpu_armv8m_dev_t + * + * \return Error code arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev); + +/** + * \brief Enable MPU Region + * + * \param[in] dev MPU device mpu_armv8m_dev_t + * \param[in] region_cfg MPU region config mpu_armv8m_region_cfg_t + * + * \return Error code arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_region_enable( + struct mpu_armv8m_dev_t *dev, + struct mpu_armv8m_region_cfg_t *region_cfg); + +/** + * \brief Disable MPU Region + * + * \param[in] dev MPU device mpu_armv8m_dev_t + * \param[in] region_nr Region number + * + * \return Error code arm_mpu_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpu_armv8m_error_t mpu_armv8m_region_disable( + struct mpu_armv8m_dev_t *dev, + uint32_t region_nr); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPU_ARMV8M_DRV_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/attest_hal.c b/ra/fsp/src/rm_tfm_port/ra/attest_hal.c new file mode 100644 index 000000000..d7a7d1740 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/attest_hal.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include "tfm_attest_hal.h" +#include "tfm_plat_boot_seed.h" +#include "tfm_plat_device_id.h" + + +/*! + * \def BOOT_SEED + * + * \brief Fixed value for boot seed used for test. + */ +#define BOOT_SEED 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, \ + 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, \ + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, \ + 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF + +static const uint8_t boot_seed[BOOT_SEED_SIZE] = {BOOT_SEED}; + +/* Example verification service URL for initial attestation token */ +static const char verification_service_url[] = "www.trustedfirmware.org"; + +/* Example profile definition document for initial attestation token */ +static const char attestation_profile_definition[] = "PSA_IOT_PROFILE_1"; + +static const uint8_t implementation_id[] = { + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, + 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, +}; + +static const uint8_t example_ean_13[] = "060456527282910010"; + +enum tfm_security_lifecycle_t tfm_attest_hal_get_security_lifecycle(void) +{ + return TFM_SLC_SECURED; +} + +const char * +tfm_attest_hal_get_verification_service(uint32_t *size) +{ + *size = sizeof(verification_service_url) - 1; + + return verification_service_url; +} + +const char * +tfm_attest_hal_get_profile_definition(uint32_t *size) +{ + *size = sizeof(attestation_profile_definition) - 1; + + return attestation_profile_definition; +} + +enum tfm_plat_err_t tfm_plat_get_boot_seed(uint32_t size, uint8_t *buf) +{ + /* FixMe: - This getter function must be ported per target platform. + * - Platform service shall provide an API to further interact this + * getter function to retrieve the boot seed. + */ + + uint32_t i; + uint8_t *p_dst = buf; + const uint8_t *p_src = boot_seed; + + if (size != BOOT_SEED_SIZE) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + for (i = size; i > 0; i--) { + *p_dst = *p_src; + p_src++; + p_dst++; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +/** + * \brief Copy the device specific ID to the destination buffer + * + * \param[out] p_dst Pointer to buffer where to store ID + * \param[in] p_src Pointer to the ID + * \param[in] size Length of the ID + */ +static inline void copy_id(uint8_t *p_dst, const uint8_t *p_src, size_t size) +{ + uint32_t i; + + for (i = size; i > 0; i--) { + *p_dst = *p_src; + p_src++; + p_dst++; + } +} + +enum tfm_plat_err_t tfm_plat_get_implementation_id(uint32_t *size, + uint8_t *buf) +{ + const uint8_t *p_impl_id = implementation_id; + uint32_t impl_id_size = sizeof(implementation_id); + + if (*size < impl_id_size) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + copy_id(buf, p_impl_id, impl_id_size); + *size = impl_id_size; + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_get_hw_version(uint32_t *size, uint8_t *buf) +{ + const uint8_t *p_hw_version = example_ean_13; + uint32_t hw_version_size = sizeof(example_ean_13) - 1; + + if (*size < hw_version_size) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + copy_id(buf, p_hw_version, hw_version_size); + *size = hw_version_size; + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/ra/fsp/src/rm_tfm_port/ra/boot_hal.c b/ra/fsp/src/rm_tfm_port/ra/boot_hal.c new file mode 100644 index 000000000..73d0850ac --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/boot_hal.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "target_cfg.h" +#include "cmsis.h" +#include "boot_hal.h" +#include "Driver_Flash.h" +#include "region_defs.h" +#include "bootutil/bootutil_log.h" + +#include "r_flash_hp.h" +#include "r_flash_api.h" + +#include "psa/crypto.h" + +#if defined(__ARMCC_VERSION) +__attribute__((naked)) void boot_clear_bl2_ram_area (void) +{ + __asm volatile ( + ".syntax unified \n" + "mov r0, #0 \n" + "ldr r1, =Image$$DATA$$Base \n" + "ldr r2, =Image$$ARM_LIB_HEAP$$ZI$$Limit \n" + "subs r2, r2, r1 \n" + "Loop: \n" + "subs r2, #4 \n" + "itt ge \n" + "strge r0, [r1, r2] \n" + "bge Loop \n" + "bx lr \n" + : : : "r0", "r1", "r2", "memory" + ); +} + +#elif defined(__GNUC__) +__attribute__((naked)) void boot_clear_bl2_ram_area (void) +{ + __asm volatile ( + ".syntax unified \n" + "mov r0, #0 \n" + "ldr r1, =__data_start__ \n" + "ldr r2, =__HeapLimit \n" + "subs r2, r2, r1 \n" + "Loop: \n" + "subs r2, #4 \n" + "itt ge \n" + "strge r0, [r1, r2] \n" + "bge Loop \n" + "bx lr \n" + : : : "r0", "r1", "r2", "memory" + ); +} + +#elif defined(__ICCARM__) +extern uint32_t HEAP$$Limit; +extern uint32_t data$$Base; +__attribute__((naked)) void boot_clear_bl2_ram_area (void) +{ + __asm volatile ( + "mov r0, #0 \n" + "ldr r1, = data$$Base \n" + "ldr r2, = HEAP$$Limit \n" + "subs r2, r2, r1 \n" + "Loop: \n" + "subs r2, #4 \n" + "itt ge \n" + "strge r0, [r1, r2] \n" + "bge Loop \n" + "bx lr \n" + : : : "r0", "r1", "r2", "memory" + ); +} + +#endif + +#ifdef BOOT_DATA_AVAILABLE + +/* + * The section 'fsp_dtc_vector_table' is reused to store boot data. + * This is done to avoid creating a BL2 specific linker script. + */ +static uint8_t g_tfm_shared_data[BOOT_TFM_SHARED_DATA_SIZE] BSP_PLACE_IN_SECTION(".fsp_dtc_vector_table"); +#endif /* BOOT_DATA_AVAILABLE */ + +#define FAW_START_ADDR (0xFFFC) +#define FAW_END_ADDR (0x200000) + +/* Flash device name must be specified by target */ +extern ARM_DRIVER_FLASH FLASH_DEV_NAME; + +/* FSP structures required by uart and flash drivers */ +extern flash_hp_instance_ctrl_t g_tfm_fsp_flash_ctrl; +extern const flash_cfg_t g_tfm_fsp_flash_cfg; + +static void flash_FAW_Set (uint32_t start_addr, uint32_t end_addr) +{ + int ret_val = 0; + + volatile uint32_t faws = (uint32_t) ((R_FACI_HP->FAWMON_b.FAWS) << 13); + volatile uint32_t fawe = (uint32_t) ((R_FACI_HP->FAWMON_b.FAWE) << 13); + + if (faws == fawe) + { + BOOT_LOG_INF("Configuring FAW settings"); + + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + ret_val = R_FLASH_HP_AccessWindowSet(&g_tfm_fsp_flash_ctrl, start_addr, end_addr); + + FSP_CRITICAL_SECTION_EXIT; + if (ret_val) + { + BOOT_LOG_ERR("Failed to set Flash Access Window: 0x%x", ret_val); + } + } +} + +/* bootloader platform-specific HW intialization */ +int32_t boot_platform_init (void) +{ + int32_t result; + + result = FLASH_DEV_NAME.Initialize(NULL); + if (ARM_DRIVER_OK != result) + { + return result; + } + +#ifdef BOOT_DATA_AVAILABLE + memset(g_tfm_shared_data, 0x0, BOOT_TFM_SHARED_DATA_SIZE); +#endif /* BOOT_DATA_AVAILABLE */ + + /* Set the FAW to lock the Secure code and data region */ + + // flash_FAW_Set(FAW_START_ADDR, FAW_END_ADDR); + + result = mbedtls_platform_setup(NULL); + if (result != 0) + { + return result;; + } + + result = psa_crypto_init(); + + return result; +} + +void boot_platform_quit (struct boot_arm_vector_table * vt) +{ + /* Clang at O0, stores variables on the stack with SP relative addressing. + * When manually set the SP then the place of reset vector is lost. + * Static variables are stored in 'data' or 'bss' section, change of SP has + * no effect on them. + */ + static struct boot_arm_vector_table * vt_cpy; + + vt_cpy = vt; +#if BSP_FEATURE_BSP_HAS_SP_MON + + /* Disable MSP monitoring */ + R_MPU_SPMON->SP[0].CTL = 0; +#endif +#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) + + /* Restore the Main Stack Pointer Limit register's reset value + * before passing execution to runtime firmware to make the + * bootloader transparent to it. + */ + __set_MSPLIM(0); +#endif + __set_MSP(vt->msp); + __DSB(); + __ISB(); + + boot_jump_to_next_image(vt_cpy->reset); +} diff --git a/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c b/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c new file mode 100644 index 000000000..3c9924103 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/crypto_keys.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2017-2019 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "tfm_common_config.h" + +#include "platform/include/tfm_plat_crypto_keys.h" +#include "platform/include/tfm_attest_hal.h" +#include +#include "psa/crypto_types.h" + +/* FIXME: Functions in this file should be implemented by platform vendor. For + * the security of the storage system, it is critical to use a hardware unique + * key. For the security of the attestation, it is critical to use a unique key + * pair and keep the private key is secret. + */ + +#define TFM_KEY_LEN_BYTES 16 + +static const uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] = +{ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \ + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +}; + +extern const psa_ecc_curve_t initial_attestation_curve_type; +extern const uint8_t initial_attestation_private_key[]; +extern const uint32_t initial_attestation_private_key_size; + +/** + * \brief Copy the key to the destination buffer + * + * \param[out] p_dst Pointer to buffer where to store the key + * \param[in] p_src Pointer to the key + * \param[in] size Length of the key + */ +static inline void copy_key (uint8_t * p_dst, const uint8_t * p_src, size_t size) +{ + uint32_t i; + + for (i = size; i > 0; i--) + { + *p_dst = *p_src; + p_src++; + p_dst++; + } +} + +enum tfm_plat_err_t tfm_plat_get_huk_derived_key (const uint8_t * label, + size_t label_size, + const uint8_t * context, + size_t context_size, + uint8_t * key, + size_t key_size) +{ + (void) label; + (void) label_size; + (void) context; + (void) context_size; + + if (key_size > TFM_KEY_LEN_BYTES) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + copy_key(key, sample_tfm_key, key_size); + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_get_initial_attest_key (uint8_t * key_buf, + uint32_t size, + struct ecc_key_t * ecc_key, + psa_ecc_curve_t * curve_type) +{ + uint32_t key_size = initial_attestation_private_key_size; + int rc; + + if (size < key_size) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Set the EC curve type which the key belongs to */ + *curve_type = initial_attestation_curve_type; + + /* Copy the private key to the buffer, it MUST be present */ + copy_key(key_buf, initial_attestation_private_key, key_size); + rc = 0; + + if (rc) + { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + ecc_key->priv_key = key_buf; + ecc_key->priv_key_size = key_size; + + ecc_key->pubx_key = NULL; + ecc_key->pubx_key_size = 0; + ecc_key->puby_key = NULL; + ecc_key->puby_key_size = 0; + + return TFM_PLAT_ERR_SUCCESS; +} + diff --git a/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h b/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h new file mode 100644 index 000000000..16905d7b5 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/inc/rm_tfm_port.h @@ -0,0 +1,33 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef RM_TFM_PORT_H +#define RM_TFM_PORT_H + +#include "tfm_common_config.h" +#include "tfm_arch.h" +#include "system_core_init.h" +#include "platform.h" + +extern void tfm_main(void); + +extern void R_BSP_WarmStart (bsp_warm_start_event_t event); + +#endif /* RM_TFM_PORT_H */ diff --git a/ra/fsp/src/rm_tfm_port/ra/nv_counters.c b/ra/fsp/src/rm_tfm_port/ra/nv_counters.c new file mode 100644 index 000000000..c80602996 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/nv_counters.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* NOTE: This API should be implemented by platform vendor. For the security of + * the secure storage system's and the bootloader's rollback protection etc. it + * is CRITICAL to use a internal (in-die) persistent memory for multiple time + * programmable (MTP) non-volatile counters or use a One-time Programmable (OTP) + * non-volatile counters solution. + * + * This dummy implementation assumes that the NV counters are the only data in + * the flash sector. To use it, one flash sector should be allocated exclusively + * for the NV counters. + * + * The current software dummy implementation is not resistant to asynchronous + * power failures and should not be used in production code. It is exclusively + * for testing purposes. + */ + +#include "platform/include/tfm_plat_nv_counters.h" + +#include +#include "Driver_Flash.h" +#include "flash_layout.h" + +/* Compilation time checks to be sure the defines are well defined */ +#ifndef TFM_NV_COUNTERS_AREA_ADDR +#error "TFM_NV_COUNTERS_AREA_ADDR must be defined in flash_layout.h" +#endif + +#ifndef TFM_NV_COUNTERS_AREA_SIZE +#error "TFM_NV_COUNTERS_AREA_SIZE must be defined in flash_layout.h" +#endif + +#ifndef TFM_NV_COUNTERS_SECTOR_ADDR +#error "TFM_NV_COUNTERS_SECTOR_ADDR must be defined in flash_layout.h" +#endif + +#ifndef TFM_NV_COUNTERS_SECTOR_SIZE +#error "TFM_NV_COUNTERS_SECTOR_SIZE must be defined in flash_layout.h" +#endif + +/* End of compilation time checks to be sure the defines are well defined */ + +#define NV_COUNTER_SIZE sizeof(uint32_t) +#define INIT_VALUE_SIZE NV_COUNTER_SIZE +#define NUM_NV_COUNTERS ((TFM_NV_COUNTERS_AREA_SIZE - INIT_VALUE_SIZE) \ + / NV_COUNTER_SIZE) + +#define NV_COUNTERS_INITIALIZED 0xC0DE0042U + +/** + * \brief Struct representing the NV counter data in flash. + */ +struct nv_counters_t { + uint32_t counters[NUM_NV_COUNTERS]; /**< Array of NV counters */ + uint32_t init_value; /**< Watermark to indicate if the NV counters have been + * initialised + */ +}; + +/* Import the CMSIS flash device driver */ +extern ARM_DRIVER_FLASH Driver_DFLASH; + +enum tfm_plat_err_t tfm_plat_init_nv_counter(void) +{ + int32_t err; + uint32_t i; + struct nv_counters_t nv_counters = {{0}, 0}; + + err = Driver_DFLASH.Initialize(NULL); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Read the NV counter area to be able to erase the sector and write later + * in the flash. + */ + err = Driver_DFLASH.ReadData(TFM_NV_COUNTERS_AREA_ADDR, &nv_counters, + TFM_NV_COUNTERS_AREA_SIZE); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + if (nv_counters.init_value == NV_COUNTERS_INITIALIZED) { + return TFM_PLAT_ERR_SUCCESS; + } + + /* Add watermark, at the end of the NV counters area, to indicate that NV + * counters have been initialized. + */ + nv_counters.init_value = NV_COUNTERS_INITIALIZED; + + /* Initialize all counters to 0 */ + for (i = 0; i < NUM_NV_COUNTERS; i++) { + nv_counters.counters[i] = 0; + } + + /* Erase sector before write in it */ + err = Driver_DFLASH.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Write in flash the in-memory NV counter content after modification */ + err = Driver_DFLASH.ProgramData(TFM_NV_COUNTERS_AREA_ADDR, &nv_counters, + TFM_NV_COUNTERS_AREA_SIZE); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id, + uint32_t size, uint8_t *val) +{ + int32_t err; + uint32_t flash_addr; + + if (size != NV_COUNTER_SIZE) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + flash_addr = TFM_NV_COUNTERS_AREA_ADDR + (counter_id * NV_COUNTER_SIZE); + + err = Driver_DFLASH.ReadData(flash_addr, val, NV_COUNTER_SIZE); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id, + uint32_t value) +{ + int32_t err; + struct nv_counters_t nv_counters = {{0}, 0}; + + /* Read the NV counter area to be able to erase the sector and write later + * in the flash. + */ + err = Driver_DFLASH.ReadData(TFM_NV_COUNTERS_AREA_ADDR, &nv_counters, + TFM_NV_COUNTERS_AREA_SIZE); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + if (value != nv_counters.counters[counter_id]) { + + if (value > nv_counters.counters[counter_id]) { + nv_counters.counters[counter_id] = value; + } else { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + /* Erase sector before write in it */ + err = Driver_DFLASH.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Write in flash the in-memory NV counter content after modification */ + err = Driver_DFLASH.ProgramData(TFM_NV_COUNTERS_AREA_ADDR, + &nv_counters, + TFM_NV_COUNTERS_AREA_SIZE); + if (err != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_increment_nv_counter( + enum tfm_nv_counter_t counter_id) +{ + uint32_t security_cnt; + enum tfm_plat_err_t err; + + err = tfm_plat_read_nv_counter(counter_id, + sizeof(security_cnt), + (uint8_t *)&security_cnt); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + if (security_cnt == UINT32_MAX) { + return TFM_PLAT_ERR_MAX_VALUE; + } + + return tfm_plat_set_nv_counter(counter_id, security_cnt + 1u); +} diff --git a/ra/fsp/src/rm_tfm_port/ra/partition/flash_layout.h b/ra/fsp/src/rm_tfm_port/ra/partition/flash_layout.h new file mode 100644 index 000000000..02bcf3145 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/partition/flash_layout.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#include "tfm_common_config.h" +#include "bsp_api.h" + +/* Size of a Secure and of a Non-secure image */ +#define FLASH_S_PARTITION_SIZE (CFG_FLASH_S_PARTITION_SIZE) /* S partition */ +#define FLASH_NS_PARTITION_SIZE (CFG_FLASH_NS_PARTITION_SIZE) /* NS partition*/ +#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \ + FLASH_NS_PARTITION_SIZE) ? \ + FLASH_S_PARTITION_SIZE : \ + FLASH_NS_PARTITION_SIZE) + +/* Sector size of the embedded flash hardware */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE) /* 32 KB */ +#define FLASH_TOTAL_SIZE (BSP_ROM_SIZE_BYTES) + +/* Sector size of the data flash hardware */ +#define DATA_FLASH_AREA_IMAGE_SECTOR_SIZE (BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE) /* 64 B */ + +/* Sector size of the QSPI flash hardware */ +#define QSPI_FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB */ +#define QSPI_FLASH_TOTAL_SIZE (0x800000) /* 8 MB */ + +/* Flash layout info for BL2 bootloader */ +#define FLASH_BASE_ADDRESS (0x00000000) + +#define DATA_FLASH_BASE_ADDRESS (BSP_FEATURE_FLASH_DATA_FLASH_START) + +/* Offset and size definitions of the flash partitions that are handled by the + * bootloader. The image swapping is done between IMAGE_PRIMARY and + * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image + * swapping. + */ +#define FLASH_AREA_BL2_OFFSET (0x0) +#define FLASH_AREA_BL2_SIZE (CFG_FLASH_AREA_BL2_SIZE) /* 64 KB */ + +#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) +/* Secure + Non-secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) +/* Secure + Non-secure secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) +/* Not used, only the Non-swapping firmware upgrade operation + * is supported. + */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#elif (MCUBOOT_IMAGE_NUMBER == 2) +/* Secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image primary slot */ +#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) +/* Secure image secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) +#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image secondary slot */ +#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE) +/* Not used, only the Non-swapping firmware upgrade operation + * is supported. + */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#else /* MCUBOOT_IMAGE_NUMBER > 2 */ +#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" +#endif /* MCUBOOT_IMAGE_NUMBER */ + +/* Not used, only the Non-swapping firmware upgrade operation + * is supported. The maximum number of status entries + * supported by the bootloader. + */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) + +/* Internal Trusted Storage (ITS) Service definitions (4 KB) */ +#define FLASH_ITS_AREA_OFFSET (CFG_DATA_FLASH_ITS_AREA_OFFSET) +#define FLASH_ITS_AREA_SIZE (CFG_DATA_FLASH_ITS_AREA_SIZE) + +/* NV Counters definitions */ +#define FLASH_NV_COUNTERS_AREA_OFFSET (CFG_DATA_FLASH_NV_COUNTERS_AREA_OFFSET) +#define FLASH_NV_COUNTERS_AREA_SIZE (CFG_DATA_FLASH_NV_COUNTERS_AREA_SIZE) + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_OFFSET (0x0) +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE + +#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \ + SECURE_IMAGE_MAX_SIZE) +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +/* Protected Storage (PS) Service definitions size is 20 KB. */ +#define QSPI_FLASH_BASE_ADDRESS (0x10000000) +#define FLASH_PS_AREA_OFFSET (0x0) +#define FLASH_PS_AREA_SIZE (5 * QSPI_FLASH_AREA_IMAGE_SECTOR_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +#define FLASH_DEV_NAME Driver_CFLASH + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define PS_FLASH_DEV_NAME Driver_QSPI_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +#define PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Dedicated flash area for PS */ +#define PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_SECTOR_SIZE QSPI_FLASH_AREA_IMAGE_SECTOR_SIZE +/* Number of PS_SECTOR_SIZE per block */ +#define PS_SECTORS_PER_BLOCK (0x1) +/* Specifies the smallest flash programmable unit in bytes */ +#define PS_FLASH_PROGRAM_UNIT (0x1) +/* The maximum asset size to be stored in the PS area */ +#define PS_MAX_ASSET_SIZE (2048) +/* The maximum number of assets to be stored in the PS area */ +#define PS_NUM_ASSETS (10) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define ITS_FLASH_DEV_NAME Driver_DFLASH + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +#define ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Dedicated flash area for ITS */ +#define ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_SECTOR_SIZE DATA_FLASH_AREA_IMAGE_SECTOR_SIZE +/* Number of ITS_SECTOR_SIZE per block */ +#define ITS_SECTORS_PER_BLOCK (CFG_TFM_ITS_SECTORS_PER_BLOCK) +/* Specifies the smallest flash programmable unit in bytes */ +#define ITS_FLASH_PROGRAM_UNIT (BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE) +/* The maximum asset size to be stored in the ITS area */ +#define ITS_MAX_ASSET_SIZE (CFG_TFM_ITS_MAX_ASSET_SIZE) +/* The maximum number of assets to be stored in the ITS area */ +#define ITS_NUM_ASSETS (CFG_TFM_ITS_NUM_ASSETS) + +/* NV Counters definitions */ +#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET +#define TFM_NV_COUNTERS_AREA_SIZE (FLASH_NV_COUNTERS_AREA_SIZE) +#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET +#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_NV_COUNTERS_AREA_SIZE + +/* Use eFlash 0 memory to store Code data */ +#define S_ROM_ALIAS_BASE (0x00000000) +#define NS_ROM_ALIAS_BASE (0x00000000) + +#define S_RAM_ALIAS_BASE (0x20000000) +#define NS_RAM_ALIAS_BASE (0x20000000) + +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE +#define TOTAL_RAM_SIZE (BSP_RAM_SIZE_BYTES) + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h b/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h new file mode 100644 index 000000000..2d9715aef --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/partition/region_defs.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +/* This size of buffer is big enough to store an attestation + * token produced by initial attestation service + */ +#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250) + +#ifdef BL2 +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) +#endif /* BL2 */ + +#ifndef LINK_TO_SECONDARY_PARTITION +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#else +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* Boot partition structure if MCUBoot is used: + * 0x0_0000 Bootloader header + * 0x0_0400 Image area + * 0x1_FC00 Trailer + */ +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ +#ifdef BL2 +#define BL2_HEADER_SIZE (0x400) /* 1 KB */ +#define BL2_TRAILER_SIZE (0x400) /* 1 KB */ +#else +/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */ +#define BL2_HEADER_SIZE (0x0) +#define BL2_TRAILER_SIZE (0x800) +#endif /* BL2 */ + +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#define IMAGE_NS_CODE_SIZE \ + (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) + +#define CMSE_VENEER_REGION_SIZE (0x400) + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET \ + (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (CFG_SECURE_RAM_SIZE) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* CMSE Veneers region */ +#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1) + +/* Non-secure regions */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (S_DATA_LIMIT + 1) +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for MPC and SAU configuration */ +#define NS_PARTITION_START \ + (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START \ + (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) + +#ifdef BL2 +/* Bootloader regions */ + +#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +#define BL2_DATA_START (S_RAM_ALIAS(0x0)) +#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE (0x400) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ + BOOT_TFM_SHARED_DATA_SIZE - 1) + +#endif /* __REGION_DEFS_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h b/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h new file mode 100644 index 000000000..c040eaaba --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/services/include/tfm_ioctl_api.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __TFM_IOCTL_API__ +#define __TFM_IOCTL_API__ + +#include +#include +#include +#include "tfm_api.h" +#include "tfm_platform_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum tfm_platform_ioctl_reqest_types_t { + TFM_PLATFORM_IOCTL_PIN_SERVICE, + TFM_PLATFORM_IOCTL_GPIO_SERVICE, + TFM_PLATFORM_IOCTL_FLASH_SERVICE, +}; + +/*! + * \enum tfm_gpio_service_type_t + * + * \brief GPIO service types (supported types may vary based on the platform) + */ +enum tfm_gpio_service_type_t { + TFM_GPIO_SERVICE_TYPE_INIT = 0, /*!< Init */ + TFM_GPIO_SERVICE_TYPE_PIN_CONFIG, /*!< Pin config */ + TFM_GPIO_SERVICE_TYPE_PIN_WRITE, /*!< Pin write */ + TFM_GPIO_SERVICE_TYPE_PIN_READ, /*!< Pin read */ + TFM_GPIO_SERVICE_TYPE_PORT_CONFIG, /*!< Port config */ + TFM_GPIO_SERVICE_TYPE_PORT_WRITE, /*!< Port write */ + TFM_GPIO_SERVICE_TYPE_PORT_READ, /*!< Port read */ + TFM_GPIO_SERVICE_TYPE_MAX = INT_MAX /*!< Max to force enum max size */ +}; + +/*! + * \enum tfm_flash_service_type_t + * + * \brief Flash service types + */ +enum tfm_flash_service_type_t { + TFM_FLASH_SERVICE_TYPE_INIT = 0, /*!< Init */ + TFM_FLASH_SERVICE_TYPE_ERASE, /*!< Flash erase */ + TFM_FLASH_SERVICE_TYPE_WRITE, /*!< Flash write */ + TFM_FLASH_SERVICE_TYPE_MAX = INT_MAX /*!< Max to force enum max size */ +}; + +/*! + * \struct tfm_gpio_service_args_t + * + * \brief Argument list for each platform GPIO service + */ +struct tfm_gpio_service_args_t { + enum tfm_gpio_service_type_t type; + union { + struct gpio_config_args { /*!< TFM_GPIO_SERVICE_TYPE_PIN_CONFIG || + TFM_GPIO_SERVICE_TYPE_PORT_CONFIG */ + uint32_t pin_num_or_mask; + uint32_t direction; + } gpio_config; + struct gpio_write_args { /*!< TFM_GPIO_SERVICE_TYPE_PIN_WRITE || + TFM_GPIO_SERVICE_TYPE_PORT_WRITE */ + uint32_t pin_num_or_mask; + uint32_t value; + } gpio_write; + struct gpio_read_args { /*!< TFM_GPIO_SERVICE_TYPE_PIN_READ || + TFM_GPIO_SERVICE_TYPE_PORT_READ */ + uint32_t pin_num_or_mask; + } gpio_read; + } u; +}; + +/*! + * \struct tfm_flash_service_args_t + * + * \brief Argument list for each platform Flash service + */ +struct tfm_flash_service_args_t { + enum tfm_flash_service_type_t type; + union { + struct flash_erase_args { /*!< TFM_FLASH_SERVICE_TYPE_ERASE */ + uint32_t addr; + uint32_t count; + } flash_erase; + struct flash_write_args { /*!< TFM_FLASH_SERVICE_TYPE_WRITE */ + uint32_t src_addr; + uint32_t flash_addr; + uint32_t count; + } flash_write; + } u; +}; + +/*! + * \struct tfm_gpio_service_out_t + * + * \brief Output list for each GPIO platform service + */ +struct tfm_gpio_service_out_t { + union { + uint32_t result; /*!< Generic result */ + struct gpio_read_result { /*!< TFM_GPIO_SERVICE_TYPE_PIN_READ || + TFM_GPIO_SERVICE_TYPE_PORT_READ */ + uint32_t result; + uint32_t data; + } gpio_read_result; + } u; +}; + +/*! + * \struct tfm_flash_service_out_t + * + * \brief Output list for each FLASH platform service + */ +struct tfm_flash_service_out_t { + union { + int32_t result; /*!< Generic result */ + struct flash_blank_check_result { /*!< TFM_FLASH_SERVICE_TYPE_BLANK_CHECK */ + int32_t result; + uint32_t blank_check_result; + } flash_blank_check_result; + } u; +}; + +/*! + * \enum tfm_pin_service_type_t + * + * \brief Pin service types + */ +enum tfm_pin_service_type_t { + TFM_PIN_SERVICE_TYPE_SET_ALTFUNC = 0, /*!< Set alternate function type */ + TFM_PIN_SERVICE_TYPE_SET_DEFAULT_IN, /*!< Set default in function type */ + TFM_PIN_SERVICE_TYPE_SET_PIN_MODE, /*!< Set pin mode function type */ + TFM_PIN_SERVICE_TYPE_MAX = INT_MAX /*!< Max to force enum max size */ +}; + +/*! + * \struct tfm_pin_service_args_t + * + * \brief Argument list for each platform pin service + */ +struct tfm_pin_service_args_t { + enum tfm_pin_service_type_t type; + union { + struct set_altfunc { /*!< TFM_PIN_SERVICE_TYPE_SET_ALTFUNC */ + uint32_t alt_func; + uint64_t pin_mask; + } set_altfunc; + struct set_default_in { /*!< TFM_PIN_SERVICE_TYPE_SET_DEFAULT_IN */ + uint32_t alt_func; + uint32_t pin_value; + bool default_in_value; + } set_default_in; + struct set_pin_mode { /*!< TFM_PIN_SERVICE_TYPE_SET_PIN_MODE */ + uint64_t pin_mask; + uint32_t pin_mode; + } set_pin_mode; + } u; +}; + +/*! + * \brief Sets pin alternate function for the given pins + * + * \param[in] alt_func Alternate function to set (allowed values vary + * based on the platform) + * \param[in] pin_mask Pin mask of the selected pins + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_set_pin_alt_func(uint32_t alt_func, uint64_t pin_mask, + uint32_t *result); + +/*! + * \brief Sets default in value to use when the alternate function is not + * selected for the pin + * + * \param[in] alt_func Alternate function to use (allowed values vary + * based on the platform) + * \param[in] pin_value Pin value to use + * \param[in] default_in_value Default in value to set + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_set_pin_default_in(uint32_t alt_func, uint32_t pin_value, + bool default_in_value, uint32_t *result); + +/*! + * \brief Sets pin mode for the selected pins + * + * \param[in] pin_mask Pin mask of the selected pins + * \param[in] pin_mode Pin mode to set for the selected pins + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_set_pin_mode(uint64_t pin_mask, uint32_t pin_mode, + uint32_t *result); + +/*! + * \brief Initializes GPIO module + * + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t tfm_platform_gpio_init(uint32_t *result); + +/*! + * \brief Configures a GPIO pin as input or output + * + * \param[in] pin_num Pin number of the selected pin + * \param[in] direction Direction of the pin: 0 for input, 1 for output + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_gpio_pin_config(uint32_t pin_num, uint32_t direction, + uint32_t *result); + +/*! + * \brief Sets state of a selected GPIO pin + * + * \param[in] pin_num Pin number of the selected pin + * \param[in] value Value to set for the pin + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_gpio_pin_write(uint32_t pin_num, uint32_t value, uint32_t *result); + +/*! + * \brief Reads state of a selected GPIO pin + * + * \param[in] pin_num Pin number of the selected pin + * \param[in,out] data Bit value read from the IO pin + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_gpio_pin_read(uint32_t pin_num, uint32_t *data, uint32_t *result); + +/*! + * \brief Configures GPIO pins as input or output + * + * \param[in] pin_mask Pin mask of the selected pins + * \param[in] direction Direction of the pin: 0 for input, 1 for output + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_gpio_port_config(uint32_t pin_mask, uint32_t direction, + uint32_t *result); + +/*! + * \brief Sets state of a selected GPIO pins + * + * \param[in] pin_mask Pin mask of the selected pins + * \param[in] value Value mask to set for the pins + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_gpio_port_write(uint32_t pin_mask, uint32_t value, + uint32_t *result); + +/*! + * \brief Reads state of a selected GPIO pins + * + * \param[in] pin_mask Pin mask of the selected pins + * \param[in,out] data Bit value mask read from the IO pins + * \param[out] result Return error value + * + * \return Returns values as specified by tfm_platform_err_t + */ +enum tfm_platform_err_t +tfm_platform_gpio_port_read(uint32_t pin_mask, uint32_t *data, + uint32_t *result); + +enum tfm_platform_err_t +tfm_platform_flash_write(uint32_t *data, uint32_t flash_address, + uint32_t count, int32_t *result); + +enum tfm_platform_err_t +tfm_platform_flash_erase(uint32_t address, uint32_t count, int32_t *result); + +enum tfm_platform_err_t +tfm_platform_flash_init(int32_t *result); + + +#ifdef __cplusplus +} +#endif + +#endif /* __TFM_IOCTL_API__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/services/src/tfm_ioctl_s_api.c b/ra/fsp/src/rm_tfm_port/ra/services/src/tfm_ioctl_s_api.c new file mode 100644 index 000000000..b191305f4 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/services/src/tfm_ioctl_s_api.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include "tfm_platform_api.h" +#include "tfm_ioctl_api.h" + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_set_pin_alt_func(uint32_t alt_func, uint64_t pin_mask, + uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_pin_service_args_t args; + + if (result == NULL) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + args.type = TFM_PIN_SERVICE_TYPE_SET_ALTFUNC; + args.u.set_altfunc.alt_func = alt_func; + args.u.set_altfunc.pin_mask = pin_mask; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)result; + out_vec.len = sizeof(*result); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_PIN_SERVICE, &in_vec, &out_vec); + + if (ret != PSA_SUCCESS) { + return TFM_PLATFORM_ERR_SYSTEM_ERROR; + } + + return TFM_PLATFORM_ERR_SUCCESS; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_set_pin_default_in(uint32_t alt_func, uint32_t pin_value, + bool default_in_value, uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_pin_service_args_t args; + + if (result == NULL) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + args.type = TFM_PIN_SERVICE_TYPE_SET_DEFAULT_IN; + args.u.set_default_in.alt_func = alt_func; + args.u.set_default_in.pin_value = pin_value; + args.u.set_default_in.default_in_value = default_in_value; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)result; + out_vec.len = sizeof(*result); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_PIN_SERVICE, &in_vec, &out_vec); + + if (ret != PSA_SUCCESS) { + return TFM_PLATFORM_ERR_SYSTEM_ERROR; + } + + return TFM_PLATFORM_ERR_SUCCESS; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_set_pin_mode(uint64_t pin_mask, uint32_t pin_mode, + uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_pin_service_args_t args; + + if (result == NULL) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + args.type = TFM_PIN_SERVICE_TYPE_SET_PIN_MODE; + args.u.set_pin_mode.pin_mask = pin_mask; + args.u.set_pin_mode.pin_mode = pin_mode; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)result; + out_vec.len = sizeof(*result); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_PIN_SERVICE, &in_vec, &out_vec); + + if (ret != PSA_SUCCESS) { + return TFM_PLATFORM_ERR_SYSTEM_ERROR; + } + + return TFM_PLATFORM_ERR_SUCCESS; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t tfm_platform_gpio_init(uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_INIT; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.result; + return ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_gpio_pin_config(uint32_t pin_num, uint32_t direction, + uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_PIN_CONFIG; + args.u.gpio_config.pin_num_or_mask = pin_num; + args.u.gpio_config.direction = direction; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.result; + return ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_gpio_pin_write(uint32_t pin_num, uint32_t value, uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_PIN_WRITE; + args.u.gpio_write.pin_num_or_mask = pin_num; + args.u.gpio_write.value = value; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.result; + return ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_gpio_pin_read(uint32_t pin_num, uint32_t *data, uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_PIN_READ; + args.u.gpio_read.pin_num_or_mask = pin_num; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.gpio_read_result.result; + *data = out.u.gpio_read_result.data; + return ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_gpio_port_config(uint32_t pin_mask, uint32_t direction, + uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_PORT_CONFIG; + args.u.gpio_config.pin_num_or_mask = pin_mask; + args.u.gpio_config.direction = direction; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.result; + return ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_gpio_port_write(uint32_t pin_mask, uint32_t value, + uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_PORT_WRITE; + args.u.gpio_write.pin_num_or_mask = pin_mask; + args.u.gpio_write.value = value; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.result; + return ret; +} + +__attribute__((section("SFN"))) +enum tfm_platform_err_t +tfm_platform_gpio_port_read(uint32_t pin_mask, uint32_t *data, uint32_t *result) +{ + psa_status_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_gpio_service_args_t args; + struct tfm_gpio_service_out_t out; + + args.type = TFM_GPIO_SERVICE_TYPE_PORT_READ; + args.u.gpio_read.pin_num_or_mask = pin_mask; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_GPIO_SERVICE, + &in_vec, + &out_vec); + + *result = out.u.gpio_read_result.result; + *data = out.u.gpio_read_result.data; + return ret; +} + diff --git a/ra/fsp/src/rm_tfm_port/ra/services/src/tfm_platform_system.c b/ra/fsp/src/rm_tfm_port/ra/services/src/tfm_platform_system.c new file mode 100644 index 000000000..4fa4bdd0c --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/services/src/tfm_platform_system.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "tfm_platform_system.h" +#include "platform_description.h" +#include "target_cfg.h" +#include "psa/client.h" +#include "tfm_ioctl_api.h" +#include "Driver_Flash.h" +#include "region_defs.h" + +/** + * \brief Flash busy values flash status \ref ARM_FLASH_STATUS + */ +enum +{ + DRIVER_STATUS_IDLE = 0u, + DRIVER_STATUS_BUSY +}; + +extern ARM_DRIVER_FLASH Driver_CFLASH; + +void tfm_platform_hal_system_reset(void) +{ + __disable_irq(); + + NVIC->ICPR[0] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[1] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[2] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[3] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[4] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[5] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[6] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[7] = UINT32_MAX; /* Clear all pending interrupts */ + + NVIC_SystemReset(); +} + +static enum tfm_platform_err_t +tfm_platform_hal_flash_service_write(struct tfm_flash_service_args_t *args, + struct tfm_flash_service_out_t *out) +{ + out->u.result = 0; + uint32_t flash_address = args->u.flash_write.flash_addr; + uint32_t count = args->u.flash_write.count; + uint32_t * source_address = (uint32_t *) args->u.flash_write.src_addr; + uint32_t * checked_source_address = cmse_check_pointed_object (source_address, CMSE_AU_NONSECURE); + + if ((flash_address < SECONDARY_PARTITION_START) || ((flash_address + count) > (TOTAL_ROM_SIZE - 1)) || + (checked_source_address != source_address)) + { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + out->u.result = Driver_CFLASH.ProgramData(flash_address, source_address, count); + return TFM_PLATFORM_ERR_SUCCESS; +} + +static enum tfm_platform_err_t +tfm_platform_hal_flash_service_erase(struct tfm_flash_service_args_t *args, + struct tfm_flash_service_out_t *out) +{ + ARM_FLASH_INFO *info; + info = Driver_CFLASH.GetInfo(); + uint32_t address = args->u.flash_erase.addr; + uint32_t sector_size = info->sector_size; + address = address & ~(sector_size - 1); + uint32_t size = ((args->u.flash_erase.count) * sector_size); + + if ((address < SECONDARY_PARTITION_START) || ((address + size) > (TOTAL_ROM_SIZE))) + { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + for(uint32_t i=0; i < args->u.flash_erase.count; i++) + { + out->u.result |= Driver_CFLASH.EraseSector(address); + address += sector_size; + } + + return TFM_PLATFORM_ERR_SUCCESS; +} + +static enum tfm_platform_err_t +tfm_platform_hal_flash_service(const psa_invec *in_vec, + const psa_outvec *out_vec) +{ + struct tfm_flash_service_args_t *args; + struct tfm_flash_service_out_t *out; + + if (in_vec->len != sizeof(struct tfm_flash_service_args_t) || + out_vec->len != sizeof(struct tfm_flash_service_out_t)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + ARM_FLASH_STATUS status = Driver_CFLASH.GetStatus(); + if (status.busy != DRIVER_STATUS_IDLE) + { + return TFM_PLATFORM_ERR_SYSTEM_ERROR; + } + + args = (struct tfm_flash_service_args_t *)in_vec->base; + out = (struct tfm_flash_service_out_t *)out_vec->base; + switch (args->type) { + case TFM_FLASH_SERVICE_TYPE_INIT: + out->u.result = Driver_CFLASH.Initialize(NULL); + break; + case TFM_FLASH_SERVICE_TYPE_ERASE: + return tfm_platform_hal_flash_service_erase(args, out); + break; + case TFM_FLASH_SERVICE_TYPE_WRITE: + return tfm_platform_hal_flash_service_write(args, out); + break; + default: + out->u.result = 1; + break; + } + + return TFM_PLATFORM_ERR_SUCCESS; +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + switch (request) { + case TFM_PLATFORM_IOCTL_PIN_SERVICE: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + case TFM_PLATFORM_IOCTL_GPIO_SERVICE: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + case TFM_PLATFORM_IOCTL_FLASH_SERVICE: + return tfm_platform_hal_flash_service(in_vec, out_vec); + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } +} + diff --git a/ra/fsp/src/rm_tfm_port/ra/spm_hal.c b/ra/fsp/src/rm_tfm_port/ra/spm_hal.c new file mode 100644 index 000000000..d02b22897 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/spm_hal.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "cmsis.h" +#include "tfm_spm_hal.h" +#include "spm_api.h" +#include "tfm_platform_core_api.h" +#include "target_cfg.h" +#include "bsp_api.h" +#include "mpu_armv8m_drv.h" +#include "region_defs.h" +#include "secure_utilities.h" +#include "region.h" + +/* Get address of memory regions to configure MPU */ +extern const struct memory_region_limits memory_regions; + +struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE }; + +#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT +#define MPU_REGION_VENEERS 0 +#define MPU_REGION_TFM_UNPRIV_CODE 1 +#define MPU_REGION_TFM_UNPRIV_DATA 2 +#define MPU_REGION_NS_STACK 3 +#define PARTITION_REGION_RO 4 +#define PARTITION_REGION_RW_STACK 5 +#define PARTITION_REGION_PERIPH_START 6 +#define PARTITION_REGION_PERIPH_MAX_NUM 2 + +uint32_t periph_num_count = 0; +#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ + +enum tfm_plat_err_t tfm_spm_hal_init_isolation_hw(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_spm_hal_configure_default_isolation( + uint32_t partition_idx, + const struct tfm_spm_partition_platform_data_t *platform_data) +{ + bool privileged = tfm_is_partition_privileged(partition_idx); +#if defined(CONFIG_TFM_ENABLE_MEMORY_PROTECT) && (TFM_LVL != 1) + struct mpu_armv8m_region_cfg_t region_cfg; +#endif + + if (!platform_data) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + +#if defined(CONFIG_TFM_ENABLE_MEMORY_PROTECT) && (TFM_LVL != 1) + if (!privileged) { + region_cfg.region_nr = PARTITION_REGION_PERIPH_START + + periph_num_count; + periph_num_count++; + if (periph_num_count >= PARTITION_REGION_PERIPH_MAX_NUM) { + return TFM_PLAT_ERR_MAX_VALUE; + } + region_cfg.region_base = platform_data->periph_start; + region_cfg.region_limit = platform_data->periph_limit; + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER; + + mpu_armv8m_disable(&dev_mpu_s); + + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) + != MPU_ARMV8M_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE, + HARDFAULT_NMI_ENABLE); + } +#endif /* defined(CONFIG_TFM_ENABLE_MEMORY_PROTECT) && (TFM_LVL != 1) */ + + return TFM_PLAT_ERR_SUCCESS; +} + +#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT +REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base); +REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit); +REGION_DECLARE(Image$$, TFM_UNPRIV_DATA, $$RW$$Base); +REGION_DECLARE(Image$$, TFM_UNPRIV_DATA, $$ZI$$Limit); +REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); +REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); +REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); +REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); +REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); +REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + +static enum spm_err_t tfm_spm_mpu_init(void) +{ + struct mpu_armv8m_region_cfg_t region_cfg; + + mpu_armv8m_clean(&dev_mpu_s); + + /* Veneer region */ + region_cfg.region_nr = MPU_REGION_VENEERS; + region_cfg.region_base = memory_regions.veneer_base; + region_cfg.region_limit = memory_regions.veneer_limit; + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK; + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) { + return SPM_ERR_INVALID_CONFIG; + } + + /* TFM Core unprivileged code region */ + region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE; + region_cfg.region_base = + (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base); + region_cfg.region_limit = + (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit); + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK; + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) { + return SPM_ERR_INVALID_CONFIG; + } + + /* TFM Core unprivileged data region */ + region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA; + region_cfg.region_base = + (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_DATA, $$RW$$Base); + region_cfg.region_limit = + (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_DATA, $$ZI$$Limit); + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER; + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) { + return SPM_ERR_INVALID_CONFIG; + } + + /* NSPM PSP */ + region_cfg.region_nr = MPU_REGION_NS_STACK; + region_cfg.region_base = + (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); + region_cfg.region_limit = + (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit); + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER; + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) { + return SPM_ERR_INVALID_CONFIG; + } + + /* RO region */ + region_cfg.region_nr = PARTITION_REGION_RO; + region_cfg.region_base = + (uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_START, $$Base); + region_cfg.region_limit = + (uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_END, $$Base); + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK; + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) { + return SPM_ERR_INVALID_CONFIG; + } + + /* RW, ZI and stack as one region */ + region_cfg.region_nr = PARTITION_REGION_RW_STACK; + region_cfg.region_base = + (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_START, $$Base); + region_cfg.region_limit = + (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_END, $$Base); + region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX; + region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV; + region_cfg.attr_sh = MPU_ARMV8M_SH_NONE; + region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER; + if (mpu_armv8m_region_enable(&dev_mpu_s, ®ion_cfg) != MPU_ARMV8M_OK) { + return SPM_ERR_INVALID_CONFIG; + } + + mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE, + HARDFAULT_NMI_ENABLE); + + return SPM_ERR_OK; +} + +enum tfm_plat_err_t tfm_spm_hal_setup_isolation_hw(void) +{ + if (tfm_spm_mpu_init() != SPM_ERR_OK) { + ERROR_MSG("Failed to set up initial MPU configuration! Halting."); + return TFM_PLAT_ERR_SYSTEM_ERR; + } + return TFM_PLAT_ERR_SUCCESS; +} +#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ + +uint32_t tfm_spm_hal_get_ns_VTOR(void) +{ + return memory_regions.non_secure_code_start; +} + +uint32_t tfm_spm_hal_get_ns_MSP(void) +{ + return *((uint32_t *)memory_regions.non_secure_code_start); +} + +uint32_t tfm_spm_hal_get_ns_entry_point(void) +{ + return *((uint32_t *)(memory_regions.non_secure_code_start+ 4)); +} + +enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line, + uint32_t priority) +{ + uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS); + NVIC_SetPriority(irq_line, quantized_priority); + return TFM_PLAT_ERR_SUCCESS; +} + +void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line) +{ + NVIC_ClearPendingIRQ(irq_line); +} + +void tfm_spm_hal_enable_irq(IRQn_Type irq_line) +{ + NVIC_EnableIRQ(irq_line); +} + +void tfm_spm_hal_disable_irq(IRQn_Type irq_line) +{ + NVIC_DisableIRQ(irq_line); +} + +enum irq_target_state_t tfm_spm_hal_set_irq_target_state( + IRQn_Type irq_line, + enum irq_target_state_t target_state) +{ + uint32_t result; + + if (target_state == TFM_IRQ_TARGET_STATE_SECURE) { + result = NVIC_ClearTargetState(irq_line); + } else { + result = NVIC_SetTargetState(irq_line); + } + + if (result) { + return TFM_IRQ_TARGET_STATE_NON_SECURE; + } else { + return TFM_IRQ_TARGET_STATE_SECURE; + } +} + +enum tfm_plat_err_t tfm_spm_hal_enable_fault_handlers(void) +{ + return enable_fault_handlers(); +} + +enum tfm_plat_err_t tfm_spm_hal_system_reset_cfg(void) +{ + return system_reset_cfg(); +} + +void tfm_spm_hal_system_reset(void) +{ + __disable_irq(); + + NVIC->ICPR[0] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[1] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[2] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[3] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[4] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[5] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[6] = UINT32_MAX; /* Clear all pending interrupts */ + NVIC->ICPR[7] = UINT32_MAX; /* Clear all pending interrupts */ + + NVIC_SystemReset(); +} + +enum tfm_plat_err_t tfm_spm_hal_init_debug(void) +{ + return init_debug(); +} + +enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_target_state_cfg(void) +{ + return nvic_interrupt_target_state_cfg(); +} + +enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_enable(void) +{ + return nvic_interrupt_enable(); +} diff --git a/ra/fsp/src/rm_tfm_port/ra/target_cfg.c b/ra/fsp/src/rm_tfm_port/ra/target_cfg.c new file mode 100644 index 000000000..0db040372 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/target_cfg.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2018 Arm Limited + * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "bsp_api.h" +#include "target_cfg.h" +#include "Driver_Common.h" +#include "platform_description.h" +#include "platform_irq.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "region.h" +#include +#include /* for debugging printfs */ + +/* The section names come from the scatter file */ +REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); +REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base); +REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit); +#ifdef BL2 +REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); +#endif /* BL2 */ + +const struct memory_region_limits memory_regions = { + .non_secure_code_start = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + BL2_HEADER_SIZE, + + .non_secure_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), + + .non_secure_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + NS_PARTITION_SIZE - 1, + + .veneer_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base), + + .veneer_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit), + +#ifdef BL2 + .secondary_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), + + .secondary_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + + SECONDARY_PARTITION_SIZE - 1, +#endif /* BL2 */ +}; + +/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, + * otherwise the processor ignores the write. + */ +#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) + +#define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \ + NIDEN_SEL_STATUS | DBGEN_SEL_STATUS) + +/* Platform data structures: + * + * struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart = { + * UART1_NS_BASE, + * UART1_NS_BASE + 0xFFF + * }; + * + * struct tfm_spm_partition_platform_data_t tfm_peripheral_timer0 = { + * TIMER0_S_BASE, + * TIMER1_S_BASE -1 + * }; + * + */ + + +enum tfm_plat_err_t enable_fault_handlers(void) +{ + /* Explicitly set secure fault priority to the highest */ + NVIC_SetPriority(SecureFault_IRQn, 0); + + /* Enables BUS, MEM, USG and Secure faults */ + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk + | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_MEMFAULTENA_Msk + | SCB_SHCSR_SECUREFAULTENA_Msk; + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t system_reset_cfg(void) +{ + + uint32_t reg_value = SCB->AIRCR; + + /* Clear SCB_AIRCR_VECTKEY value */ + reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); + + /* Enable system reset request only to the secure world */ + reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk); + + SCB->AIRCR = reg_value; + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t init_debug(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Interrupt target state is set in bsp_irq_cfg() in bsp_irq.c */ + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + +/* + * NVIC_EnableIRQ(FF_TEST_UART_IRQ); + */ + + return TFM_PLAT_ERR_SUCCESS; +} + diff --git a/ra/fsp/src/rm_tfm_port/ra/target_cfg.h b/ra/fsp/src/rm_tfm_port/ra/target_cfg.h new file mode 100644 index 000000000..3fb217ac7 --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/target_cfg.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2018-2020 Arm Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TARGET_CFG_H__ +#define __TARGET_CFG_H__ +#include +#include "tfm_peripherals_def.h" +#include "tfm_common_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define TFM_DRIVER_STDIO Driver_USART + + +/** + * \brief Store the addresses of memory regions + */ +struct memory_region_limits { + uint32_t non_secure_code_start; + uint32_t non_secure_partition_base; + uint32_t non_secure_partition_limit; + uint32_t veneer_base; + uint32_t veneer_limit; +#ifdef BL2 + uint32_t secondary_partition_base; + uint32_t secondary_partition_limit; +#endif /* BL2 */ +}; + +/** + * \brief Holds the data necessary to do isolation for a specific peripheral. + */ +struct tfm_spm_partition_platform_data_t +{ + uint32_t periph_start; + uint32_t periph_limit; +}; + + +/** + * \brief Enables the fault handlers and sets priorities. + * + * \return Returns values as specified by tfm_plat_err_t + */ +enum tfm_plat_err_t enable_fault_handlers(void); + +/** + * \brief Configures the system reset request properties + * + * \return Returns values as specified by tfm_plat_err_t + */ +enum tfm_plat_err_t system_reset_cfg(void); + +/** + * \brief Configures the system debug properties. + * + * \return Returns values as specified by tfm_plat_err_t + */ +enum tfm_plat_err_t init_debug(void); + +/** + * \brief Configures all external interrupts to target the + * NS state, apart for the ones associated to secure + * peripherals (plus MPC and PPC) + * + * \return Returns values as specified by tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); + +/** + * \brief This function enable the interrupts associated + * to the secure peripherals (plus the isolation boundary violation + * interrupts) + * + * \return Returns values as specified by tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_enable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __TARGET_CFG_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/ra/tfm_initial_attestation_key_material.c b/ra/fsp/src/rm_tfm_port/ra/tfm_initial_attestation_key_material.c new file mode 100644 index 000000000..9b2e3c9ad --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/tfm_initial_attestation_key_material.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "tfm_common_config.h" + +#include "tfm_plat_defs.h" +#include "tfm_plat_crypto_keys.h" +#include "psa/crypto_types.h" +#include "psa/crypto_values.h" + +#ifdef SYMMETRIC_INITIAL_ATTESTATION +/* + * This file contains the hard coded version of the secret key for HMAC. + * + * A HMAC-SHA256 key is 32 bytes long. + * + * This key is used to sign the initial attestation token in COSE_Mac0. + * The secret key is stored in raw format, without any encoding(ASN.1, COSE). + * + * ####### DO NOT USE THIS KEY IN PRODUCTION ####### + */ + +/* HMAC-SHA256 by default */ +const psa_algorithm_t tfm_attest_hmac_sign_alg = PSA_ALG_HMAC(PSA_ALG_SHA_256); + +/* Symmetric initial attestation key in raw format, without any encoding. + * It is used in HMAC-SHA256. + * It MUST be present on the device. + */ +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_INITIAL_ATTESTATION") +const uint8_t initial_attestation_hmac_sha256_key[] = +{ + 0xA9, 0xB4, 0x54, 0xB2, 0x6D, 0x6F, 0x90, 0xA4, + 0xEA, 0x31, 0x19, 0x35, 0x64, 0xCB, 0xA9, 0x1F, + 0xEC, 0x6F, 0x9A, 0x00, 0x2A, 0x7D, 0xC0, 0x50, + 0x4B, 0x92, 0xA1, 0x93, 0x71, 0x34, 0x58, 0x5F +}; + +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_INITIAL_ATTESTATION") +const size_t initial_attestation_hmac_sha256_key_size = + sizeof(initial_attestation_hmac_sha256_key); + +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_INITIAL_ATTESTATION") +const char *initial_attestation_kid = "kid@trustedfirmware.example"; +#else /* SYMMETRIC_INITIAL_ATTESTATION */ +/* + * This file contains the hard coded version of the ECDSA P-256 secret key in: + * platform/ext/common/template/tfm_initial_attestation_key.pem + * + * As a P-256 key, the private key is 32 bytes long. + * + * This key is used to sign the initial attestation token. + * The secret key is stored in raw format, without any encoding(ASN.1, COSE). + * + * ####### DO NOT USE THIS KEY IN PRODUCTION ####### + */ + +/* Type of the EC curve which the key belongs to, in PSA curve ID form */ +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_INITIAL_ATTESTATION") +const psa_ecc_curve_t initial_attestation_curve_type = PSA_ECC_CURVE_SECP_R1; + +/* Initial attestation private key in raw format, without any encoding. + * It belongs to the ECDSA P-256 curve. + * It MUST be present on the device. + */ +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_INITIAL_ATTESTATION") +const uint8_t initial_attestation_private_key[] = +{ + 0xA9, 0xB4, 0x54, 0xB2, 0x6D, 0x6F, 0x90, 0xA4, + 0xEA, 0x31, 0x19, 0x35, 0x64, 0xCB, 0xA9, 0x1F, + 0xEC, 0x6F, 0x9A, 0x00, 0x2A, 0x7D, 0xC0, 0x50, + 0x4B, 0x92, 0xA1, 0x93, 0x71, 0x34, 0x58, 0x5F +}; + +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_INITIAL_ATTESTATION") +const uint32_t initial_attestation_private_key_size = + sizeof(initial_attestation_private_key); +#endif /* SYMMETRIC_INITIAL_ATTESTATION */ diff --git a/ra/fsp/src/rm_tfm_port/ra/tfm_peripherals_def.h b/ra/fsp/src/rm_tfm_port/ra/tfm_peripherals_def.h new file mode 100644 index 000000000..a320a55bc --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/ra/tfm_peripherals_def.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __TFM_PERIPHERALS_DEF_H__ +#define __TFM_PERIPHERALS_DEF_H__ + +#include "platform_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Platform data is defined here: + * + * #define TFM_TIMER0_IRQ (TIMER0_IRQn) + * #define TFM_TIMER1_IRQ (TIMER1_IRQn) + * #define FF_TEST_UART_IRQ (UART1_Tx_IRQn) + * #define FF_TEST_UART_IRQ_Handler UARTTX1_Handler + * + * struct tfm_spm_partition_platform_data_t; + * + * extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart; + * extern struct tfm_spm_partition_platform_data_t tfm_peripheral_timer0; + + * #define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) + * #define TFM_PERIPHERAL_TIMER0 (&tfm_peripheral_timer0) + * + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __TFM_PERIPHERALS_DEF_H__ */ diff --git a/ra/fsp/src/rm_tfm_port/tfm_common_config.h b/ra/fsp/src/rm_tfm_port/tfm_common_config.h new file mode 100644 index 000000000..b383909ac --- /dev/null +++ b/ra/fsp/src/rm_tfm_port/tfm_common_config.h @@ -0,0 +1,26 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef TFM_COMMON_CONFIG_H +#define TFM_COMMON_CONFIG_H + +#include "rm_tfm_cfg.h" + +#endif /* TFM_COMMON_CONFIG_H */ diff --git a/ra/fsp/src/rm_touch/rm_touch.c b/ra/fsp/src/rm_touch/rm_touch.c index 57b4fc1d3..7fa08acc7 100644 --- a/ra/fsp/src/rm_touch/rm_touch.c +++ b/ra/fsp/src/rm_touch/rm_touch.c @@ -72,6 +72,16 @@ #define TOUCH_MONITOR_BUTTON_SIZE (7) #define TOUCH_MONITOR_SLIDER_SIZE (4) #define TOUCH_MONITOR_WHEEL_SIZE (4) + #if (TOUCH_CFG_PAD_ENABLE) + #define TOUCH_MONITOR_PAD_ELEMENT_SIZE (2) + #define TOUCH_MONITOR_PAD_TOUCH_MAX (10) + #define TOUCH_MONITOR_PAD_COORD_SIZE (4) + #define TOUCH_MONITOR_PAD_SIZE (11) + #define TOUCH_MONITOR_PAD_TOTAL_SIZE (TOUCH_MONITOR_PAD_COORD_SIZE * TOUCH_MONITOR_PAD_TOUCH_MAX) + \ + (TOUCH_MONITOR_PAD_SIZE) + #else + #define TOUCH_MONITOR_PAD_TOTAL_SIZE (0) + #endif #define TOUCH_MONITOR_FOOTER_SIZE (1) #define TOUCH_MONITOR_BUFFER_SIZE ((TOUCH_MONITOR_HEADER_SIZE * TOUCH_MONITOR_BLOCK_MAX) + \ (TOUCH_MONITOR_SELF_ELEMENT_SIZE * CTSU_CFG_NUM_SELF_ELEMENTS) + \ @@ -82,6 +92,7 @@ (TOUCH_MONITOR_SLIDER_SIZE * TOUCH_CFG_NUM_SLIDERS) + \ (TOUCH_MONITOR_WHEAD_SIZE * TOUCH_MONITOR_BLOCK_MAX) + \ (TOUCH_MONITOR_WHEEL_SIZE * TOUCH_CFG_NUM_WHEELS) + \ + (TOUCH_MONITOR_PAD_TOTAL_SIZE) + \ TOUCH_MONITOR_FOOTER_SIZE) #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) @@ -104,6 +115,7 @@ #define TOUCH_UART_RESPONSE_BIT (0x80) #define TOUCH_UART_RESPONSE_ERROR_BIT (0xA0) #define TOUCH_UART_RESPONSE_MONITOR (0xA1) + #define TOUCH_UART_RESPONSE_MONITOR2 (0xA2) /* Write Request Type */ #define TOUCH_UART_WRITE_DRIFT (0x01) @@ -118,6 +130,11 @@ #define TOUCH_UART_WRITE_CTSUSO (0x0A) #define TOUCH_UART_WRITE_CTSUSNUM (0x0B) #define TOUCH_UART_WRITE_CTSUSDPA (0x0C) + #define TOUCH_UART_WRTIE_PAD_THRESHOLD (0x0D) + #define TOUCH_UART_WRTIE_PAD_RX_PIXEL (0x0E) + #define TOUCH_UART_WRTIE_PAD_TX_PIXEL (0x0F) + #define TOUCH_UART_WRTIE_PAD_MAX_TOUCH (0x10) + #define TOUCH_UART_WRTIE_PAD_DRIFT (0x11) /* Method Number Maximum */ #define TOUCH_UART_INSTANCE_MAX (32) @@ -141,12 +158,32 @@ #define TOUCH_UART_CTSUSDPA_SHIFT (8) #endif #endif + +/* Method Number Maximum */ + #define TOUCH_UART_INSTANCE_MAX (32) +#endif +#if (TOUCH_CFG_PAD_ENABLE) + #define TOUCH_MAP_X (3) + #define TOUCH_MAP_Y (3) + #define TOUCH_PAD_NOT_TOUCH (0xFFFF) + #define TOUCH_PAD_TEMP_VALUE_OVERFLOW_BIT (0x8000) + #define TOUCH_PAD_MONITOR_TOUCH_NUM_MAX (10) #endif /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ +#if (TOUCH_CFG_PAD_ENABLE) +typedef struct st_touch_pad_drift_id +{ + uint16_t i; + uint16_t j; + uint16_t num_rx; + uint16_t num_tx; +} touch_pad_drift_id_t; +#endif + /*********************************************************************************************************************** * Private function prototypes **********************************************************************************************************************/ @@ -216,11 +253,22 @@ static uint8_t g_touch_wheel_index = 0; static uint16_t g_touch_wheel_position[TOUCH_CFG_NUM_WHEELS]; static uint16_t g_touch_wheel_threshold[TOUCH_CFG_NUM_WHEELS]; #endif +#if (TOUCH_CFG_PAD_ENABLE) +static uint16_t g_touch_pad_rx_coordinate[TOUCH_PAD_MONITOR_TOUCH_NUM_MAX]; +static uint16_t g_touch_pad_tx_coordinate[TOUCH_PAD_MONITOR_TOUCH_NUM_MAX]; +static uint16_t g_touch_pad_num_touch; +static uint16_t g_touch_pad_threshold; +static uint16_t g_touch_pad_rx_pixsel; +static uint16_t g_touch_pad_tx_pixsel; +static uint8_t g_touch_pad_max_touch; +static uint16_t g_touch_pad_drift_count; +static int32_t g_touch_pad_drift_buf[CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX]; +static uint16_t g_touch_pad_base[CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX]; +#endif #if TOUCH_CFG_MONITOR_ENABLE static volatile uint8_t g_touch_monitor_buf[TOUCH_MONITOR_BUFFER_SIZE]; static uint8_t g_touch_monitor_id; static uint16_t g_touch_monitor_size[TOUCH_MONITOR_BLOCK_MAX]; - #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) static touch_instance_ctrl_t * gp_touch_ctrl_list[TOUCH_UART_INSTANCE_MAX]; static uart_instance_t * gp_touch_uart_instance; @@ -245,6 +293,7 @@ const touch_api_t g_touch_on_ctsu = .open = RM_TOUCH_Open, .scanStart = RM_TOUCH_ScanStart, .dataGet = RM_TOUCH_DataGet, + .padDataGet = RM_TOUCH_PadDataGet, .close = RM_TOUCH_Close, .versionGet = RM_TOUCH_VersionGet, }; @@ -272,7 +321,8 @@ const touch_api_t g_touch_on_ctsu = fsp_err_t RM_TOUCH_Open (touch_ctrl_t * const p_ctrl, touch_cfg_t const * const p_cfg) { touch_instance_ctrl_t * p_instance_ctrl = (touch_instance_ctrl_t *) p_ctrl; -#if ((TOUCH_CFG_NUM_BUTTONS != 0) || (TOUCH_CFG_NUM_SLIDERS != 0) || (TOUCH_CFG_NUM_WHEELS != 0)) +#if ((TOUCH_CFG_NUM_BUTTONS != 0) || (TOUCH_CFG_NUM_SLIDERS != 0) || (TOUCH_CFG_NUM_WHEELS != 0) || \ + (TOUCH_CFG_PAD_ENABLE)) uint8_t id; #endif fsp_err_t err = FSP_SUCCESS; @@ -380,6 +430,30 @@ fsp_err_t RM_TOUCH_Open (touch_ctrl_t * const p_ctrl, touch_cfg_t const * const *(p_instance_ctrl->winfo.p_threshold + id) = p_cfg->p_wheels[id].threshold; } #endif +#if (TOUCH_CFG_PAD_ENABLE) + p_instance_ctrl->pinfo.p_rx_coordinate = &g_touch_pad_rx_coordinate[0]; + p_instance_ctrl->pinfo.p_tx_coordinate = &g_touch_pad_tx_coordinate[0]; + p_instance_ctrl->pinfo.p_num_touch = &g_touch_pad_num_touch; + p_instance_ctrl->pinfo.p_threshold = &g_touch_pad_threshold; + p_instance_ctrl->pinfo.p_rx_pixel = &g_touch_pad_rx_pixsel; + p_instance_ctrl->pinfo.p_tx_pixel = &g_touch_pad_tx_pixsel; + p_instance_ctrl->pinfo.p_max_touch = &g_touch_pad_max_touch; + p_instance_ctrl->pinfo.p_drift_buf = &g_touch_pad_drift_buf[0]; + p_instance_ctrl->pinfo.p_drift_count = &g_touch_pad_drift_count; + p_instance_ctrl->pinfo.p_base_buf = &g_touch_pad_base[0]; + + *(p_instance_ctrl->pinfo.p_threshold) = p_cfg->p_pad->threshold; + *(p_instance_ctrl->pinfo.p_rx_pixel) = p_cfg->p_pad->rx_pixel; + *(p_instance_ctrl->pinfo.p_tx_pixel) = p_cfg->p_pad->tx_pixel; + *(p_instance_ctrl->pinfo.p_max_touch) = p_cfg->p_pad->max_touch; + p_instance_ctrl->pinfo.num_drift = p_cfg->p_pad->num_drift; + + for (id = 0; id < (CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX); id++) + { + *(p_instance_ctrl->pinfo.p_drift_buf + id) = 0; + } + *(p_instance_ctrl->pinfo.p_drift_count) = 0; +#endif if (FSP_SUCCESS == err) { @@ -424,6 +498,15 @@ fsp_err_t RM_TOUCH_Open (touch_ctrl_t * const p_ctrl, touch_cfg_t const * const (TOUCH_MONITOR_WHEEL_SIZE * p_cfg->num_wheels)); } #endif + #if (TOUCH_CFG_PAD_ENABLE) + if (CTSU_MODE_MUTUAL_CFC_SCAN == (p_instance_ctrl->p_ctsu_instance->p_cfg->md)) + { + g_touch_monitor_size[num] = + (uint16_t) (g_touch_monitor_size[num] + TOUCH_MONITOR_PAD_SIZE + + (TOUCH_MONITOR_PAD_ELEMENT_SIZE * p_cfg->p_pad->num_elements)); + } + #endif + g_touch_monitor_size[num] = (uint16_t) (g_touch_monitor_size[num] + TOUCH_MONITOR_HEADER_SIZE + TOUCH_MONITOR_FOOTER_SIZE); @@ -650,106 +733,710 @@ fsp_err_t RM_TOUCH_DataGet (touch_ctrl_t * const p_ctrl, { if (TOUCH_UART_MONITOR_NONE == g_touch_uart_monitor_num) { - #endif + for (i = 0; i < p_instance_ctrl->p_touch_cfg->number; i++) + { + index = (uint16_t) (index + g_touch_monitor_size[i]); + } + } + + #else for (i = 0; i < p_instance_ctrl->p_touch_cfg->number; i++) { index = (uint16_t) (index + g_touch_monitor_size[i]); } + #endif + g_touch_monitor_buf[index++] = g_touch_monitor_id; + g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->number; + if ((CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->p_ctsu_instance->p_cfg->md) || + (CTSU_MODE_CURRENT_SCAN == p_instance_ctrl->p_ctsu_instance->p_cfg->md)) + { + g_touch_monitor_buf[index++] = 0x00; + element_num = p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx; + g_touch_monitor_buf[index++] = element_num; + for (i = 0; i < element_num; i++) + { + g_touch_monitor_buf[index++] = (uint8_t) (data[i]); + g_touch_monitor_buf[index++] = (uint8_t) (data[i] >> 8); + } + } + else + { + g_touch_monitor_buf[index++] = 0x01; + element_num = (uint8_t) (p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx * + p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_tx); + g_touch_monitor_buf[index++] = element_num; + for (i = 0; i < (element_num * 2); i++) + { + g_touch_monitor_buf[index++] = (uint8_t) (data[i]); + g_touch_monitor_buf[index++] = (uint8_t) (data[i] >> 8); + } + } + + #if (TOUCH_CFG_NUM_BUTTONS != 0) + if (0 < p_instance_ctrl->p_touch_cfg->num_buttons) + { + g_touch_monitor_buf[index++] = 0x00; + g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->num_buttons; + for (i = 0; i < p_instance_ctrl->p_touch_cfg->num_buttons; i++) + { + g_touch_monitor_buf[index++] = (uint8_t) ((p_instance_ctrl->binfo.status >> i) & 0x01); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_reference[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_reference[i] >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_threshold[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_threshold[i] >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_hysteresis[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_hysteresis[i] >> 8); + } + } + #endif + #if (TOUCH_CFG_NUM_SLIDERS != 0) + if (0 < p_instance_ctrl->p_touch_cfg->num_sliders) + { + g_touch_monitor_buf[index++] = 0x01; + g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->num_sliders; + for (i = 0; i < p_instance_ctrl->p_touch_cfg->num_sliders; i++) + { + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_position[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_position[i] >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_threshold[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_threshold[i] >> 8); + } + } + #endif + #if (TOUCH_CFG_NUM_WHEELS != 0) + if (0 < p_instance_ctrl->p_touch_cfg->num_wheels) + { + g_touch_monitor_buf[index++] = 0x02; + g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->num_wheels; + for (i = 0; i < p_instance_ctrl->p_touch_cfg->num_wheels; i++) + { + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_position[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_position[i] >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_threshold[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_threshold[i] >> 8); + } + } + #endif + g_touch_monitor_buf[index++] = g_touch_monitor_id++; #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) + } + + if (!g_touch_uart_transmit_flag && (p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num)) + { + g_touch_monitor_buf[index++] = TOUCH_UART_FOOTER; + g_touch_monitor_buf[2] = (uint8_t) (index); + g_touch_monitor_buf[3] = (uint8_t) (index >> 8); + g_touch_uart_transmit_flag = 1; + gp_touch_uart_instance->p_api->write(gp_touch_uart_instance->p_ctrl, + (uint8_t const * const) &g_touch_monitor_buf, + index); + } + #endif +#endif + + return FSP_SUCCESS; } + +/*******************************************************************************************************************//** + * @brief This function gets the current position of pad is being pressed. + * Implements @ref touch_api_t::padDataGet , g_touch_on_ctsu + * + * @retval FSP_SUCCESS Successfully data decoded. + * @retval FSP_ERR_ASSERTION Null pointer. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. + **********************************************************************************************************************/ +fsp_err_t RM_TOUCH_PadDataGet (touch_ctrl_t * const p_ctrl, + uint16_t * p_pad_rx_coordinate, + uint16_t * p_pad_tx_coordinate, + uint8_t * p_pad_num_touch) +{ + fsp_err_t err = FSP_SUCCESS; + touch_instance_ctrl_t * p_instance_ctrl = (touch_instance_ctrl_t *) p_ctrl; +#if (TOUCH_CFG_PAD_ENABLE) + static uint16_t count_get[CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX * 2]; + static uint8_t base_flag = 0; + uint16_t i; + uint16_t j; + uint8_t loop; + int32_t max_diff; + uint16_t max_x; + uint16_t max_y; + int32_t x_parameter; + int32_t y_parameter; + int16_t heat_map[TOUCH_MAP_X * TOUCH_MAP_Y]; + uint8_t use_map[TOUCH_MAP_X * TOUCH_MAP_Y]; + uint8_t num_x; + uint8_t num_y; + uint16_t pitch_x; + uint16_t pitch_y; + int16_t tmp_count; + uint16_t tmp_value; + int32_t tmp_diff; + int32_t tmp_heat; + int32_t tmp_x1; /* Work for calculating x parameter1 */ + int32_t tmp_x2; /* Work for calculating x parameter2 */ + int32_t tmp_x3; /* Work for calculating x parameter3 */ + int32_t tmp_x4; /* Work for calculating x parameter4 */ + int32_t tmp_y1; /* Work for calculating y parameter1 */ + int32_t tmp_y2; /* Work for calculating y parameter2 */ + int32_t tmp_y3; /* Work for calculating y parameter3 */ + int32_t tmp_y4; /* Work for calculating y parameter4 */ + uint16_t second_half; + int32_t drift_diff; + uint8_t max_touch; /* number of max touch */ + #if (TOUCH_CFG_MONITOR_ENABLE) + uint16_t index = 0; + uint8_t element_num = 0; #endif - g_touch_monitor_buf[index++] = g_touch_monitor_id; - g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->number; - if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->p_ctsu_instance->p_cfg->md) + #if (TOUCH_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_pad_rx_coordinate); + FSP_ASSERT(p_pad_tx_coordinate); + FSP_ASSERT(p_pad_num_touch); + TOUCH_ERROR_RETURN(TOUCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + + /* initialize touch number */ + *p_pad_num_touch = 0; + + /* check for max touch */ + if (*(p_instance_ctrl->pinfo.p_max_touch) > ((CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX) / 9)) { - g_touch_monitor_buf[index++] = 0x00; - element_num = p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx; - g_touch_monitor_buf[index++] = element_num; - for (i = 0; i < element_num; i++) + max_touch = (CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX) / 9; + } + else + { + max_touch = *(p_instance_ctrl->pinfo.p_max_touch); + } + + /* Get local variable (TS number & data pinch) */ + num_x = p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx; + num_y = p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_tx; + second_half = (uint16_t) (num_x * num_y); + + pitch_x = (uint16_t) (*(p_instance_ctrl->pinfo.p_rx_pixel) / num_x); + pitch_y = (uint16_t) (*(p_instance_ctrl->pinfo.p_tx_pixel) / num_y); + + /* Data get */ + err = p_instance_ctrl->p_ctsu_instance->p_api->dataGet(p_instance_ctrl->p_ctsu_instance->p_ctrl, count_get); + FSP_ERROR_RETURN(FSP_ERR_CTSU_SCANNING != err, FSP_ERR_CTSU_SCANNING); + + if (FSP_SUCCESS != err) + { + return err; + } + + /* make difference value = secondary - primary */ + for (i = 0; i < CTSU_CFG_NUM_CFC * CTSU_CFG_NUM_CFC_TX; i++) + { + /* save to buffer in the first half */ + count_get[i] = (uint16_t) (count_get[(i * 2) + 1] - count_get[i * 2]); + } + + /* Data get section */ + if (!base_flag) + { + /* format base value , changing the order */ + for (j = 0; j < num_x; j++) { - g_touch_monitor_buf[index++] = (uint8_t) (data[i]); - g_touch_monitor_buf[index++] = (uint8_t) (data[i] >> 8); + for (i = 0; i < num_y; i++) + { + *(p_instance_ctrl->pinfo.p_base_buf + j + (i * num_x)) = + (count_get[*(p_instance_ctrl->p_touch_cfg->p_pad->p_elem_index_rx + j) + + (*(p_instance_ctrl->p_touch_cfg->p_pad->p_elem_index_tx + i) * num_x)]); + } } + + base_flag = 1; } else { - g_touch_monitor_buf[index++] = 0x01; - element_num = (uint8_t) (p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx * - p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_tx); - g_touch_monitor_buf[index++] = element_num; - for (i = 0; i < (element_num * 2); i++) + /* format difference value */ + for (j = 0; j < num_x; j++) { - g_touch_monitor_buf[index++] = (uint8_t) (data[i]); - g_touch_monitor_buf[index++] = (uint8_t) (data[i] >> 8); + for (i = 0; i < num_y; i++) + { + /* get count data ,and changing the order */ + tmp_value = count_get[*(p_instance_ctrl->p_touch_cfg->p_pad->p_elem_index_rx + j) + + (*(p_instance_ctrl->p_touch_cfg->p_pad->p_elem_index_tx + i) * num_x)]; + + /* make difference from base value */ + tmp_diff = *(p_instance_ctrl->pinfo.p_base_buf + j + (i * num_x)) - tmp_value; + + /* save difference value to buffer in the second half */ + count_get[second_half + j + (i * num_x)] = (uint16_t) tmp_diff; + } } } - #if (TOUCH_CFG_NUM_BUTTONS != 0) - if (0 < p_instance_ctrl->p_touch_cfg->num_buttons) + /* Monitor part of ready */ + #if (TOUCH_CFG_MONITOR_ENABLE) + #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) + if (!g_touch_uart_transmit_flag && (p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num)) { - g_touch_monitor_buf[index++] = 0x00; - g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->num_buttons; - for (i = 0; i < p_instance_ctrl->p_touch_cfg->num_buttons; i++) + /* Monitor Data Notification */ + g_touch_monitor_buf[index++] = TOUCH_UART_HEADER; + g_touch_monitor_buf[index++] = TOUCH_UART_RESPONSE_MONITOR2; + g_touch_monitor_buf[index++] = 0; /* Temporarily input the size */ + g_touch_monitor_buf[index++] = 0; /* Temporarily input the size */ + } + + if (!g_touch_uart_transmit_flag && + ((p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num) || + (TOUCH_UART_MONITOR_NONE == g_touch_uart_monitor_num))) + { + if (TOUCH_UART_MONITOR_NONE == g_touch_uart_monitor_num) + { + for (i = 0; i < p_instance_ctrl->p_touch_cfg->number; i++) + { + index = (uint16_t) (index + g_touch_monitor_size[i]); + } + } + + if (!g_touch_uart_transmit_flag) { - g_touch_monitor_buf[index++] = (uint8_t) ((p_instance_ctrl->binfo.status >> i) & 0x01); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_reference[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_reference[i] >> 8); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_threshold[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_threshold[i] >> 8); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_hysteresis[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->binfo.p_hysteresis[i] >> 8); + g_touch_monitor_buf[index++] = g_touch_monitor_id; + g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->number; + + /* Pad data */ + g_touch_monitor_buf[index++] = 0x02; + element_num = (uint8_t) (p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx * + p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_tx); + g_touch_monitor_buf[index++] = element_num; } + + #else /* TOUCH_CFG_UART_MONITOR_SUPPORT */ + for (i = 0; i < p_instance_ctrl->p_touch_cfg->number; i++) + { + index = (uint16_t) (index + g_touch_monitor_size[i]); } - #endif - #if (TOUCH_CFG_NUM_SLIDERS != 0) - if (0 < p_instance_ctrl->p_touch_cfg->num_sliders) + + g_touch_monitor_buf[index++] = g_touch_monitor_id; + g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->number; + + /* Pad data */ + g_touch_monitor_buf[index++] = 0x02; + element_num = (uint8_t) (p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_rx * + p_instance_ctrl->p_touch_cfg->p_ctsu_instance->p_cfg->num_tx); + g_touch_monitor_buf[index++] = element_num; + #endif + + #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) + } + + if (!g_touch_uart_transmit_flag && + ((p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num) || + (TOUCH_UART_MONITOR_NONE == g_touch_uart_monitor_num))) { - g_touch_monitor_buf[index++] = 0x01; - g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->num_sliders; - for (i = 0; i < p_instance_ctrl->p_touch_cfg->num_sliders; i++) + #endif /* TOUCH_CFG_UART_MONITOR_SUPPORT */ + for (i = 0; i < element_num; i++) { - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_position[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_position[i] >> 8); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_threshold[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->sinfo.p_threshold[i] >> 8); + tmp_value = count_get[second_half + i]; + if (tmp_value & TOUCH_PAD_TEMP_VALUE_OVERFLOW_BIT) + { + tmp_value = 0; + } + + g_touch_monitor_buf[index++] = (uint8_t) (tmp_value); + g_touch_monitor_buf[index++] = (uint8_t) (tmp_value >> 8); } + + g_touch_monitor_buf[index++] = 0x03; /* id of Pad */ + g_touch_monitor_buf[index++] = 0x01; /* number of Pad */ + #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) } - #endif - #if (TOUCH_CFG_NUM_WHEELS != 0) - if (0 < p_instance_ctrl->p_touch_cfg->num_wheels) + #endif + #endif /* TOUCH_CFG_MONITOR_ENABLE */ + + if (base_flag) { - g_touch_monitor_buf[index++] = 0x02; - g_touch_monitor_buf[index++] = p_instance_ctrl->p_touch_cfg->num_wheels; - for (i = 0; i < p_instance_ctrl->p_touch_cfg->num_wheels; i++) + /* Get coordinate data for the Max touch */ + for (loop = 0; loop < max_touch; loop++) { - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_position[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_position[i] >> 8); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_threshold[i]); - g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->winfo.p_threshold[i] >> 8); + /* initialize heat-map variables */ + max_diff = 0; + max_y = 0; + max_x = 0; + + /* Clear heat map ,and initial use map */ + for (i = 0; i < (TOUCH_MAP_X * TOUCH_MAP_Y); i++) + { + heat_map[i] = 0; + use_map[i] = 1; + } + + /* Maximum value search */ + for (j = 0; j < (num_x); j++) + { + for (i = 0; i < (num_y); i++) + { + if ((int16_t) count_get[second_half + j + (i * num_x)] > max_diff) + { + max_diff = (int16_t) count_get[second_half + j + (i * num_x)]; + max_y = i; + max_x = j; + } + } + } + + /* make use map */ + if (0 == max_y) + { + /* If map position is Top. */ + use_map[0] = 0; + use_map[1] = 0; + use_map[2] = 0; + } + else if ((num_y - 1) == max_y) + { + /* If map position is Bottom. */ + use_map[6] = 0; + use_map[7] = 0; + use_map[8] = 0; + } + else + { + } + + if (0 == max_x) + { + /* If map position is Left. */ + use_map[0] = 0; + use_map[3] = 0; + use_map[6] = 0; + } + else if ((num_x - 1) == max_x) + { + /* If map position is Right. */ + use_map[2] = 0; + use_map[5] = 0; + use_map[8] = 0; + } + else + { + } + + /* make heat mapping */ + for (i = 0; i < TOUCH_MAP_X; i++) + { + for (j = 0; j < TOUCH_MAP_Y; j++) + { + if (use_map[j + (i * TOUCH_MAP_X)]) + { + heat_map[j + (i * TOUCH_MAP_X)] = + (int16_t) count_get[second_half + (max_x - 1 + j) + (max_y - 1 + i) * num_x]; + } + } + } + + /* get x value */ + /* Calculate right + bottom value. (x1/y1) */ + tmp_heat = heat_map[5] + heat_map[7]; + if (tmp_heat == 0) + { + /* When dividing by zero, set the calculation result to zero */ + tmp_x1 = 0; /* x parameter1 */ + tmp_y1 = 0; /* y parameter1 */ + } + else + { + tmp_x1 = (heat_map[8] * heat_map[5]) / tmp_heat; /* x parameter1 */ + tmp_y1 = (heat_map[8] * heat_map[7]) / tmp_heat; /* y parameter1 */ + } + + /* Calculate right + up value. (x2/y4) */ + tmp_heat = heat_map[5] + heat_map[1]; + if (tmp_heat == 0) + { + /* When dividing by zero, set the calculation result to zero */ + tmp_x2 = 0; /* x parameter2 */ + tmp_y4 = 0; /* y parameter4 */ + } + else + { + tmp_x2 = (heat_map[2] * heat_map[5]) / tmp_heat; /* x parameter2 */ + tmp_y4 = (heat_map[2] * heat_map[1]) / tmp_heat; /* y parameter4 */ + } + + /* Calculate left + up value. (x3/y3) */ + tmp_heat = heat_map[3] + heat_map[1]; + if (tmp_heat == 0) + { + /* When dividing by zero, set the calculation result to zero */ + tmp_x3 = 0; /* x parameter3 */ + tmp_y3 = 0; /* y parameter3 */ + } + else + { + tmp_x3 = (heat_map[0] * heat_map[3]) / tmp_heat; /* x parameter3 */ + tmp_y3 = (heat_map[0] * heat_map[1]) / tmp_heat; /* y parameter3 */ + } + + /* Calculate left + down value. (x4/y2) */ + tmp_heat = heat_map[3] + heat_map[7]; + if (tmp_heat == 0) + { + /* When dividing by zero, set the calculation result to zero */ + tmp_x4 = 0; /* x parameter4 */ + tmp_y2 = 0; /* y parameter2 */ + } + else + { + tmp_x4 = (heat_map[6] * heat_map[3]) / tmp_heat; /* x parameter4 */ + tmp_y2 = (heat_map[6] * heat_map[7]) / tmp_heat; /* y parameter2 */ + } + + if (heat_map[4] == 0) + { + x_parameter = 0; + } + else + { + /* x coordinate value calculation*/ + x_parameter = ((pitch_x / 2) * + (heat_map[5] + tmp_x1 + tmp_x2 - + heat_map[3] - tmp_x3 - tmp_x4) / + heat_map[4]); + } + + /* Fit to pitch */ + if (x_parameter > pitch_x / 2) + { + x_parameter = pitch_x / 2; + } + else if (x_parameter < -(pitch_x / 2)) + { + x_parameter = -(pitch_x / 2); + } + else + { + /* no operation */ + } + + /* Coordinate x value based on pitch */ + *(p_pad_rx_coordinate + loop) = (uint16_t) ((pitch_x * (max_x + 1) - pitch_x / 2) + x_parameter); + + /* get y value */ + if (heat_map[4] == 0) + { + y_parameter = 0; + } + else + { + /* y coordinate value calculation*/ + y_parameter = ((pitch_y / 2) * + (heat_map[7] + tmp_y1 + tmp_y2 - + heat_map[1] - tmp_y3 - tmp_y4) / + heat_map[4]); + } + + /* Fit to pitch */ + if (y_parameter > pitch_y / 2) + { + y_parameter = pitch_y / 2; + } + else if (y_parameter < -(pitch_y / 2)) + { + y_parameter = -(pitch_y / 2); + } + else + { + /* no operation */ + } + + /* Coordinate y value based on pitch */ + *(p_pad_tx_coordinate + loop) = (uint16_t) ((pitch_y * (max_y + 1) - pitch_y / 2) + y_parameter); + + /* touch check */ + if (max_diff >= *(p_instance_ctrl->pinfo.p_threshold)) + { + /* If touching ,then counter's being incremented */ + (*p_pad_num_touch)++; + + /* Clear heat map area */ + for (i = 0; i < TOUCH_MAP_X; i++) + { + for (j = 0; j < TOUCH_MAP_Y; j++) + { + if (use_map[i * TOUCH_MAP_X + j]) + { + count_get[second_half + (max_x - 1 + j) + (max_y - 1 + i) * num_x] = 0; + } + } + } + } + else + { + *(p_pad_rx_coordinate + loop) = TOUCH_PAD_NOT_TOUCH; + *(p_pad_tx_coordinate + loop) = TOUCH_PAD_NOT_TOUCH; + } + + if (loop < TOUCH_PAD_MONITOR_TOUCH_NUM_MAX) + { + *(p_instance_ctrl->pinfo.p_rx_coordinate + loop) = *(p_pad_rx_coordinate + loop); + *(p_instance_ctrl->pinfo.p_tx_coordinate + loop) = *(p_pad_tx_coordinate + loop); + + FSP_PARAMETER_NOT_USED(p_instance_ctrl->pinfo.p_rx_coordinate); + FSP_PARAMETER_NOT_USED(p_instance_ctrl->pinfo.p_tx_coordinate); + } + } + + /* the drift correction process. */ + if (0 < p_instance_ctrl->pinfo.num_drift) + { + if (0 == *p_pad_num_touch) + { + /* If not touching, drift correction counter's being incremented */ + (*(p_instance_ctrl->pinfo.p_drift_count))++; + + for (i = 0; i < num_y; i++) + { + for (j = 0; j < num_x; j++) + { + /* It is an addition for the drift correction average calculation */ + tmp_count = (int16_t) count_get[second_half + j + (i * num_x)]; + + *(p_instance_ctrl->pinfo.p_drift_buf + (j + (i * num_x))) += (int32_t) tmp_count; + + if (*(p_instance_ctrl->pinfo.p_drift_count) >= p_instance_ctrl->pinfo.num_drift) + { + drift_diff = (int32_t) (*(p_instance_ctrl->pinfo.p_drift_buf + j + (i * num_x)) / + *(p_instance_ctrl->pinfo.p_drift_count)); + + *(p_instance_ctrl->pinfo.p_base_buf + j + (i * num_x)) = + (uint16_t) ((int32_t) (*(p_instance_ctrl->pinfo.p_base_buf + j + (i * num_x))) - + drift_diff); + + /* Clear total value for the average */ + *(p_instance_ctrl->pinfo.p_drift_buf + (j + (i * num_x))) = 0; + } + } + } + + if (*(p_instance_ctrl->pinfo.p_drift_count) >= p_instance_ctrl->pinfo.num_drift) + { + /* Count clear */ + *(p_instance_ctrl->pinfo.p_drift_count) = 0; + } + } } } - #endif - g_touch_monitor_buf[index++] = g_touch_monitor_id++; - #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) + *(p_instance_ctrl->pinfo.p_num_touch) = *p_pad_num_touch; + + for (i = *p_pad_num_touch; i < TOUCH_PAD_MONITOR_TOUCH_NUM_MAX; i++) + { + g_touch_pad_rx_coordinate[i] = TOUCH_PAD_NOT_TOUCH; + g_touch_pad_tx_coordinate[i] = TOUCH_PAD_NOT_TOUCH; + } + + /* Monitor part of result */ + #if (TOUCH_CFG_MONITOR_ENABLE) + #if (TOUCH_CFG_UART_MONITOR_SUPPORT == 1) + if (!g_touch_uart_transmit_flag && + ((p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num) || + (TOUCH_UART_MONITOR_NONE == g_touch_uart_monitor_num))) + { + g_touch_monitor_buf[index++] = *p_pad_num_touch; /* number of touch */ + for (i = 0; i < TOUCH_PAD_MONITOR_TOUCH_NUM_MAX; i++) + { + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_rx_coordinate[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_rx_coordinate[i] >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_tx_coordinate[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_tx_coordinate[i] >> 8); + } + + g_touch_monitor_buf[index++] = (uint8_t) (*(p_instance_ctrl->pinfo.p_threshold)); + g_touch_monitor_buf[index++] = (uint8_t) ((*(p_instance_ctrl->pinfo.p_threshold)) >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (*(p_instance_ctrl->pinfo.p_rx_pixel)); + g_touch_monitor_buf[index++] = (uint8_t) ((*(p_instance_ctrl->pinfo.p_rx_pixel)) >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (*(p_instance_ctrl->pinfo.p_tx_pixel)); + g_touch_monitor_buf[index++] = (uint8_t) ((*(p_instance_ctrl->pinfo.p_tx_pixel)) >> 8); + g_touch_monitor_buf[index++] = (*(p_instance_ctrl->pinfo.p_max_touch)); + g_touch_monitor_buf[index++] = (p_instance_ctrl->pinfo.num_drift); + g_touch_monitor_buf[index++] = g_touch_monitor_id++; + + if (p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num) + { + g_touch_monitor_buf[index++] = TOUCH_UART_FOOTER; + g_touch_monitor_buf[2] = (uint8_t) (index); + g_touch_monitor_buf[3] = (uint8_t) (index >> 8); + g_touch_uart_transmit_flag = 1; + gp_touch_uart_instance->p_api->write(gp_touch_uart_instance->p_ctrl, + (uint8_t const * const) &g_touch_monitor_buf, + index); + } + } + + #else /* TOUCH_CFG_UART_MONITOR_SUPPORT */ + g_touch_monitor_buf[index++] = *p_pad_num_touch; /* number of touch */ + for (i = 0; i < TOUCH_PAD_MONITOR_TOUCH_NUM_MAX; i++) + { + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_rx_coordinate[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_rx_coordinate[i] >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_tx_coordinate[i]); + g_touch_monitor_buf[index++] = (uint8_t) (p_instance_ctrl->pinfo.p_tx_coordinate[i] >> 8); + } + + g_touch_monitor_buf[index++] = (uint8_t) (*(p_instance_ctrl->pinfo.p_threshold)); + g_touch_monitor_buf[index++] = (uint8_t) ((*(p_instance_ctrl->pinfo.p_threshold)) >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (*(p_instance_ctrl->pinfo.p_rx_pixel)); + g_touch_monitor_buf[index++] = (uint8_t) ((*(p_instance_ctrl->pinfo.p_rx_pixel)) >> 8); + g_touch_monitor_buf[index++] = (uint8_t) (*(p_instance_ctrl->pinfo.p_tx_pixel)); + g_touch_monitor_buf[index++] = (uint8_t) ((*(p_instance_ctrl->pinfo.p_tx_pixel)) >> 8); + g_touch_monitor_buf[index++] = (*(p_instance_ctrl->pinfo.p_max_touch)); + g_touch_monitor_buf[index++] = (p_instance_ctrl->pinfo.num_drift); + g_touch_monitor_buf[index++] = g_touch_monitor_id++; + #endif /* TOUCH_CFG_UART_MONITOR_SUPPORT */ + #endif /* TOUCH_CFG_MONITOR_ENABLE */ +#else /* TOUCH_CFG_PAD_ENABLE */ + #if (TOUCH_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_pad_rx_coordinate); + FSP_ASSERT(p_pad_tx_coordinate); + FSP_ASSERT(p_pad_num_touch); + TOUCH_ERROR_RETURN(TOUCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + #endif + FSP_PARAMETER_NOT_USED(p_pad_rx_coordinate); + FSP_PARAMETER_NOT_USED(p_pad_tx_coordinate); + FSP_PARAMETER_NOT_USED(p_pad_num_touch); + FSP_PARAMETER_NOT_USED(p_instance_ctrl); + FSP_PARAMETER_NOT_USED(FSP_ERR_CTSU_SCANNING); +#endif /* TOUCH_CFG_PAD_ENABLE */ + return err; } -if (!g_touch_uart_transmit_flag && (p_instance_ctrl->p_touch_cfg->number == g_touch_uart_monitor_num)) +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements touch_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t RM_TOUCH_CallbackSet (touch_ctrl_t * const p_api_ctrl, + void ( * p_callback)(touch_callback_args_t *), + void const * const p_context, + touch_callback_args_t * const p_callback_memory) { - g_touch_monitor_buf[index++] = TOUCH_UART_FOOTER; - g_touch_monitor_buf[2] = (uint8_t) (index); - g_touch_monitor_buf[3] = (uint8_t) (index >> 8); - g_touch_uart_transmit_flag = 1; - gp_touch_uart_instance->p_api->write(gp_touch_uart_instance->p_ctrl, - (uint8_t const * const) &g_touch_monitor_buf, - index); -} - #endif + fsp_err_t err = FSP_SUCCESS; + touch_instance_ctrl_t * p_ctrl = (touch_instance_ctrl_t *) p_api_ctrl; + +#if (TOUCH_CFG_PARAM_CHECKING_ENABLE == 1) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(TOUCH_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); #endif - return FSP_SUCCESS; + err = p_ctrl->p_ctsu_instance->p_api->callbackSet(p_ctrl->p_ctsu_instance->p_ctrl, + p_callback, + p_context, + p_callback_memory); + + return err; } /*******************************************************************************************************************//** @@ -762,7 +1449,7 @@ if (!g_touch_uart_transmit_flag && (p_instance_ctrl->p_touch_cfg->number == g_to fsp_err_t RM_TOUCH_Close (touch_ctrl_t * const p_ctrl) { touch_instance_ctrl_t * p_instance_ctrl = (touch_instance_ctrl_t *) p_ctrl; - fsp_err_t err = FSP_SUCCESS; + fsp_err_t err = FSP_SUCCESS; FSP_ASSERT(p_instance_ctrl); TOUCH_ERROR_RETURN(TOUCH_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); @@ -933,7 +1620,7 @@ void touch_button_on (touch_button_info_t * p_binfo, uint16_t value, uint8_t but /* ===== touch ON result ===== */ if (p_binfo->on_freq <= (*(p_binfo->p_on_count + button_id))) { - p_binfo->status |= (uint64_t) (1 << button_id); + p_binfo->status |= ((uint64_t) 1 << button_id); } else { @@ -946,7 +1633,7 @@ void touch_button_on (touch_button_info_t * p_binfo, uint16_t value, uint8_t but /* If reaching max_on_threshold, it makes result off and it revises a drift. */ if (p_binfo->cancel_freq <= (*(p_binfo->p_on_count + button_id))) { - p_binfo->status &= ~((uint64_t) (1 << button_id)); + p_binfo->status &= ~((uint64_t) 1 << button_id); *(p_binfo->p_on_count + button_id) = 0; *(p_binfo->p_reference + button_id) = value; } @@ -972,7 +1659,7 @@ void touch_button_off (touch_button_info_t * p_binfo, uint8_t button_id) /* ===== touch OFF result ===== */ if (p_binfo->off_freq <= (*(p_binfo->p_off_count + button_id))) { - p_binfo->status &= ~((uint64_t) (1 << button_id)); + p_binfo->status &= ~(((uint64_t) 1 << button_id)); } else { @@ -993,7 +1680,7 @@ void touch_button_drift (touch_button_info_t * p_binfo, uint16_t value, uint8_t if (0 != p_binfo->drift_freq) { /* In case of doing drift correction being and moreover On/Off judgment result 1=OFF */ - if (0 == (p_binfo->status & ((uint64_t) (1 << button_id)))) + if (0 == (p_binfo->status & ((uint64_t) 1 << button_id))) { /* It is an addition for the drift correction average calculation */ *(p_binfo->p_drift_buf + button_id) += value; @@ -1041,8 +1728,8 @@ void touch_button_drift (touch_button_info_t * p_binfo, uint16_t value, uint8_t void touch_slider_decode (touch_slider_info_t * p_sinfo, uint16_t * slider_data, uint8_t num_elements, uint8_t slider_id) { - uint8_t loop; - uint8_t max_data_num; + uint8_t loop; + uint8_t max_data_num; uint16_t d1; uint16_t d2; uint16_t d3; @@ -1167,8 +1854,8 @@ void touch_slider_decode (touch_slider_info_t * p_sinfo, uint16_t * slider_data, ***********************************************************************************************************************/ void touch_wheel_decode (touch_wheel_info_t * p_winfo, uint16_t * wheel_data, uint8_t num_elements, uint8_t wheel_id) { - uint8_t loop; - uint8_t max_data_num; + uint8_t loop; + uint8_t max_data_num; uint16_t d1; uint16_t d2; uint16_t d3; @@ -1263,10 +1950,10 @@ void touch_wheel_decode (touch_wheel_info_t * p_winfo, uint16_t * wheel_data, ui void touch_uart_callback (uart_callback_args_t * p_args) { ctsu_instance_ctrl_t * p_ctsu_ctrl; - uint16_t write_data; - uint16_t ctsuso; - uint8_t ctsusdpa; - uint8_t ctsusnum; + uint16_t write_data; + uint16_t ctsuso; + uint8_t ctsusdpa; + uint8_t ctsusnum; #if (BSP_FEATURE_CTSU_VERSION == 2) uint32_t * p_ctsuso; uint32_t * p_ctsusdpa; @@ -1277,8 +1964,8 @@ void touch_uart_callback (uart_callback_args_t * p_args) uint16_t * p_ctsusdpa; uint16_t * p_ctsusnum; #endif - uint8_t num; - uint8_t element; + uint8_t num; + uint8_t element; uint16_t index; if (NULL == gp_touch_uart_instance) @@ -1499,6 +2186,39 @@ void touch_uart_callback (uart_callback_args_t * p_args) break; } + #if (TOUCH_CFG_PAD_ENABLE) + + /* write command */ + case TOUCH_UART_WRTIE_PAD_THRESHOLD: + { + *gp_touch_ctrl_list[num]->pinfo.p_threshold = write_data; + break; + } + + case TOUCH_UART_WRTIE_PAD_RX_PIXEL: + { + *gp_touch_ctrl_list[num]->pinfo.p_rx_pixel = write_data; + break; + } + + case TOUCH_UART_WRTIE_PAD_TX_PIXEL: + { + *gp_touch_ctrl_list[num]->pinfo.p_tx_pixel = write_data; + break; + } + + case TOUCH_UART_WRTIE_PAD_MAX_TOUCH: + { + *gp_touch_ctrl_list[num]->pinfo.p_max_touch = (uint8_t) write_data; + break; + } + + case TOUCH_UART_WRTIE_PAD_DRIFT: + { + gp_touch_ctrl_list[num]->pinfo.num_drift = (uint8_t) write_data; + break; + } + #endif /* TOUCH_CFG_PAD_ENABLE */ default: { break; diff --git a/ra/fsp/src/rm_tz_context/tz_context.c b/ra/fsp/src/rm_tz_context/tz_context.c new file mode 100644 index 000000000..3a8595905 --- /dev/null +++ b/ra/fsp/src/rm_tz_context/tz_context.c @@ -0,0 +1,224 @@ +/*********************************************************************************************************************** + * Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/* This file is based on a template provided in ARM CMSIS_5: + * https://github.com/ARM-software/CMSIS_5/blob/5.6.0/CMSIS/Core/Template/ARMv8-M/tz_context.c */ + +/* UNCRUSTIFY-OFF */ + +#include "bsp_api.h" + +#if BSP_TZ_SECURE_BUILD + +#include "tz_context.h" +#include "rm_tz_context_cfg.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +/// MPU is not yet supported +#define RM_TZ_CONTEXT_CFG_MPU_ENABLE 0U + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint32_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/sizeof(uint32_t)] BSP_ALIGN_VARIABLE(8); +static uint32_t ProcessStackFreeSlot = UINT32_MAX; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +BSP_CMSE_NONSECURE_ENTRY +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = UINT32_MAX; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + +#if RM_TZ_CONTEXT_CFG_MPU_ENABLE + { + /* Configure thread mode to use PSP and to be unprivileged. */ + __set_CONTROL(0x03U); + } +#else + { + /* Configure thread mode to use PSP and to be privileged. */ + __set_CONTROL(0x02U); + } +#endif + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +BSP_CMSE_NONSECURE_ENTRY +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + FSP_PARAMETER_NOT_USED(module); // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == UINT32_MAX) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +BSP_CMSE_NONSECURE_ENTRY +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +BSP_CMSE_NONSECURE_ENTRY +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +BSP_CMSE_NONSECURE_ENTRY +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + __asm volatile ( + "MRS R1, PSP \n" /* r1 = PSP. */ + "VSTMDB R1!, {S0} \n" /* Trigger the deferred stacking of FPU registers. */ + "VLDMIA R1!, {S0} \n" /* Nullify the effect of the pervious statement. */ + ::: "r1", "memory" + ); + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} + +#endif diff --git a/ra/fsp/src/rm_vee_flash/rm_vee_flash.c b/ra/fsp/src/rm_vee_flash/rm_vee_flash.c index 00d067bb4..faa1f6fa9 100644 --- a/ra/fsp/src/rm_vee_flash/rm_vee_flash.c +++ b/ra/fsp/src/rm_vee_flash/rm_vee_flash.c @@ -114,6 +114,12 @@ typedef enum e_rm_vee_flash_refresh_refresh RM_VEE_FLASH_PRV_REFRESH_RECORD_OVFL } rm_vee_flash_refresh_refresh_t; +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * volatile rm_vee_flash_prv_ns_callback)(rm_vee_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile rm_vee_flash_prv_ns_callback)(rm_vee_callback_args_t * p_args); +#endif + /*********************************************************************************************************************** * External functions **********************************************************************************************************************/ @@ -215,6 +221,7 @@ fsp_err_t RM_VEE_FLASH_Open (rm_vee_ctrl_t * const p_api_ctrl, rm_vee_cfg_t cons FSP_ERROR_RETURN(2 <= p_cfg->num_segments, FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(BSP_DATA_FLASH_SIZE_BYTES >= p_cfg->total_size, FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(0 == (p_cfg->total_size % p_cfg->num_segments), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(0 == ((p_cfg->total_size / p_cfg->num_segments) % 4), FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(0 == (p_cfg->ref_data_size % RM_VEE_FLASH_DF_WRITE_SIZE), FSP_ERR_INVALID_ARGUMENT); #endif @@ -289,6 +296,14 @@ fsp_err_t RM_VEE_FLASH_Open (rm_vee_ctrl_t * const p_api_ctrl, rm_vee_cfg_t cons p_ctrl->ref_hdr.pad = 0; p_ctrl->ref_hdr.valid_code = RM_VEE_FLASH_VALID_CODE; +#if BSP_TZ_SECURE_BUILD + p_ctrl->callback_is_secure = true; +#endif + + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + p_ctrl->mode = RM_VEE_FLASH_PRV_MODE_NORMAL; p_ctrl->open = RM_VEE_FLASH_OPEN; @@ -608,6 +623,52 @@ fsp_err_t RM_VEE_FLASH_Format (rm_vee_ctrl_t * const p_api_ctrl, uint8_t const * return err; } +/*******************************************************************************************************************//** + * Updates the user callback with the option to provide memory for the callback argument structure. + * + * Implements @ref rm_vee_api_t::callbackSet. + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t RM_VEE_FLASH_CallbackSet (rm_vee_ctrl_t * const p_api_ctrl, + void ( * p_callback)(rm_vee_callback_args_t *), + void const * const p_context, + rm_vee_callback_args_t * const p_callback_memory) +{ + rm_vee_flash_instance_ctrl_t * p_ctrl = (rm_vee_flash_instance_ctrl_t *) p_api_ctrl; + +#if (RM_VEE_FLASH_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(RM_VEE_FLASH_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + p_ctrl->callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if (RM_VEE_FLASH_CFG_PARAM_CHECKING_ENABLE) + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + rm_vee_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(p_ctrl->callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ + p_ctrl->p_callback = p_callback; + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + /*******************************************************************************************************************//** * Get the current status of the driver. * @@ -1452,6 +1513,61 @@ static fsp_err_t rm_vee_start_seg_refresh (rm_vee_flash_instance_ctrl_t * const return err; } +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to the control block + * @param[in] p_args Pointer to arguments on stack + **********************************************************************************************************************/ +static void rm_vee_call_callback (rm_vee_flash_instance_ctrl_t * p_ctrl, rm_vee_callback_args_t * p_args) +{ + rm_vee_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + rm_vee_callback_args_t * p_args_memory = p_ctrl->p_callback_memory; + if (NULL == p_args_memory) + { + /* Use provided args struct on stack */ + p_args_memory = p_args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args_memory; + + /* Copy the stacked args to callback memory */ + *p_args_memory = *p_args; + } + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (p_ctrl->callback_is_secure) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args_memory); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + rm_vee_flash_prv_ns_callback p_callback = (rm_vee_flash_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args_memory); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args_memory); +#endif + + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + /*******************************************************************************************************************//** * This function is called at the interrupt level every time a flash operation completes. If this function * is called during VEE initialization, a global flag is set and the function exits immediately (driver is @@ -1659,13 +1775,13 @@ void rm_vee_flash_callback (flash_callback_args_t * p_args) rm_vee_flash_err_handle(p_ctrl, err); - if ((RM_VEE_FLASH_PRV_STATES_READY == p_ctrl->state) && (NULL != p_ctrl->p_cfg->p_callback)) + if ((RM_VEE_FLASH_PRV_STATES_READY == p_ctrl->state) && (NULL != p_ctrl->p_callback)) { rm_vee_callback_args_t args; rm_vee_state_get(p_ctrl, &args.state); - args.p_context = p_ctrl->p_cfg->p_context; - p_ctrl->p_cfg->p_callback(&args); + args.p_context = p_ctrl->p_context; + rm_vee_call_callback(p_ctrl, &args); } } diff --git a/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c b/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c index ee70f76d4..63dc900cb 100644 --- a/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c +++ b/ra/fsp/src/rm_wifi_onchip_silex/aws_secure_sockets.c @@ -28,6 +28,7 @@ #include "semphr.h" #include "limits.h" #include "rm_wifi_onchip_silex.h" +#include "rm_wifi_onchip_silex_cfg.h" /* Undefine the macro for Keil Compiler to avoid conflict: */ /* __PASTE macro redefinition [-Wmacro-redefinition] */ @@ -37,9 +38,11 @@ #endif #include "iot_secure_sockets.h" -#include "iot_tls.h" -#include "iot_pkcs11.h" -#include "iot_crypto.h" +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT + #include "iot_tls.h" + #include "iot_pkcs11.h" + #include "iot_crypto.h" +#endif #if defined(__ARMCC_VERSION) #pragma GCC diagnostic pop @@ -230,7 +233,7 @@ Socket_t SOCKETS_Socket (int32_t lDomain, int32_t lType, int32_t lProtocol) * * @return * * SOCKETS_ERROR_NONE if a connection is established. - * * If an error occured, a negative value is returned. + * * If an error occured, a negative value is returned. */ int32_t SOCKETS_Connect (Socket_t xSocket, SocketsSockaddr_t * pxAddress, Socklen_t xAddressLength) { @@ -240,9 +243,6 @@ int32_t SOCKETS_Connect (Socket_t xSocket, SocketsSockaddr_t * pxAddress, Sockle int32_t ret = SOCKETS_SOCKET_ERROR; SSOCKETContextPtr_t pxContext = (SSOCKETContextPtr_t) xSocket; /*lint !e9087 cast used for portability. */ - TLSParams_t xTLSParams = - {0}; - if ((pxContext->xSocket != SOCKETS_INVALID_SOCKET) && (pxAddress != NULL)) { ret = @@ -256,8 +256,10 @@ int32_t SOCKETS_Connect (Socket_t xSocket, SocketsSockaddr_t * pxAddress, Sockle } /* Negotiate TLS if requested. */ +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT if ((SOCKETS_ERROR_NONE == lStatus) && (pdTRUE == pxContext->xRequireTLS)) { + TLSParams_t xTLSParams = {0}; xTLSParams.ulSize = sizeof(xTLSParams); xTLSParams.pcDestination = pxContext->pcDestination; xTLSParams.pcServerCertificate = pxContext->pcServerCertificate; @@ -276,6 +278,7 @@ int32_t SOCKETS_Connect (Socket_t xSocket, SocketsSockaddr_t * pxAddress, Sockle } } } +#endif } else { @@ -302,7 +305,7 @@ int32_t SOCKETS_Connect (Socket_t xSocket, SocketsSockaddr_t * pxAddress, Sockle * buffer pointed to by pvBuffer) is returned. * * If a timeout occurred before data could be received then 0 is returned (timeout * is set using SOCKETS_SO_RCVTIMEO). - * * If an error occured, a negative value is returned. + * * If an error occured, a negative value is returned. */ int32_t SOCKETS_Recv (Socket_t xSocket, void * pvBuffer, size_t xBufferLength, uint32_t ulFlags) { @@ -312,13 +315,14 @@ int32_t SOCKETS_Recv (Socket_t xSocket, void * pvBuffer, size_t xBufferLength, u if ((xSocket != SOCKETS_INVALID_SOCKET) && (pvBuffer != NULL)) { pxContext->xRecvFlags = (BaseType_t) ulFlags; - +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT if (pdTRUE == pxContext->xRequireTLS) { /* Receive through TLS pipe, if negotiated. */ lStatus = TLS_Recv(pxContext->pvTLSContext, pvBuffer, xBufferLength); } else +#endif { /* Receive unencrypted. */ lStatus = prvNetworkRecv(pxContext, pvBuffer, xBufferLength); @@ -341,7 +345,7 @@ int32_t SOCKETS_Recv (Socket_t xSocket, void * pvBuffer, size_t xBufferLength, u * * @return * * On success, the number of bytes actually sent is returned. - * * If an error occured, a negative value is returned. + * * If an error occured, a negative value is returned. */ int32_t SOCKETS_Send (Socket_t xSocket, const void * pvBuffer, size_t xDataLength, uint32_t ulFlags) { @@ -352,12 +356,14 @@ int32_t SOCKETS_Send (Socket_t xSocket, const void * pvBuffer, size_t xDataLengt { pxContext->xSendFlags = (BaseType_t) ulFlags; +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT if (pdTRUE == pxContext->xRequireTLS) { /* Send through TLS pipe, if negotiated. */ lStatus = TLS_Send(pxContext->pvTLSContext, pvBuffer, xDataLength); } else +#endif { /* Send unencrypted. */ lStatus = prvNetworkSend(pxContext, pvBuffer, xDataLength); @@ -376,7 +382,7 @@ int32_t SOCKETS_Send (Socket_t xSocket, const void * pvBuffer, size_t xDataLengt * * @return * * If the operation was successful, 0 is returned. - * * If an error occured, a negative value is returned. + * * If an error occured, a negative value is returned. * */ int32_t SOCKETS_Shutdown (Socket_t xSocket, uint32_t ulHow) @@ -426,7 +432,7 @@ int32_t SOCKETS_Shutdown (Socket_t xSocket, uint32_t ulHow) * * @return * * On success, 0 is returned. - * * If an error occurred, a negative value is returned. + * * If an error occurred, a negative value is returned. */ int32_t SOCKETS_Close (Socket_t xSocket) { @@ -436,6 +442,7 @@ int32_t SOCKETS_Close (Socket_t xSocket) if (((int) NULL != (int) pxContext) && ((int) SOCKETS_INVALID_SOCKET != (int) pxContext) && ((int) pxContext->xSocket < WIFI_ONCHIP_SILEX_CFG_NUM_CREATEABLE_SOCKETS)) { +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT if (NULL != pxContext->pcDestination) { vPortFree(pxContext->pcDestination); @@ -450,6 +457,7 @@ int32_t SOCKETS_Close (Socket_t xSocket) { TLS_Cleanup(pxContext->pvTLSContext); } +#endif ret = (int32_t) rm_wifi_onchip_silex_socket_disconnect(((uint32_t) pxContext->xSocket)); if (ret != 0) @@ -528,7 +536,7 @@ int32_t SOCKETS_Close (Socket_t xSocket) * * @return * * On success, 0 is returned. - * * If an error occured, a negative value is returned. + * * If an error occured, a negative value is returned. */ int32_t SOCKETS_SetSockOpt (Socket_t xSocket, int32_t lLevel, @@ -557,6 +565,8 @@ int32_t SOCKETS_SetSockOpt (Socket_t xSocket, { case SOCKETS_SO_SERVER_NAME_INDICATION: { +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT + /* Do not set the SNI options if the socket is possibly already connected. */ if (WIFI_ONCHIP_SILEX_SOCKET_STATUS_CONNECTED == status) { @@ -578,11 +588,16 @@ int32_t SOCKETS_SetSockOpt (Socket_t xSocket, } } +#else + lStatus = SOCKETS_EINVAL; +#endif break; } case SOCKETS_SO_TRUSTED_SERVER_CERTIFICATE: { +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT + /* Do not set the trusted server certificate if the socket is possibly already connected. */ if (WIFI_ONCHIP_SILEX_SOCKET_STATUS_CONNECTED == status) { @@ -604,11 +619,16 @@ int32_t SOCKETS_SetSockOpt (Socket_t xSocket, } } +#else + lStatus = SOCKETS_EINVAL; +#endif break; } case SOCKETS_SO_REQUIRE_TLS: { +#if WIFI_ONCHIP_SILEX_CFG_TLS_SUPPORT + /* Do not set the TLS option if the socket is possibly already connected. */ if (WIFI_ONCHIP_SILEX_SOCKET_STATUS_CONNECTED == status) { @@ -619,6 +639,10 @@ int32_t SOCKETS_SetSockOpt (Socket_t xSocket, pxContext->xRequireTLS = pdTRUE; } +#else + lStatus = SOCKETS_EINVAL; +#endif + break; } @@ -724,159 +748,6 @@ BaseType_t SOCKETS_Init (void) return pdPASS; } -static CK_RV prvSocketsGetCryptoSession (CK_SESSION_HANDLE * pxSession, CK_FUNCTION_LIST_PTR_PTR ppxFunctionList) -{ - CK_RV xResult = 0; - CK_C_GetFunctionList pxCkGetFunctionList = NULL; - static CK_SESSION_HANDLE xPkcs11Session = 0; - static CK_FUNCTION_LIST_PTR pxPkcs11FunctionList = NULL; - CK_ULONG ulCount = 1; - CK_SLOT_ID xSlotId = 0; - - portENTER_CRITICAL(); - - if (0 == xPkcs11Session) - { - /* One-time initialization. */ - - /* Ensure that the PKCS#11 module is initialized. */ - if (0 == xResult) - { - pxCkGetFunctionList = C_GetFunctionList; - xResult = pxCkGetFunctionList(&pxPkcs11FunctionList); - } - - if (0 == xResult) - { - xResult = pxPkcs11FunctionList->C_Initialize(NULL); - } - - /* Get the default slot ID. */ - if (0 == xResult) - { - xResult = pxPkcs11FunctionList->C_GetSlotList(CK_TRUE, &xSlotId, &ulCount); - } - - /* Start a session with the PKCS#11 module. */ - if (0 == xResult) - { - xResult = pxPkcs11FunctionList->C_OpenSession(xSlotId, CKF_SERIAL_SESSION, NULL, NULL, &xPkcs11Session); - } - } - - portEXIT_CRITICAL(); - - /* Output the shared function pointers and session handle. */ - *ppxFunctionList = pxPkcs11FunctionList; - *pxSession = xPkcs11Session; - - return xResult; -} - -/** - * Generate a TCP Initial Sequence Number that is reasonably difficult - * to predict, per https://tools.ietf.org/html/rfc6528. - */ -uint32_t ulApplicationGetNextSequenceNumber (uint32_t ulSourceAddress, - uint16_t usSourcePort, - uint32_t ulDestinationAddress, - uint16_t usDestinationPort) -{ - CK_RV xResult = 0; - CK_SESSION_HANDLE xPkcs11Session = 0; - CK_FUNCTION_LIST_PTR pxPkcs11FunctionList = NULL; - CK_MECHANISM xMechSha256 = - {0}; - uint8_t ucSha256Result[cryptoSHA256_DIGEST_BYTES]; - CK_ULONG ulLength = sizeof(ucSha256Result); - uint32_t ulNextSequenceNumber = 0; - static uint64_t ullKey = 0; - - /* Acquire a crypto session handle. */ - xResult = prvSocketsGetCryptoSession(&xPkcs11Session, &pxPkcs11FunctionList); - - if (0 == xResult) - { - portENTER_CRITICAL(); - if (0 == ullKey) - { - /* One-time initialization, per boot, of the random seed. */ - xResult = pxPkcs11FunctionList->C_GenerateRandom(xPkcs11Session, (CK_BYTE_PTR) &ullKey, sizeof(ullKey)); - } - - portEXIT_CRITICAL(); - } - - /* Lock the shared crypto session. */ - portENTER_CRITICAL(); - - /* Start a hash. */ - if (0 == xResult) - { - xMechSha256.mechanism = CKM_SHA256; - xResult = pxPkcs11FunctionList->C_DigestInit(xPkcs11Session, &xMechSha256); - } - - /* Hash the seed. */ - if (0 == xResult) - { - xResult = pxPkcs11FunctionList->C_DigestUpdate(xPkcs11Session, (CK_BYTE_PTR) &ullKey, sizeof(ullKey)); - } - - /* Hash the source address. */ - if (0 == xResult) - { - xResult = - pxPkcs11FunctionList->C_DigestUpdate(xPkcs11Session, (CK_BYTE_PTR) &ulSourceAddress, - sizeof(ulSourceAddress)); - } - - /* Hash the source port. */ - if (0 == xResult) - { - xResult = - pxPkcs11FunctionList->C_DigestUpdate(xPkcs11Session, (CK_BYTE_PTR) &usSourcePort, sizeof(usSourcePort)); - } - - /* Hash the destination address. */ - if (0 == xResult) - { - xResult = - pxPkcs11FunctionList->C_DigestUpdate(xPkcs11Session, (CK_BYTE_PTR) &ulDestinationAddress, - sizeof(ulDestinationAddress)); - } - - /* Hash the destination port. */ - if (0 == xResult) - { - xResult = - pxPkcs11FunctionList->C_DigestUpdate(xPkcs11Session, (CK_BYTE_PTR) &usDestinationPort, - sizeof(usDestinationPort)); - } - - /* Get the hash. */ - if (0 == xResult) - { - xResult = pxPkcs11FunctionList->C_DigestFinal(xPkcs11Session, ucSha256Result, &ulLength); - } - - portEXIT_CRITICAL(); - - /* Use the first four bytes of the hash result as the starting point for - * all initial sequence numbers for connections based on the input 4-tuple. */ - if (0 == xResult) - { - memcpy(&ulNextSequenceNumber, ucSha256Result, sizeof(ulNextSequenceNumber)); - - /* Add the tick count of four-tick intervals. In theory, per the RFC - * (see above), this approach still allows server equipment to optimize - * handling of connections from the same device that haven't fully timed out. */ - ulNextSequenceNumber += xTaskGetTickCount() / 4; - } - - return ulNextSequenceNumber; -} - /*******************************************************************************************************************//** * @} (end addtogroup WIFI_ONCHIP_SILEX) **********************************************************************************************************************/